drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_calc.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "display_mode_lib.h"
  27 #include "display_mode_vba.h"
  28 #include "display_rq_dlg_calc.h"
  29
  30 static void calculate_ttu_cursor(struct display_mode_lib *mode_lib,
  31                 double *refcyc_per_req_delivery_pre_cur,
  32                 double *refcyc_per_req_delivery_cur,
  33                 double refclk_freq_in_mhz,
  34                 double ref_freq_to_pix_freq,
  35                 double hscale_pixel_rate_l,
  36                 double hscl_ratio,
  37                 double vratio_pre_l,
  38                 double vratio_l,
  39                 unsigned int cur_width,
  40                 enum cursor_bpp cur_bpp);
  41
  42 #include "dml_inline_defs.h"
  43
  44 static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma)
  45 {
  46         unsigned int ret_val = 0;
  47
  48         if (source_format == dm_444_16) {
  49                 if (!is_chroma)
  50                         ret_val = 2;
  51         } else if (source_format == dm_444_32) {
  52                 if (!is_chroma)
  53                         ret_val = 4;
  54         } else if (source_format == dm_444_64) {
  55                 if (!is_chroma)
  56                         ret_val = 8;
  57         } else if (source_format == dm_420_8) {
  58                 if (is_chroma)
  59                         ret_val = 2;
  60                 else
  61                         ret_val = 1;
  62         } else if (source_format == dm_420_10) {
  63                 if (is_chroma)
  64                         ret_val = 4;
  65                 else
  66                         ret_val = 2;
  67         } else if (source_format == dm_444_8) {
  68                 ret_val = 1;
  69         }
  70         return ret_val;
  71 }
  72
  73 static bool is_dual_plane(enum source_format_class source_format)
  74 {
  75         bool ret_val = 0;
  76
  77         if ((source_format == dm_420_8) || (source_format == dm_420_10))
  78                 ret_val = 1;
  79
  80         return ret_val;
  81 }
  82
  83 static double get_refcyc_per_delivery(struct display_mode_lib *mode_lib,
  84                 double refclk_freq_in_mhz,
  85                 double pclk_freq_in_mhz,
  86                 bool odm_combine,
  87                 unsigned int recout_width,
  88                 unsigned int hactive,
  89                 double vratio,
  90                 double hscale_pixel_rate,
  91                 unsigned int delivery_width,
  92                 unsigned int req_per_swath_ub)
  93 {
  94         double refcyc_per_delivery = 0.0;
  95
  96         if (vratio <= 1.0) {
  97                 if (odm_combine)
  98                         refcyc_per_delivery = (double) refclk_freq_in_mhz
  99                                         * dml_min((double) recout_width, (double) hactive / 2.0)
 100                                         / pclk_freq_in_mhz / (double) req_per_swath_ub;
 101                 else
 102                         refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width
 103                                         / pclk_freq_in_mhz / (double) req_per_swath_ub;
 104         } else {
 105                 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width
 106                                 / (double) hscale_pixel_rate / (double) req_per_swath_ub;
 107         }
 108
 109         dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz);
 110         dml_print("DML_DLG: %s: pclk_freq_in_mhz   = %3.2f\n", __func__, pclk_freq_in_mhz);
 111         dml_print("DML_DLG: %s: recout_width       = %d\n", __func__, recout_width);
 112         dml_print("DML_DLG: %s: vratio             = %3.2f\n", __func__, vratio);
 113         dml_print("DML_DLG: %s: req_per_swath_ub   = %d\n", __func__, req_per_swath_ub);
 114         dml_print("DML_DLG: %s: refcyc_per_delivery= %3.2f\n", __func__, refcyc_per_delivery);
 115
 116         return refcyc_per_delivery;
 117
 118 }
 119
 120 static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size)
 121 {
 122         if (tile_size == dm_256k_tile)
 123                 return (256 * 1024);
 124         else if (tile_size == dm_64k_tile)
 125                 return (64 * 1024);
 126         else
 127                 return (4 * 1024);
 128 }
 129
 130 static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib,
 131                 display_data_rq_regs_st *rq_regs,
 132                 const display_data_rq_sizing_params_st rq_sizing)
 133 {
 134         dml_print("DML_DLG: %s: rq_sizing param\n", __func__);
 135         print__data_rq_sizing_params_st(mode_lib, rq_sizing);
 136
 137         rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10;
 138
 139         if (rq_sizing.min_chunk_bytes == 0)
 140                 rq_regs->min_chunk_size = 0;
 141         else
 142                 rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1;
 143
 144         rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10;
 145         if (rq_sizing.min_meta_chunk_bytes == 0)
 146                 rq_regs->min_meta_chunk_size = 0;
 147         else
 148                 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1;
 149
 150         rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6;
 151         rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6;
 152 }
 153
 154 static void extract_rq_regs(struct display_mode_lib *mode_lib,
 155                 display_rq_regs_st *rq_regs,
 156                 const display_rq_params_st rq_param)
 157 {
 158         unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
 159         unsigned int detile_buf_plane1_addr = 0;
 160
 161         extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l);
 162
 163         rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height),
 164                         1) - 3;
 165
 166         if (rq_param.yuv420) {
 167                 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c);
 168                 rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height),
 169                                 1) - 3;
 170         }
 171
 172         rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height);
 173         rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height);
 174
 175         // FIXME: take the max between luma, chroma chunk size?
 176         // okay for now, as we are setting chunk_bytes to 8kb anyways
 177         if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb
 178                 rq_regs->drq_expansion_mode = 0;
 179         } else {
 180                 rq_regs->drq_expansion_mode = 2;
 181         }
 182         rq_regs->prq_expansion_mode = 1;
 183         rq_regs->mrq_expansion_mode = 1;
 184         rq_regs->crq_expansion_mode = 1;
 185
 186         if (rq_param.yuv420) {
 187                 if ((double) rq_param.misc.rq_l.stored_swath_bytes
 188                                 / (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) {
 189                         detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma
 190                 } else {
 191                         detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0),
 192                                         256,
 193                                         0) / 64.0; // 2/3 to chroma
 194                 }
 195         }
 196         rq_regs->plane1_base_address = detile_buf_plane1_addr;
 197 }
 198
 199 static void handle_det_buf_split(struct display_mode_lib *mode_lib,
 200                 display_rq_params_st *rq_param,
 201                 const display_pipe_source_params_st pipe_src_param)
 202 {
 203         unsigned int total_swath_bytes = 0;
 204         unsigned int swath_bytes_l = 0;
 205         unsigned int swath_bytes_c = 0;
 206         unsigned int full_swath_bytes_packed_l = 0;
 207         unsigned int full_swath_bytes_packed_c = 0;
 208         bool req128_l = 0;
 209         bool req128_c = 0;
 210         bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear);
 211         bool surf_vert = (pipe_src_param.source_scan == dm_vert);
 212         unsigned int log2_swath_height_l = 0;
 213         unsigned int log2_swath_height_c = 0;
 214         unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024;
 215
 216         full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes;
 217         full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes;
 218
 219         if (rq_param->yuv420_10bpc) {
 220                 full_swath_bytes_packed_l = dml_round_to_multiple(rq_param->misc.rq_l.full_swath_bytes * 2 / 3,
 221                                 256,
 222                                 1) + 256;
 223                 full_swath_bytes_packed_c = dml_round_to_multiple(rq_param->misc.rq_c.full_swath_bytes * 2 / 3,
 224                                 256,
 225                                 1) + 256;
 226         }
 227
 228         if (rq_param->yuv420) {
 229                 total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c;
 230
 231                 if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request
 232                         req128_l = 0;
 233                         req128_c = 0;
 234                         swath_bytes_l = full_swath_bytes_packed_l;
 235                         swath_bytes_c = full_swath_bytes_packed_c;
 236                 } else { //128b request (for luma only for yuv420 8bpc)
 237                         req128_l = 1;
 238                         req128_c = 0;
 239                         swath_bytes_l = full_swath_bytes_packed_l / 2;
 240                         swath_bytes_c = full_swath_bytes_packed_c;
 241                 }
 242                 // Note: assumption, the config that pass in will fit into
 243                 //       the detiled buffer.
 244         } else {
 245                 total_swath_bytes = 2 * full_swath_bytes_packed_l;
 246
 247                 if (total_swath_bytes <= detile_buf_size_in_bytes)
 248                         req128_l = 0;
 249                 else
 250                         req128_l = 1;
 251
 252                 swath_bytes_l = total_swath_bytes;
 253                 swath_bytes_c = 0;
 254         }
 255         rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l;
 256         rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c;
 257
 258         if (surf_linear) {
 259                 log2_swath_height_l = 0;
 260                 log2_swath_height_c = 0;
 261         } else if (!surf_vert) {
 262                 log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_height) - req128_l;
 263                 log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_height) - req128_c;
 264         } else {
 265                 log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_width) - req128_l;
 266                 log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_width) - req128_c;
 267         }
 268         rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l;
 269         rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c;
 270
 271         dml_print("DML_DLG: %s: req128_l = %0d\n", __func__, req128_l);
 272         dml_print("DML_DLG: %s: req128_c = %0d\n", __func__, req128_c);
 273         dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d\n",
 274                         __func__,
 275                         full_swath_bytes_packed_l);
 276         dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d\n",
 277                         __func__,
 278                         full_swath_bytes_packed_c);
 279 }
 280
 281 static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib,
 282                 display_data_rq_dlg_params_st *rq_dlg_param,
 283                 display_data_rq_misc_params_st *rq_misc_param,
 284                 display_data_rq_sizing_params_st *rq_sizing_param,
 285                 unsigned int vp_width,
 286                 unsigned int vp_height,
 287                 unsigned int data_pitch,
 288                 unsigned int meta_pitch,
 289                 unsigned int source_format,
 290                 unsigned int tiling,
 291                 unsigned int macro_tile_size,
 292                 unsigned int source_scan,
 293                 unsigned int is_chroma)
 294 {
 295         bool surf_linear = (tiling == dm_sw_linear);
 296         bool surf_vert = (source_scan == dm_vert);
 297
 298         unsigned int bytes_per_element;
 299         unsigned int bytes_per_element_y = get_bytes_per_element((enum source_format_class)(source_format),
 300                         false);
 301         unsigned int bytes_per_element_c = get_bytes_per_element((enum source_format_class)(source_format),
 302                         true);
 303
 304         unsigned int blk256_width = 0;
 305         unsigned int blk256_height = 0;
 306
 307         unsigned int blk256_width_y = 0;
 308         unsigned int blk256_height_y = 0;
 309         unsigned int blk256_width_c = 0;
 310         unsigned int blk256_height_c = 0;
 311         unsigned int log2_bytes_per_element;
 312         unsigned int log2_blk256_width;
 313         unsigned int log2_blk256_height;
 314         unsigned int blk_bytes;
 315         unsigned int log2_blk_bytes;
 316         unsigned int log2_blk_height;
 317         unsigned int log2_blk_width;
 318         unsigned int log2_meta_req_bytes;
 319         unsigned int log2_meta_req_height;
 320         unsigned int log2_meta_req_width;
 321         unsigned int meta_req_width;
 322         unsigned int meta_req_height;
 323         unsigned int log2_meta_row_height;
 324         unsigned int meta_row_width_ub;
 325         unsigned int log2_meta_chunk_bytes;
 326         unsigned int log2_meta_chunk_height;
 327
 328         //full sized meta chunk width in unit of data elements
 329         unsigned int log2_meta_chunk_width;
 330         unsigned int log2_min_meta_chunk_bytes;
 331         unsigned int min_meta_chunk_width;
 332         unsigned int meta_chunk_width;
 333         unsigned int meta_chunk_per_row_int;
 334         unsigned int meta_row_remainder;
 335         unsigned int meta_chunk_threshold;
 336         unsigned int meta_blk_bytes;
 337         unsigned int meta_blk_height;
 338         unsigned int meta_blk_width;
 339         unsigned int meta_surface_bytes;
 340         unsigned int vmpg_bytes;
 341         unsigned int meta_pte_req_per_frame_ub;
 342         unsigned int meta_pte_bytes_per_frame_ub;
 343         const unsigned int log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes);
 344         const unsigned int dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs;
 345         const unsigned int pde_proc_buffer_size_64k_reqs =
 346                         mode_lib->ip.pde_proc_buffer_size_64k_reqs;
 347
 348         unsigned int log2_vmpg_height = 0;
 349         unsigned int log2_vmpg_width = 0;
 350         unsigned int log2_dpte_req_height_ptes = 0;
 351         unsigned int log2_dpte_req_height = 0;
 352         unsigned int log2_dpte_req_width = 0;
 353         unsigned int log2_dpte_row_height_linear = 0;
 354         unsigned int log2_dpte_row_height = 0;
 355         unsigned int log2_dpte_group_width = 0;
 356         unsigned int dpte_row_width_ub = 0;
 357         unsigned int dpte_req_height = 0;
 358         unsigned int dpte_req_width = 0;
 359         unsigned int dpte_group_width = 0;
 360         unsigned int log2_dpte_group_bytes = 0;
 361         unsigned int log2_dpte_group_length = 0;
 362         unsigned int pde_buf_entries;
 363         bool yuv420 = (source_format == dm_420_8 || source_format == dm_420_10);
 364
 365         Calculate256BBlockSizes((enum source_format_class)(source_format),
 366                         (enum dm_swizzle_mode)(tiling),
 367                         bytes_per_element_y,
 368                         bytes_per_element_c,
 369                         &blk256_height_y,
 370                         &blk256_height_c,
 371                         &blk256_width_y,
 372                         &blk256_width_c);
 373
 374         if (!is_chroma) {
 375                 blk256_width = blk256_width_y;
 376                 blk256_height = blk256_height_y;
 377                 bytes_per_element = bytes_per_element_y;
 378         } else {
 379                 blk256_width = blk256_width_c;
 380                 blk256_height = blk256_height_c;
 381                 bytes_per_element = bytes_per_element_c;
 382         }
 383
 384         log2_bytes_per_element = dml_log2(bytes_per_element);
 385
 386         dml_print("DML_DLG: %s: surf_linear        = %d\n", __func__, surf_linear);
 387         dml_print("DML_DLG: %s: surf_vert          = %d\n", __func__, surf_vert);
 388         dml_print("DML_DLG: %s: blk256_width       = %d\n", __func__, blk256_width);
 389         dml_print("DML_DLG: %s: blk256_height      = %d\n", __func__, blk256_height);
 390
 391         log2_blk256_width = dml_log2((double) blk256_width);
 392         log2_blk256_height = dml_log2((double) blk256_height);
 393         blk_bytes = surf_linear ?
 394                         256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size);
 395         log2_blk_bytes = dml_log2((double) blk_bytes);
 396         log2_blk_height = 0;
 397         log2_blk_width = 0;
 398
 399         // remember log rule
 400         // "+" in log is multiply
 401         // "-" in log is divide
 402         // "/2" is like square root
 403         // blk is vertical biased
 404         if (tiling != dm_sw_linear)
 405                 log2_blk_height = log2_blk256_height
 406                                 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1);
 407         else
 408                 log2_blk_height = 0;  // blk height of 1
 409
 410         log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height;
 411
 412         if (!surf_vert) {
 413                 rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1)
 414                                 + blk256_width;
 415                 rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width;
 416         } else {
 417                 rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_height - 1, blk256_height, 1)
 418                                 + blk256_height;
 419                 rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height;
 420         }
 421
 422         if (!surf_vert)
 423                 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height
 424                                 * bytes_per_element;
 425         else
 426                 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width
 427                                 * bytes_per_element;
 428
 429         rq_misc_param->blk256_height = blk256_height;
 430         rq_misc_param->blk256_width = blk256_width;
 431
 432         // -------
 433         // meta
 434         // -------
 435         log2_meta_req_bytes = 6; // meta request is 64b and is 8x8byte meta element
 436
 437         // each 64b meta request for dcn is 8x8 meta elements and
 438         // a meta element covers one 256b block of the the data surface.
 439         log2_meta_req_height = log2_blk256_height + 3; // meta req is 8x8 byte, each byte represent 1 blk256
 440         log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element
 441                         - log2_meta_req_height;
 442         meta_req_width = 1 << log2_meta_req_width;
 443         meta_req_height = 1 << log2_meta_req_height;
 444         log2_meta_row_height = 0;
 445         meta_row_width_ub = 0;
 446
 447         // the dimensions of a meta row are meta_row_width x meta_row_height in elements.
 448         // calculate upper bound of the meta_row_width
 449         if (!surf_vert) {
 450                 log2_meta_row_height = log2_meta_req_height;
 451                 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1)
 452                                 + meta_req_width;
 453                 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width;
 454         } else {
 455                 log2_meta_row_height = log2_meta_req_width;
 456                 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1)
 457                                 + meta_req_height;
 458                 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height;
 459         }
 460         rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64;
 461
 462         rq_dlg_param->meta_row_height = 1 << log2_meta_row_height;
 463
 464         log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes);
 465         log2_meta_chunk_height = log2_meta_row_height;
 466
 467         //full sized meta chunk width in unit of data elements
 468         log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element
 469                         - log2_meta_chunk_height;
 470         log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes);
 471         min_meta_chunk_width = 1
 472                         << (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element
 473                                         - log2_meta_chunk_height);
 474         meta_chunk_width = 1 << log2_meta_chunk_width;
 475         meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width);
 476         meta_row_remainder = meta_row_width_ub % meta_chunk_width;
 477         meta_chunk_threshold = 0;
 478         meta_blk_bytes = 4096;
 479         meta_blk_height = blk256_height * 64;
 480         meta_blk_width = meta_blk_bytes * 256 / bytes_per_element / meta_blk_height;
 481         meta_surface_bytes = meta_pitch
 482                         * (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1) + meta_blk_height)
 483                         * bytes_per_element / 256;
 484         vmpg_bytes = mode_lib->soc.vmm_page_size_bytes;
 485         meta_pte_req_per_frame_ub = (dml_round_to_multiple(meta_surface_bytes - vmpg_bytes,
 486                         8 * vmpg_bytes,
 487                         1) + 8 * vmpg_bytes) / (8 * vmpg_bytes);
 488         meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; //64B mpte request
 489         rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub;
 490
 491         dml_print("DML_DLG: %s: meta_blk_height             = %d\n", __func__, meta_blk_height);
 492         dml_print("DML_DLG: %s: meta_blk_width              = %d\n", __func__, meta_blk_width);
 493         dml_print("DML_DLG: %s: meta_surface_bytes          = %d\n", __func__, meta_surface_bytes);
 494         dml_print("DML_DLG: %s: meta_pte_req_per_frame_ub   = %d\n",
 495                         __func__,
 496                         meta_pte_req_per_frame_ub);
 497         dml_print("DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d\n",
 498                         __func__,
 499                         meta_pte_bytes_per_frame_ub);
 500
 501         if (!surf_vert)
 502                 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width;
 503         else
 504                 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height;
 505
 506         if (meta_row_remainder <= meta_chunk_threshold)
 507                 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1;
 508         else
 509                 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2;
 510
 511         // ------
 512         // dpte
 513         // ------
 514         if (surf_linear) {
 515                 log2_vmpg_height = 0;   // one line high
 516         } else {
 517                 log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height;
 518         }
 519         log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height;
 520
 521         // only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4.
 522         if (surf_linear) { //one 64B PTE request returns 8 PTEs
 523                 log2_dpte_req_height_ptes = 0;
 524                 log2_dpte_req_width = log2_vmpg_width + 3;
 525                 log2_dpte_req_height = 0;
 526         } else if (log2_blk_bytes == 12) { //4KB tile means 4kB page size
 527                 //one 64B req gives 8x1 PTEs for 4KB tile
 528                 log2_dpte_req_height_ptes = 0;
 529                 log2_dpte_req_width = log2_blk_width + 3;
 530                 log2_dpte_req_height = log2_blk_height + 0;
 531         } else if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) { // tile block >= 64KB
 532                 //two 64B reqs of 2x4 PTEs give 16 PTEs to cover 64KB
 533                 log2_dpte_req_height_ptes = 4;
 534                 log2_dpte_req_width = log2_blk256_width + 4; // log2_64KB_width
 535                 log2_dpte_req_height = log2_blk256_height + 4; // log2_64KB_height
 536         } else { //64KB page size and must 64KB tile block
 537                  //one 64B req gives 8x1 PTEs for 64KB tile
 538                 log2_dpte_req_height_ptes = 0;
 539                 log2_dpte_req_width = log2_blk_width + 3;
 540                 log2_dpte_req_height = log2_blk_height + 0;
 541         }
 542
 543         // The dpte request dimensions in data elements is dpte_req_width x dpte_req_height
 544         // log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent
 545         // That depends on the pte shape (i.e. 8x1, 4x2, 2x4)
 546         //log2_dpte_req_height    = log2_vmpg_height + log2_dpte_req_height_ptes;
 547         //log2_dpte_req_width     = log2_vmpg_width + log2_dpte_req_width_ptes;
 548         dpte_req_height = 1 << log2_dpte_req_height;
 549         dpte_req_width = 1 << log2_dpte_req_width;
 550
 551         // calculate pitch dpte row buffer can hold
 552         // round the result down to a power of two.
 553         pde_buf_entries = yuv420 ? (pde_proc_buffer_size_64k_reqs >> 1) : pde_proc_buffer_size_64k_reqs;
 554         if (surf_linear) {
 555                 unsigned int dpte_row_height;
 556
 557                 log2_dpte_row_height_linear = dml_floor(dml_log2(dml_min(64 * 1024 * pde_buf_entries
 558                                                                                 / bytes_per_element,
 559                                                                 dpte_buf_in_pte_reqs
 560                                                                                 * dpte_req_width)
 561                                                                 / data_pitch),
 562                                 1);
 563
 564                 ASSERT(log2_dpte_row_height_linear >= 3);
 565
 566                 if (log2_dpte_row_height_linear > 7)
 567                         log2_dpte_row_height_linear = 7;
 568
 569                 log2_dpte_row_height = log2_dpte_row_height_linear;
 570                 // For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary.
 571                 // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
 572                 dpte_row_height = 1 << log2_dpte_row_height;
 573                 dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1,
 574                                 dpte_req_width,
 575                                 1) + dpte_req_width;
 576                 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
 577         } else {
 578                 // the upper bound of the dpte_row_width without dependency on viewport position follows.
 579                 // for tiled mode, row height is the same as req height and row store up to vp size upper bound
 580                 if (!surf_vert) {
 581                         log2_dpte_row_height = log2_dpte_req_height;
 582                         dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1)
 583                                         + dpte_req_width;
 584                         rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width;
 585                 } else {
 586                         log2_dpte_row_height =
 587                                         (log2_blk_width < log2_dpte_req_width) ?
 588                                                         log2_blk_width : log2_dpte_req_width;
 589                         dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1)
 590                                         + dpte_req_height;
 591                         rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height;
 592                 }
 593         }
 594         if (log2_blk_bytes >= 16 && log2_vmpg_bytes == 12) // tile block >= 64KB
 595                 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request
 596         else
 597                 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request
 598
 599         rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
 600
 601         // the dpte_group_bytes is reduced for the specific case of vertical
 602         // access of a tile surface that has dpte request of 8x1 ptes.
 603         if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group
 604                 rq_sizing_param->dpte_group_bytes = 512;
 605         else
 606                 //full size
 607                 rq_sizing_param->dpte_group_bytes = 2048;
 608
 609         //since pte request size is 64byte, the number of data pte requests per full sized group is as follows.
 610         log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes);
 611         log2_dpte_group_length = log2_dpte_group_bytes - 6; //length in 64b requests
 612
 613         // full sized data pte group width in elements
 614         if (!surf_vert)
 615                 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width;
 616         else
 617                 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height;
 618
 619         //But if the tile block >=64KB and the page size is 4KB, then each dPTE request is 2*64B
 620         if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) // tile block >= 64KB
 621                 log2_dpte_group_width = log2_dpte_group_width - 1;
 622
 623         dpte_group_width = 1 << log2_dpte_group_width;
 624
 625         // since dpte groups are only aligned to dpte_req_width and not dpte_group_width,
 626         // the upper bound for the dpte groups per row is as follows.
 627         rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width,
 628                         1);
 629 }
 630
 631 static void get_surf_rq_param(struct display_mode_lib *mode_lib,
 632                 display_data_rq_sizing_params_st *rq_sizing_param,
 633                 display_data_rq_dlg_params_st *rq_dlg_param,
 634                 display_data_rq_misc_params_st *rq_misc_param,
 635                 const display_pipe_source_params_st pipe_src_param,
 636                 bool is_chroma)
 637 {
 638         bool mode_422 = 0;
 639         unsigned int vp_width = 0;
 640         unsigned int vp_height = 0;
 641         unsigned int data_pitch = 0;
 642         unsigned int meta_pitch = 0;
 643         unsigned int ppe = mode_422 ? 2 : 1;
 644
 645         // FIXME check if ppe apply for both luma and chroma in 422 case
 646         if (is_chroma) {
 647                 vp_width = pipe_src_param.viewport_width_c / ppe;
 648                 vp_height = pipe_src_param.viewport_height_c;
 649                 data_pitch = pipe_src_param.data_pitch_c;
 650                 meta_pitch = pipe_src_param.meta_pitch_c;
 651         } else {
 652                 vp_width = pipe_src_param.viewport_width / ppe;
 653                 vp_height = pipe_src_param.viewport_height;
 654                 data_pitch = pipe_src_param.data_pitch;
 655                 meta_pitch = pipe_src_param.meta_pitch;
 656         }
 657
 658         rq_sizing_param->chunk_bytes = 8192;
 659
 660         if (rq_sizing_param->chunk_bytes == 64 * 1024)
 661                 rq_sizing_param->min_chunk_bytes = 0;
 662         else
 663                 rq_sizing_param->min_chunk_bytes = 1024;
 664
 665         rq_sizing_param->meta_chunk_bytes = 2048;
 666         rq_sizing_param->min_meta_chunk_bytes = 256;
 667
 668         rq_sizing_param->mpte_group_bytes = 2048;
 669
 670         get_meta_and_pte_attr(mode_lib,
 671                         rq_dlg_param,
 672                         rq_misc_param,
 673                         rq_sizing_param,
 674                         vp_width,
 675                         vp_height,
 676                         data_pitch,
 677                         meta_pitch,
 678                         pipe_src_param.source_format,
 679                         pipe_src_param.sw_mode,
 680                         pipe_src_param.macro_tile_size,
 681                         pipe_src_param.source_scan,
 682                         is_chroma);
 683 }
 684
 685 void dml_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib,
 686                 display_rq_params_st *rq_param,
 687                 const display_pipe_source_params_st pipe_src_param)
 688 {
 689         // get param for luma surface
 690         rq_param->yuv420 = pipe_src_param.source_format == dm_420_8
 691                         || pipe_src_param.source_format == dm_420_10;
 692         rq_param->yuv420_10bpc = pipe_src_param.source_format == dm_420_10;
 693
 694         get_surf_rq_param(mode_lib,
 695                         &(rq_param->sizing.rq_l),
 696                         &(rq_param->dlg.rq_l),
 697                         &(rq_param->misc.rq_l),
 698                         pipe_src_param,
 699                         0);
 700
 701         if (is_dual_plane((enum source_format_class)(pipe_src_param.source_format))) {
 702                 // get param for chroma surface
 703                 get_surf_rq_param(mode_lib,
 704                                 &(rq_param->sizing.rq_c),
 705                                 &(rq_param->dlg.rq_c),
 706                                 &(rq_param->misc.rq_c),
 707                                 pipe_src_param,
 708                                 1);
 709         }
 710
 711         // calculate how to split the det buffer space between luma and chroma
 712         handle_det_buf_split(mode_lib, rq_param, pipe_src_param);
 713         print__rq_params_st(mode_lib, *rq_param);
 714 }
 715
 716 void dml_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib,
 717                 display_rq_regs_st *rq_regs,
 718                 const display_pipe_source_params_st pipe_src_param)
 719 {
 720         display_rq_params_st rq_param = {0};
 721
 722         memset(rq_regs, 0, sizeof(*rq_regs));
 723         dml_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_src_param);
 724         extract_rq_regs(mode_lib, rq_regs, rq_param);
 725
 726         print__rq_regs_st(mode_lib, *rq_regs);
 727 }
 728
 729 // Note: currently taken in as is.
 730 // Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma.
 731 void dml_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib,
 732                 const display_e2e_pipe_params_st *e2e_pipe_param,
 733                 const unsigned int num_pipes,
 734                 const unsigned int pipe_idx,
 735                 display_dlg_regs_st *disp_dlg_regs,
 736                 display_ttu_regs_st *disp_ttu_regs,
 737                 const display_rq_dlg_params_st rq_dlg_param,
 738                 const display_dlg_sys_params_st dlg_sys_param,
 739                 const bool cstate_en,
 740                 const bool pstate_en,
 741                 const bool vm_en,
 742                 const bool ignore_viewport_pos,
 743                 const bool immediate_flip_support)
 744 {
 745         const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src;
 746         const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest;
 747         const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout;
 748         const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg;
 749         const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth;
 750         const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps;
 751
 752         // -------------------------
 753         // Section 1.15.2.1: OTG dependent Params
 754         // -------------------------
 755         // Timing
 756         unsigned int htotal = dst->htotal;
 757 //    unsigned int hblank_start = dst.hblank_start; // TODO: Remove
 758         unsigned int hblank_end = dst->hblank_end;
 759         unsigned int vblank_start = dst->vblank_start;
 760         unsigned int vblank_end = dst->vblank_end;
 761         unsigned int min_vblank = mode_lib->ip.min_vblank_lines;
 762
 763         double dppclk_freq_in_mhz = clks->dppclk_mhz;
 764         double dispclk_freq_in_mhz = clks->dispclk_mhz;
 765         double refclk_freq_in_mhz = clks->refclk_mhz;
 766         double pclk_freq_in_mhz = dst->pixel_rate_mhz;
 767         bool interlaced = dst->interlaced;
 768
 769         double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz;
 770
 771         double min_dcfclk_mhz;
 772         double t_calc_us;
 773         double min_ttu_vblank;
 774
 775         double min_dst_y_ttu_vblank;
 776         unsigned int dlg_vblank_start;
 777         bool dual_plane;
 778         bool mode_422;
 779         unsigned int access_dir;
 780         unsigned int vp_height_l;
 781         unsigned int vp_width_l;
 782         unsigned int vp_height_c;
 783         unsigned int vp_width_c;
 784
 785         // Scaling
 786         unsigned int htaps_l;
 787         unsigned int htaps_c;
 788         double hratio_l;
 789         double hratio_c;
 790         double vratio_l;
 791         double vratio_c;
 792         bool scl_enable;
 793
 794         double line_time_in_us;
 795         //    double vinit_l;
 796         //    double vinit_c;
 797         //    double vinit_bot_l;
 798         //    double vinit_bot_c;
 799
 800         //    unsigned int swath_height_l;
 801         unsigned int swath_width_ub_l;
 802         //    unsigned int dpte_bytes_per_row_ub_l;
 803         unsigned int dpte_groups_per_row_ub_l;
 804         //    unsigned int meta_pte_bytes_per_frame_ub_l;
 805         //    unsigned int meta_bytes_per_row_ub_l;
 806
 807         //    unsigned int swath_height_c;
 808         unsigned int swath_width_ub_c;
 809         //   unsigned int dpte_bytes_per_row_ub_c;
 810         unsigned int dpte_groups_per_row_ub_c;
 811
 812         unsigned int meta_chunks_per_row_ub_l;
 813         unsigned int meta_chunks_per_row_ub_c;
 814         unsigned int vupdate_offset;
 815         unsigned int vupdate_width;
 816         unsigned int vready_offset;
 817
 818         unsigned int dppclk_delay_subtotal;
 819         unsigned int dispclk_delay_subtotal;
 820         unsigned int pixel_rate_delay_subtotal;
 821
 822         unsigned int vstartup_start;
 823         unsigned int dst_x_after_scaler;
 824         unsigned int dst_y_after_scaler;
 825         double line_wait;
 826         double dst_y_prefetch;
 827         double dst_y_per_vm_vblank;
 828         double dst_y_per_row_vblank;
 829         double dst_y_per_vm_flip;
 830         double dst_y_per_row_flip;
 831         double min_dst_y_per_vm_vblank;
 832         double min_dst_y_per_row_vblank;
 833         double lsw;
 834         double vratio_pre_l;
 835         double vratio_pre_c;
 836         unsigned int req_per_swath_ub_l;
 837         unsigned int req_per_swath_ub_c;
 838         unsigned int meta_row_height_l;
 839         unsigned int meta_row_height_c;
 840         unsigned int swath_width_pixels_ub_l;
 841         unsigned int swath_width_pixels_ub_c;
 842         unsigned int scaler_rec_in_width_l;
 843         unsigned int scaler_rec_in_width_c;
 844         unsigned int dpte_row_height_l;
 845         unsigned int dpte_row_height_c;
 846         double hscale_pixel_rate_l;
 847         double hscale_pixel_rate_c;
 848         double min_hratio_fact_l;
 849         double min_hratio_fact_c;
 850         double refcyc_per_line_delivery_pre_l;
 851         double refcyc_per_line_delivery_pre_c;
 852         double refcyc_per_line_delivery_l;
 853         double refcyc_per_line_delivery_c;
 854
 855         double refcyc_per_req_delivery_pre_l;
 856         double refcyc_per_req_delivery_pre_c;
 857         double refcyc_per_req_delivery_l;
 858         double refcyc_per_req_delivery_c;
 859
 860         unsigned int full_recout_width;
 861         double xfc_transfer_delay;
 862         double xfc_precharge_delay;
 863         double xfc_remote_surface_flip_latency;
 864         double xfc_dst_y_delta_drq_limit;
 865         double xfc_prefetch_margin;
 866         double refcyc_per_req_delivery_pre_cur0;
 867         double refcyc_per_req_delivery_cur0;
 868         double refcyc_per_req_delivery_pre_cur1;
 869         double refcyc_per_req_delivery_cur1;
 870
 871         memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs));
 872         memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs));
 873
 874         dml_print("DML_DLG: %s:  cstate_en = %d\n", __func__, cstate_en);
 875         dml_print("DML_DLG: %s:  pstate_en = %d\n", __func__, pstate_en);
 876         dml_print("DML_DLG: %s:  vm_en     = %d\n", __func__, vm_en);
 877         dml_print("DML_DLG: %s:  ignore_viewport_pos  = %d\n", __func__, ignore_viewport_pos);
 878         dml_print("DML_DLG: %s:  immediate_flip_support  = %d\n", __func__, immediate_flip_support);
 879
 880         dml_print("DML_DLG: %s: dppclk_freq_in_mhz     = %3.2f\n", __func__, dppclk_freq_in_mhz);
 881         dml_print("DML_DLG: %s: dispclk_freq_in_mhz    = %3.2f\n", __func__, dispclk_freq_in_mhz);
 882         dml_print("DML_DLG: %s: refclk_freq_in_mhz     = %3.2f\n", __func__, refclk_freq_in_mhz);
 883         dml_print("DML_DLG: %s: pclk_freq_in_mhz       = %3.2f\n", __func__, pclk_freq_in_mhz);
 884         dml_print("DML_DLG: %s: interlaced             = %d\n", __func__, interlaced);
 885         ASSERT(ref_freq_to_pix_freq < 4.0);
 886
 887         disp_dlg_regs->ref_freq_to_pix_freq =
 888                         (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19));
 889         disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal
 890                         * dml_pow(2, 8));
 891         disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits
 892         disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end
 893                         * (double) ref_freq_to_pix_freq);
 894         ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13));
 895
 896         min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz;
 897         set_prefetch_mode(mode_lib, cstate_en, pstate_en, ignore_viewport_pos, immediate_flip_support);
 898         t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes);
 899         min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
 900
 901         min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal;
 902         dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start;
 903
 904         disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start
 905                         + min_dst_y_ttu_vblank) * dml_pow(2, 2));
 906         ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18));
 907
 908         dml_print("DML_DLG: %s: min_dcfclk_mhz                         = %3.2f\n",
 909                         __func__,
 910                         min_dcfclk_mhz);
 911         dml_print("DML_DLG: %s: min_ttu_vblank                         = %3.2f\n",
 912                         __func__,
 913                         min_ttu_vblank);
 914         dml_print("DML_DLG: %s: min_dst_y_ttu_vblank                   = %3.2f\n",
 915                         __func__,
 916                         min_dst_y_ttu_vblank);
 917         dml_print("DML_DLG: %s: t_calc_us                              = %3.2f\n",
 918                         __func__,
 919                         t_calc_us);
 920         dml_print("DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start    = 0x%0x\n",
 921                         __func__,
 922                         disp_dlg_regs->min_dst_y_next_start);
 923         dml_print("DML_DLG: %s: ref_freq_to_pix_freq                   = %3.2f\n",
 924                         __func__,
 925                         ref_freq_to_pix_freq);
 926
 927         // -------------------------
 928         // Section 1.15.2.2: Prefetch, Active and TTU
 929         // -------------------------
 930         // Prefetch Calc
 931         // Source
 932 //             dcc_en              = src.dcc;
 933         dual_plane = is_dual_plane((enum source_format_class)(src->source_format));
 934         mode_422 = 0; // FIXME
 935         access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed
 936 //      bytes_per_element_l = get_bytes_per_element(source_format_class(src.source_format), 0);
 937 //      bytes_per_element_c = get_bytes_per_element(source_format_class(src.source_format), 1);
 938         vp_height_l = src->viewport_height;
 939         vp_width_l = src->viewport_width;
 940         vp_height_c = src->viewport_height_c;
 941         vp_width_c = src->viewport_width_c;
 942
 943         // Scaling
 944         htaps_l = taps->htaps;
 945         htaps_c = taps->htaps_c;
 946         hratio_l = scl->hscl_ratio;
 947         hratio_c = scl->hscl_ratio_c;
 948         vratio_l = scl->vscl_ratio;
 949         vratio_c = scl->vscl_ratio_c;
 950         scl_enable = scl->scl_enable;
 951
 952         line_time_in_us = (htotal / pclk_freq_in_mhz);
 953 //     vinit_l         = scl.vinit;
 954 //     vinit_c         = scl.vinit_c;
 955 //     vinit_bot_l     = scl.vinit_bot;
 956 //     vinit_bot_c     = scl.vinit_bot_c;
 957
 958 //    unsigned int swath_height_l                 = rq_dlg_param.rq_l.swath_height;
 959         swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub;
 960 //    unsigned int dpte_bytes_per_row_ub_l        = rq_dlg_param.rq_l.dpte_bytes_per_row_ub;
 961         dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub;
 962 //    unsigned int meta_pte_bytes_per_frame_ub_l  = rq_dlg_param.rq_l.meta_pte_bytes_per_frame_ub;
 963 //    unsigned int meta_bytes_per_row_ub_l        = rq_dlg_param.rq_l.meta_bytes_per_row_ub;
 964
 965 //    unsigned int swath_height_c                 = rq_dlg_param.rq_c.swath_height;
 966         swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub;
 967         //   dpte_bytes_per_row_ub_c        = rq_dlg_param.rq_c.dpte_bytes_per_row_ub;
 968         dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub;
 969
 970         meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub;
 971         meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub;
 972         vupdate_offset = dst->vupdate_offset;
 973         vupdate_width = dst->vupdate_width;
 974         vready_offset = dst->vready_offset;
 975
 976         dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal;
 977         dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal;
 978
 979         if (scl_enable)
 980                 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl;
 981         else
 982                 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl_lb_only;
 983
 984         dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_cnvc_formatter
 985                         + src->num_cursors * mode_lib->ip.dppclk_delay_cnvc_cursor;
 986
 987         if (dout->dsc_enable) {
 988                 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
 989
 990                 dispclk_delay_subtotal += dsc_delay;
 991         }
 992
 993         pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz
 994                         + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz;
 995
 996         vstartup_start = dst->vstartup_start;
 997         if (interlaced) {
 998                 if (vstartup_start / 2.0
 999                                 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
1000                                 <= vblank_end / 2.0)
1001                         disp_dlg_regs->vready_after_vcount0 = 1;
1002                 else
1003                         disp_dlg_regs->vready_after_vcount0 = 0;
1004         } else {
1005                 if (vstartup_start
1006                                 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
1007                                 <= vblank_end)
1008                         disp_dlg_regs->vready_after_vcount0 = 1;
1009                 else
1010                         disp_dlg_regs->vready_after_vcount0 = 0;
1011         }
1012
1013         // TODO: Where is this coming from?
1014         if (interlaced)
1015                 vstartup_start = vstartup_start / 2;
1016
1017         // TODO: What if this min_vblank doesn't match the value in the dml_config_settings.cpp?
1018         if (vstartup_start >= min_vblank) {
1019                 dml_print("WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d\n",
1020                                 __func__,
1021                                 vblank_start,
1022                                 vblank_end);
1023                 dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n",
1024                                 __func__,
1025                                 vstartup_start,
1026                                 min_vblank);
1027                 min_vblank = vstartup_start + 1;
1028                 dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n",
1029                                 __func__,
1030                                 vstartup_start,
1031                                 min_vblank);
1032         }
1033
1034         dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1035         dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1036
1037         dml_print("DML_DLG: %s: htotal                                 = %d\n", __func__, htotal);
1038         dml_print("DML_DLG: %s: pixel_rate_delay_subtotal              = %d\n",
1039                         __func__,
1040                         pixel_rate_delay_subtotal);
1041         dml_print("DML_DLG: %s: dst_x_after_scaler                     = %d\n",
1042                         __func__,
1043                         dst_x_after_scaler);
1044         dml_print("DML_DLG: %s: dst_y_after_scaler                     = %d\n",
1045                         __func__,
1046                         dst_y_after_scaler);
1047
1048         // Lwait
1049         line_wait = mode_lib->soc.urgent_latency_us;
1050         if (cstate_en)
1051                 line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait);
1052         if (pstate_en)
1053                 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us
1054                                                 + mode_lib->soc.urgent_latency_us,
1055                                 line_wait);
1056         line_wait = line_wait / line_time_in_us;
1057
1058         dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1059         dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch);
1060
1061         dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(mode_lib,
1062                         e2e_pipe_param,
1063                         num_pipes,
1064                         pipe_idx);
1065         dst_y_per_row_vblank = get_dst_y_per_row_vblank(mode_lib,
1066                         e2e_pipe_param,
1067                         num_pipes,
1068                         pipe_idx);
1069         dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1070         dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1071
1072         min_dst_y_per_vm_vblank = 8.0;
1073         min_dst_y_per_row_vblank = 16.0;
1074
1075         // magic!
1076         if (htotal <= 75) {
1077                 min_vblank = 300;
1078                 min_dst_y_per_vm_vblank = 100.0;
1079                 min_dst_y_per_row_vblank = 100.0;
1080         }
1081
1082         dml_print("DML_DLG: %s: dst_y_per_vm_vblank    = %3.2f\n", __func__, dst_y_per_vm_vblank);
1083         dml_print("DML_DLG: %s: dst_y_per_row_vblank   = %3.2f\n", __func__, dst_y_per_row_vblank);
1084
1085         ASSERT(dst_y_per_vm_vblank < min_dst_y_per_vm_vblank);
1086         ASSERT(dst_y_per_row_vblank < min_dst_y_per_row_vblank);
1087
1088         ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank));
1089         lsw = dst_y_prefetch - (dst_y_per_vm_vblank + dst_y_per_row_vblank);
1090
1091         dml_print("DML_DLG: %s: lsw = %3.2f\n", __func__, lsw);
1092
1093         vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1094         vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1095
1096         dml_print("DML_DLG: %s: vratio_pre_l=%3.2f\n", __func__, vratio_pre_l);
1097         dml_print("DML_DLG: %s: vratio_pre_c=%3.2f\n", __func__, vratio_pre_c);
1098
1099         // Active
1100         req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub;
1101         req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub;
1102         meta_row_height_l = rq_dlg_param.rq_l.meta_row_height;
1103         meta_row_height_c = rq_dlg_param.rq_c.meta_row_height;
1104         swath_width_pixels_ub_l = 0;
1105         swath_width_pixels_ub_c = 0;
1106         scaler_rec_in_width_l = 0;
1107         scaler_rec_in_width_c = 0;
1108         dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height;
1109         dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height;
1110
1111         if (mode_422) {
1112                 swath_width_pixels_ub_l = swath_width_ub_l * 2;  // *2 for 2 pixel per element
1113                 swath_width_pixels_ub_c = swath_width_ub_c * 2;
1114         } else {
1115                 swath_width_pixels_ub_l = swath_width_ub_l * 1;
1116                 swath_width_pixels_ub_c = swath_width_ub_c * 1;
1117         }
1118
1119         hscale_pixel_rate_l = 0.;
1120         hscale_pixel_rate_c = 0.;
1121         min_hratio_fact_l = 1.0;
1122         min_hratio_fact_c = 1.0;
1123
1124         if (htaps_l <= 1)
1125                 min_hratio_fact_l = 2.0;
1126         else if (htaps_l <= 6) {
1127                 if ((hratio_l * 2.0) > 4.0)
1128                         min_hratio_fact_l = 4.0;
1129                 else
1130                         min_hratio_fact_l = hratio_l * 2.0;
1131         } else {
1132                 if (hratio_l > 4.0)
1133                         min_hratio_fact_l = 4.0;
1134                 else
1135                         min_hratio_fact_l = hratio_l;
1136         }
1137
1138         hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz;
1139
1140         if (htaps_c <= 1)
1141                 min_hratio_fact_c = 2.0;
1142         else if (htaps_c <= 6) {
1143                 if ((hratio_c * 2.0) > 4.0)
1144                         min_hratio_fact_c = 4.0;
1145                 else
1146                         min_hratio_fact_c = hratio_c * 2.0;
1147         } else {
1148                 if (hratio_c > 4.0)
1149                         min_hratio_fact_c = 4.0;
1150                 else
1151                         min_hratio_fact_c = hratio_c;
1152         }
1153
1154         hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz;
1155
1156         refcyc_per_line_delivery_pre_l = 0.;
1157         refcyc_per_line_delivery_pre_c = 0.;
1158         refcyc_per_line_delivery_l = 0.;
1159         refcyc_per_line_delivery_c = 0.;
1160
1161         refcyc_per_req_delivery_pre_l = 0.;
1162         refcyc_per_req_delivery_pre_c = 0.;
1163         refcyc_per_req_delivery_l = 0.;
1164         refcyc_per_req_delivery_c = 0.;
1165
1166         full_recout_width = 0;
1167         // In ODM
1168         if (src->is_hsplit) {
1169                 // This "hack"  is only allowed (and valid) for MPC combine. In ODM
1170                 // combine, you MUST specify the full_recout_width...according to Oswin
1171                 if (dst->full_recout_width == 0 && !dst->odm_combine) {
1172                         dml_print("DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n",
1173                                         __func__);
1174                         full_recout_width = dst->recout_width * 2; // assume half split for dcn1
1175                 } else
1176                         full_recout_width = dst->full_recout_width;
1177         } else
1178                 full_recout_width = dst->recout_width;
1179
1180         // mpc_combine and odm_combine are mutually exclusive
1181         refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(mode_lib,
1182                         refclk_freq_in_mhz,
1183                         pclk_freq_in_mhz,
1184                         dst->odm_combine,
1185                         full_recout_width,
1186                         dst->hactive,
1187                         vratio_pre_l,
1188                         hscale_pixel_rate_l,
1189                         swath_width_pixels_ub_l,
1190                         1); // per line
1191
1192         refcyc_per_line_delivery_l = get_refcyc_per_delivery(mode_lib,
1193                         refclk_freq_in_mhz,
1194                         pclk_freq_in_mhz,
1195                         dst->odm_combine,
1196                         full_recout_width,
1197                         dst->hactive,
1198                         vratio_l,
1199                         hscale_pixel_rate_l,
1200                         swath_width_pixels_ub_l,
1201                         1); // per line
1202
1203         dml_print("DML_DLG: %s: full_recout_width              = %d\n",
1204                         __func__,
1205                         full_recout_width);
1206         dml_print("DML_DLG: %s: hscale_pixel_rate_l            = %3.2f\n",
1207                         __func__,
1208                         hscale_pixel_rate_l);
1209         dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n",
1210                         __func__,
1211                         refcyc_per_line_delivery_pre_l);
1212         dml_print("DML_DLG: %s: refcyc_per_line_delivery_l     = %3.2f\n",
1213                         __func__,
1214                         refcyc_per_line_delivery_l);
1215
1216         if (dual_plane) {
1217                 refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery(mode_lib,
1218                                 refclk_freq_in_mhz,
1219                                 pclk_freq_in_mhz,
1220                                 dst->odm_combine,
1221                                 full_recout_width,
1222                                 dst->hactive,
1223                                 vratio_pre_c,
1224                                 hscale_pixel_rate_c,
1225                                 swath_width_pixels_ub_c,
1226                                 1); // per line
1227
1228                 refcyc_per_line_delivery_c = get_refcyc_per_delivery(mode_lib,
1229                                 refclk_freq_in_mhz,
1230                                 pclk_freq_in_mhz,
1231                                 dst->odm_combine,
1232                                 full_recout_width,
1233                                 dst->hactive,
1234                                 vratio_c,
1235                                 hscale_pixel_rate_c,
1236                                 swath_width_pixels_ub_c,
1237                                 1);  // per line
1238
1239                 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n",
1240                                 __func__,
1241                                 refcyc_per_line_delivery_pre_c);
1242                 dml_print("DML_DLG: %s: refcyc_per_line_delivery_c     = %3.2f\n",
1243                                 __func__,
1244                                 refcyc_per_line_delivery_c);
1245         }
1246
1247         // TTU - Luma / Chroma
1248         if (access_dir) {  // vertical access
1249                 scaler_rec_in_width_l = vp_height_l;
1250                 scaler_rec_in_width_c = vp_height_c;
1251         } else {
1252                 scaler_rec_in_width_l = vp_width_l;
1253                 scaler_rec_in_width_c = vp_width_c;
1254         }
1255
1256         refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery(mode_lib,
1257                         refclk_freq_in_mhz,
1258                         pclk_freq_in_mhz,
1259                         dst->odm_combine,
1260                         full_recout_width,
1261                         dst->hactive,
1262                         vratio_pre_l,
1263                         hscale_pixel_rate_l,
1264                         scaler_rec_in_width_l,
1265                         req_per_swath_ub_l);  // per req
1266         refcyc_per_req_delivery_l = get_refcyc_per_delivery(mode_lib,
1267                         refclk_freq_in_mhz,
1268                         pclk_freq_in_mhz,
1269                         dst->odm_combine,
1270                         full_recout_width,
1271                         dst->hactive,
1272                         vratio_l,
1273                         hscale_pixel_rate_l,
1274                         scaler_rec_in_width_l,
1275                         req_per_swath_ub_l);  // per req
1276
1277         dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n",
1278                         __func__,
1279                         refcyc_per_req_delivery_pre_l);
1280         dml_print("DML_DLG: %s: refcyc_per_req_delivery_l     = %3.2f\n",
1281                         __func__,
1282                         refcyc_per_req_delivery_l);
1283
1284         ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13));
1285         ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13));
1286
1287         if (dual_plane) {
1288                 refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery(mode_lib,
1289                                 refclk_freq_in_mhz,
1290                                 pclk_freq_in_mhz,
1291                                 dst->odm_combine,
1292                                 full_recout_width,
1293                                 dst->hactive,
1294                                 vratio_pre_c,
1295                                 hscale_pixel_rate_c,
1296                                 scaler_rec_in_width_c,
1297                                 req_per_swath_ub_c);  // per req
1298                 refcyc_per_req_delivery_c = get_refcyc_per_delivery(mode_lib,
1299                                 refclk_freq_in_mhz,
1300                                 pclk_freq_in_mhz,
1301                                 dst->odm_combine,
1302                                 full_recout_width,
1303                                 dst->hactive,
1304                                 vratio_c,
1305                                 hscale_pixel_rate_c,
1306                                 scaler_rec_in_width_c,
1307                                 req_per_swath_ub_c);  // per req
1308
1309                 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n",
1310                                 __func__,
1311                                 refcyc_per_req_delivery_pre_c);
1312                 dml_print("DML_DLG: %s: refcyc_per_req_delivery_c     = %3.2f\n",
1313                                 __func__,
1314                                 refcyc_per_req_delivery_c);
1315
1316                 ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13));
1317                 ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13));
1318         }
1319
1320         // XFC
1321         xfc_transfer_delay = get_xfc_transfer_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx);
1322         xfc_precharge_delay = get_xfc_precharge_delay(mode_lib,
1323                         e2e_pipe_param,
1324                         num_pipes,
1325                         pipe_idx);
1326         xfc_remote_surface_flip_latency = get_xfc_remote_surface_flip_latency(mode_lib,
1327                         e2e_pipe_param,
1328                         num_pipes,
1329                         pipe_idx);
1330         xfc_dst_y_delta_drq_limit = xfc_remote_surface_flip_latency;
1331         xfc_prefetch_margin = get_xfc_prefetch_margin(mode_lib,
1332                         e2e_pipe_param,
1333                         num_pipes,
1334                         pipe_idx);
1335
1336         // TTU - Cursor
1337         refcyc_per_req_delivery_pre_cur0 = 0.0;
1338         refcyc_per_req_delivery_cur0 = 0.0;
1339         if (src->num_cursors > 0) {
1340                 calculate_ttu_cursor(mode_lib,
1341                                 &refcyc_per_req_delivery_pre_cur0,
1342                                 &refcyc_per_req_delivery_cur0,
1343                                 refclk_freq_in_mhz,
1344                                 ref_freq_to_pix_freq,
1345                                 hscale_pixel_rate_l,
1346                                 scl->hscl_ratio,
1347                                 vratio_pre_l,
1348                                 vratio_l,
1349                                 src->cur0_src_width,
1350                                 (enum cursor_bpp)(src->cur0_bpp));
1351         }
1352
1353         refcyc_per_req_delivery_pre_cur1 = 0.0;
1354         refcyc_per_req_delivery_cur1 = 0.0;
1355         if (src->num_cursors > 1) {
1356                 calculate_ttu_cursor(mode_lib,
1357                                 &refcyc_per_req_delivery_pre_cur1,
1358                                 &refcyc_per_req_delivery_cur1,
1359                                 refclk_freq_in_mhz,
1360                                 ref_freq_to_pix_freq,
1361                                 hscale_pixel_rate_l,
1362                                 scl->hscl_ratio,
1363                                 vratio_pre_l,
1364                                 vratio_l,
1365                                 src->cur1_src_width,
1366                                 (enum cursor_bpp)(src->cur1_bpp));
1367         }
1368
1369         // TTU - Misc
1370         // all hard-coded
1371
1372         // Assignment to register structures
1373         disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line
1374         disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk
1375         ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13));
1376         disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2));
1377         disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2));
1378         disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2));
1379         disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2));
1380         disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2));
1381
1382         disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19));
1383         disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19));
1384
1385         disp_dlg_regs->refcyc_per_pte_group_vblank_l =
1386                         (unsigned int) (dst_y_per_row_vblank * (double) htotal
1387                                         * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l);
1388         ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13));
1389
1390         if (dual_plane) {
1391                 disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank
1392                                 * (double) htotal * ref_freq_to_pix_freq
1393                                 / (double) dpte_groups_per_row_ub_c);
1394                 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c
1395                                                 < (unsigned int) dml_pow(2, 13));
1396         }
1397
1398         disp_dlg_regs->refcyc_per_meta_chunk_vblank_l =
1399                         (unsigned int) (dst_y_per_row_vblank * (double) htotal
1400                                         * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l);
1401         ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13));
1402
1403         disp_dlg_regs->refcyc_per_meta_chunk_vblank_c =
1404                         disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now
1405
1406         disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal
1407                         * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l;
1408         disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal
1409                         * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l;
1410
1411         if (dual_plane) {
1412                 disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip
1413                                 * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c;
1414                 disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip
1415                                 * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c;
1416         }
1417
1418         disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l
1419                         / (double) vratio_l * dml_pow(2, 2));
1420         ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17));
1421
1422         if (dual_plane) {
1423                 disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c
1424                                 / (double) vratio_c * dml_pow(2, 2));
1425                 if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) {
1426                         dml_print("DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n",
1427                                         __func__,
1428                                         disp_dlg_regs->dst_y_per_pte_row_nom_c,
1429                                         (unsigned int) dml_pow(2, 17) - 1);
1430                 }
1431         }
1432
1433         disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l
1434                         / (double) vratio_l * dml_pow(2, 2));
1435         ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17));
1436
1437         disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now
1438
1439         disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l
1440                         / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
1441                         / (double) dpte_groups_per_row_ub_l);
1442         if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23))
1443                 disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1;
1444         disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l
1445                         / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq
1446                         / (double) meta_chunks_per_row_ub_l);
1447         if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23))
1448                 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1;
1449
1450         if (dual_plane) {
1451                 disp_dlg_regs->refcyc_per_pte_group_nom_c =
1452                                 (unsigned int) ((double) dpte_row_height_c / (double) vratio_c
1453                                                 * (double) htotal * ref_freq_to_pix_freq
1454                                                 / (double) dpte_groups_per_row_ub_c);
1455                 if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23))
1456                         disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1;
1457
1458                 // TODO: Is this the right calculation? Does htotal need to be halved?
1459                 disp_dlg_regs->refcyc_per_meta_chunk_nom_c =
1460                                 (unsigned int) ((double) meta_row_height_c / (double) vratio_c
1461                                                 * (double) htotal * ref_freq_to_pix_freq
1462                                                 / (double) meta_chunks_per_row_ub_c);
1463                 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23))
1464                         disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1;
1465         }
1466
1467         disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l,
1468                         1);
1469         disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l,
1470                         1);
1471         ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13));
1472         ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13));
1473
1474         disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c,
1475                         1);
1476         disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(refcyc_per_line_delivery_c,
1477                         1);
1478         ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13));
1479         ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13));
1480
1481         disp_dlg_regs->chunk_hdl_adjust_cur0 = 3;
1482         disp_dlg_regs->dst_y_offset_cur0 = 0;
1483         disp_dlg_regs->chunk_hdl_adjust_cur1 = 3;
1484         disp_dlg_regs->dst_y_offset_cur1 = 0;
1485
1486         disp_dlg_regs->xfc_reg_transfer_delay = xfc_transfer_delay;
1487         disp_dlg_regs->xfc_reg_precharge_delay = xfc_precharge_delay;
1488         disp_dlg_regs->xfc_reg_remote_surface_flip_latency = xfc_remote_surface_flip_latency;
1489         disp_dlg_regs->xfc_reg_prefetch_margin = dml_ceil(xfc_prefetch_margin * refclk_freq_in_mhz,
1490                         1);
1491
1492         // slave has to have this value also set to off
1493         if (src->xfc_enable && !src->xfc_slave)
1494                 disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1);
1495         else
1496                 disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off
1497
1498         disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l
1499                         * dml_pow(2, 10));
1500         disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l
1501                         * dml_pow(2, 10));
1502         disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c
1503                         * dml_pow(2, 10));
1504         disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c
1505                         * dml_pow(2, 10));
1506         disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 =
1507                         (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10));
1508         disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0
1509                         * dml_pow(2, 10));
1510         disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 =
1511                         (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10));
1512         disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1
1513                         * dml_pow(2, 10));
1514         disp_ttu_regs->qos_level_low_wm = 0;
1515         ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
1516         disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal
1517                         * ref_freq_to_pix_freq);
1518         ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));
1519
1520         disp_ttu_regs->qos_level_flip = 14;
1521         disp_ttu_regs->qos_level_fixed_l = 8;
1522         disp_ttu_regs->qos_level_fixed_c = 8;
1523         disp_ttu_regs->qos_level_fixed_cur0 = 8;
1524         disp_ttu_regs->qos_ramp_disable_l = 0;
1525         disp_ttu_regs->qos_ramp_disable_c = 0;
1526         disp_ttu_regs->qos_ramp_disable_cur0 = 0;
1527
1528         disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz;
1529         ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24));
1530
1531         print__ttu_regs_st(mode_lib, *disp_ttu_regs);
1532         print__dlg_regs_st(mode_lib, *disp_dlg_regs);
1533 }
1534
1535 void dml_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
1536                 display_dlg_regs_st *dlg_regs,
1537                 display_ttu_regs_st *ttu_regs,
1538                 display_e2e_pipe_params_st *e2e_pipe_param,
1539                 const unsigned int num_pipes,
1540                 const unsigned int pipe_idx,
1541                 const bool cstate_en,
1542                 const bool pstate_en,
1543                 const bool vm_en,
1544                 const bool ignore_viewport_pos,
1545                 const bool immediate_flip_support)
1546 {
1547         display_rq_params_st rq_param = {0};
1548         display_dlg_sys_params_st dlg_sys_param = {0};
1549
1550         // Get watermark and Tex.
1551         dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes);
1552         dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib,
1553                         e2e_pipe_param,
1554                         num_pipes);
1555         dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes);
1556         dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes);
1557         dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes);
1558         dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes);
1559         dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib,
1560                         e2e_pipe_param,
1561                         num_pipes);
1562         dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib,
1563                         e2e_pipe_param,
1564                         num_pipes);
1565         dlg_sys_param.t_srx_delay_us = mode_lib->ip.dcfclk_cstate_latency
1566                         / dlg_sys_param.deepsleep_dcfclk_mhz; // TODO: Deprecated
1567
1568         print__dlg_sys_params_st(mode_lib, dlg_sys_param);
1569
1570         // system parameter calculation done
1571
1572         dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx);
1573         dml_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe.src);
1574         dml_rq_dlg_get_dlg_params(mode_lib,
1575                         e2e_pipe_param,
1576                         num_pipes,
1577                         pipe_idx,
1578                         dlg_regs,
1579                         ttu_regs,
1580                         rq_param.dlg,
1581                         dlg_sys_param,
1582                         cstate_en,
1583                         pstate_en,
1584                         vm_en,
1585                         ignore_viewport_pos,
1586                         immediate_flip_support);
1587         dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx);
1588 }
1589
1590 void dml_rq_dlg_get_arb_params(struct display_mode_lib *mode_lib, display_arb_params_st *arb_param)
1591 {
1592         memset(arb_param, 0, sizeof(*arb_param));
1593         arb_param->max_req_outstanding = 256;
1594         arb_param->min_req_outstanding = 68;
1595         arb_param->sat_level_us = 60;
1596 }
1597
1598 void calculate_ttu_cursor(struct display_mode_lib *mode_lib,
1599                 double *refcyc_per_req_delivery_pre_cur,
1600                 double *refcyc_per_req_delivery_cur,
1601                 double refclk_freq_in_mhz,
1602                 double ref_freq_to_pix_freq,
1603                 double hscale_pixel_rate_l,
1604                 double hscl_ratio,
1605                 double vratio_pre_l,
1606                 double vratio_l,
1607                 unsigned int cur_width,
1608                 enum cursor_bpp cur_bpp)
1609 {
1610         unsigned int cur_src_width = cur_width;
1611         unsigned int cur_req_size = 0;
1612         unsigned int cur_req_width = 0;
1613         double cur_width_ub = 0.0;
1614         double cur_req_per_width = 0.0;
1615         double hactive_cur = 0.0;
1616
1617         ASSERT(cur_src_width <= 256);
1618
1619         *refcyc_per_req_delivery_pre_cur = 0.0;
1620         *refcyc_per_req_delivery_cur = 0.0;
1621         if (cur_src_width > 0) {
1622                 unsigned int cur_bit_per_pixel = 0;
1623
1624                 if (cur_bpp == dm_cur_2bit) {
1625                         cur_req_size = 64; // byte
1626                         cur_bit_per_pixel = 2;
1627                 } else { // 32bit
1628                         cur_bit_per_pixel = 32;
1629                         if (cur_src_width >= 1 && cur_src_width <= 16)
1630                                 cur_req_size = 64;
1631                         else if (cur_src_width >= 17 && cur_src_width <= 31)
1632                                 cur_req_size = 128;
1633                         else
1634                                 cur_req_size = 256;
1635                 }
1636
1637                 cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0);
1638                 cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1)
1639                                 * (double) cur_req_width;
1640                 cur_req_per_width = cur_width_ub / (double) cur_req_width;
1641                 hactive_cur = (double) cur_src_width / hscl_ratio; // FIXME: oswin to think about what to do for cursor
1642
1643                 if (vratio_pre_l <= 1.0) {
1644                         *refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq
1645                                         / (double) cur_req_per_width;
1646                 } else {
1647                         *refcyc_per_req_delivery_pre_cur = (double) refclk_freq_in_mhz
1648                                         * (double) cur_src_width / hscale_pixel_rate_l
1649                                         / (double) cur_req_per_width;
1650                 }
1651
1652                 ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13));
1653
1654                 if (vratio_l <= 1.0) {
1655                         *refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq
1656                                         / (double) cur_req_per_width;
1657                 } else {
1658                         *refcyc_per_req_delivery_cur = (double) refclk_freq_in_mhz
1659                                         * (double) cur_src_width / hscale_pixel_rate_l
1660                                         / (double) cur_req_per_width;
1661                 }
1662
1663                 dml_print("DML_DLG: %s: cur_req_width                     = %d\n",
1664                                 __func__,
1665                                 cur_req_width);
1666                 dml_print("DML_DLG: %s: cur_width_ub                      = %3.2f\n",
1667                                 __func__,
1668                                 cur_width_ub);
1669                 dml_print("DML_DLG: %s: cur_req_per_width                 = %3.2f\n",
1670                                 __func__,
1671                                 cur_req_per_width);
1672                 dml_print("DML_DLG: %s: hactive_cur                       = %3.2f\n",
1673                                 __func__,
1674                                 hactive_cur);
1675                 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur   = %3.2f\n",
1676                                 __func__,
1677                                 *refcyc_per_req_delivery_pre_cur);
1678                 dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur       = %3.2f\n",
1679                                 __func__,
1680                                 *refcyc_per_req_delivery_cur);
1681
1682                 ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13));
1683         }
1684 }
1685
1686 unsigned int dml_rq_dlg_get_calculated_vstartup(struct display_mode_lib *mode_lib,
1687                 display_e2e_pipe_params_st *e2e_pipe_param,
1688                 const unsigned int num_pipes,
1689                 const unsigned int pipe_idx)
1690 {
1691         unsigned int vstartup_pipe[DC__NUM_PIPES__MAX];
1692         bool visited[DC__NUM_PIPES__MAX];
1693         unsigned int pipe_inst = 0;
1694         unsigned int i, j, k;
1695
1696         for (k = 0; k < num_pipes; ++k)
1697                 visited[k] = false;
1698
1699         for (i = 0; i < num_pipes; i++) {
1700                 if (e2e_pipe_param[i].pipe.src.is_hsplit && !visited[i]) {
1701                         unsigned int grp = e2e_pipe_param[i].pipe.src.hsplit_grp;
1702
1703                         for (j = i; j < num_pipes; j++) {
1704                                 if (e2e_pipe_param[j].pipe.src.hsplit_grp == grp
1705                                                 && e2e_pipe_param[j].pipe.src.is_hsplit
1706                                                 && !visited[j]) {
1707                                         vstartup_pipe[j] = get_vstartup_calculated(mode_lib,
1708                                                         e2e_pipe_param,
1709                                                         num_pipes,
1710                                                         pipe_inst);
1711                                         visited[j] = true;
1712                                 }
1713                         }
1714
1715                         pipe_inst++;
1716                 }
1717
1718                 if (!visited[i]) {
1719                         vstartup_pipe[i] = get_vstartup_calculated(mode_lib,
1720                                         e2e_pipe_param,
1721                                         num_pipes,
1722                                         pipe_inst);
1723                         visited[i] = true;
1724                         pipe_inst++;
1725                 }
1726         }
1727
1728         return vstartup_pipe[pipe_idx];
1729
1730 }
1731
1732 void dml_rq_dlg_get_row_heights(struct display_mode_lib *mode_lib,
1733                 unsigned int *o_dpte_row_height,
1734                 unsigned int *o_meta_row_height,
1735                 unsigned int vp_width,
1736                 unsigned int data_pitch,
1737                 int source_format,
1738                 int tiling,
1739                 int macro_tile_size,
1740                 int source_scan,
1741                 int is_chroma)
1742 {
1743         display_data_rq_dlg_params_st rq_dlg_param;
1744         display_data_rq_misc_params_st rq_misc_param;
1745         display_data_rq_sizing_params_st rq_sizing_param;
1746
1747         get_meta_and_pte_attr(mode_lib,
1748                         &rq_dlg_param,
1749                         &rq_misc_param,
1750                         &rq_sizing_param,
1751                         vp_width,
1752                         0, // dummy
1753                         data_pitch,
1754                         0, // dummy
1755                         source_format,
1756                         tiling,
1757                         macro_tile_size,
1758                         source_scan,
1759                         is_chroma);
1760
1761         *o_dpte_row_height = rq_dlg_param.dpte_row_height;
1762         *o_meta_row_height = rq_dlg_param.meta_row_height;
1763 }