drivers/pinctrl/pinctrl-single.c

   1 /*
   2  * Generic device tree based pinctrl driver for one register per pin
   3  * type pinmux controllers
   4  *
   5  * Copyright (C) 2012 Texas Instruments, Inc.
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2. This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/module.h>
  14 #include <linux/io.h>
  15 #include <linux/slab.h>
  16 #include <linux/err.h>
  17 #include <linux/list.h>
  18 #include <linux/interrupt.h>
  19
  20 #include <linux/irqchip/chained_irq.h>
  21
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/of_address.h>
  25 #include <linux/of_irq.h>
  26
  27 #include <linux/pinctrl/pinctrl.h>
  28 #include <linux/pinctrl/pinmux.h>
  29 #include <linux/pinctrl/pinconf-generic.h>
  30
  31 #include <linux/platform_data/pinctrl-single.h>
  32
  33 #include "core.h"
  34 #include "devicetree.h"
  35 #include "pinconf.h"
  36 #include "pinmux.h"
  37
  38 #define DRIVER_NAME                     "pinctrl-single"
  39 #define PCS_OFF_DISABLED                ~0U
  40
  41 /**
  42  * struct pcs_func_vals - mux function register offset and value pair
  43  * @reg:        register virtual address
  44  * @val:        register value
  45  * @mask:       mask
  46  */
  47 struct pcs_func_vals {
  48         void __iomem *reg;
  49         unsigned val;
  50         unsigned mask;
  51 };
  52
  53 /**
  54  * struct pcs_conf_vals - pinconf parameter, pinconf register offset
  55  * and value, enable, disable, mask
  56  * @param:      config parameter
  57  * @val:        user input bits in the pinconf register
  58  * @enable:     enable bits in the pinconf register
  59  * @disable:    disable bits in the pinconf register
  60  * @mask:       mask bits in the register value
  61  */
  62 struct pcs_conf_vals {
  63         enum pin_config_param param;
  64         unsigned val;
  65         unsigned enable;
  66         unsigned disable;
  67         unsigned mask;
  68 };
  69
  70 /**
  71  * struct pcs_conf_type - pinconf property name, pinconf param pair
  72  * @name:       property name in DTS file
  73  * @param:      config parameter
  74  */
  75 struct pcs_conf_type {
  76         const char *name;
  77         enum pin_config_param param;
  78 };
  79
  80 /**
  81  * struct pcs_function - pinctrl function
  82  * @name:       pinctrl function name
  83  * @vals:       register and vals array
  84  * @nvals:      number of entries in vals array
  85  * @pgnames:    array of pingroup names the function uses
  86  * @npgnames:   number of pingroup names the function uses
  87  * @conf:       array of pin configurations
  88  * @nconfs:     number of pin configurations available
  89  * @node:       list node
  90  */
  91 struct pcs_function {
  92         const char *name;
  93         struct pcs_func_vals *vals;
  94         unsigned nvals;
  95         const char **pgnames;
  96         int npgnames;
  97         struct pcs_conf_vals *conf;
  98         int nconfs;
  99         struct list_head node;
 100 };
 101
 102 /**
 103  * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
 104  * @offset:     offset base of pins
 105  * @npins:      number pins with the same mux value of gpio function
 106  * @gpiofunc:   mux value of gpio function
 107  * @node:       list node
 108  */
 109 struct pcs_gpiofunc_range {
 110         unsigned offset;
 111         unsigned npins;
 112         unsigned gpiofunc;
 113         struct list_head node;
 114 };
 115
 116 /**
 117  * struct pcs_data - wrapper for data needed by pinctrl framework
 118  * @pa:         pindesc array
 119  * @cur:        index to current element
 120  *
 121  * REVISIT: We should be able to drop this eventually by adding
 122  * support for registering pins individually in the pinctrl
 123  * framework for those drivers that don't need a static array.
 124  */
 125 struct pcs_data {
 126         struct pinctrl_pin_desc *pa;
 127         int cur;
 128 };
 129
 130 /**
 131  * struct pcs_soc_data - SoC specific settings
 132  * @flags:      initial SoC specific PCS_FEAT_xxx values
 133  * @irq:        optional interrupt for the controller
 134  * @irq_enable_mask:    optional SoC specific interrupt enable mask
 135  * @irq_status_mask:    optional SoC specific interrupt status mask
 136  * @rearm:      optional SoC specific wake-up rearm function
 137  */
 138 struct pcs_soc_data {
 139         unsigned flags;
 140         int irq;
 141         unsigned irq_enable_mask;
 142         unsigned irq_status_mask;
 143         void (*rearm)(void);
 144 };
 145
 146 /**
 147  * struct pcs_device - pinctrl device instance
 148  * @res:        resources
 149  * @base:       virtual address of the controller
 150  * @saved_vals: saved values for the controller
 151  * @size:       size of the ioremapped area
 152  * @dev:        device entry
 153  * @np:         device tree node
 154  * @pctl:       pin controller device
 155  * @flags:      mask of PCS_FEAT_xxx values
 156  * @missing_nr_pinctrl_cells: for legacy binding, may go away
 157  * @socdata:    soc specific data
 158  * @lock:       spinlock for register access
 159  * @mutex:      mutex protecting the lists
 160  * @width:      bits per mux register
 161  * @fmask:      function register mask
 162  * @fshift:     function register shift
 163  * @foff:       value to turn mux off
 164  * @fmax:       max number of functions in fmask
 165  * @bits_per_mux: number of bits per mux
 166  * @bits_per_pin: number of bits per pin
 167  * @pins:       physical pins on the SoC
 168  * @gpiofuncs:  list of gpio functions
 169  * @irqs:       list of interrupt registers
 170  * @chip:       chip container for this instance
 171  * @domain:     IRQ domain for this instance
 172  * @desc:       pin controller descriptor
 173  * @read:       register read function to use
 174  * @write:      register write function to use
 175  */
 176 struct pcs_device {
 177         struct resource *res;
 178         void __iomem *base;
 179         void *saved_vals;
 180         unsigned size;
 181         struct device *dev;
 182         struct device_node *np;
 183         struct pinctrl_dev *pctl;
 184         unsigned flags;
 185 #define PCS_CONTEXT_LOSS_OFF    (1 << 3)
 186 #define PCS_QUIRK_SHARED_IRQ    (1 << 2)
 187 #define PCS_FEAT_IRQ            (1 << 1)
 188 #define PCS_FEAT_PINCONF        (1 << 0)
 189         struct property *missing_nr_pinctrl_cells;
 190         struct pcs_soc_data socdata;
 191         raw_spinlock_t lock;
 192         struct mutex mutex;
 193         unsigned width;
 194         unsigned fmask;
 195         unsigned fshift;
 196         unsigned foff;
 197         unsigned fmax;
 198         bool bits_per_mux;
 199         unsigned bits_per_pin;
 200         struct pcs_data pins;
 201         struct list_head gpiofuncs;
 202         struct list_head irqs;
 203         struct irq_chip chip;
 204         struct irq_domain *domain;
 205         struct pinctrl_desc desc;
 206         unsigned (*read)(void __iomem *reg);
 207         void (*write)(unsigned val, void __iomem *reg);
 208 };
 209
 210 #define PCS_QUIRK_HAS_SHARED_IRQ        (pcs->flags & PCS_QUIRK_SHARED_IRQ)
 211 #define PCS_HAS_IRQ             (pcs->flags & PCS_FEAT_IRQ)
 212 #define PCS_HAS_PINCONF         (pcs->flags & PCS_FEAT_PINCONF)
 213
 214 static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
 215                            unsigned long *config);
 216 static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
 217                            unsigned long *configs, unsigned num_configs);
 218
 219 static enum pin_config_param pcs_bias[] = {
 220         PIN_CONFIG_BIAS_PULL_DOWN,
 221         PIN_CONFIG_BIAS_PULL_UP,
 222 };
 223
 224 /*
 225  * This lock class tells lockdep that irqchip core that this single
 226  * pinctrl can be in a different category than its parents, so it won't
 227  * report false recursion.
 228  */
 229 static struct lock_class_key pcs_lock_class;
 230
 231 /* Class for the IRQ request mutex */
 232 static struct lock_class_key pcs_request_class;
 233
 234 /*
 235  * REVISIT: Reads and writes could eventually use regmap or something
 236  * generic. But at least on omaps, some mux registers are performance
 237  * critical as they may need to be remuxed every time before and after
 238  * idle. Adding tests for register access width for every read and
 239  * write like regmap is doing is not desired, and caching the registers
 240  * does not help in this case.
 241  */
 242
 243 static unsigned __maybe_unused pcs_readb(void __iomem *reg)
 244 {
 245         return readb(reg);
 246 }
 247
 248 static unsigned __maybe_unused pcs_readw(void __iomem *reg)
 249 {
 250         return readw(reg);
 251 }
 252
 253 static unsigned __maybe_unused pcs_readl(void __iomem *reg)
 254 {
 255         return readl(reg);
 256 }
 257
 258 static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
 259 {
 260         writeb(val, reg);
 261 }
 262
 263 static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
 264 {
 265         writew(val, reg);
 266 }
 267
 268 static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
 269 {
 270         writel(val, reg);
 271 }
 272
 273 static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
 274                                         struct seq_file *s,
 275                                         unsigned pin)
 276 {
 277         struct pcs_device *pcs;
 278         unsigned val, mux_bytes;
 279         unsigned long offset;
 280         size_t pa;
 281
 282         pcs = pinctrl_dev_get_drvdata(pctldev);
 283
 284         mux_bytes = pcs->width / BITS_PER_BYTE;
 285         offset = pin * mux_bytes;
 286         val = pcs->read(pcs->base + offset);
 287         pa = pcs->res->start + offset;
 288
 289         seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
 290 }
 291
 292 static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
 293                                 struct pinctrl_map *map, unsigned num_maps)
 294 {
 295         struct pcs_device *pcs;
 296
 297         pcs = pinctrl_dev_get_drvdata(pctldev);
 298         devm_kfree(pcs->dev, map);
 299 }
 300
 301 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
 302                                 struct device_node *np_config,
 303                                 struct pinctrl_map **map, unsigned *num_maps);
 304
 305 static const struct pinctrl_ops pcs_pinctrl_ops = {
 306         .get_groups_count = pinctrl_generic_get_group_count,
 307         .get_group_name = pinctrl_generic_get_group_name,
 308         .get_group_pins = pinctrl_generic_get_group_pins,
 309         .pin_dbg_show = pcs_pin_dbg_show,
 310         .dt_node_to_map = pcs_dt_node_to_map,
 311         .dt_free_map = pcs_dt_free_map,
 312 };
 313
 314 static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
 315                             struct pcs_function **func)
 316 {
 317         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 318         struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
 319         const struct pinctrl_setting_mux *setting;
 320         struct function_desc *function;
 321         unsigned fselector;
 322
 323         /* If pin is not described in DTS & enabled, mux_setting is NULL. */
 324         setting = pdesc->mux_setting;
 325         if (!setting)
 326                 return -ENOTSUPP;
 327         fselector = setting->func;
 328         function = pinmux_generic_get_function(pctldev, fselector);
 329         *func = function->data;
 330         if (!(*func)) {
 331                 dev_err(pcs->dev, "%s could not find function%i\n",
 332                         __func__, fselector);
 333                 return -ENOTSUPP;
 334         }
 335         return 0;
 336 }
 337
 338 static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
 339         unsigned group)
 340 {
 341         struct pcs_device *pcs;
 342         struct function_desc *function;
 343         struct pcs_function *func;
 344         int i;
 345
 346         pcs = pinctrl_dev_get_drvdata(pctldev);
 347         /* If function mask is null, needn't enable it. */
 348         if (!pcs->fmask)
 349                 return 0;
 350         function = pinmux_generic_get_function(pctldev, fselector);
 351         func = function->data;
 352         if (!func)
 353                 return -EINVAL;
 354
 355         dev_dbg(pcs->dev, "enabling %s function%i\n",
 356                 func->name, fselector);
 357
 358         for (i = 0; i < func->nvals; i++) {
 359                 struct pcs_func_vals *vals;
 360                 unsigned long flags;
 361                 unsigned val, mask;
 362
 363                 vals = &func->vals[i];
 364                 raw_spin_lock_irqsave(&pcs->lock, flags);
 365                 val = pcs->read(vals->reg);
 366
 367                 if (pcs->bits_per_mux)
 368                         mask = vals->mask;
 369                 else
 370                         mask = pcs->fmask;
 371
 372                 val &= ~mask;
 373                 val |= (vals->val & mask);
 374                 pcs->write(val, vals->reg);
 375                 raw_spin_unlock_irqrestore(&pcs->lock, flags);
 376         }
 377
 378         return 0;
 379 }
 380
 381 static int pcs_request_gpio(struct pinctrl_dev *pctldev,
 382                             struct pinctrl_gpio_range *range, unsigned pin)
 383 {
 384         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 385         struct pcs_gpiofunc_range *frange = NULL;
 386         struct list_head *pos, *tmp;
 387         int mux_bytes = 0;
 388         unsigned data;
 389
 390         /* If function mask is null, return directly. */
 391         if (!pcs->fmask)
 392                 return -ENOTSUPP;
 393
 394         list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
 395                 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
 396                 if (pin >= frange->offset + frange->npins
 397                         || pin < frange->offset)
 398                         continue;
 399                 mux_bytes = pcs->width / BITS_PER_BYTE;
 400
 401                 if (pcs->bits_per_mux) {
 402                         int byte_num, offset, pin_shift;
 403
 404                         byte_num = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
 405                         offset = (byte_num / mux_bytes) * mux_bytes;
 406                         pin_shift = pin % (pcs->width / pcs->bits_per_pin) *
 407                                     pcs->bits_per_pin;
 408
 409                         data = pcs->read(pcs->base + offset);
 410                         data &= ~(pcs->fmask << pin_shift);
 411                         data |= frange->gpiofunc << pin_shift;
 412                         pcs->write(data, pcs->base + offset);
 413                 } else {
 414                         data = pcs->read(pcs->base + pin * mux_bytes);
 415                         data &= ~pcs->fmask;
 416                         data |= frange->gpiofunc;
 417                         pcs->write(data, pcs->base + pin * mux_bytes);
 418                 }
 419                 break;
 420         }
 421         return 0;
 422 }
 423
 424 static const struct pinmux_ops pcs_pinmux_ops = {
 425         .get_functions_count = pinmux_generic_get_function_count,
 426         .get_function_name = pinmux_generic_get_function_name,
 427         .get_function_groups = pinmux_generic_get_function_groups,
 428         .set_mux = pcs_set_mux,
 429         .gpio_request_enable = pcs_request_gpio,
 430 };
 431
 432 /* Clear BIAS value */
 433 static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
 434 {
 435         unsigned long config;
 436         int i;
 437         for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
 438                 config = pinconf_to_config_packed(pcs_bias[i], 0);
 439                 pcs_pinconf_set(pctldev, pin, &config, 1);
 440         }
 441 }
 442
 443 /*
 444  * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
 445  * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
 446  */
 447 static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
 448 {
 449         unsigned long config;
 450         int i;
 451
 452         for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
 453                 config = pinconf_to_config_packed(pcs_bias[i], 0);
 454                 if (!pcs_pinconf_get(pctldev, pin, &config))
 455                         goto out;
 456         }
 457         return true;
 458 out:
 459         return false;
 460 }
 461
 462 static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
 463                                 unsigned pin, unsigned long *config)
 464 {
 465         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 466         struct pcs_function *func;
 467         enum pin_config_param param;
 468         unsigned offset = 0, data = 0, i, j, ret;
 469
 470         ret = pcs_get_function(pctldev, pin, &func);
 471         if (ret)
 472                 return ret;
 473
 474         for (i = 0; i < func->nconfs; i++) {
 475                 param = pinconf_to_config_param(*config);
 476                 if (param == PIN_CONFIG_BIAS_DISABLE) {
 477                         if (pcs_pinconf_bias_disable(pctldev, pin)) {
 478                                 *config = 0;
 479                                 return 0;
 480                         } else {
 481                                 return -ENOTSUPP;
 482                         }
 483                 } else if (param != func->conf[i].param) {
 484                         continue;
 485                 }
 486
 487                 offset = pin * (pcs->width / BITS_PER_BYTE);
 488                 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
 489                 switch (func->conf[i].param) {
 490                 /* 4 parameters */
 491                 case PIN_CONFIG_BIAS_PULL_DOWN:
 492                 case PIN_CONFIG_BIAS_PULL_UP:
 493                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 494                         if ((data != func->conf[i].enable) ||
 495                             (data == func->conf[i].disable))
 496                                 return -ENOTSUPP;
 497                         *config = 0;
 498                         break;
 499                 /* 2 parameters */
 500                 case PIN_CONFIG_INPUT_SCHMITT:
 501                         for (j = 0; j < func->nconfs; j++) {
 502                                 switch (func->conf[j].param) {
 503                                 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 504                                         if (data != func->conf[j].enable)
 505                                                 return -ENOTSUPP;
 506                                         break;
 507                                 default:
 508                                         break;
 509                                 }
 510                         }
 511                         *config = data;
 512                         break;
 513                 case PIN_CONFIG_DRIVE_STRENGTH:
 514                 case PIN_CONFIG_SLEW_RATE:
 515                 case PIN_CONFIG_LOW_POWER_MODE:
 516                 default:
 517                         *config = data;
 518                         break;
 519                 }
 520                 return 0;
 521         }
 522         return -ENOTSUPP;
 523 }
 524
 525 static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
 526                                 unsigned pin, unsigned long *configs,
 527                                 unsigned num_configs)
 528 {
 529         struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
 530         struct pcs_function *func;
 531         unsigned offset = 0, shift = 0, i, data, ret;
 532         u32 arg;
 533         int j;
 534
 535         ret = pcs_get_function(pctldev, pin, &func);
 536         if (ret)
 537                 return ret;
 538
 539         for (j = 0; j < num_configs; j++) {
 540                 for (i = 0; i < func->nconfs; i++) {
 541                         if (pinconf_to_config_param(configs[j])
 542                                 != func->conf[i].param)
 543                                 continue;
 544
 545                         offset = pin * (pcs->width / BITS_PER_BYTE);
 546                         data = pcs->read(pcs->base + offset);
 547                         arg = pinconf_to_config_argument(configs[j]);
 548                         switch (func->conf[i].param) {
 549                         /* 2 parameters */
 550                         case PIN_CONFIG_INPUT_SCHMITT:
 551                         case PIN_CONFIG_DRIVE_STRENGTH:
 552                         case PIN_CONFIG_SLEW_RATE:
 553                         case PIN_CONFIG_LOW_POWER_MODE:
 554                                 shift = ffs(func->conf[i].mask) - 1;
 555                                 data &= ~func->conf[i].mask;
 556                                 data |= (arg << shift) & func->conf[i].mask;
 557                                 break;
 558                         /* 4 parameters */
 559                         case PIN_CONFIG_BIAS_DISABLE:
 560                                 pcs_pinconf_clear_bias(pctldev, pin);
 561                                 break;
 562                         case PIN_CONFIG_BIAS_PULL_DOWN:
 563                         case PIN_CONFIG_BIAS_PULL_UP:
 564                                 if (arg)
 565                                         pcs_pinconf_clear_bias(pctldev, pin);
 566                                 fallthrough;
 567                         case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 568                                 data &= ~func->conf[i].mask;
 569                                 if (arg)
 570                                         data |= func->conf[i].enable;
 571                                 else
 572                                         data |= func->conf[i].disable;
 573                                 break;
 574                         default:
 575                                 return -ENOTSUPP;
 576                         }
 577                         pcs->write(data, pcs->base + offset);
 578
 579                         break;
 580                 }
 581                 if (i >= func->nconfs)
 582                         return -ENOTSUPP;
 583         } /* for each config */
 584
 585         return 0;
 586 }
 587
 588 static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
 589                                 unsigned group, unsigned long *config)
 590 {
 591         const unsigned *pins;
 592         unsigned npins, old = 0;
 593         int i, ret;
 594
 595         ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
 596         if (ret)
 597                 return ret;
 598         for (i = 0; i < npins; i++) {
 599                 if (pcs_pinconf_get(pctldev, pins[i], config))
 600                         return -ENOTSUPP;
 601                 /* configs do not match between two pins */
 602                 if (i && (old != *config))
 603                         return -ENOTSUPP;
 604                 old = *config;
 605         }
 606         return 0;
 607 }
 608
 609 static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
 610                                 unsigned group, unsigned long *configs,
 611                                 unsigned num_configs)
 612 {
 613         const unsigned *pins;
 614         unsigned npins;
 615         int i, ret;
 616
 617         ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
 618         if (ret)
 619                 return ret;
 620         for (i = 0; i < npins; i++) {
 621                 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
 622                         return -ENOTSUPP;
 623         }
 624         return 0;
 625 }
 626
 627 static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
 628                                 struct seq_file *s, unsigned pin)
 629 {
 630 }
 631
 632 static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
 633                                 struct seq_file *s, unsigned selector)
 634 {
 635 }
 636
 637 static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
 638                                         struct seq_file *s,
 639                                         unsigned long config)
 640 {
 641         pinconf_generic_dump_config(pctldev, s, config);
 642 }
 643
 644 static const struct pinconf_ops pcs_pinconf_ops = {
 645         .pin_config_get = pcs_pinconf_get,
 646         .pin_config_set = pcs_pinconf_set,
 647         .pin_config_group_get = pcs_pinconf_group_get,
 648         .pin_config_group_set = pcs_pinconf_group_set,
 649         .pin_config_dbg_show = pcs_pinconf_dbg_show,
 650         .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
 651         .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
 652         .is_generic = true,
 653 };
 654
 655 /**
 656  * pcs_add_pin() - add a pin to the static per controller pin array
 657  * @pcs: pcs driver instance
 658  * @offset: register offset from base
 659  * @pin_pos: unused
 660  */
 661 static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
 662                 unsigned pin_pos)
 663 {
 664         struct pcs_soc_data *pcs_soc = &pcs->socdata;
 665         struct pinctrl_pin_desc *pin;
 666         int i;
 667
 668         i = pcs->pins.cur;
 669         if (i >= pcs->desc.npins) {
 670                 dev_err(pcs->dev, "too many pins, max %i\n",
 671                         pcs->desc.npins);
 672                 return -ENOMEM;
 673         }
 674
 675         if (pcs_soc->irq_enable_mask) {
 676                 unsigned val;
 677
 678                 val = pcs->read(pcs->base + offset);
 679                 if (val & pcs_soc->irq_enable_mask) {
 680                         dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
 681                                 (unsigned long)pcs->res->start + offset, val);
 682                         val &= ~pcs_soc->irq_enable_mask;
 683                         pcs->write(val, pcs->base + offset);
 684                 }
 685         }
 686
 687         pin = &pcs->pins.pa[i];
 688         pin->number = i;
 689         pcs->pins.cur++;
 690
 691         return i;
 692 }
 693
 694 /**
 695  * pcs_allocate_pin_table() - adds all the pins for the pinctrl driver
 696  * @pcs: pcs driver instance
 697  *
 698  * In case of errors, resources are freed in pcs_free_resources.
 699  *
 700  * If your hardware needs holes in the address space, then just set
 701  * up multiple driver instances.
 702  */
 703 static int pcs_allocate_pin_table(struct pcs_device *pcs)
 704 {
 705         int mux_bytes, nr_pins, i;
 706         int num_pins_in_register = 0;
 707
 708         mux_bytes = pcs->width / BITS_PER_BYTE;
 709
 710         if (pcs->bits_per_mux) {
 711                 pcs->bits_per_pin = fls(pcs->fmask);
 712                 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
 713                 num_pins_in_register = pcs->width / pcs->bits_per_pin;
 714         } else {
 715                 nr_pins = pcs->size / mux_bytes;
 716         }
 717
 718         dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
 719         pcs->pins.pa = devm_kcalloc(pcs->dev,
 720                                 nr_pins, sizeof(*pcs->pins.pa),
 721                                 GFP_KERNEL);
 722         if (!pcs->pins.pa)
 723                 return -ENOMEM;
 724
 725         pcs->desc.pins = pcs->pins.pa;
 726         pcs->desc.npins = nr_pins;
 727
 728         for (i = 0; i < pcs->desc.npins; i++) {
 729                 unsigned offset;
 730                 int res;
 731                 int byte_num;
 732                 int pin_pos = 0;
 733
 734                 if (pcs->bits_per_mux) {
 735                         byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
 736                         offset = (byte_num / mux_bytes) * mux_bytes;
 737                         pin_pos = i % num_pins_in_register;
 738                 } else {
 739                         offset = i * mux_bytes;
 740                 }
 741                 res = pcs_add_pin(pcs, offset, pin_pos);
 742                 if (res < 0) {
 743                         dev_err(pcs->dev, "error adding pins: %i\n", res);
 744                         return res;
 745                 }
 746         }
 747
 748         return 0;
 749 }
 750
 751 /**
 752  * pcs_add_function() - adds a new function to the function list
 753  * @pcs: pcs driver instance
 754  * @fcn: new function allocated
 755  * @name: name of the function
 756  * @vals: array of mux register value pairs used by the function
 757  * @nvals: number of mux register value pairs
 758  * @pgnames: array of pingroup names for the function
 759  * @npgnames: number of pingroup names
 760  *
 761  * Caller must take care of locking.
 762  */
 763 static int pcs_add_function(struct pcs_device *pcs,
 764                             struct pcs_function **fcn,
 765                             const char *name,
 766                             struct pcs_func_vals *vals,
 767                             unsigned int nvals,
 768                             const char **pgnames,
 769                             unsigned int npgnames)
 770 {
 771         struct pcs_function *function;
 772         int selector;
 773
 774         function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
 775         if (!function)
 776                 return -ENOMEM;
 777
 778         function->vals = vals;
 779         function->nvals = nvals;
 780
 781         selector = pinmux_generic_add_function(pcs->pctl, name,
 782                                                pgnames, npgnames,
 783                                                function);
 784         if (selector < 0) {
 785                 devm_kfree(pcs->dev, function);
 786                 *fcn = NULL;
 787         } else {
 788                 *fcn = function;
 789         }
 790
 791         return selector;
 792 }
 793
 794 /**
 795  * pcs_get_pin_by_offset() - get a pin index based on the register offset
 796  * @pcs: pcs driver instance
 797  * @offset: register offset from the base
 798  *
 799  * Note that this is OK as long as the pins are in a static array.
 800  */
 801 static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
 802 {
 803         unsigned index;
 804
 805         if (offset >= pcs->size) {
 806                 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
 807                         offset, pcs->size);
 808                 return -EINVAL;
 809         }
 810
 811         if (pcs->bits_per_mux)
 812                 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
 813         else
 814                 index = offset / (pcs->width / BITS_PER_BYTE);
 815
 816         return index;
 817 }
 818
 819 /*
 820  * check whether data matches enable bits or disable bits
 821  * Return value: 1 for matching enable bits, 0 for matching disable bits,
 822  *               and negative value for matching failure.
 823  */
 824 static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
 825 {
 826         int ret = -EINVAL;
 827
 828         if (data == enable)
 829                 ret = 1;
 830         else if (data == disable)
 831                 ret = 0;
 832         return ret;
 833 }
 834
 835 static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
 836                        unsigned value, unsigned enable, unsigned disable,
 837                        unsigned mask)
 838 {
 839         (*conf)->param = param;
 840         (*conf)->val = value;
 841         (*conf)->enable = enable;
 842         (*conf)->disable = disable;
 843         (*conf)->mask = mask;
 844         (*conf)++;
 845 }
 846
 847 static void add_setting(unsigned long **setting, enum pin_config_param param,
 848                         unsigned arg)
 849 {
 850         **setting = pinconf_to_config_packed(param, arg);
 851         (*setting)++;
 852 }
 853
 854 /* add pinconf setting with 2 parameters */
 855 static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
 856                           const char *name, enum pin_config_param param,
 857                           struct pcs_conf_vals **conf, unsigned long **settings)
 858 {
 859         unsigned value[2], shift;
 860         int ret;
 861
 862         ret = of_property_read_u32_array(np, name, value, 2);
 863         if (ret)
 864                 return;
 865         /* set value & mask */
 866         value[0] &= value[1];
 867         shift = ffs(value[1]) - 1;
 868         /* skip enable & disable */
 869         add_config(conf, param, value[0], 0, 0, value[1]);
 870         add_setting(settings, param, value[0] >> shift);
 871 }
 872
 873 /* add pinconf setting with 4 parameters */
 874 static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
 875                           const char *name, enum pin_config_param param,
 876                           struct pcs_conf_vals **conf, unsigned long **settings)
 877 {
 878         unsigned value[4];
 879         int ret;
 880
 881         /* value to set, enable, disable, mask */
 882         ret = of_property_read_u32_array(np, name, value, 4);
 883         if (ret)
 884                 return;
 885         if (!value[3]) {
 886                 dev_err(pcs->dev, "mask field of the property can't be 0\n");
 887                 return;
 888         }
 889         value[0] &= value[3];
 890         value[1] &= value[3];
 891         value[2] &= value[3];
 892         ret = pcs_config_match(value[0], value[1], value[2]);
 893         if (ret < 0)
 894                 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
 895         add_config(conf, param, value[0], value[1], value[2], value[3]);
 896         add_setting(settings, param, ret);
 897 }
 898
 899 static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
 900                              struct pcs_function *func,
 901                              struct pinctrl_map **map)
 902
 903 {
 904         struct pinctrl_map *m = *map;
 905         int i = 0, nconfs = 0;
 906         unsigned long *settings = NULL, *s = NULL;
 907         struct pcs_conf_vals *conf = NULL;
 908         static const struct pcs_conf_type prop2[] = {
 909                 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
 910                 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
 911                 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
 912                 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
 913         };
 914         static const struct pcs_conf_type prop4[] = {
 915                 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
 916                 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
 917                 { "pinctrl-single,input-schmitt-enable",
 918                         PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
 919         };
 920
 921         /* If pinconf isn't supported, don't parse properties in below. */
 922         if (!PCS_HAS_PINCONF)
 923                 return -ENOTSUPP;
 924
 925         /* cacluate how much properties are supported in current node */
 926         for (i = 0; i < ARRAY_SIZE(prop2); i++) {
 927                 if (of_find_property(np, prop2[i].name, NULL))
 928                         nconfs++;
 929         }
 930         for (i = 0; i < ARRAY_SIZE(prop4); i++) {
 931                 if (of_find_property(np, prop4[i].name, NULL))
 932                         nconfs++;
 933         }
 934         if (!nconfs)
 935                 return -ENOTSUPP;
 936
 937         func->conf = devm_kcalloc(pcs->dev,
 938                                   nconfs, sizeof(struct pcs_conf_vals),
 939                                   GFP_KERNEL);
 940         if (!func->conf)
 941                 return -ENOMEM;
 942         func->nconfs = nconfs;
 943         conf = &(func->conf[0]);
 944         m++;
 945         settings = devm_kcalloc(pcs->dev, nconfs, sizeof(unsigned long),
 946                                 GFP_KERNEL);
 947         if (!settings)
 948                 return -ENOMEM;
 949         s = &settings[0];
 950
 951         for (i = 0; i < ARRAY_SIZE(prop2); i++)
 952                 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
 953                               &conf, &s);
 954         for (i = 0; i < ARRAY_SIZE(prop4); i++)
 955                 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
 956                               &conf, &s);
 957         m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
 958         m->data.configs.group_or_pin = np->name;
 959         m->data.configs.configs = settings;
 960         m->data.configs.num_configs = nconfs;
 961         return 0;
 962 }
 963
 964 /**
 965  * pcs_parse_one_pinctrl_entry() - parses a device tree mux entry
 966  * @pcs: pinctrl driver instance
 967  * @np: device node of the mux entry
 968  * @map: map entry
 969  * @num_maps: number of map
 970  * @pgnames: pingroup names
 971  *
 972  * Note that this binding currently supports only sets of one register + value.
 973  *
 974  * Also note that this driver tries to avoid understanding pin and function
 975  * names because of the extra bloat they would cause especially in the case of
 976  * a large number of pins. This driver just sets what is specified for the board
 977  * in the .dts file. Further user space debugging tools can be developed to
 978  * decipher the pin and function names using debugfs.
 979  *
 980  * If you are concerned about the boot time, set up the static pins in
 981  * the bootloader, and only set up selected pins as device tree entries.
 982  */
 983 static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
 984                                                 struct device_node *np,
 985                                                 struct pinctrl_map **map,
 986                                                 unsigned *num_maps,
 987                                                 const char **pgnames)
 988 {
 989         const char *name = "pinctrl-single,pins";
 990         struct pcs_func_vals *vals;
 991         int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
 992         struct pcs_function *function = NULL;
 993
 994         rows = pinctrl_count_index_with_args(np, name);
 995         if (rows <= 0) {
 996                 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
 997                 return -EINVAL;
 998         }
 999
1000         vals = devm_kcalloc(pcs->dev, rows, sizeof(*vals), GFP_KERNEL);
1001         if (!vals)
1002                 return -ENOMEM;
1003
1004         pins = devm_kcalloc(pcs->dev, rows, sizeof(*pins), GFP_KERNEL);
1005         if (!pins)
1006                 goto free_vals;
1007
1008         for (i = 0; i < rows; i++) {
1009                 struct of_phandle_args pinctrl_spec;
1010                 unsigned int offset;
1011                 int pin;
1012
1013                 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1014                 if (res)
1015                         return res;
1016
1017                 if (pinctrl_spec.args_count < 2) {
1018                         dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1019                                 pinctrl_spec.args_count);
1020                         break;
1021                 }
1022
1023                 offset = pinctrl_spec.args[0];
1024                 vals[found].reg = pcs->base + offset;
1025
1026                 switch (pinctrl_spec.args_count) {
1027                 case 2:
1028                         vals[found].val = pinctrl_spec.args[1];
1029                         break;
1030                 case 3:
1031                         vals[found].val = (pinctrl_spec.args[1] | pinctrl_spec.args[2]);
1032                         break;
1033                 }
1034
1035                 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x\n",
1036                         pinctrl_spec.np, offset, pinctrl_spec.args[1]);
1037
1038                 pin = pcs_get_pin_by_offset(pcs, offset);
1039                 if (pin < 0) {
1040                         dev_err(pcs->dev,
1041                                 "could not add functions for %pOFn %ux\n",
1042                                 np, offset);
1043                         break;
1044                 }
1045                 pins[found++] = pin;
1046         }
1047
1048         pgnames[0] = np->name;
1049         mutex_lock(&pcs->mutex);
1050         fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1051                                 pgnames, 1);
1052         if (fsel < 0) {
1053                 res = fsel;
1054                 goto free_pins;
1055         }
1056
1057         gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1058         if (gsel < 0) {
1059                 res = gsel;
1060                 goto free_function;
1061         }
1062
1063         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1064         (*map)->data.mux.group = np->name;
1065         (*map)->data.mux.function = np->name;
1066
1067         if (PCS_HAS_PINCONF && function) {
1068                 res = pcs_parse_pinconf(pcs, np, function, map);
1069                 if (res == 0)
1070                         *num_maps = 2;
1071                 else if (res == -ENOTSUPP)
1072                         *num_maps = 1;
1073                 else
1074                         goto free_pingroups;
1075         } else {
1076                 *num_maps = 1;
1077         }
1078         mutex_unlock(&pcs->mutex);
1079
1080         return 0;
1081
1082 free_pingroups:
1083         pinctrl_generic_remove_group(pcs->pctl, gsel);
1084         *num_maps = 1;
1085 free_function:
1086         pinmux_generic_remove_function(pcs->pctl, fsel);
1087 free_pins:
1088         mutex_unlock(&pcs->mutex);
1089         devm_kfree(pcs->dev, pins);
1090
1091 free_vals:
1092         devm_kfree(pcs->dev, vals);
1093
1094         return res;
1095 }
1096
1097 static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1098                                                 struct device_node *np,
1099                                                 struct pinctrl_map **map,
1100                                                 unsigned *num_maps,
1101                                                 const char **pgnames)
1102 {
1103         const char *name = "pinctrl-single,bits";
1104         struct pcs_func_vals *vals;
1105         int rows, *pins, found = 0, res = -ENOMEM, i, fsel, gsel;
1106         int npins_in_row;
1107         struct pcs_function *function = NULL;
1108
1109         rows = pinctrl_count_index_with_args(np, name);
1110         if (rows <= 0) {
1111                 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1112                 return -EINVAL;
1113         }
1114
1115         npins_in_row = pcs->width / pcs->bits_per_pin;
1116
1117         vals = devm_kzalloc(pcs->dev,
1118                             array3_size(rows, npins_in_row, sizeof(*vals)),
1119                             GFP_KERNEL);
1120         if (!vals)
1121                 return -ENOMEM;
1122
1123         pins = devm_kzalloc(pcs->dev,
1124                             array3_size(rows, npins_in_row, sizeof(*pins)),
1125                             GFP_KERNEL);
1126         if (!pins)
1127                 goto free_vals;
1128
1129         for (i = 0; i < rows; i++) {
1130                 struct of_phandle_args pinctrl_spec;
1131                 unsigned offset, val;
1132                 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1133                 unsigned pin_num_from_lsb;
1134                 int pin;
1135
1136                 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1137                 if (res)
1138                         return res;
1139
1140                 if (pinctrl_spec.args_count < 3) {
1141                         dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1142                                 pinctrl_spec.args_count);
1143                         break;
1144                 }
1145
1146                 /* Index plus two value cells */
1147                 offset = pinctrl_spec.args[0];
1148                 val = pinctrl_spec.args[1];
1149                 mask = pinctrl_spec.args[2];
1150
1151                 dev_dbg(pcs->dev, "%pOFn index: 0x%x value: 0x%x mask: 0x%x\n",
1152                         pinctrl_spec.np, offset, val, mask);
1153
1154                 /* Parse pins in each row from LSB */
1155                 while (mask) {
1156                         bit_pos = __ffs(mask);
1157                         pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1158                         mask_pos = ((pcs->fmask) << bit_pos);
1159                         val_pos = val & mask_pos;
1160                         submask = mask & mask_pos;
1161
1162                         if ((mask & mask_pos) == 0) {
1163                                 dev_err(pcs->dev,
1164                                         "Invalid mask for %pOFn at 0x%x\n",
1165                                         np, offset);
1166                                 break;
1167                         }
1168
1169                         mask &= ~mask_pos;
1170
1171                         if (submask != mask_pos) {
1172                                 dev_warn(pcs->dev,
1173                                                 "Invalid submask 0x%x for %pOFn at 0x%x\n",
1174                                                 submask, np, offset);
1175                                 continue;
1176                         }
1177
1178                         vals[found].mask = submask;
1179                         vals[found].reg = pcs->base + offset;
1180                         vals[found].val = val_pos;
1181
1182                         pin = pcs_get_pin_by_offset(pcs, offset);
1183                         if (pin < 0) {
1184                                 dev_err(pcs->dev,
1185                                         "could not add functions for %pOFn %ux\n",
1186                                         np, offset);
1187                                 break;
1188                         }
1189                         pins[found++] = pin + pin_num_from_lsb;
1190                 }
1191         }
1192
1193         pgnames[0] = np->name;
1194         mutex_lock(&pcs->mutex);
1195         fsel = pcs_add_function(pcs, &function, np->name, vals, found,
1196                                 pgnames, 1);
1197         if (fsel < 0) {
1198                 res = fsel;
1199                 goto free_pins;
1200         }
1201
1202         gsel = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1203         if (gsel < 0) {
1204                 res = gsel;
1205                 goto free_function;
1206         }
1207
1208         (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1209         (*map)->data.mux.group = np->name;
1210         (*map)->data.mux.function = np->name;
1211
1212         if (PCS_HAS_PINCONF) {
1213                 dev_err(pcs->dev, "pinconf not supported\n");
1214                 goto free_pingroups;
1215         }
1216
1217         *num_maps = 1;
1218         mutex_unlock(&pcs->mutex);
1219
1220         return 0;
1221
1222 free_pingroups:
1223         pinctrl_generic_remove_group(pcs->pctl, gsel);
1224         *num_maps = 1;
1225 free_function:
1226         pinmux_generic_remove_function(pcs->pctl, fsel);
1227 free_pins:
1228         mutex_unlock(&pcs->mutex);
1229         devm_kfree(pcs->dev, pins);
1230
1231 free_vals:
1232         devm_kfree(pcs->dev, vals);
1233
1234         return res;
1235 }
1236 /**
1237  * pcs_dt_node_to_map() - allocates and parses pinctrl maps
1238  * @pctldev: pinctrl instance
1239  * @np_config: device tree pinmux entry
1240  * @map: array of map entries
1241  * @num_maps: number of maps
1242  */
1243 static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1244                                 struct device_node *np_config,
1245                                 struct pinctrl_map **map, unsigned *num_maps)
1246 {
1247         struct pcs_device *pcs;
1248         const char **pgnames;
1249         int ret;
1250
1251         pcs = pinctrl_dev_get_drvdata(pctldev);
1252
1253         /* create 2 maps. One is for pinmux, and the other is for pinconf. */
1254         *map = devm_kcalloc(pcs->dev, 2, sizeof(**map), GFP_KERNEL);
1255         if (!*map)
1256                 return -ENOMEM;
1257
1258         *num_maps = 0;
1259
1260         pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1261         if (!pgnames) {
1262                 ret = -ENOMEM;
1263                 goto free_map;
1264         }
1265
1266         if (pcs->bits_per_mux) {
1267                 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1268                                 num_maps, pgnames);
1269                 if (ret < 0) {
1270                         dev_err(pcs->dev, "no pins entries for %pOFn\n",
1271                                 np_config);
1272                         goto free_pgnames;
1273                 }
1274         } else {
1275                 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1276                                 num_maps, pgnames);
1277                 if (ret < 0) {
1278                         dev_err(pcs->dev, "no pins entries for %pOFn\n",
1279                                 np_config);
1280                         goto free_pgnames;
1281                 }
1282         }
1283
1284         return 0;
1285
1286 free_pgnames:
1287         devm_kfree(pcs->dev, pgnames);
1288 free_map:
1289         devm_kfree(pcs->dev, *map);
1290
1291         return ret;
1292 }
1293
1294 /**
1295  * pcs_irq_free() - free interrupt
1296  * @pcs: pcs driver instance
1297  */
1298 static void pcs_irq_free(struct pcs_device *pcs)
1299 {
1300         struct pcs_soc_data *pcs_soc = &pcs->socdata;
1301
1302         if (pcs_soc->irq < 0)
1303                 return;
1304
1305         if (pcs->domain)
1306                 irq_domain_remove(pcs->domain);
1307
1308         if (PCS_QUIRK_HAS_SHARED_IRQ)
1309                 free_irq(pcs_soc->irq, pcs_soc);
1310         else
1311                 irq_set_chained_handler(pcs_soc->irq, NULL);
1312 }
1313
1314 /**
1315  * pcs_free_resources() - free memory used by this driver
1316  * @pcs: pcs driver instance
1317  */
1318 static void pcs_free_resources(struct pcs_device *pcs)
1319 {
1320         pcs_irq_free(pcs);
1321         pinctrl_unregister(pcs->pctl);
1322
1323 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1324         if (pcs->missing_nr_pinctrl_cells)
1325                 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);
1326 #endif
1327 }
1328
1329 static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1330 {
1331         const char *propname = "pinctrl-single,gpio-range";
1332         const char *cellname = "#pinctrl-single,gpio-range-cells";
1333         struct of_phandle_args gpiospec;
1334         struct pcs_gpiofunc_range *range;
1335         int ret, i;
1336
1337         for (i = 0; ; i++) {
1338                 ret = of_parse_phandle_with_args(node, propname, cellname,
1339                                                  i, &gpiospec);
1340                 /* Do not treat it as error. Only treat it as end condition. */
1341                 if (ret) {
1342                         ret = 0;
1343                         break;
1344                 }
1345                 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1346                 if (!range) {
1347                         ret = -ENOMEM;
1348                         break;
1349                 }
1350                 range->offset = gpiospec.args[0];
1351                 range->npins = gpiospec.args[1];
1352                 range->gpiofunc = gpiospec.args[2];
1353                 mutex_lock(&pcs->mutex);
1354                 list_add_tail(&range->node, &pcs->gpiofuncs);
1355                 mutex_unlock(&pcs->mutex);
1356         }
1357         return ret;
1358 }
1359
1360 /**
1361  * struct pcs_interrupt
1362  * @reg:        virtual address of interrupt register
1363  * @hwirq:      hardware irq number
1364  * @irq:        virtual irq number
1365  * @node:       list node
1366  */
1367 struct pcs_interrupt {
1368         void __iomem *reg;
1369         irq_hw_number_t hwirq;
1370         unsigned int irq;
1371         struct list_head node;
1372 };
1373
1374 /**
1375  * pcs_irq_set() - enables or disables an interrupt
1376  * @pcs_soc: SoC specific settings
1377  * @irq: interrupt
1378  * @enable: enable or disable the interrupt
1379  *
1380  * Note that this currently assumes one interrupt per pinctrl
1381  * register that is typically used for wake-up events.
1382  */
1383 static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1384                                int irq, const bool enable)
1385 {
1386         struct pcs_device *pcs;
1387         struct list_head *pos;
1388         unsigned mask;
1389
1390         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1391         list_for_each(pos, &pcs->irqs) {
1392                 struct pcs_interrupt *pcswi;
1393                 unsigned soc_mask;
1394
1395                 pcswi = list_entry(pos, struct pcs_interrupt, node);
1396                 if (irq != pcswi->irq)
1397                         continue;
1398
1399                 soc_mask = pcs_soc->irq_enable_mask;
1400                 raw_spin_lock(&pcs->lock);
1401                 mask = pcs->read(pcswi->reg);
1402                 if (enable)
1403                         mask |= soc_mask;
1404                 else
1405                         mask &= ~soc_mask;
1406                 pcs->write(mask, pcswi->reg);
1407
1408                 /* flush posted write */
1409                 mask = pcs->read(pcswi->reg);
1410                 raw_spin_unlock(&pcs->lock);
1411         }
1412
1413         if (pcs_soc->rearm)
1414                 pcs_soc->rearm();
1415 }
1416
1417 /**
1418  * pcs_irq_mask() - mask pinctrl interrupt
1419  * @d: interrupt data
1420  */
1421 static void pcs_irq_mask(struct irq_data *d)
1422 {
1423         struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1424
1425         pcs_irq_set(pcs_soc, d->irq, false);
1426 }
1427
1428 /**
1429  * pcs_irq_unmask() - unmask pinctrl interrupt
1430  * @d: interrupt data
1431  */
1432 static void pcs_irq_unmask(struct irq_data *d)
1433 {
1434         struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1435
1436         pcs_irq_set(pcs_soc, d->irq, true);
1437 }
1438
1439 /**
1440  * pcs_irq_set_wake() - toggle the suspend and resume wake up
1441  * @d: interrupt data
1442  * @state: wake-up state
1443  *
1444  * Note that this should be called only for suspend and resume.
1445  * For runtime PM, the wake-up events should be enabled by default.
1446  */
1447 static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1448 {
1449         if (state)
1450                 pcs_irq_unmask(d);
1451         else
1452                 pcs_irq_mask(d);
1453
1454         return 0;
1455 }
1456
1457 /**
1458  * pcs_irq_handle() - common interrupt handler
1459  * @pcs_soc: SoC specific settings
1460  *
1461  * Note that this currently assumes we have one interrupt bit per
1462  * mux register. This interrupt is typically used for wake-up events.
1463  * For more complex interrupts different handlers can be specified.
1464  */
1465 static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1466 {
1467         struct pcs_device *pcs;
1468         struct list_head *pos;
1469         int count = 0;
1470
1471         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1472         list_for_each(pos, &pcs->irqs) {
1473                 struct pcs_interrupt *pcswi;
1474                 unsigned mask;
1475
1476                 pcswi = list_entry(pos, struct pcs_interrupt, node);
1477                 raw_spin_lock(&pcs->lock);
1478                 mask = pcs->read(pcswi->reg);
1479                 raw_spin_unlock(&pcs->lock);
1480                 if (mask & pcs_soc->irq_status_mask) {
1481                         generic_handle_irq(irq_find_mapping(pcs->domain,
1482                                                             pcswi->hwirq));
1483                         count++;
1484                 }
1485         }
1486
1487         return count;
1488 }
1489
1490 /**
1491  * pcs_irq_handler() - handler for the shared interrupt case
1492  * @irq: interrupt
1493  * @d: data
1494  *
1495  * Use this for cases where multiple instances of
1496  * pinctrl-single share a single interrupt like on omaps.
1497  */
1498 static irqreturn_t pcs_irq_handler(int irq, void *d)
1499 {
1500         struct pcs_soc_data *pcs_soc = d;
1501
1502         return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1503 }
1504
1505 /**
1506  * pcs_irq_handle() - handler for the dedicated chained interrupt case
1507  * @desc: interrupt descriptor
1508  *
1509  * Use this if you have a separate interrupt for each
1510  * pinctrl-single instance.
1511  */
1512 static void pcs_irq_chain_handler(struct irq_desc *desc)
1513 {
1514         struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1515         struct irq_chip *chip;
1516
1517         chip = irq_desc_get_chip(desc);
1518         chained_irq_enter(chip, desc);
1519         pcs_irq_handle(pcs_soc);
1520         /* REVISIT: export and add handle_bad_irq(irq, desc)? */
1521         chained_irq_exit(chip, desc);
1522 }
1523
1524 static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1525                              irq_hw_number_t hwirq)
1526 {
1527         struct pcs_soc_data *pcs_soc = d->host_data;
1528         struct pcs_device *pcs;
1529         struct pcs_interrupt *pcswi;
1530
1531         pcs = container_of(pcs_soc, struct pcs_device, socdata);
1532         pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1533         if (!pcswi)
1534                 return -ENOMEM;
1535
1536         pcswi->reg = pcs->base + hwirq;
1537         pcswi->hwirq = hwirq;
1538         pcswi->irq = irq;
1539
1540         mutex_lock(&pcs->mutex);
1541         list_add_tail(&pcswi->node, &pcs->irqs);
1542         mutex_unlock(&pcs->mutex);
1543
1544         irq_set_chip_data(irq, pcs_soc);
1545         irq_set_chip_and_handler(irq, &pcs->chip,
1546                                  handle_level_irq);
1547         irq_set_lockdep_class(irq, &pcs_lock_class, &pcs_request_class);
1548         irq_set_noprobe(irq);
1549
1550         return 0;
1551 }
1552
1553 static const struct irq_domain_ops pcs_irqdomain_ops = {
1554         .map = pcs_irqdomain_map,
1555         .xlate = irq_domain_xlate_onecell,
1556 };
1557
1558 /**
1559  * pcs_irq_init_chained_handler() - set up a chained interrupt handler
1560  * @pcs: pcs driver instance
1561  * @np: device node pointer
1562  */
1563 static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1564                                         struct device_node *np)
1565 {
1566         struct pcs_soc_data *pcs_soc = &pcs->socdata;
1567         const char *name = "pinctrl";
1568         int num_irqs;
1569
1570         if (!pcs_soc->irq_enable_mask ||
1571             !pcs_soc->irq_status_mask) {
1572                 pcs_soc->irq = -1;
1573                 return -EINVAL;
1574         }
1575
1576         INIT_LIST_HEAD(&pcs->irqs);
1577         pcs->chip.name = name;
1578         pcs->chip.irq_ack = pcs_irq_mask;
1579         pcs->chip.irq_mask = pcs_irq_mask;
1580         pcs->chip.irq_unmask = pcs_irq_unmask;
1581         pcs->chip.irq_set_wake = pcs_irq_set_wake;
1582
1583         if (PCS_QUIRK_HAS_SHARED_IRQ) {
1584                 int res;
1585
1586                 res = request_irq(pcs_soc->irq, pcs_irq_handler,
1587                                   IRQF_SHARED | IRQF_NO_SUSPEND |
1588                                   IRQF_NO_THREAD,
1589                                   name, pcs_soc);
1590                 if (res) {
1591                         pcs_soc->irq = -1;
1592                         return res;
1593                 }
1594         } else {
1595                 irq_set_chained_handler_and_data(pcs_soc->irq,
1596                                                  pcs_irq_chain_handler,
1597                                                  pcs_soc);
1598         }
1599
1600         /*
1601          * We can use the register offset as the hardirq
1602          * number as irq_domain_add_simple maps them lazily.
1603          * This way we can easily support more than one
1604          * interrupt per function if needed.
1605          */
1606         num_irqs = pcs->size;
1607
1608         pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1609                                             &pcs_irqdomain_ops,
1610                                             pcs_soc);
1611         if (!pcs->domain) {
1612                 irq_set_chained_handler(pcs_soc->irq, NULL);
1613                 return -EINVAL;
1614         }
1615
1616         return 0;
1617 }
1618
1619 #ifdef CONFIG_PM
1620 static int pcs_save_context(struct pcs_device *pcs)
1621 {
1622         int i, mux_bytes;
1623         u64 *regsl;
1624         u32 *regsw;
1625         u16 *regshw;
1626
1627         mux_bytes = pcs->width / BITS_PER_BYTE;
1628
1629         if (!pcs->saved_vals) {
1630                 pcs->saved_vals = devm_kzalloc(pcs->dev, pcs->size, GFP_ATOMIC);
1631                 if (!pcs->saved_vals)
1632                         return -ENOMEM;
1633         }
1634
1635         switch (pcs->width) {
1636         case 64:
1637                 regsl = pcs->saved_vals;
1638                 for (i = 0; i < pcs->size; i += mux_bytes)
1639                         *regsl++ = pcs->read(pcs->base + i);
1640                 break;
1641         case 32:
1642                 regsw = pcs->saved_vals;
1643                 for (i = 0; i < pcs->size; i += mux_bytes)
1644                         *regsw++ = pcs->read(pcs->base + i);
1645                 break;
1646         case 16:
1647                 regshw = pcs->saved_vals;
1648                 for (i = 0; i < pcs->size; i += mux_bytes)
1649                         *regshw++ = pcs->read(pcs->base + i);
1650                 break;
1651         }
1652
1653         return 0;
1654 }
1655
1656 static void pcs_restore_context(struct pcs_device *pcs)
1657 {
1658         int i, mux_bytes;
1659         u64 *regsl;
1660         u32 *regsw;
1661         u16 *regshw;
1662
1663         mux_bytes = pcs->width / BITS_PER_BYTE;
1664
1665         switch (pcs->width) {
1666         case 64:
1667                 regsl = pcs->saved_vals;
1668                 for (i = 0; i < pcs->size; i += mux_bytes)
1669                         pcs->write(*regsl++, pcs->base + i);
1670                 break;
1671         case 32:
1672                 regsw = pcs->saved_vals;
1673                 for (i = 0; i < pcs->size; i += mux_bytes)
1674                         pcs->write(*regsw++, pcs->base + i);
1675                 break;
1676         case 16:
1677                 regshw = pcs->saved_vals;
1678                 for (i = 0; i < pcs->size; i += mux_bytes)
1679                         pcs->write(*regshw++, pcs->base + i);
1680                 break;
1681         }
1682 }
1683
1684 static int pinctrl_single_suspend(struct platform_device *pdev,
1685                                         pm_message_t state)
1686 {
1687         struct pcs_device *pcs;
1688
1689         pcs = platform_get_drvdata(pdev);
1690         if (!pcs)
1691                 return -EINVAL;
1692
1693         if (pcs->flags & PCS_CONTEXT_LOSS_OFF) {
1694                 int ret;
1695
1696                 ret = pcs_save_context(pcs);
1697                 if (ret < 0)
1698                         return ret;
1699         }
1700
1701         return pinctrl_force_sleep(pcs->pctl);
1702 }
1703
1704 static int pinctrl_single_resume(struct platform_device *pdev)
1705 {
1706         struct pcs_device *pcs;
1707
1708         pcs = platform_get_drvdata(pdev);
1709         if (!pcs)
1710                 return -EINVAL;
1711
1712         if (pcs->flags & PCS_CONTEXT_LOSS_OFF)
1713                 pcs_restore_context(pcs);
1714
1715         return pinctrl_force_default(pcs->pctl);
1716 }
1717 #endif
1718
1719 /**
1720  * pcs_quirk_missing_pinctrl_cells - handle legacy binding
1721  * @pcs: pinctrl driver instance
1722  * @np: device tree node
1723  * @cells: number of cells
1724  *
1725  * Handle legacy binding with no #pinctrl-cells. This should be
1726  * always two pinctrl-single,bit-per-mux and one for others.
1727  * At some point we may want to consider removing this.
1728  */
1729 static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
1730                                            struct device_node *np,
1731                                            int cells)
1732 {
1733         struct property *p;
1734         const char *name = "#pinctrl-cells";
1735         int error;
1736         u32 val;
1737
1738         error = of_property_read_u32(np, name, &val);
1739         if (!error)
1740                 return 0;
1741
1742         dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
1743                  name, cells);
1744
1745         p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);
1746         if (!p)
1747                 return -ENOMEM;
1748
1749         p->length = sizeof(__be32);
1750         p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);
1751         if (!p->value)
1752                 return -ENOMEM;
1753         *(__be32 *)p->value = cpu_to_be32(cells);
1754
1755         p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);
1756         if (!p->name)
1757                 return -ENOMEM;
1758
1759         pcs->missing_nr_pinctrl_cells = p;
1760
1761 #if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1762         error = of_add_property(np, pcs->missing_nr_pinctrl_cells);
1763 #endif
1764
1765         return error;
1766 }
1767
1768 static int pcs_probe(struct platform_device *pdev)
1769 {
1770         struct device_node *np = pdev->dev.of_node;
1771         struct pcs_pdata *pdata;
1772         struct resource *res;
1773         struct pcs_device *pcs;
1774         const struct pcs_soc_data *soc;
1775         int ret;
1776
1777         soc = of_device_get_match_data(&pdev->dev);
1778         if (WARN_ON(!soc))
1779                 return -EINVAL;
1780
1781         pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1782         if (!pcs)
1783                 return -ENOMEM;
1784
1785         pcs->dev = &pdev->dev;
1786         pcs->np = np;
1787         raw_spin_lock_init(&pcs->lock);
1788         mutex_init(&pcs->mutex);
1789         INIT_LIST_HEAD(&pcs->gpiofuncs);
1790         pcs->flags = soc->flags;
1791         memcpy(&pcs->socdata, soc, sizeof(*soc));
1792
1793         ret = of_property_read_u32(np, "pinctrl-single,register-width",
1794                                    &pcs->width);
1795         if (ret) {
1796                 dev_err(pcs->dev, "register width not specified\n");
1797
1798                 return ret;
1799         }
1800
1801         ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1802                                    &pcs->fmask);
1803         if (!ret) {
1804                 pcs->fshift = __ffs(pcs->fmask);
1805                 pcs->fmax = pcs->fmask >> pcs->fshift;
1806         } else {
1807                 /* If mask property doesn't exist, function mux is invalid. */
1808                 pcs->fmask = 0;
1809                 pcs->fshift = 0;
1810                 pcs->fmax = 0;
1811         }
1812
1813         ret = of_property_read_u32(np, "pinctrl-single,function-off",
1814                                         &pcs->foff);
1815         if (ret)
1816                 pcs->foff = PCS_OFF_DISABLED;
1817
1818         pcs->bits_per_mux = of_property_read_bool(np,
1819                                                   "pinctrl-single,bit-per-mux");
1820         ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
1821                                               pcs->bits_per_mux ? 2 : 1);
1822         if (ret) {
1823                 dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n");
1824
1825                 return ret;
1826         }
1827
1828         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1829         if (!res) {
1830                 dev_err(pcs->dev, "could not get resource\n");
1831                 return -ENODEV;
1832         }
1833
1834         pcs->res = devm_request_mem_region(pcs->dev, res->start,
1835                         resource_size(res), DRIVER_NAME);
1836         if (!pcs->res) {
1837                 dev_err(pcs->dev, "could not get mem_region\n");
1838                 return -EBUSY;
1839         }
1840
1841         pcs->size = resource_size(pcs->res);
1842         pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1843         if (!pcs->base) {
1844                 dev_err(pcs->dev, "could not ioremap\n");
1845                 return -ENODEV;
1846         }
1847
1848         platform_set_drvdata(pdev, pcs);
1849
1850         switch (pcs->width) {
1851         case 8:
1852                 pcs->read = pcs_readb;
1853                 pcs->write = pcs_writeb;
1854                 break;
1855         case 16:
1856                 pcs->read = pcs_readw;
1857                 pcs->write = pcs_writew;
1858                 break;
1859         case 32:
1860                 pcs->read = pcs_readl;
1861                 pcs->write = pcs_writel;
1862                 break;
1863         default:
1864                 break;
1865         }
1866
1867         pcs->desc.name = DRIVER_NAME;
1868         pcs->desc.pctlops = &pcs_pinctrl_ops;
1869         pcs->desc.pmxops = &pcs_pinmux_ops;
1870         if (PCS_HAS_PINCONF)
1871                 pcs->desc.confops = &pcs_pinconf_ops;
1872         pcs->desc.owner = THIS_MODULE;
1873
1874         ret = pcs_allocate_pin_table(pcs);
1875         if (ret < 0)
1876                 goto free;
1877
1878         ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl);
1879         if (ret) {
1880                 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1881                 goto free;
1882         }
1883
1884         ret = pcs_add_gpio_func(np, pcs);
1885         if (ret < 0)
1886                 goto free;
1887
1888         pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1889         if (pcs->socdata.irq)
1890                 pcs->flags |= PCS_FEAT_IRQ;
1891
1892         /* We still need auxdata for some omaps for PRM interrupts */
1893         pdata = dev_get_platdata(&pdev->dev);
1894         if (pdata) {
1895                 if (pdata->rearm)
1896                         pcs->socdata.rearm = pdata->rearm;
1897                 if (pdata->irq) {
1898                         pcs->socdata.irq = pdata->irq;
1899                         pcs->flags |= PCS_FEAT_IRQ;
1900                 }
1901         }
1902
1903         if (PCS_HAS_IRQ) {
1904                 ret = pcs_irq_init_chained_handler(pcs, np);
1905                 if (ret < 0)
1906                         dev_warn(pcs->dev, "initialized with no interrupts\n");
1907         }
1908
1909         dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
1910
1911         return pinctrl_enable(pcs->pctl);
1912
1913 free:
1914         pcs_free_resources(pcs);
1915
1916         return ret;
1917 }
1918
1919 static int pcs_remove(struct platform_device *pdev)
1920 {
1921         struct pcs_device *pcs = platform_get_drvdata(pdev);
1922
1923         if (!pcs)
1924                 return 0;
1925
1926         pcs_free_resources(pcs);
1927
1928         return 0;
1929 }
1930
1931 static const struct pcs_soc_data pinctrl_single_omap_wkup = {
1932         .flags = PCS_QUIRK_SHARED_IRQ,
1933         .irq_enable_mask = (1 << 14),   /* OMAP_WAKEUP_EN */
1934         .irq_status_mask = (1 << 15),   /* OMAP_WAKEUP_EVENT */
1935 };
1936
1937 static const struct pcs_soc_data pinctrl_single_dra7 = {
1938         .irq_enable_mask = (1 << 24),   /* WAKEUPENABLE */
1939         .irq_status_mask = (1 << 25),   /* WAKEUPEVENT */
1940 };
1941
1942 static const struct pcs_soc_data pinctrl_single_am437x = {
1943         .flags = PCS_QUIRK_SHARED_IRQ | PCS_CONTEXT_LOSS_OFF,
1944         .irq_enable_mask = (1 << 29),   /* OMAP_WAKEUP_EN */
1945         .irq_status_mask = (1 << 30),   /* OMAP_WAKEUP_EVENT */
1946 };
1947
1948 static const struct pcs_soc_data pinctrl_single = {
1949 };
1950
1951 static const struct pcs_soc_data pinconf_single = {
1952         .flags = PCS_FEAT_PINCONF,
1953 };
1954
1955 static const struct of_device_id pcs_of_match[] = {
1956         { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1957         { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1958         { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1959         { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
1960         { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1961         { .compatible = "pinctrl-single", .data = &pinctrl_single },
1962         { .compatible = "pinconf-single", .data = &pinconf_single },
1963         { },
1964 };
1965 MODULE_DEVICE_TABLE(of, pcs_of_match);
1966
1967 static struct platform_driver pcs_driver = {
1968         .probe          = pcs_probe,
1969         .remove         = pcs_remove,
1970         .driver = {
1971                 .name           = DRIVER_NAME,
1972                 .of_match_table = pcs_of_match,
1973         },
1974 #ifdef CONFIG_PM
1975         .suspend = pinctrl_single_suspend,
1976         .resume = pinctrl_single_resume,
1977 #endif
1978 };
1979
1980 module_platform_driver(pcs_driver);
1981
1982 MODULE_AUTHOR("Tony Lindgren <[email protected]>");
1983 MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
1984 MODULE_LICENSE("GPL v2");