drivers/gpu/drm/i915/gvt/scheduler.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Zhi Wang <[email protected]>
  25  *
  26  * Contributors:
  27  *    Ping Gao <[email protected]>
  28  *    Tina Zhang <[email protected]>
  29  *    Chanbin Du <[email protected]>
  30  *    Min He <[email protected]>
  31  *    Bing Niu <[email protected]>
  32  *    Zhenyu Wang <[email protected]>
  33  *
  34  */
  35
  36 #include <linux/kthread.h>
  37
  38 #include "gem/i915_gem_pm.h"
  39 #include "gt/intel_context.h"
  40 #include "gt/intel_ring.h"
  41
  42 #include "i915_drv.h"
  43 #include "i915_gem_gtt.h"
  44 #include "gvt.h"
  45
  46 #define RING_CTX_OFF(x) \
  47         offsetof(struct execlist_ring_context, x)
  48
  49 static void set_context_pdp_root_pointer(
  50                 struct execlist_ring_context *ring_context,
  51                 u32 pdp[8])
  52 {
  53         int i;
  54
  55         for (i = 0; i < 8; i++)
  56                 ring_context->pdps[i].val = pdp[7 - i];
  57 }
  58
  59 static void update_shadow_pdps(struct intel_vgpu_workload *workload)
  60 {
  61         struct execlist_ring_context *shadow_ring_context;
  62         struct intel_context *ctx = workload->req->context;
  63
  64         if (WARN_ON(!workload->shadow_mm))
  65                 return;
  66
  67         if (WARN_ON(!atomic_read(&workload->shadow_mm->pincount)))
  68                 return;
  69
  70         shadow_ring_context = (struct execlist_ring_context *)ctx->lrc_reg_state;
  71         set_context_pdp_root_pointer(shadow_ring_context,
  72                         (void *)workload->shadow_mm->ppgtt_mm.shadow_pdps);
  73 }
  74
  75 /*
  76  * when populating shadow ctx from guest, we should not overrride oa related
  77  * registers, so that they will not be overlapped by guest oa configs. Thus
  78  * made it possible to capture oa data from host for both host and guests.
  79  */
  80 static void sr_oa_regs(struct intel_vgpu_workload *workload,
  81                 u32 *reg_state, bool save)
  82 {
  83         struct drm_i915_private *dev_priv = workload->vgpu->gvt->gt->i915;
  84         u32 ctx_oactxctrl = dev_priv->perf.ctx_oactxctrl_offset;
  85         u32 ctx_flexeu0 = dev_priv->perf.ctx_flexeu0_offset;
  86         int i = 0;
  87         u32 flex_mmio[] = {
  88                 i915_mmio_reg_offset(EU_PERF_CNTL0),
  89                 i915_mmio_reg_offset(EU_PERF_CNTL1),
  90                 i915_mmio_reg_offset(EU_PERF_CNTL2),
  91                 i915_mmio_reg_offset(EU_PERF_CNTL3),
  92                 i915_mmio_reg_offset(EU_PERF_CNTL4),
  93                 i915_mmio_reg_offset(EU_PERF_CNTL5),
  94                 i915_mmio_reg_offset(EU_PERF_CNTL6),
  95         };
  96
  97         if (workload->engine->id != RCS0)
  98                 return;
  99
 100         if (save) {
 101                 workload->oactxctrl = reg_state[ctx_oactxctrl + 1];
 102
 103                 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
 104                         u32 state_offset = ctx_flexeu0 + i * 2;
 105
 106                         workload->flex_mmio[i] = reg_state[state_offset + 1];
 107                 }
 108         } else {
 109                 reg_state[ctx_oactxctrl] =
 110                         i915_mmio_reg_offset(GEN8_OACTXCONTROL);
 111                 reg_state[ctx_oactxctrl + 1] = workload->oactxctrl;
 112
 113                 for (i = 0; i < ARRAY_SIZE(workload->flex_mmio); i++) {
 114                         u32 state_offset = ctx_flexeu0 + i * 2;
 115                         u32 mmio = flex_mmio[i];
 116
 117                         reg_state[state_offset] = mmio;
 118                         reg_state[state_offset + 1] = workload->flex_mmio[i];
 119                 }
 120         }
 121 }
 122
 123 static int populate_shadow_context(struct intel_vgpu_workload *workload)
 124 {
 125         struct intel_vgpu *vgpu = workload->vgpu;
 126         struct intel_gvt *gvt = vgpu->gvt;
 127         struct intel_context *ctx = workload->req->context;
 128         struct execlist_ring_context *shadow_ring_context;
 129         void *dst;
 130         void *context_base;
 131         unsigned long context_gpa, context_page_num;
 132         unsigned long gpa_base; /* first gpa of consecutive GPAs */
 133         unsigned long gpa_size; /* size of consecutive GPAs */
 134         struct intel_vgpu_submission *s = &vgpu->submission;
 135         int i;
 136         bool skip = false;
 137         int ring_id = workload->engine->id;
 138
 139         GEM_BUG_ON(!intel_context_is_pinned(ctx));
 140
 141         context_base = (void *) ctx->lrc_reg_state -
 142                                 (LRC_STATE_PN << I915_GTT_PAGE_SHIFT);
 143
 144         shadow_ring_context = (void *) ctx->lrc_reg_state;
 145
 146         sr_oa_regs(workload, (u32 *)shadow_ring_context, true);
 147 #define COPY_REG(name) \
 148         intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
 149                 + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
 150 #define COPY_REG_MASKED(name) {\
 151                 intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
 152                                               + RING_CTX_OFF(name.val),\
 153                                               &shadow_ring_context->name.val, 4);\
 154                 shadow_ring_context->name.val |= 0xffff << 16;\
 155         }
 156
 157         COPY_REG_MASKED(ctx_ctrl);
 158         COPY_REG(ctx_timestamp);
 159
 160         if (workload->engine->id == RCS0) {
 161                 COPY_REG(bb_per_ctx_ptr);
 162                 COPY_REG(rcs_indirect_ctx);
 163                 COPY_REG(rcs_indirect_ctx_offset);
 164         }
 165 #undef COPY_REG
 166 #undef COPY_REG_MASKED
 167
 168         intel_gvt_hypervisor_read_gpa(vgpu,
 169                         workload->ring_context_gpa +
 170                         sizeof(*shadow_ring_context),
 171                         (void *)shadow_ring_context +
 172                         sizeof(*shadow_ring_context),
 173                         I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
 174
 175         sr_oa_regs(workload, (u32 *)shadow_ring_context, false);
 176
 177         gvt_dbg_sched("ring %s workload lrca %x, ctx_id %x, ctx gpa %llx",
 178                         workload->engine->name, workload->ctx_desc.lrca,
 179                         workload->ctx_desc.context_id,
 180                         workload->ring_context_gpa);
 181
 182         /* only need to ensure this context is not pinned/unpinned during the
 183          * period from last submission to this this submission.
 184          * Upon reaching this function, the currently submitted context is not
 185          * supposed to get unpinned. If a misbehaving guest driver ever does
 186          * this, it would corrupt itself.
 187          */
 188         if (s->last_ctx[ring_id].valid &&
 189                         (s->last_ctx[ring_id].lrca ==
 190                                 workload->ctx_desc.lrca) &&
 191                         (s->last_ctx[ring_id].ring_context_gpa ==
 192                                 workload->ring_context_gpa))
 193                 skip = true;
 194
 195         s->last_ctx[ring_id].lrca = workload->ctx_desc.lrca;
 196         s->last_ctx[ring_id].ring_context_gpa = workload->ring_context_gpa;
 197
 198         if (IS_RESTORE_INHIBIT(shadow_ring_context->ctx_ctrl.val) || skip)
 199                 return 0;
 200
 201         s->last_ctx[ring_id].valid = false;
 202         context_page_num = workload->engine->context_size;
 203         context_page_num = context_page_num >> PAGE_SHIFT;
 204
 205         if (IS_BROADWELL(gvt->gt->i915) && workload->engine->id == RCS0)
 206                 context_page_num = 19;
 207
 208         /* find consecutive GPAs from gma until the first inconsecutive GPA.
 209          * read from the continuous GPAs into dst virtual address
 210          */
 211         gpa_size = 0;
 212         for (i = 2; i < context_page_num; i++) {
 213                 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
 214                                 (u32)((workload->ctx_desc.lrca + i) <<
 215                                 I915_GTT_PAGE_SHIFT));
 216                 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
 217                         gvt_vgpu_err("Invalid guest context descriptor\n");
 218                         return -EFAULT;
 219                 }
 220
 221                 if (gpa_size == 0) {
 222                         gpa_base = context_gpa;
 223                         dst = context_base + (i << I915_GTT_PAGE_SHIFT);
 224                 } else if (context_gpa != gpa_base + gpa_size)
 225                         goto read;
 226
 227                 gpa_size += I915_GTT_PAGE_SIZE;
 228
 229                 if (i == context_page_num - 1)
 230                         goto read;
 231
 232                 continue;
 233
 234 read:
 235                 intel_gvt_hypervisor_read_gpa(vgpu, gpa_base, dst, gpa_size);
 236                 gpa_base = context_gpa;
 237                 gpa_size = I915_GTT_PAGE_SIZE;
 238                 dst = context_base + (i << I915_GTT_PAGE_SHIFT);
 239         }
 240         s->last_ctx[ring_id].valid = true;
 241         return 0;
 242 }
 243
 244 static inline bool is_gvt_request(struct i915_request *rq)
 245 {
 246         return intel_context_force_single_submission(rq->context);
 247 }
 248
 249 static void save_ring_hw_state(struct intel_vgpu *vgpu,
 250                                const struct intel_engine_cs *engine)
 251 {
 252         struct intel_uncore *uncore = engine->uncore;
 253         i915_reg_t reg;
 254
 255         reg = RING_INSTDONE(engine->mmio_base);
 256         vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =
 257                 intel_uncore_read(uncore, reg);
 258
 259         reg = RING_ACTHD(engine->mmio_base);
 260         vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =
 261                 intel_uncore_read(uncore, reg);
 262
 263         reg = RING_ACTHD_UDW(engine->mmio_base);
 264         vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) =
 265                 intel_uncore_read(uncore, reg);
 266 }
 267
 268 static int shadow_context_status_change(struct notifier_block *nb,
 269                 unsigned long action, void *data)
 270 {
 271         struct i915_request *rq = data;
 272         struct intel_gvt *gvt = container_of(nb, struct intel_gvt,
 273                                 shadow_ctx_notifier_block[rq->engine->id]);
 274         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 275         enum intel_engine_id ring_id = rq->engine->id;
 276         struct intel_vgpu_workload *workload;
 277         unsigned long flags;
 278
 279         if (!is_gvt_request(rq)) {
 280                 spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
 281                 if (action == INTEL_CONTEXT_SCHEDULE_IN &&
 282                     scheduler->engine_owner[ring_id]) {
 283                         /* Switch ring from vGPU to host. */
 284                         intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
 285                                               NULL, rq->engine);
 286                         scheduler->engine_owner[ring_id] = NULL;
 287                 }
 288                 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
 289
 290                 return NOTIFY_OK;
 291         }
 292
 293         workload = scheduler->current_workload[ring_id];
 294         if (unlikely(!workload))
 295                 return NOTIFY_OK;
 296
 297         switch (action) {
 298         case INTEL_CONTEXT_SCHEDULE_IN:
 299                 spin_lock_irqsave(&scheduler->mmio_context_lock, flags);
 300                 if (workload->vgpu != scheduler->engine_owner[ring_id]) {
 301                         /* Switch ring from host to vGPU or vGPU to vGPU. */
 302                         intel_gvt_switch_mmio(scheduler->engine_owner[ring_id],
 303                                               workload->vgpu, rq->engine);
 304                         scheduler->engine_owner[ring_id] = workload->vgpu;
 305                 } else
 306                         gvt_dbg_sched("skip ring %d mmio switch for vgpu%d\n",
 307                                       ring_id, workload->vgpu->id);
 308                 spin_unlock_irqrestore(&scheduler->mmio_context_lock, flags);
 309                 atomic_set(&workload->shadow_ctx_active, 1);
 310                 break;
 311         case INTEL_CONTEXT_SCHEDULE_OUT:
 312                 save_ring_hw_state(workload->vgpu, rq->engine);
 313                 atomic_set(&workload->shadow_ctx_active, 0);
 314                 break;
 315         case INTEL_CONTEXT_SCHEDULE_PREEMPTED:
 316                 save_ring_hw_state(workload->vgpu, rq->engine);
 317                 break;
 318         default:
 319                 WARN_ON(1);
 320                 return NOTIFY_OK;
 321         }
 322         wake_up(&workload->shadow_ctx_status_wq);
 323         return NOTIFY_OK;
 324 }
 325
 326 static void
 327 shadow_context_descriptor_update(struct intel_context *ce,
 328                                  struct intel_vgpu_workload *workload)
 329 {
 330         u64 desc = ce->lrc.desc;
 331
 332         /*
 333          * Update bits 0-11 of the context descriptor which includes flags
 334          * like GEN8_CTX_* cached in desc_template
 335          */
 336         desc &= ~(0x3ull << GEN8_CTX_ADDRESSING_MODE_SHIFT);
 337         desc |= (u64)workload->ctx_desc.addressing_mode <<
 338                 GEN8_CTX_ADDRESSING_MODE_SHIFT;
 339
 340         ce->lrc.desc = desc;
 341 }
 342
 343 static int copy_workload_to_ring_buffer(struct intel_vgpu_workload *workload)
 344 {
 345         struct intel_vgpu *vgpu = workload->vgpu;
 346         struct i915_request *req = workload->req;
 347         void *shadow_ring_buffer_va;
 348         u32 *cs;
 349         int err;
 350
 351         if (IS_GEN(req->engine->i915, 9) && is_inhibit_context(req->context))
 352                 intel_vgpu_restore_inhibit_context(vgpu, req);
 353
 354         /*
 355          * To track whether a request has started on HW, we can emit a
 356          * breadcrumb at the beginning of the request and check its
 357          * timeline's HWSP to see if the breadcrumb has advanced past the
 358          * start of this request. Actually, the request must have the
 359          * init_breadcrumb if its timeline set has_init_bread_crumb, or the
 360          * scheduler might get a wrong state of it during reset. Since the
 361          * requests from gvt always set the has_init_breadcrumb flag, here
 362          * need to do the emit_init_breadcrumb for all the requests.
 363          */
 364         if (req->engine->emit_init_breadcrumb) {
 365                 err = req->engine->emit_init_breadcrumb(req);
 366                 if (err) {
 367                         gvt_vgpu_err("fail to emit init breadcrumb\n");
 368                         return err;
 369                 }
 370         }
 371
 372         /* allocate shadow ring buffer */
 373         cs = intel_ring_begin(workload->req, workload->rb_len / sizeof(u32));
 374         if (IS_ERR(cs)) {
 375                 gvt_vgpu_err("fail to alloc size =%ld shadow  ring buffer\n",
 376                         workload->rb_len);
 377                 return PTR_ERR(cs);
 378         }
 379
 380         shadow_ring_buffer_va = workload->shadow_ring_buffer_va;
 381
 382         /* get shadow ring buffer va */
 383         workload->shadow_ring_buffer_va = cs;
 384
 385         memcpy(cs, shadow_ring_buffer_va,
 386                         workload->rb_len);
 387
 388         cs += workload->rb_len / sizeof(u32);
 389         intel_ring_advance(workload->req, cs);
 390
 391         return 0;
 392 }
 393
 394 static void release_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
 395 {
 396         if (!wa_ctx->indirect_ctx.obj)
 397                 return;
 398
 399         i915_gem_object_unpin_map(wa_ctx->indirect_ctx.obj);
 400         i915_gem_object_put(wa_ctx->indirect_ctx.obj);
 401
 402         wa_ctx->indirect_ctx.obj = NULL;
 403         wa_ctx->indirect_ctx.shadow_va = NULL;
 404 }
 405
 406 static void set_context_ppgtt_from_shadow(struct intel_vgpu_workload *workload,
 407                                           struct intel_context *ce)
 408 {
 409         struct intel_vgpu_mm *mm = workload->shadow_mm;
 410         struct i915_ppgtt *ppgtt = i915_vm_to_ppgtt(ce->vm);
 411         int i = 0;
 412
 413         if (mm->ppgtt_mm.root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
 414                 px_dma(ppgtt->pd) = mm->ppgtt_mm.shadow_pdps[0];
 415         } else {
 416                 for (i = 0; i < GVT_RING_CTX_NR_PDPS; i++) {
 417                         struct i915_page_directory * const pd =
 418                                 i915_pd_entry(ppgtt->pd, i);
 419                         /* skip now as current i915 ppgtt alloc won't allocate
 420                            top level pdp for non 4-level table, won't impact
 421                            shadow ppgtt. */
 422                         if (!pd)
 423                                 break;
 424                         px_dma(pd) = mm->ppgtt_mm.shadow_pdps[i];
 425                 }
 426         }
 427 }
 428
 429 static int
 430 intel_gvt_workload_req_alloc(struct intel_vgpu_workload *workload)
 431 {
 432         struct intel_vgpu *vgpu = workload->vgpu;
 433         struct intel_vgpu_submission *s = &vgpu->submission;
 434         struct i915_request *rq;
 435
 436         if (workload->req)
 437                 return 0;
 438
 439         rq = i915_request_create(s->shadow[workload->engine->id]);
 440         if (IS_ERR(rq)) {
 441                 gvt_vgpu_err("fail to allocate gem request\n");
 442                 return PTR_ERR(rq);
 443         }
 444
 445         workload->req = i915_request_get(rq);
 446         return 0;
 447 }
 448
 449 /**
 450  * intel_gvt_scan_and_shadow_workload - audit the workload by scanning and
 451  * shadow it as well, include ringbuffer,wa_ctx and ctx.
 452  * @workload: an abstract entity for each execlist submission.
 453  *
 454  * This function is called before the workload submitting to i915, to make
 455  * sure the content of the workload is valid.
 456  */
 457 int intel_gvt_scan_and_shadow_workload(struct intel_vgpu_workload *workload)
 458 {
 459         struct intel_vgpu *vgpu = workload->vgpu;
 460         struct intel_vgpu_submission *s = &vgpu->submission;
 461         int ret;
 462
 463         lockdep_assert_held(&vgpu->vgpu_lock);
 464
 465         if (workload->shadow)
 466                 return 0;
 467
 468         if (!test_and_set_bit(workload->engine->id, s->shadow_ctx_desc_updated))
 469                 shadow_context_descriptor_update(s->shadow[workload->engine->id],
 470                                                  workload);
 471
 472         ret = intel_gvt_scan_and_shadow_ringbuffer(workload);
 473         if (ret)
 474                 return ret;
 475
 476         if (workload->engine->id == RCS0 &&
 477             workload->wa_ctx.indirect_ctx.size) {
 478                 ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx);
 479                 if (ret)
 480                         goto err_shadow;
 481         }
 482
 483         workload->shadow = true;
 484         return 0;
 485
 486 err_shadow:
 487         release_shadow_wa_ctx(&workload->wa_ctx);
 488         return ret;
 489 }
 490
 491 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload);
 492
 493 static int prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload)
 494 {
 495         struct intel_gvt *gvt = workload->vgpu->gvt;
 496         const int gmadr_bytes = gvt->device_info.gmadr_bytes_in_cmd;
 497         struct intel_vgpu_shadow_bb *bb;
 498         int ret;
 499
 500         list_for_each_entry(bb, &workload->shadow_bb, list) {
 501                 /* For privilge batch buffer and not wa_ctx, the bb_start_cmd_va
 502                  * is only updated into ring_scan_buffer, not real ring address
 503                  * allocated in later copy_workload_to_ring_buffer. pls be noted
 504                  * shadow_ring_buffer_va is now pointed to real ring buffer va
 505                  * in copy_workload_to_ring_buffer.
 506                  */
 507
 508                 if (bb->bb_offset)
 509                         bb->bb_start_cmd_va = workload->shadow_ring_buffer_va
 510                                 + bb->bb_offset;
 511
 512                 /*
 513                  * For non-priv bb, scan&shadow is only for
 514                  * debugging purpose, so the content of shadow bb
 515                  * is the same as original bb. Therefore,
 516                  * here, rather than switch to shadow bb's gma
 517                  * address, we directly use original batch buffer's
 518                  * gma address, and send original bb to hardware
 519                  * directly
 520                  */
 521                 if (!bb->ppgtt) {
 522                         bb->vma = i915_gem_object_ggtt_pin(bb->obj,
 523                                                            NULL, 0, 0, 0);
 524                         if (IS_ERR(bb->vma)) {
 525                                 ret = PTR_ERR(bb->vma);
 526                                 goto err;
 527                         }
 528
 529                         /* relocate shadow batch buffer */
 530                         bb->bb_start_cmd_va[1] = i915_ggtt_offset(bb->vma);
 531                         if (gmadr_bytes == 8)
 532                                 bb->bb_start_cmd_va[2] = 0;
 533
 534                         ret = i915_vma_move_to_active(bb->vma,
 535                                                       workload->req,
 536                                                       0);
 537                         if (ret)
 538                                 goto err;
 539                 }
 540
 541                 /* No one is going to touch shadow bb from now on. */
 542                 i915_gem_object_flush_map(bb->obj);
 543         }
 544         return 0;
 545 err:
 546         release_shadow_batch_buffer(workload);
 547         return ret;
 548 }
 549
 550 static void update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx *wa_ctx)
 551 {
 552         struct intel_vgpu_workload *workload =
 553                 container_of(wa_ctx, struct intel_vgpu_workload, wa_ctx);
 554         struct i915_request *rq = workload->req;
 555         struct execlist_ring_context *shadow_ring_context =
 556                 (struct execlist_ring_context *)rq->context->lrc_reg_state;
 557
 558         shadow_ring_context->bb_per_ctx_ptr.val =
 559                 (shadow_ring_context->bb_per_ctx_ptr.val &
 560                 (~PER_CTX_ADDR_MASK)) | wa_ctx->per_ctx.shadow_gma;
 561         shadow_ring_context->rcs_indirect_ctx.val =
 562                 (shadow_ring_context->rcs_indirect_ctx.val &
 563                 (~INDIRECT_CTX_ADDR_MASK)) | wa_ctx->indirect_ctx.shadow_gma;
 564 }
 565
 566 static int prepare_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
 567 {
 568         struct i915_vma *vma;
 569         unsigned char *per_ctx_va =
 570                 (unsigned char *)wa_ctx->indirect_ctx.shadow_va +
 571                 wa_ctx->indirect_ctx.size;
 572
 573         if (wa_ctx->indirect_ctx.size == 0)
 574                 return 0;
 575
 576         vma = i915_gem_object_ggtt_pin(wa_ctx->indirect_ctx.obj, NULL,
 577                                        0, CACHELINE_BYTES, 0);
 578         if (IS_ERR(vma))
 579                 return PTR_ERR(vma);
 580
 581         /* FIXME: we are not tracking our pinned VMA leaving it
 582          * up to the core to fix up the stray pin_count upon
 583          * free.
 584          */
 585
 586         wa_ctx->indirect_ctx.shadow_gma = i915_ggtt_offset(vma);
 587
 588         wa_ctx->per_ctx.shadow_gma = *((unsigned int *)per_ctx_va + 1);
 589         memset(per_ctx_va, 0, CACHELINE_BYTES);
 590
 591         update_wa_ctx_2_shadow_ctx(wa_ctx);
 592         return 0;
 593 }
 594
 595 static void update_vreg_in_ctx(struct intel_vgpu_workload *workload)
 596 {
 597         vgpu_vreg_t(workload->vgpu, RING_START(workload->engine->mmio_base)) =
 598                 workload->rb_start;
 599 }
 600
 601 static void release_shadow_batch_buffer(struct intel_vgpu_workload *workload)
 602 {
 603         struct intel_vgpu_shadow_bb *bb, *pos;
 604
 605         if (list_empty(&workload->shadow_bb))
 606                 return;
 607
 608         bb = list_first_entry(&workload->shadow_bb,
 609                         struct intel_vgpu_shadow_bb, list);
 610
 611         list_for_each_entry_safe(bb, pos, &workload->shadow_bb, list) {
 612                 if (bb->obj) {
 613                         if (bb->va && !IS_ERR(bb->va))
 614                                 i915_gem_object_unpin_map(bb->obj);
 615
 616                         if (bb->vma && !IS_ERR(bb->vma))
 617                                 i915_vma_unpin(bb->vma);
 618
 619                         i915_gem_object_put(bb->obj);
 620                 }
 621                 list_del(&bb->list);
 622                 kfree(bb);
 623         }
 624 }
 625
 626 static int
 627 intel_vgpu_shadow_mm_pin(struct intel_vgpu_workload *workload)
 628 {
 629         struct intel_vgpu *vgpu = workload->vgpu;
 630         struct intel_vgpu_mm *m;
 631         int ret = 0;
 632
 633         ret = intel_vgpu_pin_mm(workload->shadow_mm);
 634         if (ret) {
 635                 gvt_vgpu_err("fail to vgpu pin mm\n");
 636                 return ret;
 637         }
 638
 639         if (workload->shadow_mm->type != INTEL_GVT_MM_PPGTT ||
 640             !workload->shadow_mm->ppgtt_mm.shadowed) {
 641                 gvt_vgpu_err("workload shadow ppgtt isn't ready\n");
 642                 return -EINVAL;
 643         }
 644
 645         if (!list_empty(&workload->lri_shadow_mm)) {
 646                 list_for_each_entry(m, &workload->lri_shadow_mm,
 647                                     ppgtt_mm.link) {
 648                         ret = intel_vgpu_pin_mm(m);
 649                         if (ret) {
 650                                 list_for_each_entry_from_reverse(m,
 651                                                                  &workload->lri_shadow_mm,
 652                                                                  ppgtt_mm.link)
 653                                         intel_vgpu_unpin_mm(m);
 654                                 gvt_vgpu_err("LRI shadow ppgtt fail to pin\n");
 655                                 break;
 656                         }
 657                 }
 658         }
 659
 660         if (ret)
 661                 intel_vgpu_unpin_mm(workload->shadow_mm);
 662
 663         return ret;
 664 }
 665
 666 static void
 667 intel_vgpu_shadow_mm_unpin(struct intel_vgpu_workload *workload)
 668 {
 669         struct intel_vgpu_mm *m;
 670
 671         if (!list_empty(&workload->lri_shadow_mm)) {
 672                 list_for_each_entry(m, &workload->lri_shadow_mm,
 673                                     ppgtt_mm.link)
 674                         intel_vgpu_unpin_mm(m);
 675         }
 676         intel_vgpu_unpin_mm(workload->shadow_mm);
 677 }
 678
 679 static int prepare_workload(struct intel_vgpu_workload *workload)
 680 {
 681         struct intel_vgpu *vgpu = workload->vgpu;
 682         struct intel_vgpu_submission *s = &vgpu->submission;
 683         int ret = 0;
 684
 685         ret = intel_vgpu_shadow_mm_pin(workload);
 686         if (ret) {
 687                 gvt_vgpu_err("fail to pin shadow mm\n");
 688                 return ret;
 689         }
 690
 691         update_shadow_pdps(workload);
 692
 693         set_context_ppgtt_from_shadow(workload, s->shadow[workload->engine->id]);
 694
 695         ret = intel_vgpu_sync_oos_pages(workload->vgpu);
 696         if (ret) {
 697                 gvt_vgpu_err("fail to vgpu sync oos pages\n");
 698                 goto err_unpin_mm;
 699         }
 700
 701         ret = intel_vgpu_flush_post_shadow(workload->vgpu);
 702         if (ret) {
 703                 gvt_vgpu_err("fail to flush post shadow\n");
 704                 goto err_unpin_mm;
 705         }
 706
 707         ret = copy_workload_to_ring_buffer(workload);
 708         if (ret) {
 709                 gvt_vgpu_err("fail to generate request\n");
 710                 goto err_unpin_mm;
 711         }
 712
 713         ret = prepare_shadow_batch_buffer(workload);
 714         if (ret) {
 715                 gvt_vgpu_err("fail to prepare_shadow_batch_buffer\n");
 716                 goto err_unpin_mm;
 717         }
 718
 719         ret = prepare_shadow_wa_ctx(&workload->wa_ctx);
 720         if (ret) {
 721                 gvt_vgpu_err("fail to prepare_shadow_wa_ctx\n");
 722                 goto err_shadow_batch;
 723         }
 724
 725         if (workload->prepare) {
 726                 ret = workload->prepare(workload);
 727                 if (ret)
 728                         goto err_shadow_wa_ctx;
 729         }
 730
 731         return 0;
 732 err_shadow_wa_ctx:
 733         release_shadow_wa_ctx(&workload->wa_ctx);
 734 err_shadow_batch:
 735         release_shadow_batch_buffer(workload);
 736 err_unpin_mm:
 737         intel_vgpu_shadow_mm_unpin(workload);
 738         return ret;
 739 }
 740
 741 static int dispatch_workload(struct intel_vgpu_workload *workload)
 742 {
 743         struct intel_vgpu *vgpu = workload->vgpu;
 744         struct i915_request *rq;
 745         int ret;
 746
 747         gvt_dbg_sched("ring id %s prepare to dispatch workload %p\n",
 748                       workload->engine->name, workload);
 749
 750         mutex_lock(&vgpu->vgpu_lock);
 751
 752         ret = intel_gvt_workload_req_alloc(workload);
 753         if (ret)
 754                 goto err_req;
 755
 756         ret = intel_gvt_scan_and_shadow_workload(workload);
 757         if (ret)
 758                 goto out;
 759
 760         ret = populate_shadow_context(workload);
 761         if (ret) {
 762                 release_shadow_wa_ctx(&workload->wa_ctx);
 763                 goto out;
 764         }
 765
 766         ret = prepare_workload(workload);
 767 out:
 768         if (ret) {
 769                 /* We might still need to add request with
 770                  * clean ctx to retire it properly..
 771                  */
 772                 rq = fetch_and_zero(&workload->req);
 773                 i915_request_put(rq);
 774         }
 775
 776         if (!IS_ERR_OR_NULL(workload->req)) {
 777                 gvt_dbg_sched("ring id %s submit workload to i915 %p\n",
 778                               workload->engine->name, workload->req);
 779                 i915_request_add(workload->req);
 780                 workload->dispatched = true;
 781         }
 782 err_req:
 783         if (ret)
 784                 workload->status = ret;
 785         mutex_unlock(&vgpu->vgpu_lock);
 786         return ret;
 787 }
 788
 789 static struct intel_vgpu_workload *
 790 pick_next_workload(struct intel_gvt *gvt, struct intel_engine_cs *engine)
 791 {
 792         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 793         struct intel_vgpu_workload *workload = NULL;
 794
 795         mutex_lock(&gvt->sched_lock);
 796
 797         /*
 798          * no current vgpu / will be scheduled out / no workload
 799          * bail out
 800          */
 801         if (!scheduler->current_vgpu) {
 802                 gvt_dbg_sched("ring %s stop - no current vgpu\n", engine->name);
 803                 goto out;
 804         }
 805
 806         if (scheduler->need_reschedule) {
 807                 gvt_dbg_sched("ring %s stop - will reschedule\n", engine->name);
 808                 goto out;
 809         }
 810
 811         if (!scheduler->current_vgpu->active ||
 812             list_empty(workload_q_head(scheduler->current_vgpu, engine)))
 813                 goto out;
 814
 815         /*
 816          * still have current workload, maybe the workload disptacher
 817          * fail to submit it for some reason, resubmit it.
 818          */
 819         if (scheduler->current_workload[engine->id]) {
 820                 workload = scheduler->current_workload[engine->id];
 821                 gvt_dbg_sched("ring %s still have current workload %p\n",
 822                               engine->name, workload);
 823                 goto out;
 824         }
 825
 826         /*
 827          * pick a workload as current workload
 828          * once current workload is set, schedule policy routines
 829          * will wait the current workload is finished when trying to
 830          * schedule out a vgpu.
 831          */
 832         scheduler->current_workload[engine->id] =
 833                 list_first_entry(workload_q_head(scheduler->current_vgpu,
 834                                                  engine),
 835                                  struct intel_vgpu_workload, list);
 836
 837         workload = scheduler->current_workload[engine->id];
 838
 839         gvt_dbg_sched("ring %s pick new workload %p\n", engine->name, workload);
 840
 841         atomic_inc(&workload->vgpu->submission.running_workload_num);
 842 out:
 843         mutex_unlock(&gvt->sched_lock);
 844         return workload;
 845 }
 846
 847 static void update_guest_pdps(struct intel_vgpu *vgpu,
 848                               u64 ring_context_gpa, u32 pdp[8])
 849 {
 850         u64 gpa;
 851         int i;
 852
 853         gpa = ring_context_gpa + RING_CTX_OFF(pdps[0].val);
 854
 855         for (i = 0; i < 8; i++)
 856                 intel_gvt_hypervisor_write_gpa(vgpu,
 857                                 gpa + i * 8, &pdp[7 - i], 4);
 858 }
 859
 860 static __maybe_unused bool
 861 check_shadow_context_ppgtt(struct execlist_ring_context *c, struct intel_vgpu_mm *m)
 862 {
 863         if (m->ppgtt_mm.root_entry_type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY) {
 864                 u64 shadow_pdp = c->pdps[7].val | (u64) c->pdps[6].val << 32;
 865
 866                 if (shadow_pdp != m->ppgtt_mm.shadow_pdps[0]) {
 867                         gvt_dbg_mm("4-level context ppgtt not match LRI command\n");
 868                         return false;
 869                 }
 870                 return true;
 871         } else {
 872                 /* see comment in LRI handler in cmd_parser.c */
 873                 gvt_dbg_mm("invalid shadow mm type\n");
 874                 return false;
 875         }
 876 }
 877
 878 static void update_guest_context(struct intel_vgpu_workload *workload)
 879 {
 880         struct i915_request *rq = workload->req;
 881         struct intel_vgpu *vgpu = workload->vgpu;
 882         struct execlist_ring_context *shadow_ring_context;
 883         struct intel_context *ctx = workload->req->context;
 884         void *context_base;
 885         void *src;
 886         unsigned long context_gpa, context_page_num;
 887         unsigned long gpa_base; /* first gpa of consecutive GPAs */
 888         unsigned long gpa_size; /* size of consecutive GPAs*/
 889         int i;
 890         u32 ring_base;
 891         u32 head, tail;
 892         u16 wrap_count;
 893
 894         gvt_dbg_sched("ring id %d workload lrca %x\n", rq->engine->id,
 895                       workload->ctx_desc.lrca);
 896
 897         GEM_BUG_ON(!intel_context_is_pinned(ctx));
 898
 899         head = workload->rb_head;
 900         tail = workload->rb_tail;
 901         wrap_count = workload->guest_rb_head >> RB_HEAD_WRAP_CNT_OFF;
 902
 903         if (tail < head) {
 904                 if (wrap_count == RB_HEAD_WRAP_CNT_MAX)
 905                         wrap_count = 0;
 906                 else
 907                         wrap_count += 1;
 908         }
 909
 910         head = (wrap_count << RB_HEAD_WRAP_CNT_OFF) | tail;
 911
 912         ring_base = rq->engine->mmio_base;
 913         vgpu_vreg_t(vgpu, RING_TAIL(ring_base)) = tail;
 914         vgpu_vreg_t(vgpu, RING_HEAD(ring_base)) = head;
 915
 916         context_page_num = rq->engine->context_size;
 917         context_page_num = context_page_num >> PAGE_SHIFT;
 918
 919         if (IS_BROADWELL(rq->engine->i915) && rq->engine->id == RCS0)
 920                 context_page_num = 19;
 921
 922         context_base = (void *) ctx->lrc_reg_state -
 923                         (LRC_STATE_PN << I915_GTT_PAGE_SHIFT);
 924
 925         /* find consecutive GPAs from gma until the first inconsecutive GPA.
 926          * write to the consecutive GPAs from src virtual address
 927          */
 928         gpa_size = 0;
 929         for (i = 2; i < context_page_num; i++) {
 930                 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
 931                                 (u32)((workload->ctx_desc.lrca + i) <<
 932                                         I915_GTT_PAGE_SHIFT));
 933                 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
 934                         gvt_vgpu_err("invalid guest context descriptor\n");
 935                         return;
 936                 }
 937
 938                 if (gpa_size == 0) {
 939                         gpa_base = context_gpa;
 940                         src = context_base + (i << I915_GTT_PAGE_SHIFT);
 941                 } else if (context_gpa != gpa_base + gpa_size)
 942                         goto write;
 943
 944                 gpa_size += I915_GTT_PAGE_SIZE;
 945
 946                 if (i == context_page_num - 1)
 947                         goto write;
 948
 949                 continue;
 950
 951 write:
 952                 intel_gvt_hypervisor_write_gpa(vgpu, gpa_base, src, gpa_size);
 953                 gpa_base = context_gpa;
 954                 gpa_size = I915_GTT_PAGE_SIZE;
 955                 src = context_base + (i << I915_GTT_PAGE_SHIFT);
 956         }
 957
 958         intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa +
 959                 RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4);
 960
 961         shadow_ring_context = (void *) ctx->lrc_reg_state;
 962
 963         if (!list_empty(&workload->lri_shadow_mm)) {
 964                 struct intel_vgpu_mm *m = list_last_entry(&workload->lri_shadow_mm,
 965                                                           struct intel_vgpu_mm,
 966                                                           ppgtt_mm.link);
 967                 GEM_BUG_ON(!check_shadow_context_ppgtt(shadow_ring_context, m));
 968                 update_guest_pdps(vgpu, workload->ring_context_gpa,
 969                                   (void *)m->ppgtt_mm.guest_pdps);
 970         }
 971
 972 #define COPY_REG(name) \
 973         intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \
 974                 RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
 975
 976         COPY_REG(ctx_ctrl);
 977         COPY_REG(ctx_timestamp);
 978
 979 #undef COPY_REG
 980
 981         intel_gvt_hypervisor_write_gpa(vgpu,
 982                         workload->ring_context_gpa +
 983                         sizeof(*shadow_ring_context),
 984                         (void *)shadow_ring_context +
 985                         sizeof(*shadow_ring_context),
 986                         I915_GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
 987 }
 988
 989 void intel_vgpu_clean_workloads(struct intel_vgpu *vgpu,
 990                                 intel_engine_mask_t engine_mask)
 991 {
 992         struct intel_vgpu_submission *s = &vgpu->submission;
 993         struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
 994         struct intel_engine_cs *engine;
 995         struct intel_vgpu_workload *pos, *n;
 996         intel_engine_mask_t tmp;
 997
 998         /* free the unsubmited workloads in the queues. */
 999         for_each_engine_masked(engine, &dev_priv->gt, engine_mask, tmp) {
1000                 list_for_each_entry_safe(pos, n,
1001                         &s->workload_q_head[engine->id], list) {
1002                         list_del_init(&pos->list);
1003                         intel_vgpu_destroy_workload(pos);
1004                 }
1005                 clear_bit(engine->id, s->shadow_ctx_desc_updated);
1006         }
1007 }
1008
1009 static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
1010 {
1011         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1012         struct intel_vgpu_workload *workload =
1013                 scheduler->current_workload[ring_id];
1014         struct intel_vgpu *vgpu = workload->vgpu;
1015         struct intel_vgpu_submission *s = &vgpu->submission;
1016         struct i915_request *rq = workload->req;
1017         int event;
1018
1019         mutex_lock(&vgpu->vgpu_lock);
1020         mutex_lock(&gvt->sched_lock);
1021
1022         /* For the workload w/ request, needs to wait for the context
1023          * switch to make sure request is completed.
1024          * For the workload w/o request, directly complete the workload.
1025          */
1026         if (rq) {
1027                 wait_event(workload->shadow_ctx_status_wq,
1028                            !atomic_read(&workload->shadow_ctx_active));
1029
1030                 /* If this request caused GPU hang, req->fence.error will
1031                  * be set to -EIO. Use -EIO to set workload status so
1032                  * that when this request caused GPU hang, didn't trigger
1033                  * context switch interrupt to guest.
1034                  */
1035                 if (likely(workload->status == -EINPROGRESS)) {
1036                         if (workload->req->fence.error == -EIO)
1037                                 workload->status = -EIO;
1038                         else
1039                                 workload->status = 0;
1040                 }
1041
1042                 if (!workload->status &&
1043                     !(vgpu->resetting_eng & BIT(ring_id))) {
1044                         update_guest_context(workload);
1045
1046                         for_each_set_bit(event, workload->pending_events,
1047                                          INTEL_GVT_EVENT_MAX)
1048                                 intel_vgpu_trigger_virtual_event(vgpu, event);
1049                 }
1050
1051                 i915_request_put(fetch_and_zero(&workload->req));
1052         }
1053
1054         gvt_dbg_sched("ring id %d complete workload %p status %d\n",
1055                         ring_id, workload, workload->status);
1056
1057         scheduler->current_workload[ring_id] = NULL;
1058
1059         list_del_init(&workload->list);
1060
1061         if (workload->status || vgpu->resetting_eng & BIT(ring_id)) {
1062                 /* if workload->status is not successful means HW GPU
1063                  * has occurred GPU hang or something wrong with i915/GVT,
1064                  * and GVT won't inject context switch interrupt to guest.
1065                  * So this error is a vGPU hang actually to the guest.
1066                  * According to this we should emunlate a vGPU hang. If
1067                  * there are pending workloads which are already submitted
1068                  * from guest, we should clean them up like HW GPU does.
1069                  *
1070                  * if it is in middle of engine resetting, the pending
1071                  * workloads won't be submitted to HW GPU and will be
1072                  * cleaned up during the resetting process later, so doing
1073                  * the workload clean up here doesn't have any impact.
1074                  **/
1075                 intel_vgpu_clean_workloads(vgpu, BIT(ring_id));
1076         }
1077
1078         workload->complete(workload);
1079
1080         intel_vgpu_shadow_mm_unpin(workload);
1081         intel_vgpu_destroy_workload(workload);
1082
1083         atomic_dec(&s->running_workload_num);
1084         wake_up(&scheduler->workload_complete_wq);
1085
1086         if (gvt->scheduler.need_reschedule)
1087                 intel_gvt_request_service(gvt, INTEL_GVT_REQUEST_EVENT_SCHED);
1088
1089         mutex_unlock(&gvt->sched_lock);
1090         mutex_unlock(&vgpu->vgpu_lock);
1091 }
1092
1093 static int workload_thread(void *arg)
1094 {
1095         struct intel_engine_cs *engine = arg;
1096         const bool need_force_wake = INTEL_GEN(engine->i915) >= 9;
1097         struct intel_gvt *gvt = engine->i915->gvt;
1098         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1099         struct intel_vgpu_workload *workload = NULL;
1100         struct intel_vgpu *vgpu = NULL;
1101         int ret;
1102         DEFINE_WAIT_FUNC(wait, woken_wake_function);
1103
1104         gvt_dbg_core("workload thread for ring %s started\n", engine->name);
1105
1106         while (!kthread_should_stop()) {
1107                 intel_wakeref_t wakeref;
1108
1109                 add_wait_queue(&scheduler->waitq[engine->id], &wait);
1110                 do {
1111                         workload = pick_next_workload(gvt, engine);
1112                         if (workload)
1113                                 break;
1114                         wait_woken(&wait, TASK_INTERRUPTIBLE,
1115                                    MAX_SCHEDULE_TIMEOUT);
1116                 } while (!kthread_should_stop());
1117                 remove_wait_queue(&scheduler->waitq[engine->id], &wait);
1118
1119                 if (!workload)
1120                         break;
1121
1122                 gvt_dbg_sched("ring %s next workload %p vgpu %d\n",
1123                               engine->name, workload,
1124                               workload->vgpu->id);
1125
1126                 wakeref = intel_runtime_pm_get(engine->uncore->rpm);
1127
1128                 gvt_dbg_sched("ring %s will dispatch workload %p\n",
1129                               engine->name, workload);
1130
1131                 if (need_force_wake)
1132                         intel_uncore_forcewake_get(engine->uncore,
1133                                                    FORCEWAKE_ALL);
1134                 /*
1135                  * Update the vReg of the vGPU which submitted this
1136                  * workload. The vGPU may use these registers for checking
1137                  * the context state. The value comes from GPU commands
1138                  * in this workload.
1139                  */
1140                 update_vreg_in_ctx(workload);
1141
1142                 ret = dispatch_workload(workload);
1143
1144                 if (ret) {
1145                         vgpu = workload->vgpu;
1146                         gvt_vgpu_err("fail to dispatch workload, skip\n");
1147                         goto complete;
1148                 }
1149
1150                 gvt_dbg_sched("ring %s wait workload %p\n",
1151                               engine->name, workload);
1152                 i915_request_wait(workload->req, 0, MAX_SCHEDULE_TIMEOUT);
1153
1154 complete:
1155                 gvt_dbg_sched("will complete workload %p, status: %d\n",
1156                               workload, workload->status);
1157
1158                 complete_current_workload(gvt, engine->id);
1159
1160                 if (need_force_wake)
1161                         intel_uncore_forcewake_put(engine->uncore,
1162                                                    FORCEWAKE_ALL);
1163
1164                 intel_runtime_pm_put(engine->uncore->rpm, wakeref);
1165                 if (ret && (vgpu_is_vm_unhealthy(ret)))
1166                         enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1167         }
1168         return 0;
1169 }
1170
1171 void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu)
1172 {
1173         struct intel_vgpu_submission *s = &vgpu->submission;
1174         struct intel_gvt *gvt = vgpu->gvt;
1175         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1176
1177         if (atomic_read(&s->running_workload_num)) {
1178                 gvt_dbg_sched("wait vgpu idle\n");
1179
1180                 wait_event(scheduler->workload_complete_wq,
1181                                 !atomic_read(&s->running_workload_num));
1182         }
1183 }
1184
1185 void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt)
1186 {
1187         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1188         struct intel_engine_cs *engine;
1189         enum intel_engine_id i;
1190
1191         gvt_dbg_core("clean workload scheduler\n");
1192
1193         for_each_engine(engine, gvt->gt, i) {
1194                 atomic_notifier_chain_unregister(
1195                                         &engine->context_status_notifier,
1196                                         &gvt->shadow_ctx_notifier_block[i]);
1197                 kthread_stop(scheduler->thread[i]);
1198         }
1199 }
1200
1201 int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt)
1202 {
1203         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
1204         struct intel_engine_cs *engine;
1205         enum intel_engine_id i;
1206         int ret;
1207
1208         gvt_dbg_core("init workload scheduler\n");
1209
1210         init_waitqueue_head(&scheduler->workload_complete_wq);
1211
1212         for_each_engine(engine, gvt->gt, i) {
1213                 init_waitqueue_head(&scheduler->waitq[i]);
1214
1215                 scheduler->thread[i] = kthread_run(workload_thread, engine,
1216                                                    "gvt:%s", engine->name);
1217                 if (IS_ERR(scheduler->thread[i])) {
1218                         gvt_err("fail to create workload thread\n");
1219                         ret = PTR_ERR(scheduler->thread[i]);
1220                         goto err;
1221                 }
1222
1223                 gvt->shadow_ctx_notifier_block[i].notifier_call =
1224                                         shadow_context_status_change;
1225                 atomic_notifier_chain_register(&engine->context_status_notifier,
1226                                         &gvt->shadow_ctx_notifier_block[i]);
1227         }
1228
1229         return 0;
1230
1231 err:
1232         intel_gvt_clean_workload_scheduler(gvt);
1233         return ret;
1234 }
1235
1236 static void
1237 i915_context_ppgtt_root_restore(struct intel_vgpu_submission *s,
1238                                 struct i915_ppgtt *ppgtt)
1239 {
1240         int i;
1241
1242         if (i915_vm_is_4lvl(&ppgtt->vm)) {
1243                 px_dma(ppgtt->pd) = s->i915_context_pml4;
1244         } else {
1245                 for (i = 0; i < GEN8_3LVL_PDPES; i++) {
1246                         struct i915_page_directory * const pd =
1247                                 i915_pd_entry(ppgtt->pd, i);
1248
1249                         px_dma(pd) = s->i915_context_pdps[i];
1250                 }
1251         }
1252 }
1253
1254 /**
1255  * intel_vgpu_clean_submission - free submission-related resource for vGPU
1256  * @vgpu: a vGPU
1257  *
1258  * This function is called when a vGPU is being destroyed.
1259  *
1260  */
1261 void intel_vgpu_clean_submission(struct intel_vgpu *vgpu)
1262 {
1263         struct intel_vgpu_submission *s = &vgpu->submission;
1264         struct intel_engine_cs *engine;
1265         enum intel_engine_id id;
1266
1267         intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
1268
1269         i915_context_ppgtt_root_restore(s, i915_vm_to_ppgtt(s->shadow[0]->vm));
1270         for_each_engine(engine, vgpu->gvt->gt, id)
1271                 intel_context_unpin(s->shadow[id]);
1272
1273         kmem_cache_destroy(s->workloads);
1274 }
1275
1276
1277 /**
1278  * intel_vgpu_reset_submission - reset submission-related resource for vGPU
1279  * @vgpu: a vGPU
1280  * @engine_mask: engines expected to be reset
1281  *
1282  * This function is called when a vGPU is being destroyed.
1283  *
1284  */
1285 void intel_vgpu_reset_submission(struct intel_vgpu *vgpu,
1286                                  intel_engine_mask_t engine_mask)
1287 {
1288         struct intel_vgpu_submission *s = &vgpu->submission;
1289
1290         if (!s->active)
1291                 return;
1292
1293         intel_vgpu_clean_workloads(vgpu, engine_mask);
1294         s->ops->reset(vgpu, engine_mask);
1295 }
1296
1297 static void
1298 i915_context_ppgtt_root_save(struct intel_vgpu_submission *s,
1299                              struct i915_ppgtt *ppgtt)
1300 {
1301         int i;
1302
1303         if (i915_vm_is_4lvl(&ppgtt->vm)) {
1304                 s->i915_context_pml4 = px_dma(ppgtt->pd);
1305         } else {
1306                 for (i = 0; i < GEN8_3LVL_PDPES; i++) {
1307                         struct i915_page_directory * const pd =
1308                                 i915_pd_entry(ppgtt->pd, i);
1309
1310                         s->i915_context_pdps[i] = px_dma(pd);
1311                 }
1312         }
1313 }
1314
1315 /**
1316  * intel_vgpu_setup_submission - setup submission-related resource for vGPU
1317  * @vgpu: a vGPU
1318  *
1319  * This function is called when a vGPU is being created.
1320  *
1321  * Returns:
1322  * Zero on success, negative error code if failed.
1323  *
1324  */
1325 int intel_vgpu_setup_submission(struct intel_vgpu *vgpu)
1326 {
1327         struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1328         struct intel_vgpu_submission *s = &vgpu->submission;
1329         struct intel_engine_cs *engine;
1330         struct i915_ppgtt *ppgtt;
1331         enum intel_engine_id i;
1332         int ret;
1333
1334         ppgtt = i915_ppgtt_create(&i915->gt);
1335         if (IS_ERR(ppgtt))
1336                 return PTR_ERR(ppgtt);
1337
1338         i915_context_ppgtt_root_save(s, ppgtt);
1339
1340         for_each_engine(engine, vgpu->gvt->gt, i) {
1341                 struct intel_context *ce;
1342
1343                 INIT_LIST_HEAD(&s->workload_q_head[i]);
1344                 s->shadow[i] = ERR_PTR(-EINVAL);
1345
1346                 ce = intel_context_create(engine);
1347                 if (IS_ERR(ce)) {
1348                         ret = PTR_ERR(ce);
1349                         goto out_shadow_ctx;
1350                 }
1351
1352                 i915_vm_put(ce->vm);
1353                 ce->vm = i915_vm_get(&ppgtt->vm);
1354                 intel_context_set_single_submission(ce);
1355
1356                 /* Max ring buffer size */
1357                 if (!intel_uc_wants_guc_submission(&engine->gt->uc)) {
1358                         const unsigned int ring_size = 512 * SZ_4K;
1359
1360                         ce->ring = __intel_context_ring_size(ring_size);
1361                 }
1362
1363                 ret = intel_context_pin(ce);
1364                 intel_context_put(ce);
1365                 if (ret)
1366                         goto out_shadow_ctx;
1367
1368                 s->shadow[i] = ce;
1369         }
1370
1371         bitmap_zero(s->shadow_ctx_desc_updated, I915_NUM_ENGINES);
1372
1373         s->workloads = kmem_cache_create_usercopy("gvt-g_vgpu_workload",
1374                                                   sizeof(struct intel_vgpu_workload), 0,
1375                                                   SLAB_HWCACHE_ALIGN,
1376                                                   offsetof(struct intel_vgpu_workload, rb_tail),
1377                                                   sizeof_field(struct intel_vgpu_workload, rb_tail),
1378                                                   NULL);
1379
1380         if (!s->workloads) {
1381                 ret = -ENOMEM;
1382                 goto out_shadow_ctx;
1383         }
1384
1385         atomic_set(&s->running_workload_num, 0);
1386         bitmap_zero(s->tlb_handle_pending, I915_NUM_ENGINES);
1387
1388         memset(s->last_ctx, 0, sizeof(s->last_ctx));
1389
1390         i915_vm_put(&ppgtt->vm);
1391         return 0;
1392
1393 out_shadow_ctx:
1394         i915_context_ppgtt_root_restore(s, ppgtt);
1395         for_each_engine(engine, vgpu->gvt->gt, i) {
1396                 if (IS_ERR(s->shadow[i]))
1397                         break;
1398
1399                 intel_context_unpin(s->shadow[i]);
1400                 intel_context_put(s->shadow[i]);
1401         }
1402         i915_vm_put(&ppgtt->vm);
1403         return ret;
1404 }
1405
1406 /**
1407  * intel_vgpu_select_submission_ops - select virtual submission interface
1408  * @vgpu: a vGPU
1409  * @engine_mask: either ALL_ENGINES or target engine mask
1410  * @interface: expected vGPU virtual submission interface
1411  *
1412  * This function is called when guest configures submission interface.
1413  *
1414  * Returns:
1415  * Zero on success, negative error code if failed.
1416  *
1417  */
1418 int intel_vgpu_select_submission_ops(struct intel_vgpu *vgpu,
1419                                      intel_engine_mask_t engine_mask,
1420                                      unsigned int interface)
1421 {
1422         struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
1423         struct intel_vgpu_submission *s = &vgpu->submission;
1424         const struct intel_vgpu_submission_ops *ops[] = {
1425                 [INTEL_VGPU_EXECLIST_SUBMISSION] =
1426                         &intel_vgpu_execlist_submission_ops,
1427         };
1428         int ret;
1429
1430         if (drm_WARN_ON(&i915->drm, interface >= ARRAY_SIZE(ops)))
1431                 return -EINVAL;
1432
1433         if (drm_WARN_ON(&i915->drm,
1434                         interface == 0 && engine_mask != ALL_ENGINES))
1435                 return -EINVAL;
1436
1437         if (s->active)
1438                 s->ops->clean(vgpu, engine_mask);
1439
1440         if (interface == 0) {
1441                 s->ops = NULL;
1442                 s->virtual_submission_interface = 0;
1443                 s->active = false;
1444                 gvt_dbg_core("vgpu%d: remove submission ops\n", vgpu->id);
1445                 return 0;
1446         }
1447
1448         ret = ops[interface]->init(vgpu, engine_mask);
1449         if (ret)
1450                 return ret;
1451
1452         s->ops = ops[interface];
1453         s->virtual_submission_interface = interface;
1454         s->active = true;
1455
1456         gvt_dbg_core("vgpu%d: activate ops [ %s ]\n",
1457                         vgpu->id, s->ops->name);
1458
1459         return 0;
1460 }
1461
1462 /**
1463  * intel_vgpu_destroy_workload - destroy a vGPU workload
1464  * @workload: workload to destroy
1465  *
1466  * This function is called when destroy a vGPU workload.
1467  *
1468  */
1469 void intel_vgpu_destroy_workload(struct intel_vgpu_workload *workload)
1470 {
1471         struct intel_vgpu_submission *s = &workload->vgpu->submission;
1472
1473         release_shadow_batch_buffer(workload);
1474         release_shadow_wa_ctx(&workload->wa_ctx);
1475
1476         if (!list_empty(&workload->lri_shadow_mm)) {
1477                 struct intel_vgpu_mm *m, *mm;
1478                 list_for_each_entry_safe(m, mm, &workload->lri_shadow_mm,
1479                                          ppgtt_mm.link) {
1480                         list_del(&m->ppgtt_mm.link);
1481                         intel_vgpu_mm_put(m);
1482                 }
1483         }
1484
1485         GEM_BUG_ON(!list_empty(&workload->lri_shadow_mm));
1486         if (workload->shadow_mm)
1487                 intel_vgpu_mm_put(workload->shadow_mm);
1488
1489         kmem_cache_free(s->workloads, workload);
1490 }
1491
1492 static struct intel_vgpu_workload *
1493 alloc_workload(struct intel_vgpu *vgpu)
1494 {
1495         struct intel_vgpu_submission *s = &vgpu->submission;
1496         struct intel_vgpu_workload *workload;
1497
1498         workload = kmem_cache_zalloc(s->workloads, GFP_KERNEL);
1499         if (!workload)
1500                 return ERR_PTR(-ENOMEM);
1501
1502         INIT_LIST_HEAD(&workload->list);
1503         INIT_LIST_HEAD(&workload->shadow_bb);
1504         INIT_LIST_HEAD(&workload->lri_shadow_mm);
1505
1506         init_waitqueue_head(&workload->shadow_ctx_status_wq);
1507         atomic_set(&workload->shadow_ctx_active, 0);
1508
1509         workload->status = -EINPROGRESS;
1510         workload->vgpu = vgpu;
1511
1512         return workload;
1513 }
1514
1515 #define RING_CTX_OFF(x) \
1516         offsetof(struct execlist_ring_context, x)
1517
1518 static void read_guest_pdps(struct intel_vgpu *vgpu,
1519                 u64 ring_context_gpa, u32 pdp[8])
1520 {
1521         u64 gpa;
1522         int i;
1523
1524         gpa = ring_context_gpa + RING_CTX_OFF(pdps[0].val);
1525
1526         for (i = 0; i < 8; i++)
1527                 intel_gvt_hypervisor_read_gpa(vgpu,
1528                                 gpa + i * 8, &pdp[7 - i], 4);
1529 }
1530
1531 static int prepare_mm(struct intel_vgpu_workload *workload)
1532 {
1533         struct execlist_ctx_descriptor_format *desc = &workload->ctx_desc;
1534         struct intel_vgpu_mm *mm;
1535         struct intel_vgpu *vgpu = workload->vgpu;
1536         enum intel_gvt_gtt_type root_entry_type;
1537         u64 pdps[GVT_RING_CTX_NR_PDPS];
1538
1539         switch (desc->addressing_mode) {
1540         case 1: /* legacy 32-bit */
1541                 root_entry_type = GTT_TYPE_PPGTT_ROOT_L3_ENTRY;
1542                 break;
1543         case 3: /* legacy 64-bit */
1544                 root_entry_type = GTT_TYPE_PPGTT_ROOT_L4_ENTRY;
1545                 break;
1546         default:
1547                 gvt_vgpu_err("Advanced Context mode(SVM) is not supported!\n");
1548                 return -EINVAL;
1549         }
1550
1551         read_guest_pdps(workload->vgpu, workload->ring_context_gpa, (void *)pdps);
1552
1553         mm = intel_vgpu_get_ppgtt_mm(workload->vgpu, root_entry_type, pdps);
1554         if (IS_ERR(mm))
1555                 return PTR_ERR(mm);
1556
1557         workload->shadow_mm = mm;
1558         return 0;
1559 }
1560
1561 #define same_context(a, b) (((a)->context_id == (b)->context_id) && \
1562                 ((a)->lrca == (b)->lrca))
1563
1564 /**
1565  * intel_vgpu_create_workload - create a vGPU workload
1566  * @vgpu: a vGPU
1567  * @engine: the engine
1568  * @desc: a guest context descriptor
1569  *
1570  * This function is called when creating a vGPU workload.
1571  *
1572  * Returns:
1573  * struct intel_vgpu_workload * on success, negative error code in
1574  * pointer if failed.
1575  *
1576  */
1577 struct intel_vgpu_workload *
1578 intel_vgpu_create_workload(struct intel_vgpu *vgpu,
1579                            const struct intel_engine_cs *engine,
1580                            struct execlist_ctx_descriptor_format *desc)
1581 {
1582         struct intel_vgpu_submission *s = &vgpu->submission;
1583         struct list_head *q = workload_q_head(vgpu, engine);
1584         struct intel_vgpu_workload *last_workload = NULL;
1585         struct intel_vgpu_workload *workload = NULL;
1586         u64 ring_context_gpa;
1587         u32 head, tail, start, ctl, ctx_ctl, per_ctx, indirect_ctx;
1588         u32 guest_head;
1589         int ret;
1590
1591         ring_context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
1592                         (u32)((desc->lrca + 1) << I915_GTT_PAGE_SHIFT));
1593         if (ring_context_gpa == INTEL_GVT_INVALID_ADDR) {
1594                 gvt_vgpu_err("invalid guest context LRCA: %x\n", desc->lrca);
1595                 return ERR_PTR(-EINVAL);
1596         }
1597
1598         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1599                         RING_CTX_OFF(ring_header.val), &head, 4);
1600
1601         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1602                         RING_CTX_OFF(ring_tail.val), &tail, 4);
1603
1604         guest_head = head;
1605
1606         head &= RB_HEAD_OFF_MASK;
1607         tail &= RB_TAIL_OFF_MASK;
1608
1609         list_for_each_entry_reverse(last_workload, q, list) {
1610
1611                 if (same_context(&last_workload->ctx_desc, desc)) {
1612                         gvt_dbg_el("ring %s cur workload == last\n",
1613                                    engine->name);
1614                         gvt_dbg_el("ctx head %x real head %lx\n", head,
1615                                    last_workload->rb_tail);
1616                         /*
1617                          * cannot use guest context head pointer here,
1618                          * as it might not be updated at this time
1619                          */
1620                         head = last_workload->rb_tail;
1621                         break;
1622                 }
1623         }
1624
1625         gvt_dbg_el("ring %s begin a new workload\n", engine->name);
1626
1627         /* record some ring buffer register values for scan and shadow */
1628         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1629                         RING_CTX_OFF(rb_start.val), &start, 4);
1630         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1631                         RING_CTX_OFF(rb_ctrl.val), &ctl, 4);
1632         intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1633                         RING_CTX_OFF(ctx_ctrl.val), &ctx_ctl, 4);
1634
1635         if (!intel_gvt_ggtt_validate_range(vgpu, start,
1636                                 _RING_CTL_BUF_SIZE(ctl))) {
1637                 gvt_vgpu_err("context contain invalid rb at: 0x%x\n", start);
1638                 return ERR_PTR(-EINVAL);
1639         }
1640
1641         workload = alloc_workload(vgpu);
1642         if (IS_ERR(workload))
1643                 return workload;
1644
1645         workload->engine = engine;
1646         workload->ctx_desc = *desc;
1647         workload->ring_context_gpa = ring_context_gpa;
1648         workload->rb_head = head;
1649         workload->guest_rb_head = guest_head;
1650         workload->rb_tail = tail;
1651         workload->rb_start = start;
1652         workload->rb_ctl = ctl;
1653
1654         if (engine->id == RCS0) {
1655                 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1656                         RING_CTX_OFF(bb_per_ctx_ptr.val), &per_ctx, 4);
1657                 intel_gvt_hypervisor_read_gpa(vgpu, ring_context_gpa +
1658                         RING_CTX_OFF(rcs_indirect_ctx.val), &indirect_ctx, 4);
1659
1660                 workload->wa_ctx.indirect_ctx.guest_gma =
1661                         indirect_ctx & INDIRECT_CTX_ADDR_MASK;
1662                 workload->wa_ctx.indirect_ctx.size =
1663                         (indirect_ctx & INDIRECT_CTX_SIZE_MASK) *
1664                         CACHELINE_BYTES;
1665
1666                 if (workload->wa_ctx.indirect_ctx.size != 0) {
1667                         if (!intel_gvt_ggtt_validate_range(vgpu,
1668                                 workload->wa_ctx.indirect_ctx.guest_gma,
1669                                 workload->wa_ctx.indirect_ctx.size)) {
1670                                 gvt_vgpu_err("invalid wa_ctx at: 0x%lx\n",
1671                                     workload->wa_ctx.indirect_ctx.guest_gma);
1672                                 kmem_cache_free(s->workloads, workload);
1673                                 return ERR_PTR(-EINVAL);
1674                         }
1675                 }
1676
1677                 workload->wa_ctx.per_ctx.guest_gma =
1678                         per_ctx & PER_CTX_ADDR_MASK;
1679                 workload->wa_ctx.per_ctx.valid = per_ctx & 1;
1680                 if (workload->wa_ctx.per_ctx.valid) {
1681                         if (!intel_gvt_ggtt_validate_range(vgpu,
1682                                 workload->wa_ctx.per_ctx.guest_gma,
1683                                 CACHELINE_BYTES)) {
1684                                 gvt_vgpu_err("invalid per_ctx at: 0x%lx\n",
1685                                         workload->wa_ctx.per_ctx.guest_gma);
1686                                 kmem_cache_free(s->workloads, workload);
1687                                 return ERR_PTR(-EINVAL);
1688                         }
1689                 }
1690         }
1691
1692         gvt_dbg_el("workload %p ring %s head %x tail %x start %x ctl %x\n",
1693                    workload, engine->name, head, tail, start, ctl);
1694
1695         ret = prepare_mm(workload);
1696         if (ret) {
1697                 kmem_cache_free(s->workloads, workload);
1698                 return ERR_PTR(ret);
1699         }
1700
1701         /* Only scan and shadow the first workload in the queue
1702          * as there is only one pre-allocated buf-obj for shadow.
1703          */
1704         if (list_empty(q)) {
1705                 intel_wakeref_t wakeref;
1706
1707                 with_intel_runtime_pm(engine->gt->uncore->rpm, wakeref)
1708                         ret = intel_gvt_scan_and_shadow_workload(workload);
1709         }
1710
1711         if (ret) {
1712                 if (vgpu_is_vm_unhealthy(ret))
1713                         enter_failsafe_mode(vgpu, GVT_FAILSAFE_GUEST_ERR);
1714                 intel_vgpu_destroy_workload(workload);
1715                 return ERR_PTR(ret);
1716         }
1717
1718         return workload;
1719 }
1720
1721 /**
1722  * intel_vgpu_queue_workload - Qeue a vGPU workload
1723  * @workload: the workload to queue in
1724  */
1725 void intel_vgpu_queue_workload(struct intel_vgpu_workload *workload)
1726 {
1727         list_add_tail(&workload->list,
1728                       workload_q_head(workload->vgpu, workload->engine));
1729         intel_gvt_kick_schedule(workload->vgpu->gvt);
1730         wake_up(&workload->vgpu->gvt->scheduler.waitq[workload->engine->id]);
1731 }