drivers/gpu/drm/i915/display/intel_hdmi.c

   1 /*
   2  * Copyright 2006 Dave Airlie <[email protected]>
   3  * Copyright © 2006-2009 Intel Corporation
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <[email protected]>
  26  *      Jesse Barnes <[email protected]>
  27  */
  28
  29 #include <linux/delay.h>
  30 #include <linux/hdmi.h>
  31 #include <linux/i2c.h>
  32 #include <linux/slab.h>
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_edid.h>
  37 #include <drm/drm_hdcp.h>
  38 #include <drm/drm_scdc_helper.h>
  39 #include <drm/intel_lpe_audio.h>
  40
  41 #include "i915_debugfs.h"
  42 #include "i915_drv.h"
  43 #include "intel_atomic.h"
  44 #include "intel_audio.h"
  45 #include "intel_connector.h"
  46 #include "intel_ddi.h"
  47 #include "intel_display_types.h"
  48 #include "intel_dp.h"
  49 #include "intel_dpio_phy.h"
  50 #include "intel_fifo_underrun.h"
  51 #include "intel_gmbus.h"
  52 #include "intel_hdcp.h"
  53 #include "intel_hdmi.h"
  54 #include "intel_hotplug.h"
  55 #include "intel_lspcon.h"
  56 #include "intel_panel.h"
  57 #include "intel_sdvo.h"
  58 #include "intel_sideband.h"
  59
  60 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
  61 {
  62         return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
  63 }
  64
  65 static void
  66 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  67 {
  68         struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
  69         struct drm_i915_private *dev_priv = to_i915(dev);
  70         u32 enabled_bits;
  71
  72         enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  73
  74         drm_WARN(dev,
  75                  intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits,
  76                  "HDMI port enabled, expecting disabled\n");
  77 }
  78
  79 static void
  80 assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
  81                                      enum transcoder cpu_transcoder)
  82 {
  83         drm_WARN(&dev_priv->drm,
  84                  intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
  85                  TRANS_DDI_FUNC_ENABLE,
  86                  "HDMI transcoder function enabled, expecting disabled\n");
  87 }
  88
  89 struct intel_hdmi *enc_to_intel_hdmi(struct intel_encoder *encoder)
  90 {
  91         struct intel_digital_port *dig_port =
  92                 container_of(&encoder->base, struct intel_digital_port,
  93                              base.base);
  94         return &dig_port->hdmi;
  95 }
  96
  97 static struct intel_hdmi *intel_attached_hdmi(struct intel_connector *connector)
  98 {
  99         return enc_to_intel_hdmi(intel_attached_encoder(connector));
 100 }
 101
 102 static u32 g4x_infoframe_index(unsigned int type)
 103 {
 104         switch (type) {
 105         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 106                 return VIDEO_DIP_SELECT_GAMUT;
 107         case HDMI_INFOFRAME_TYPE_AVI:
 108                 return VIDEO_DIP_SELECT_AVI;
 109         case HDMI_INFOFRAME_TYPE_SPD:
 110                 return VIDEO_DIP_SELECT_SPD;
 111         case HDMI_INFOFRAME_TYPE_VENDOR:
 112                 return VIDEO_DIP_SELECT_VENDOR;
 113         default:
 114                 MISSING_CASE(type);
 115                 return 0;
 116         }
 117 }
 118
 119 static u32 g4x_infoframe_enable(unsigned int type)
 120 {
 121         switch (type) {
 122         case HDMI_PACKET_TYPE_GENERAL_CONTROL:
 123                 return VIDEO_DIP_ENABLE_GCP;
 124         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 125                 return VIDEO_DIP_ENABLE_GAMUT;
 126         case DP_SDP_VSC:
 127                 return 0;
 128         case HDMI_INFOFRAME_TYPE_AVI:
 129                 return VIDEO_DIP_ENABLE_AVI;
 130         case HDMI_INFOFRAME_TYPE_SPD:
 131                 return VIDEO_DIP_ENABLE_SPD;
 132         case HDMI_INFOFRAME_TYPE_VENDOR:
 133                 return VIDEO_DIP_ENABLE_VENDOR;
 134         case HDMI_INFOFRAME_TYPE_DRM:
 135                 return 0;
 136         default:
 137                 MISSING_CASE(type);
 138                 return 0;
 139         }
 140 }
 141
 142 static u32 hsw_infoframe_enable(unsigned int type)
 143 {
 144         switch (type) {
 145         case HDMI_PACKET_TYPE_GENERAL_CONTROL:
 146                 return VIDEO_DIP_ENABLE_GCP_HSW;
 147         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 148                 return VIDEO_DIP_ENABLE_GMP_HSW;
 149         case DP_SDP_VSC:
 150                 return VIDEO_DIP_ENABLE_VSC_HSW;
 151         case DP_SDP_PPS:
 152                 return VDIP_ENABLE_PPS;
 153         case HDMI_INFOFRAME_TYPE_AVI:
 154                 return VIDEO_DIP_ENABLE_AVI_HSW;
 155         case HDMI_INFOFRAME_TYPE_SPD:
 156                 return VIDEO_DIP_ENABLE_SPD_HSW;
 157         case HDMI_INFOFRAME_TYPE_VENDOR:
 158                 return VIDEO_DIP_ENABLE_VS_HSW;
 159         case HDMI_INFOFRAME_TYPE_DRM:
 160                 return VIDEO_DIP_ENABLE_DRM_GLK;
 161         default:
 162                 MISSING_CASE(type);
 163                 return 0;
 164         }
 165 }
 166
 167 static i915_reg_t
 168 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 169                  enum transcoder cpu_transcoder,
 170                  unsigned int type,
 171                  int i)
 172 {
 173         switch (type) {
 174         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 175                 return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
 176         case DP_SDP_VSC:
 177                 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
 178         case DP_SDP_PPS:
 179                 return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
 180         case HDMI_INFOFRAME_TYPE_AVI:
 181                 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 182         case HDMI_INFOFRAME_TYPE_SPD:
 183                 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 184         case HDMI_INFOFRAME_TYPE_VENDOR:
 185                 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 186         case HDMI_INFOFRAME_TYPE_DRM:
 187                 return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
 188         default:
 189                 MISSING_CASE(type);
 190                 return INVALID_MMIO_REG;
 191         }
 192 }
 193
 194 static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
 195                              unsigned int type)
 196 {
 197         switch (type) {
 198         case DP_SDP_VSC:
 199                 return VIDEO_DIP_VSC_DATA_SIZE;
 200         case DP_SDP_PPS:
 201                 return VIDEO_DIP_PPS_DATA_SIZE;
 202         case HDMI_PACKET_TYPE_GAMUT_METADATA:
 203                 if (INTEL_GEN(dev_priv) >= 11)
 204                         return VIDEO_DIP_GMP_DATA_SIZE;
 205                 else
 206                         return VIDEO_DIP_DATA_SIZE;
 207         default:
 208                 return VIDEO_DIP_DATA_SIZE;
 209         }
 210 }
 211
 212 static void g4x_write_infoframe(struct intel_encoder *encoder,
 213                                 const struct intel_crtc_state *crtc_state,
 214                                 unsigned int type,
 215                                 const void *frame, ssize_t len)
 216 {
 217         const u32 *data = frame;
 218         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 219         u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
 220         int i;
 221
 222         drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 223                  "Writing DIP with CTL reg disabled\n");
 224
 225         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 226         val |= g4x_infoframe_index(type);
 227
 228         val &= ~g4x_infoframe_enable(type);
 229
 230         intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
 231
 232         for (i = 0; i < len; i += 4) {
 233                 intel_de_write(dev_priv, VIDEO_DIP_DATA, *data);
 234                 data++;
 235         }
 236         /* Write every possible data byte to force correct ECC calculation. */
 237         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 238                 intel_de_write(dev_priv, VIDEO_DIP_DATA, 0);
 239
 240         val |= g4x_infoframe_enable(type);
 241         val &= ~VIDEO_DIP_FREQ_MASK;
 242         val |= VIDEO_DIP_FREQ_VSYNC;
 243
 244         intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
 245         intel_de_posting_read(dev_priv, VIDEO_DIP_CTL);
 246 }
 247
 248 static void g4x_read_infoframe(struct intel_encoder *encoder,
 249                                const struct intel_crtc_state *crtc_state,
 250                                unsigned int type,
 251                                void *frame, ssize_t len)
 252 {
 253         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 254         u32 val, *data = frame;
 255         int i;
 256
 257         val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
 258
 259         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 260         val |= g4x_infoframe_index(type);
 261
 262         intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
 263
 264         for (i = 0; i < len; i += 4)
 265                 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA);
 266 }
 267
 268 static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
 269                                   const struct intel_crtc_state *pipe_config)
 270 {
 271         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 272         u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
 273
 274         if ((val & VIDEO_DIP_ENABLE) == 0)
 275                 return 0;
 276
 277         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 278                 return 0;
 279
 280         return val & (VIDEO_DIP_ENABLE_AVI |
 281                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 282 }
 283
 284 static void ibx_write_infoframe(struct intel_encoder *encoder,
 285                                 const struct intel_crtc_state *crtc_state,
 286                                 unsigned int type,
 287                                 const void *frame, ssize_t len)
 288 {
 289         const u32 *data = frame;
 290         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 291         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
 292         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 293         u32 val = intel_de_read(dev_priv, reg);
 294         int i;
 295
 296         drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 297                  "Writing DIP with CTL reg disabled\n");
 298
 299         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 300         val |= g4x_infoframe_index(type);
 301
 302         val &= ~g4x_infoframe_enable(type);
 303
 304         intel_de_write(dev_priv, reg, val);
 305
 306         for (i = 0; i < len; i += 4) {
 307                 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe),
 308                                *data);
 309                 data++;
 310         }
 311         /* Write every possible data byte to force correct ECC calculation. */
 312         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 313                 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 314
 315         val |= g4x_infoframe_enable(type);
 316         val &= ~VIDEO_DIP_FREQ_MASK;
 317         val |= VIDEO_DIP_FREQ_VSYNC;
 318
 319         intel_de_write(dev_priv, reg, val);
 320         intel_de_posting_read(dev_priv, reg);
 321 }
 322
 323 static void ibx_read_infoframe(struct intel_encoder *encoder,
 324                                const struct intel_crtc_state *crtc_state,
 325                                unsigned int type,
 326                                void *frame, ssize_t len)
 327 {
 328         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 329         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 330         u32 val, *data = frame;
 331         int i;
 332
 333         val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
 334
 335         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 336         val |= g4x_infoframe_index(type);
 337
 338         intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
 339
 340         for (i = 0; i < len; i += 4)
 341                 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
 342 }
 343
 344 static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
 345                                   const struct intel_crtc_state *pipe_config)
 346 {
 347         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 348         enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
 349         i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 350         u32 val = intel_de_read(dev_priv, reg);
 351
 352         if ((val & VIDEO_DIP_ENABLE) == 0)
 353                 return 0;
 354
 355         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 356                 return 0;
 357
 358         return val & (VIDEO_DIP_ENABLE_AVI |
 359                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 360                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 361 }
 362
 363 static void cpt_write_infoframe(struct intel_encoder *encoder,
 364                                 const struct intel_crtc_state *crtc_state,
 365                                 unsigned int type,
 366                                 const void *frame, ssize_t len)
 367 {
 368         const u32 *data = frame;
 369         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 370         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
 371         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
 372         u32 val = intel_de_read(dev_priv, reg);
 373         int i;
 374
 375         drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 376                  "Writing DIP with CTL reg disabled\n");
 377
 378         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 379         val |= g4x_infoframe_index(type);
 380
 381         /* The DIP control register spec says that we need to update the AVI
 382          * infoframe without clearing its enable bit */
 383         if (type != HDMI_INFOFRAME_TYPE_AVI)
 384                 val &= ~g4x_infoframe_enable(type);
 385
 386         intel_de_write(dev_priv, reg, val);
 387
 388         for (i = 0; i < len; i += 4) {
 389                 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe),
 390                                *data);
 391                 data++;
 392         }
 393         /* Write every possible data byte to force correct ECC calculation. */
 394         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 395                 intel_de_write(dev_priv, TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 396
 397         val |= g4x_infoframe_enable(type);
 398         val &= ~VIDEO_DIP_FREQ_MASK;
 399         val |= VIDEO_DIP_FREQ_VSYNC;
 400
 401         intel_de_write(dev_priv, reg, val);
 402         intel_de_posting_read(dev_priv, reg);
 403 }
 404
 405 static void cpt_read_infoframe(struct intel_encoder *encoder,
 406                                const struct intel_crtc_state *crtc_state,
 407                                unsigned int type,
 408                                void *frame, ssize_t len)
 409 {
 410         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 411         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 412         u32 val, *data = frame;
 413         int i;
 414
 415         val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(crtc->pipe));
 416
 417         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 418         val |= g4x_infoframe_index(type);
 419
 420         intel_de_write(dev_priv, TVIDEO_DIP_CTL(crtc->pipe), val);
 421
 422         for (i = 0; i < len; i += 4)
 423                 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
 424 }
 425
 426 static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
 427                                   const struct intel_crtc_state *pipe_config)
 428 {
 429         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 430         enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
 431         u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe));
 432
 433         if ((val & VIDEO_DIP_ENABLE) == 0)
 434                 return 0;
 435
 436         return val & (VIDEO_DIP_ENABLE_AVI |
 437                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 438                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 439 }
 440
 441 static void vlv_write_infoframe(struct intel_encoder *encoder,
 442                                 const struct intel_crtc_state *crtc_state,
 443                                 unsigned int type,
 444                                 const void *frame, ssize_t len)
 445 {
 446         const u32 *data = frame;
 447         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 448         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
 449         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
 450         u32 val = intel_de_read(dev_priv, reg);
 451         int i;
 452
 453         drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 454                  "Writing DIP with CTL reg disabled\n");
 455
 456         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 457         val |= g4x_infoframe_index(type);
 458
 459         val &= ~g4x_infoframe_enable(type);
 460
 461         intel_de_write(dev_priv, reg, val);
 462
 463         for (i = 0; i < len; i += 4) {
 464                 intel_de_write(dev_priv,
 465                                VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
 466                 data++;
 467         }
 468         /* Write every possible data byte to force correct ECC calculation. */
 469         for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 470                 intel_de_write(dev_priv,
 471                                VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
 472
 473         val |= g4x_infoframe_enable(type);
 474         val &= ~VIDEO_DIP_FREQ_MASK;
 475         val |= VIDEO_DIP_FREQ_VSYNC;
 476
 477         intel_de_write(dev_priv, reg, val);
 478         intel_de_posting_read(dev_priv, reg);
 479 }
 480
 481 static void vlv_read_infoframe(struct intel_encoder *encoder,
 482                                const struct intel_crtc_state *crtc_state,
 483                                unsigned int type,
 484                                void *frame, ssize_t len)
 485 {
 486         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 487         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 488         u32 val, *data = frame;
 489         int i;
 490
 491         val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe));
 492
 493         val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 494         val |= g4x_infoframe_index(type);
 495
 496         intel_de_write(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe), val);
 497
 498         for (i = 0; i < len; i += 4)
 499                 *data++ = intel_de_read(dev_priv,
 500                                         VLV_TVIDEO_DIP_DATA(crtc->pipe));
 501 }
 502
 503 static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
 504                                   const struct intel_crtc_state *pipe_config)
 505 {
 506         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 507         enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
 508         u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe));
 509
 510         if ((val & VIDEO_DIP_ENABLE) == 0)
 511                 return 0;
 512
 513         if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 514                 return 0;
 515
 516         return val & (VIDEO_DIP_ENABLE_AVI |
 517                       VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 518                       VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 519 }
 520
 521 static void hsw_write_infoframe(struct intel_encoder *encoder,
 522                                 const struct intel_crtc_state *crtc_state,
 523                                 unsigned int type,
 524                                 const void *frame, ssize_t len)
 525 {
 526         const u32 *data = frame;
 527         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 528         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 529         i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 530         int data_size;
 531         int i;
 532         u32 val = intel_de_read(dev_priv, ctl_reg);
 533
 534         data_size = hsw_dip_data_size(dev_priv, type);
 535
 536         drm_WARN_ON(&dev_priv->drm, len > data_size);
 537
 538         val &= ~hsw_infoframe_enable(type);
 539         intel_de_write(dev_priv, ctl_reg, val);
 540
 541         for (i = 0; i < len; i += 4) {
 542                 intel_de_write(dev_priv,
 543                                hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
 544                                *data);
 545                 data++;
 546         }
 547         /* Write every possible data byte to force correct ECC calculation. */
 548         for (; i < data_size; i += 4)
 549                 intel_de_write(dev_priv,
 550                                hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
 551                                0);
 552
 553         val |= hsw_infoframe_enable(type);
 554         intel_de_write(dev_priv, ctl_reg, val);
 555         intel_de_posting_read(dev_priv, ctl_reg);
 556 }
 557
 558 static void hsw_read_infoframe(struct intel_encoder *encoder,
 559                                const struct intel_crtc_state *crtc_state,
 560                                unsigned int type,
 561                                void *frame, ssize_t len)
 562 {
 563         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 564         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 565         u32 val, *data = frame;
 566         int i;
 567
 568         val = intel_de_read(dev_priv, HSW_TVIDEO_DIP_CTL(cpu_transcoder));
 569
 570         for (i = 0; i < len; i += 4)
 571                 *data++ = intel_de_read(dev_priv,
 572                                         hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2));
 573 }
 574
 575 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
 576                                   const struct intel_crtc_state *pipe_config)
 577 {
 578         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 579         u32 val = intel_de_read(dev_priv,
 580                                 HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
 581         u32 mask;
 582
 583         mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 584                 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 585                 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 586
 587         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 588                 mask |= VIDEO_DIP_ENABLE_DRM_GLK;
 589
 590         return val & mask;
 591 }
 592
 593 static const u8 infoframe_type_to_idx[] = {
 594         HDMI_PACKET_TYPE_GENERAL_CONTROL,
 595         HDMI_PACKET_TYPE_GAMUT_METADATA,
 596         DP_SDP_VSC,
 597         HDMI_INFOFRAME_TYPE_AVI,
 598         HDMI_INFOFRAME_TYPE_SPD,
 599         HDMI_INFOFRAME_TYPE_VENDOR,
 600         HDMI_INFOFRAME_TYPE_DRM,
 601 };
 602
 603 u32 intel_hdmi_infoframe_enable(unsigned int type)
 604 {
 605         int i;
 606
 607         for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
 608                 if (infoframe_type_to_idx[i] == type)
 609                         return BIT(i);
 610         }
 611
 612         return 0;
 613 }
 614
 615 u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
 616                                   const struct intel_crtc_state *crtc_state)
 617 {
 618         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 619         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 620         u32 val, ret = 0;
 621         int i;
 622
 623         val = dig_port->infoframes_enabled(encoder, crtc_state);
 624
 625         /* map from hardware bits to dip idx */
 626         for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
 627                 unsigned int type = infoframe_type_to_idx[i];
 628
 629                 if (HAS_DDI(dev_priv)) {
 630                         if (val & hsw_infoframe_enable(type))
 631                                 ret |= BIT(i);
 632                 } else {
 633                         if (val & g4x_infoframe_enable(type))
 634                                 ret |= BIT(i);
 635                 }
 636         }
 637
 638         return ret;
 639 }
 640
 641 /*
 642  * The data we write to the DIP data buffer registers is 1 byte bigger than the
 643  * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 644  * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 645  * used for both technologies.
 646  *
 647  * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 648  * DW1:       DB3       | DB2 | DB1 | DB0
 649  * DW2:       DB7       | DB6 | DB5 | DB4
 650  * DW3: ...
 651  *
 652  * (HB is Header Byte, DB is Data Byte)
 653  *
 654  * The hdmi pack() functions don't know about that hardware specific hole so we
 655  * trick them by giving an offset into the buffer and moving back the header
 656  * bytes by one.
 657  */
 658 static void intel_write_infoframe(struct intel_encoder *encoder,
 659                                   const struct intel_crtc_state *crtc_state,
 660                                   enum hdmi_infoframe_type type,
 661                                   const union hdmi_infoframe *frame)
 662 {
 663         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 664         u8 buffer[VIDEO_DIP_DATA_SIZE];
 665         ssize_t len;
 666
 667         if ((crtc_state->infoframes.enable &
 668              intel_hdmi_infoframe_enable(type)) == 0)
 669                 return;
 670
 671         if (drm_WARN_ON(encoder->base.dev, frame->any.type != type))
 672                 return;
 673
 674         /* see comment above for the reason for this offset */
 675         len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
 676         if (drm_WARN_ON(encoder->base.dev, len < 0))
 677                 return;
 678
 679         /* Insert the 'hole' (see big comment above) at position 3 */
 680         memmove(&buffer[0], &buffer[1], 3);
 681         buffer[3] = 0;
 682         len++;
 683
 684         dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
 685 }
 686
 687 void intel_read_infoframe(struct intel_encoder *encoder,
 688                           const struct intel_crtc_state *crtc_state,
 689                           enum hdmi_infoframe_type type,
 690                           union hdmi_infoframe *frame)
 691 {
 692         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 693         u8 buffer[VIDEO_DIP_DATA_SIZE];
 694         int ret;
 695
 696         if ((crtc_state->infoframes.enable &
 697              intel_hdmi_infoframe_enable(type)) == 0)
 698                 return;
 699
 700         dig_port->read_infoframe(encoder, crtc_state,
 701                                        type, buffer, sizeof(buffer));
 702
 703         /* Fill the 'hole' (see big comment above) at position 3 */
 704         memmove(&buffer[1], &buffer[0], 3);
 705
 706         /* see comment above for the reason for this offset */
 707         ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
 708         if (ret) {
 709                 drm_dbg_kms(encoder->base.dev,
 710                             "Failed to unpack infoframe type 0x%02x\n", type);
 711                 return;
 712         }
 713
 714         if (frame->any.type != type)
 715                 drm_dbg_kms(encoder->base.dev,
 716                             "Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
 717                             frame->any.type, type);
 718 }
 719
 720 static bool
 721 intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
 722                                  struct intel_crtc_state *crtc_state,
 723                                  struct drm_connector_state *conn_state)
 724 {
 725         struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
 726         const struct drm_display_mode *adjusted_mode =
 727                 &crtc_state->hw.adjusted_mode;
 728         struct drm_connector *connector = conn_state->connector;
 729         int ret;
 730
 731         if (!crtc_state->has_infoframe)
 732                 return true;
 733
 734         crtc_state->infoframes.enable |=
 735                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
 736
 737         ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
 738                                                        adjusted_mode);
 739         if (ret)
 740                 return false;
 741
 742         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 743                 frame->colorspace = HDMI_COLORSPACE_YUV420;
 744         else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 745                 frame->colorspace = HDMI_COLORSPACE_YUV444;
 746         else
 747                 frame->colorspace = HDMI_COLORSPACE_RGB;
 748
 749         drm_hdmi_avi_infoframe_colorspace(frame, conn_state);
 750
 751         /* nonsense combination */
 752         drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
 753                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
 754
 755         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
 756                 drm_hdmi_avi_infoframe_quant_range(frame, connector,
 757                                                    adjusted_mode,
 758                                                    crtc_state->limited_color_range ?
 759                                                    HDMI_QUANTIZATION_RANGE_LIMITED :
 760                                                    HDMI_QUANTIZATION_RANGE_FULL);
 761         } else {
 762                 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
 763                 frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
 764         }
 765
 766         drm_hdmi_avi_infoframe_content_type(frame, conn_state);
 767
 768         /* TODO: handle pixel repetition for YCBCR420 outputs */
 769
 770         ret = hdmi_avi_infoframe_check(frame);
 771         if (drm_WARN_ON(encoder->base.dev, ret))
 772                 return false;
 773
 774         return true;
 775 }
 776
 777 static bool
 778 intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
 779                                  struct intel_crtc_state *crtc_state,
 780                                  struct drm_connector_state *conn_state)
 781 {
 782         struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
 783         int ret;
 784
 785         if (!crtc_state->has_infoframe)
 786                 return true;
 787
 788         crtc_state->infoframes.enable |=
 789                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
 790
 791         ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
 792         if (drm_WARN_ON(encoder->base.dev, ret))
 793                 return false;
 794
 795         frame->sdi = HDMI_SPD_SDI_PC;
 796
 797         ret = hdmi_spd_infoframe_check(frame);
 798         if (drm_WARN_ON(encoder->base.dev, ret))
 799                 return false;
 800
 801         return true;
 802 }
 803
 804 static bool
 805 intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
 806                                   struct intel_crtc_state *crtc_state,
 807                                   struct drm_connector_state *conn_state)
 808 {
 809         struct hdmi_vendor_infoframe *frame =
 810                 &crtc_state->infoframes.hdmi.vendor.hdmi;
 811         const struct drm_display_info *info =
 812                 &conn_state->connector->display_info;
 813         int ret;
 814
 815         if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
 816                 return true;
 817
 818         crtc_state->infoframes.enable |=
 819                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
 820
 821         ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
 822                                                           conn_state->connector,
 823                                                           &crtc_state->hw.adjusted_mode);
 824         if (drm_WARN_ON(encoder->base.dev, ret))
 825                 return false;
 826
 827         ret = hdmi_vendor_infoframe_check(frame);
 828         if (drm_WARN_ON(encoder->base.dev, ret))
 829                 return false;
 830
 831         return true;
 832 }
 833
 834 static bool
 835 intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
 836                                  struct intel_crtc_state *crtc_state,
 837                                  struct drm_connector_state *conn_state)
 838 {
 839         struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
 840         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 841         int ret;
 842
 843         if (!(INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
 844                 return true;
 845
 846         if (!crtc_state->has_infoframe)
 847                 return true;
 848
 849         if (!conn_state->hdr_output_metadata)
 850                 return true;
 851
 852         crtc_state->infoframes.enable |=
 853                 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
 854
 855         ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
 856         if (ret < 0) {
 857                 drm_dbg_kms(&dev_priv->drm,
 858                             "couldn't set HDR metadata in infoframe\n");
 859                 return false;
 860         }
 861
 862         ret = hdmi_drm_infoframe_check(frame);
 863         if (drm_WARN_ON(&dev_priv->drm, ret))
 864                 return false;
 865
 866         return true;
 867 }
 868
 869 static void g4x_set_infoframes(struct intel_encoder *encoder,
 870                                bool enable,
 871                                const struct intel_crtc_state *crtc_state,
 872                                const struct drm_connector_state *conn_state)
 873 {
 874         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 875         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 876         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
 877         i915_reg_t reg = VIDEO_DIP_CTL;
 878         u32 val = intel_de_read(dev_priv, reg);
 879         u32 port = VIDEO_DIP_PORT(encoder->port);
 880
 881         assert_hdmi_port_disabled(intel_hdmi);
 882
 883         /* If the registers were not initialized yet, they might be zeroes,
 884          * which means we're selecting the AVI DIP and we're setting its
 885          * frequency to once. This seems to really confuse the HW and make
 886          * things stop working (the register spec says the AVI always needs to
 887          * be sent every VSync). So here we avoid writing to the register more
 888          * than we need and also explicitly select the AVI DIP and explicitly
 889          * set its frequency to every VSync. Avoiding to write it twice seems to
 890          * be enough to solve the problem, but being defensive shouldn't hurt us
 891          * either. */
 892         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 893
 894         if (!enable) {
 895                 if (!(val & VIDEO_DIP_ENABLE))
 896                         return;
 897                 if (port != (val & VIDEO_DIP_PORT_MASK)) {
 898                         drm_dbg_kms(&dev_priv->drm,
 899                                     "video DIP still enabled on port %c\n",
 900                                     (val & VIDEO_DIP_PORT_MASK) >> 29);
 901                         return;
 902                 }
 903                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 904                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 905                 intel_de_write(dev_priv, reg, val);
 906                 intel_de_posting_read(dev_priv, reg);
 907                 return;
 908         }
 909
 910         if (port != (val & VIDEO_DIP_PORT_MASK)) {
 911                 if (val & VIDEO_DIP_ENABLE) {
 912                         drm_dbg_kms(&dev_priv->drm,
 913                                     "video DIP already enabled on port %c\n",
 914                                     (val & VIDEO_DIP_PORT_MASK) >> 29);
 915                         return;
 916                 }
 917                 val &= ~VIDEO_DIP_PORT_MASK;
 918                 val |= port;
 919         }
 920
 921         val |= VIDEO_DIP_ENABLE;
 922         val &= ~(VIDEO_DIP_ENABLE_AVI |
 923                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 924
 925         intel_de_write(dev_priv, reg, val);
 926         intel_de_posting_read(dev_priv, reg);
 927
 928         intel_write_infoframe(encoder, crtc_state,
 929                               HDMI_INFOFRAME_TYPE_AVI,
 930                               &crtc_state->infoframes.avi);
 931         intel_write_infoframe(encoder, crtc_state,
 932                               HDMI_INFOFRAME_TYPE_SPD,
 933                               &crtc_state->infoframes.spd);
 934         intel_write_infoframe(encoder, crtc_state,
 935                               HDMI_INFOFRAME_TYPE_VENDOR,
 936                               &crtc_state->infoframes.hdmi);
 937 }
 938
 939 /*
 940  * Determine if default_phase=1 can be indicated in the GCP infoframe.
 941  *
 942  * From HDMI specification 1.4a:
 943  * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 944  * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 945  * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 946  * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 947  *   phase of 0
 948  */
 949 static bool gcp_default_phase_possible(int pipe_bpp,
 950                                        const struct drm_display_mode *mode)
 951 {
 952         unsigned int pixels_per_group;
 953
 954         switch (pipe_bpp) {
 955         case 30:
 956                 /* 4 pixels in 5 clocks */
 957                 pixels_per_group = 4;
 958                 break;
 959         case 36:
 960                 /* 2 pixels in 3 clocks */
 961                 pixels_per_group = 2;
 962                 break;
 963         case 48:
 964                 /* 1 pixel in 2 clocks */
 965                 pixels_per_group = 1;
 966                 break;
 967         default:
 968                 /* phase information not relevant for 8bpc */
 969                 return false;
 970         }
 971
 972         return mode->crtc_hdisplay % pixels_per_group == 0 &&
 973                 mode->crtc_htotal % pixels_per_group == 0 &&
 974                 mode->crtc_hblank_start % pixels_per_group == 0 &&
 975                 mode->crtc_hblank_end % pixels_per_group == 0 &&
 976                 mode->crtc_hsync_start % pixels_per_group == 0 &&
 977                 mode->crtc_hsync_end % pixels_per_group == 0 &&
 978                 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 979                  mode->crtc_htotal/2 % pixels_per_group == 0);
 980 }
 981
 982 static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
 983                                          const struct intel_crtc_state *crtc_state,
 984                                          const struct drm_connector_state *conn_state)
 985 {
 986         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 987         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 988         i915_reg_t reg;
 989
 990         if ((crtc_state->infoframes.enable &
 991              intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
 992                 return false;
 993
 994         if (HAS_DDI(dev_priv))
 995                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 996         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 997                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 998         else if (HAS_PCH_SPLIT(dev_priv))
 999                 reg = TVIDEO_DIP_GCP(crtc->pipe);
1000         else
1001                 return false;
1002
1003         intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp);
1004
1005         return true;
1006 }
1007
1008 void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
1009                                    struct intel_crtc_state *crtc_state)
1010 {
1011         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1012         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1013         i915_reg_t reg;
1014
1015         if ((crtc_state->infoframes.enable &
1016              intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
1017                 return;
1018
1019         if (HAS_DDI(dev_priv))
1020                 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
1021         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1022                 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
1023         else if (HAS_PCH_SPLIT(dev_priv))
1024                 reg = TVIDEO_DIP_GCP(crtc->pipe);
1025         else
1026                 return;
1027
1028         crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg);
1029 }
1030
1031 static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
1032                                              struct intel_crtc_state *crtc_state,
1033                                              struct drm_connector_state *conn_state)
1034 {
1035         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1036
1037         if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1038                 return;
1039
1040         crtc_state->infoframes.enable |=
1041                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1042
1043         /* Indicate color indication for deep color mode */
1044         if (crtc_state->pipe_bpp > 24)
1045                 crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1046
1047         /* Enable default_phase whenever the display mode is suitably aligned */
1048         if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1049                                        &crtc_state->hw.adjusted_mode))
1050                 crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1051 }
1052
1053 static void ibx_set_infoframes(struct intel_encoder *encoder,
1054                                bool enable,
1055                                const struct intel_crtc_state *crtc_state,
1056                                const struct drm_connector_state *conn_state)
1057 {
1058         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1059         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1060         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1061         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
1062         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1063         u32 val = intel_de_read(dev_priv, reg);
1064         u32 port = VIDEO_DIP_PORT(encoder->port);
1065
1066         assert_hdmi_port_disabled(intel_hdmi);
1067
1068         /* See the big comment in g4x_set_infoframes() */
1069         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1070
1071         if (!enable) {
1072                 if (!(val & VIDEO_DIP_ENABLE))
1073                         return;
1074                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1075                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1076                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1077                 intel_de_write(dev_priv, reg, val);
1078                 intel_de_posting_read(dev_priv, reg);
1079                 return;
1080         }
1081
1082         if (port != (val & VIDEO_DIP_PORT_MASK)) {
1083                 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1084                          "DIP already enabled on port %c\n",
1085                          (val & VIDEO_DIP_PORT_MASK) >> 29);
1086                 val &= ~VIDEO_DIP_PORT_MASK;
1087                 val |= port;
1088         }
1089
1090         val |= VIDEO_DIP_ENABLE;
1091         val &= ~(VIDEO_DIP_ENABLE_AVI |
1092                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1093                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1094
1095         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1096                 val |= VIDEO_DIP_ENABLE_GCP;
1097
1098         intel_de_write(dev_priv, reg, val);
1099         intel_de_posting_read(dev_priv, reg);
1100
1101         intel_write_infoframe(encoder, crtc_state,
1102                               HDMI_INFOFRAME_TYPE_AVI,
1103                               &crtc_state->infoframes.avi);
1104         intel_write_infoframe(encoder, crtc_state,
1105                               HDMI_INFOFRAME_TYPE_SPD,
1106                               &crtc_state->infoframes.spd);
1107         intel_write_infoframe(encoder, crtc_state,
1108                               HDMI_INFOFRAME_TYPE_VENDOR,
1109                               &crtc_state->infoframes.hdmi);
1110 }
1111
1112 static void cpt_set_infoframes(struct intel_encoder *encoder,
1113                                bool enable,
1114                                const struct intel_crtc_state *crtc_state,
1115                                const struct drm_connector_state *conn_state)
1116 {
1117         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1118         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1119         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1120         i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
1121         u32 val = intel_de_read(dev_priv, reg);
1122
1123         assert_hdmi_port_disabled(intel_hdmi);
1124
1125         /* See the big comment in g4x_set_infoframes() */
1126         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1127
1128         if (!enable) {
1129                 if (!(val & VIDEO_DIP_ENABLE))
1130                         return;
1131                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1132                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1133                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1134                 intel_de_write(dev_priv, reg, val);
1135                 intel_de_posting_read(dev_priv, reg);
1136                 return;
1137         }
1138
1139         /* Set both together, unset both together: see the spec. */
1140         val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1141         val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1142                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1143
1144         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1145                 val |= VIDEO_DIP_ENABLE_GCP;
1146
1147         intel_de_write(dev_priv, reg, val);
1148         intel_de_posting_read(dev_priv, reg);
1149
1150         intel_write_infoframe(encoder, crtc_state,
1151                               HDMI_INFOFRAME_TYPE_AVI,
1152                               &crtc_state->infoframes.avi);
1153         intel_write_infoframe(encoder, crtc_state,
1154                               HDMI_INFOFRAME_TYPE_SPD,
1155                               &crtc_state->infoframes.spd);
1156         intel_write_infoframe(encoder, crtc_state,
1157                               HDMI_INFOFRAME_TYPE_VENDOR,
1158                               &crtc_state->infoframes.hdmi);
1159 }
1160
1161 static void vlv_set_infoframes(struct intel_encoder *encoder,
1162                                bool enable,
1163                                const struct intel_crtc_state *crtc_state,
1164                                const struct drm_connector_state *conn_state)
1165 {
1166         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1167         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1168         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1169         i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
1170         u32 val = intel_de_read(dev_priv, reg);
1171         u32 port = VIDEO_DIP_PORT(encoder->port);
1172
1173         assert_hdmi_port_disabled(intel_hdmi);
1174
1175         /* See the big comment in g4x_set_infoframes() */
1176         val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1177
1178         if (!enable) {
1179                 if (!(val & VIDEO_DIP_ENABLE))
1180                         return;
1181                 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1182                          VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1183                          VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1184                 intel_de_write(dev_priv, reg, val);
1185                 intel_de_posting_read(dev_priv, reg);
1186                 return;
1187         }
1188
1189         if (port != (val & VIDEO_DIP_PORT_MASK)) {
1190                 drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1191                          "DIP already enabled on port %c\n",
1192                          (val & VIDEO_DIP_PORT_MASK) >> 29);
1193                 val &= ~VIDEO_DIP_PORT_MASK;
1194                 val |= port;
1195         }
1196
1197         val |= VIDEO_DIP_ENABLE;
1198         val &= ~(VIDEO_DIP_ENABLE_AVI |
1199                  VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1200                  VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1201
1202         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1203                 val |= VIDEO_DIP_ENABLE_GCP;
1204
1205         intel_de_write(dev_priv, reg, val);
1206         intel_de_posting_read(dev_priv, reg);
1207
1208         intel_write_infoframe(encoder, crtc_state,
1209                               HDMI_INFOFRAME_TYPE_AVI,
1210                               &crtc_state->infoframes.avi);
1211         intel_write_infoframe(encoder, crtc_state,
1212                               HDMI_INFOFRAME_TYPE_SPD,
1213                               &crtc_state->infoframes.spd);
1214         intel_write_infoframe(encoder, crtc_state,
1215                               HDMI_INFOFRAME_TYPE_VENDOR,
1216                               &crtc_state->infoframes.hdmi);
1217 }
1218
1219 static void hsw_set_infoframes(struct intel_encoder *encoder,
1220                                bool enable,
1221                                const struct intel_crtc_state *crtc_state,
1222                                const struct drm_connector_state *conn_state)
1223 {
1224         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1225         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1226         u32 val = intel_de_read(dev_priv, reg);
1227
1228         assert_hdmi_transcoder_func_disabled(dev_priv,
1229                                              crtc_state->cpu_transcoder);
1230
1231         val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1232                  VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1233                  VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1234                  VIDEO_DIP_ENABLE_DRM_GLK);
1235
1236         if (!enable) {
1237                 intel_de_write(dev_priv, reg, val);
1238                 intel_de_posting_read(dev_priv, reg);
1239                 return;
1240         }
1241
1242         if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1243                 val |= VIDEO_DIP_ENABLE_GCP_HSW;
1244
1245         intel_de_write(dev_priv, reg, val);
1246         intel_de_posting_read(dev_priv, reg);
1247
1248         intel_write_infoframe(encoder, crtc_state,
1249                               HDMI_INFOFRAME_TYPE_AVI,
1250                               &crtc_state->infoframes.avi);
1251         intel_write_infoframe(encoder, crtc_state,
1252                               HDMI_INFOFRAME_TYPE_SPD,
1253                               &crtc_state->infoframes.spd);
1254         intel_write_infoframe(encoder, crtc_state,
1255                               HDMI_INFOFRAME_TYPE_VENDOR,
1256                               &crtc_state->infoframes.hdmi);
1257         intel_write_infoframe(encoder, crtc_state,
1258                               HDMI_INFOFRAME_TYPE_DRM,
1259                               &crtc_state->infoframes.drm);
1260 }
1261
1262 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1263 {
1264         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1265         struct i2c_adapter *adapter =
1266                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1267
1268         if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1269                 return;
1270
1271         drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n",
1272                     enable ? "Enabling" : "Disabling");
1273
1274         drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
1275                                          adapter, enable);
1276 }
1277
1278 static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port,
1279                                 unsigned int offset, void *buffer, size_t size)
1280 {
1281         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1282         struct intel_hdmi *hdmi = &dig_port->hdmi;
1283         struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1284                                                               hdmi->ddc_bus);
1285         int ret;
1286         u8 start = offset & 0xff;
1287         struct i2c_msg msgs[] = {
1288                 {
1289                         .addr = DRM_HDCP_DDC_ADDR,
1290                         .flags = 0,
1291                         .len = 1,
1292                         .buf = &start,
1293                 },
1294                 {
1295                         .addr = DRM_HDCP_DDC_ADDR,
1296                         .flags = I2C_M_RD,
1297                         .len = size,
1298                         .buf = buffer
1299                 }
1300         };
1301         ret = i2c_transfer(adapter, msgs, ARRAY_SIZE(msgs));
1302         if (ret == ARRAY_SIZE(msgs))
1303                 return 0;
1304         return ret >= 0 ? -EIO : ret;
1305 }
1306
1307 static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port,
1308                                  unsigned int offset, void *buffer, size_t size)
1309 {
1310         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1311         struct intel_hdmi *hdmi = &dig_port->hdmi;
1312         struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1313                                                               hdmi->ddc_bus);
1314         int ret;
1315         u8 *write_buf;
1316         struct i2c_msg msg;
1317
1318         write_buf = kzalloc(size + 1, GFP_KERNEL);
1319         if (!write_buf)
1320                 return -ENOMEM;
1321
1322         write_buf[0] = offset & 0xff;
1323         memcpy(&write_buf[1], buffer, size);
1324
1325         msg.addr = DRM_HDCP_DDC_ADDR;
1326         msg.flags = 0,
1327         msg.len = size + 1,
1328         msg.buf = write_buf;
1329
1330         ret = i2c_transfer(adapter, &msg, 1);
1331         if (ret == 1)
1332                 ret = 0;
1333         else if (ret >= 0)
1334                 ret = -EIO;
1335
1336         kfree(write_buf);
1337         return ret;
1338 }
1339
1340 static
1341 int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
1342                                   u8 *an)
1343 {
1344         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1345         struct intel_hdmi *hdmi = &dig_port->hdmi;
1346         struct i2c_adapter *adapter = intel_gmbus_get_adapter(i915,
1347                                                               hdmi->ddc_bus);
1348         int ret;
1349
1350         ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an,
1351                                     DRM_HDCP_AN_LEN);
1352         if (ret) {
1353                 drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n",
1354                             ret);
1355                 return ret;
1356         }
1357
1358         ret = intel_gmbus_output_aksv(adapter);
1359         if (ret < 0) {
1360                 drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret);
1361                 return ret;
1362         }
1363         return 0;
1364 }
1365
1366 static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port,
1367                                      u8 *bksv)
1368 {
1369         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1370
1371         int ret;
1372         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv,
1373                                    DRM_HDCP_KSV_LEN);
1374         if (ret)
1375                 drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n",
1376                             ret);
1377         return ret;
1378 }
1379
1380 static
1381 int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port,
1382                                  u8 *bstatus)
1383 {
1384         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1385
1386         int ret;
1387         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS,
1388                                    bstatus, DRM_HDCP_BSTATUS_LEN);
1389         if (ret)
1390                 drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n",
1391                             ret);
1392         return ret;
1393 }
1394
1395 static
1396 int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port,
1397                                      bool *repeater_present)
1398 {
1399         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1400         int ret;
1401         u8 val;
1402
1403         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1404         if (ret) {
1405                 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1406                             ret);
1407                 return ret;
1408         }
1409         *repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1410         return 0;
1411 }
1412
1413 static
1414 int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
1415                                   u8 *ri_prime)
1416 {
1417         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1418
1419         int ret;
1420         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME,
1421                                    ri_prime, DRM_HDCP_RI_LEN);
1422         if (ret)
1423                 drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n",
1424                             ret);
1425         return ret;
1426 }
1427
1428 static
1429 int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
1430                                    bool *ksv_ready)
1431 {
1432         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1433         int ret;
1434         u8 val;
1435
1436         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1437         if (ret) {
1438                 drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1439                             ret);
1440                 return ret;
1441         }
1442         *ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1443         return 0;
1444 }
1445
1446 static
1447 int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
1448                                   int num_downstream, u8 *ksv_fifo)
1449 {
1450         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1451         int ret;
1452         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO,
1453                                    ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1454         if (ret) {
1455                 drm_dbg_kms(&i915->drm,
1456                             "Read ksv fifo over DDC failed (%d)\n", ret);
1457                 return ret;
1458         }
1459         return 0;
1460 }
1461
1462 static
1463 int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
1464                                       int i, u32 *part)
1465 {
1466         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1467         int ret;
1468
1469         if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1470                 return -EINVAL;
1471
1472         ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i),
1473                                    part, DRM_HDCP_V_PRIME_PART_LEN);
1474         if (ret)
1475                 drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n",
1476                             i, ret);
1477         return ret;
1478 }
1479
1480 static int kbl_repositioning_enc_en_signal(struct intel_connector *connector)
1481 {
1482         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1483         struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1484         struct drm_crtc *crtc = connector->base.state->crtc;
1485         struct intel_crtc *intel_crtc = container_of(crtc,
1486                                                      struct intel_crtc, base);
1487         u32 scanline;
1488         int ret;
1489
1490         for (;;) {
1491                 scanline = intel_de_read(dev_priv, PIPEDSL(intel_crtc->pipe));
1492                 if (scanline > 100 && scanline < 200)
1493                         break;
1494                 usleep_range(25, 50);
1495         }
1496
1497         ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, false);
1498         if (ret) {
1499                 drm_err(&dev_priv->drm,
1500                         "Disable HDCP signalling failed (%d)\n", ret);
1501                 return ret;
1502         }
1503         ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, true);
1504         if (ret) {
1505                 drm_err(&dev_priv->drm,
1506                         "Enable HDCP signalling failed (%d)\n", ret);
1507                 return ret;
1508         }
1509
1510         return 0;
1511 }
1512
1513 static
1514 int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
1515                                       bool enable)
1516 {
1517         struct intel_hdmi *hdmi = &dig_port->hdmi;
1518         struct intel_connector *connector = hdmi->attached_connector;
1519         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1520         int ret;
1521
1522         if (!enable)
1523                 usleep_range(6, 60); /* Bspec says >= 6us */
1524
1525         ret = intel_ddi_toggle_hdcp_signalling(&dig_port->base, enable);
1526         if (ret) {
1527                 drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
1528                         enable ? "Enable" : "Disable", ret);
1529                 return ret;
1530         }
1531
1532         /*
1533          * WA: To fix incorrect positioning of the window of
1534          * opportunity and enc_en signalling in KABYLAKE.
1535          */
1536         if (IS_KABYLAKE(dev_priv) && enable)
1537                 return kbl_repositioning_enc_en_signal(connector);
1538
1539         return 0;
1540 }
1541
1542 static
1543 bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port)
1544 {
1545         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1546         struct intel_connector *connector =
1547                 dig_port->hdmi.attached_connector;
1548         enum port port = dig_port->base.port;
1549         enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1550         int ret;
1551         union {
1552                 u32 reg;
1553                 u8 shim[DRM_HDCP_RI_LEN];
1554         } ri;
1555
1556         ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim);
1557         if (ret)
1558                 return false;
1559
1560         intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg);
1561
1562         /* Wait for Ri prime match */
1563         if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &
1564                       (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
1565                      (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1566                 drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n",
1567                         intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
1568                                                         port)));
1569                 return false;
1570         }
1571         return true;
1572 }
1573
1574 static
1575 bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port)
1576 {
1577         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1578         int retry;
1579
1580         for (retry = 0; retry < 3; retry++)
1581                 if (intel_hdmi_hdcp_check_link_once(dig_port))
1582                         return true;
1583
1584         drm_err(&i915->drm, "Link check failed\n");
1585         return false;
1586 }
1587
1588 struct hdcp2_hdmi_msg_timeout {
1589         u8 msg_id;
1590         u16 timeout;
1591 };
1592
1593 static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
1594         { HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, },
1595         { HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, },
1596         { HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, },
1597         { HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, },
1598         { HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, },
1599 };
1600
1601 static
1602 int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
1603                                     u8 *rx_status)
1604 {
1605         return intel_hdmi_hdcp_read(dig_port,
1606                                     HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1607                                     rx_status,
1608                                     HDCP_2_2_HDMI_RXSTATUS_LEN);
1609 }
1610
1611 static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1612 {
1613         int i;
1614
1615         if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) {
1616                 if (is_paired)
1617                         return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS;
1618                 else
1619                         return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS;
1620         }
1621
1622         for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) {
1623                 if (hdcp2_msg_timeout[i].msg_id == msg_id)
1624                         return hdcp2_msg_timeout[i].timeout;
1625         }
1626
1627         return -EINVAL;
1628 }
1629
1630 static int
1631 hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
1632                               u8 msg_id, bool *msg_ready,
1633                               ssize_t *msg_sz)
1634 {
1635         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1636         u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1637         int ret;
1638
1639         ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1640         if (ret < 0) {
1641                 drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n",
1642                             ret);
1643                 return ret;
1644         }
1645
1646         *msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1647                   rx_status[0]);
1648
1649         if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1650                 *msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1651                              *msg_sz);
1652         else
1653                 *msg_ready = *msg_sz;
1654
1655         return 0;
1656 }
1657
1658 static ssize_t
1659 intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
1660                               u8 msg_id, bool paired)
1661 {
1662         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1663         bool msg_ready = false;
1664         int timeout, ret;
1665         ssize_t msg_sz = 0;
1666
1667         timeout = get_hdcp2_msg_timeout(msg_id, paired);
1668         if (timeout < 0)
1669                 return timeout;
1670
1671         ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port,
1672                                                              msg_id, &msg_ready,
1673                                                              &msg_sz),
1674                          !ret && msg_ready && msg_sz, timeout * 1000,
1675                          1000, 5 * 1000);
1676         if (ret)
1677                 drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n",
1678                             msg_id, ret, timeout);
1679
1680         return ret ? ret : msg_sz;
1681 }
1682
1683 static
1684 int intel_hdmi_hdcp2_write_msg(struct intel_digital_port *dig_port,
1685                                void *buf, size_t size)
1686 {
1687         unsigned int offset;
1688
1689         offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1690         return intel_hdmi_hdcp_write(dig_port, offset, buf, size);
1691 }
1692
1693 static
1694 int intel_hdmi_hdcp2_read_msg(struct intel_digital_port *dig_port,
1695                               u8 msg_id, void *buf, size_t size)
1696 {
1697         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1698         struct intel_hdmi *hdmi = &dig_port->hdmi;
1699         struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1700         unsigned int offset;
1701         ssize_t ret;
1702
1703         ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id,
1704                                             hdcp->is_paired);
1705         if (ret < 0)
1706                 return ret;
1707
1708         /*
1709          * Available msg size should be equal to or lesser than the
1710          * available buffer.
1711          */
1712         if (ret > size) {
1713                 drm_dbg_kms(&i915->drm,
1714                             "msg_sz(%zd) is more than exp size(%zu)\n",
1715                             ret, size);
1716                 return -1;
1717         }
1718
1719         offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1720         ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret);
1721         if (ret)
1722                 drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n",
1723                             msg_id, ret);
1724
1725         return ret;
1726 }
1727
1728 static
1729 int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port)
1730 {
1731         u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1732         int ret;
1733
1734         ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1735         if (ret)
1736                 return ret;
1737
1738         /*
1739          * Re-auth request and Link Integrity Failures are represented by
1740          * same bit. i.e reauth_req.
1741          */
1742         if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1743                 ret = HDCP_REAUTH_REQUEST;
1744         else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1745                 ret = HDCP_TOPOLOGY_CHANGE;
1746
1747         return ret;
1748 }
1749
1750 static
1751 int intel_hdmi_hdcp2_capable(struct intel_digital_port *dig_port,
1752                              bool *capable)
1753 {
1754         u8 hdcp2_version;
1755         int ret;
1756
1757         *capable = false;
1758         ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1759                                    &hdcp2_version, sizeof(hdcp2_version));
1760         if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1761                 *capable = true;
1762
1763         return ret;
1764 }
1765
1766 static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1767         .write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1768         .read_bksv = intel_hdmi_hdcp_read_bksv,
1769         .read_bstatus = intel_hdmi_hdcp_read_bstatus,
1770         .repeater_present = intel_hdmi_hdcp_repeater_present,
1771         .read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1772         .read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1773         .read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1774         .read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1775         .toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1776         .check_link = intel_hdmi_hdcp_check_link,
1777         .write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1778         .read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1779         .check_2_2_link = intel_hdmi_hdcp2_check_link,
1780         .hdcp_2_2_capable = intel_hdmi_hdcp2_capable,
1781         .protocol = HDCP_PROTOCOL_HDMI,
1782 };
1783
1784 static void intel_hdmi_prepare(struct intel_encoder *encoder,
1785                                const struct intel_crtc_state *crtc_state)
1786 {
1787         struct drm_device *dev = encoder->base.dev;
1788         struct drm_i915_private *dev_priv = to_i915(dev);
1789         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1790         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1791         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
1792         u32 hdmi_val;
1793
1794         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1795
1796         hdmi_val = SDVO_ENCODING_HDMI;
1797         if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1798                 hdmi_val |= HDMI_COLOR_RANGE_16_235;
1799         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1800                 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
1801         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1802                 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
1803
1804         if (crtc_state->pipe_bpp > 24)
1805                 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
1806         else
1807                 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
1808
1809         if (crtc_state->has_hdmi_sink)
1810                 hdmi_val |= HDMI_MODE_SELECT_HDMI;
1811
1812         if (HAS_PCH_CPT(dev_priv))
1813                 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1814         else if (IS_CHERRYVIEW(dev_priv))
1815                 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
1816         else
1817                 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
1818
1819         intel_de_write(dev_priv, intel_hdmi->hdmi_reg, hdmi_val);
1820         intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
1821 }
1822
1823 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
1824                                     enum pipe *pipe)
1825 {
1826         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1827         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1828         intel_wakeref_t wakeref;
1829         bool ret;
1830
1831         wakeref = intel_display_power_get_if_enabled(dev_priv,
1832                                                      encoder->power_domain);
1833         if (!wakeref)
1834                 return false;
1835
1836         ret = intel_sdvo_port_enabled(dev_priv, intel_hdmi->hdmi_reg, pipe);
1837
1838         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1839
1840         return ret;
1841 }
1842
1843 static void intel_hdmi_get_config(struct intel_encoder *encoder,
1844                                   struct intel_crtc_state *pipe_config)
1845 {
1846         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1847         struct drm_device *dev = encoder->base.dev;
1848         struct drm_i915_private *dev_priv = to_i915(dev);
1849         u32 tmp, flags = 0;
1850         int dotclock;
1851
1852         pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
1853
1854         tmp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
1855
1856         if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
1857                 flags |= DRM_MODE_FLAG_PHSYNC;
1858         else
1859                 flags |= DRM_MODE_FLAG_NHSYNC;
1860
1861         if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
1862                 flags |= DRM_MODE_FLAG_PVSYNC;
1863         else
1864                 flags |= DRM_MODE_FLAG_NVSYNC;
1865
1866         if (tmp & HDMI_MODE_SELECT_HDMI)
1867                 pipe_config->has_hdmi_sink = true;
1868
1869         pipe_config->infoframes.enable |=
1870                 intel_hdmi_infoframes_enabled(encoder, pipe_config);
1871
1872         if (pipe_config->infoframes.enable)
1873                 pipe_config->has_infoframe = true;
1874
1875         if (tmp & HDMI_AUDIO_ENABLE)
1876                 pipe_config->has_audio = true;
1877
1878         if (!HAS_PCH_SPLIT(dev_priv) &&
1879             tmp & HDMI_COLOR_RANGE_16_235)
1880                 pipe_config->limited_color_range = true;
1881
1882         pipe_config->hw.adjusted_mode.flags |= flags;
1883
1884         if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
1885                 dotclock = pipe_config->port_clock * 2 / 3;
1886         else
1887                 dotclock = pipe_config->port_clock;
1888
1889         if (pipe_config->pixel_multiplier)
1890                 dotclock /= pipe_config->pixel_multiplier;
1891
1892         pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
1893
1894         pipe_config->lane_count = 4;
1895
1896         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
1897
1898         intel_read_infoframe(encoder, pipe_config,
1899                              HDMI_INFOFRAME_TYPE_AVI,
1900                              &pipe_config->infoframes.avi);
1901         intel_read_infoframe(encoder, pipe_config,
1902                              HDMI_INFOFRAME_TYPE_SPD,
1903                              &pipe_config->infoframes.spd);
1904         intel_read_infoframe(encoder, pipe_config,
1905                              HDMI_INFOFRAME_TYPE_VENDOR,
1906                              &pipe_config->infoframes.hdmi);
1907 }
1908
1909 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1910                                     const struct intel_crtc_state *pipe_config,
1911                                     const struct drm_connector_state *conn_state)
1912 {
1913         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1914         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1915
1916         drm_WARN_ON(&i915->drm, !pipe_config->has_hdmi_sink);
1917         drm_dbg_kms(&i915->drm, "Enabling HDMI audio on pipe %c\n",
1918                     pipe_name(crtc->pipe));
1919         intel_audio_codec_enable(encoder, pipe_config, conn_state);
1920 }
1921
1922 static void g4x_enable_hdmi(struct intel_atomic_state *state,
1923                             struct intel_encoder *encoder,
1924                             const struct intel_crtc_state *pipe_config,
1925                             const struct drm_connector_state *conn_state)
1926 {
1927         struct drm_device *dev = encoder->base.dev;
1928         struct drm_i915_private *dev_priv = to_i915(dev);
1929         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1930         u32 temp;
1931
1932         temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
1933
1934         temp |= SDVO_ENABLE;
1935         if (pipe_config->has_audio)
1936                 temp |= HDMI_AUDIO_ENABLE;
1937
1938         intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
1939         intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
1940
1941         if (pipe_config->has_audio)
1942                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1943 }
1944
1945 static void ibx_enable_hdmi(struct intel_atomic_state *state,
1946                             struct intel_encoder *encoder,
1947                             const struct intel_crtc_state *pipe_config,
1948                             const struct drm_connector_state *conn_state)
1949 {
1950         struct drm_device *dev = encoder->base.dev;
1951         struct drm_i915_private *dev_priv = to_i915(dev);
1952         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1953         u32 temp;
1954
1955         temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
1956
1957         temp |= SDVO_ENABLE;
1958         if (pipe_config->has_audio)
1959                 temp |= HDMI_AUDIO_ENABLE;
1960
1961         /*
1962          * HW workaround, need to write this twice for issue
1963          * that may result in first write getting masked.
1964          */
1965         intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
1966         intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
1967         intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
1968         intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
1969
1970         /*
1971          * HW workaround, need to toggle enable bit off and on
1972          * for 12bpc with pixel repeat.
1973          *
1974          * FIXME: BSpec says this should be done at the end of
1975          * of the modeset sequence, so not sure if this isn't too soon.
1976          */
1977         if (pipe_config->pipe_bpp > 24 &&
1978             pipe_config->pixel_multiplier > 1) {
1979                 intel_de_write(dev_priv, intel_hdmi->hdmi_reg,
1980                                temp & ~SDVO_ENABLE);
1981                 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
1982
1983                 /*
1984                  * HW workaround, need to write this twice for issue
1985                  * that may result in first write getting masked.
1986                  */
1987                 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
1988                 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
1989                 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
1990                 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
1991         }
1992
1993         if (pipe_config->has_audio)
1994                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1995 }
1996
1997 static void cpt_enable_hdmi(struct intel_atomic_state *state,
1998                             struct intel_encoder *encoder,
1999                             const struct intel_crtc_state *pipe_config,
2000                             const struct drm_connector_state *conn_state)
2001 {
2002         struct drm_device *dev = encoder->base.dev;
2003         struct drm_i915_private *dev_priv = to_i915(dev);
2004         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2005         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2006         enum pipe pipe = crtc->pipe;
2007         u32 temp;
2008
2009         temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
2010
2011         temp |= SDVO_ENABLE;
2012         if (pipe_config->has_audio)
2013                 temp |= HDMI_AUDIO_ENABLE;
2014
2015         /*
2016          * WaEnableHDMI8bpcBefore12bpc:snb,ivb
2017          *
2018          * The procedure for 12bpc is as follows:
2019          * 1. disable HDMI clock gating
2020          * 2. enable HDMI with 8bpc
2021          * 3. enable HDMI with 12bpc
2022          * 4. enable HDMI clock gating
2023          */
2024
2025         if (pipe_config->pipe_bpp > 24) {
2026                 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe),
2027                                intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) | TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
2028
2029                 temp &= ~SDVO_COLOR_FORMAT_MASK;
2030                 temp |= SDVO_COLOR_FORMAT_8bpc;
2031         }
2032
2033         intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
2034         intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
2035
2036         if (pipe_config->pipe_bpp > 24) {
2037                 temp &= ~SDVO_COLOR_FORMAT_MASK;
2038                 temp |= HDMI_COLOR_FORMAT_12bpc;
2039
2040                 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
2041                 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
2042
2043                 intel_de_write(dev_priv, TRANS_CHICKEN1(pipe),
2044                                intel_de_read(dev_priv, TRANS_CHICKEN1(pipe)) & ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
2045         }
2046
2047         if (pipe_config->has_audio)
2048                 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
2049 }
2050
2051 static void vlv_enable_hdmi(struct intel_atomic_state *state,
2052                             struct intel_encoder *encoder,
2053                             const struct intel_crtc_state *pipe_config,
2054                             const struct drm_connector_state *conn_state)
2055 {
2056 }
2057
2058 static void intel_disable_hdmi(struct intel_atomic_state *state,
2059                                struct intel_encoder *encoder,
2060                                const struct intel_crtc_state *old_crtc_state,
2061                                const struct drm_connector_state *old_conn_state)
2062 {
2063         struct drm_device *dev = encoder->base.dev;
2064         struct drm_i915_private *dev_priv = to_i915(dev);
2065         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2066         struct intel_digital_port *dig_port =
2067                 hdmi_to_dig_port(intel_hdmi);
2068         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
2069         u32 temp;
2070
2071         temp = intel_de_read(dev_priv, intel_hdmi->hdmi_reg);
2072
2073         temp &= ~(SDVO_ENABLE | HDMI_AUDIO_ENABLE);
2074         intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
2075         intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
2076
2077         /*
2078          * HW workaround for IBX, we need to move the port
2079          * to transcoder A after disabling it to allow the
2080          * matching DP port to be enabled on transcoder A.
2081          */
2082         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
2083                 /*
2084                  * We get CPU/PCH FIFO underruns on the other pipe when
2085                  * doing the workaround. Sweep them under the rug.
2086                  */
2087                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
2088                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
2089
2090                 temp &= ~SDVO_PIPE_SEL_MASK;
2091                 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
2092                 /*
2093                  * HW workaround, need to write this twice for issue
2094                  * that may result in first write getting masked.
2095                  */
2096                 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
2097                 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
2098                 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
2099                 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
2100
2101                 temp &= ~SDVO_ENABLE;
2102                 intel_de_write(dev_priv, intel_hdmi->hdmi_reg, temp);
2103                 intel_de_posting_read(dev_priv, intel_hdmi->hdmi_reg);
2104
2105                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
2106                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
2107                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
2108         }
2109
2110         dig_port->set_infoframes(encoder,
2111                                        false,
2112                                        old_crtc_state, old_conn_state);
2113
2114         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2115 }
2116
2117 static void g4x_disable_hdmi(struct intel_atomic_state *state,
2118                              struct intel_encoder *encoder,
2119                              const struct intel_crtc_state *old_crtc_state,
2120                              const struct drm_connector_state *old_conn_state)
2121 {
2122         if (old_crtc_state->has_audio)
2123                 intel_audio_codec_disable(encoder,
2124                                           old_crtc_state, old_conn_state);
2125
2126         intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state);
2127 }
2128
2129 static void pch_disable_hdmi(struct intel_atomic_state *state,
2130                              struct intel_encoder *encoder,
2131                              const struct intel_crtc_state *old_crtc_state,
2132                              const struct drm_connector_state *old_conn_state)
2133 {
2134         if (old_crtc_state->has_audio)
2135                 intel_audio_codec_disable(encoder,
2136                                           old_crtc_state, old_conn_state);
2137 }
2138
2139 static void pch_post_disable_hdmi(struct intel_atomic_state *state,
2140                                   struct intel_encoder *encoder,
2141                                   const struct intel_crtc_state *old_crtc_state,
2142                                   const struct drm_connector_state *old_conn_state)
2143 {
2144         intel_disable_hdmi(state, encoder, old_crtc_state, old_conn_state);
2145 }
2146
2147 static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
2148 {
2149         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2150         int max_tmds_clock, vbt_max_tmds_clock;
2151
2152         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2153                 max_tmds_clock = 594000;
2154         else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv))
2155                 max_tmds_clock = 300000;
2156         else if (INTEL_GEN(dev_priv) >= 5)
2157                 max_tmds_clock = 225000;
2158         else
2159                 max_tmds_clock = 165000;
2160
2161         vbt_max_tmds_clock = intel_bios_max_tmds_clock(encoder);
2162         if (vbt_max_tmds_clock)
2163                 max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock);
2164
2165         return max_tmds_clock;
2166 }
2167
2168 static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi,
2169                                 const struct drm_connector_state *conn_state)
2170 {
2171         return hdmi->has_hdmi_sink &&
2172                 READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
2173 }
2174
2175 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
2176                                  bool respect_downstream_limits,
2177                                  bool has_hdmi_sink)
2178 {
2179         struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
2180         int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
2181
2182         if (respect_downstream_limits) {
2183                 struct intel_connector *connector = hdmi->attached_connector;
2184                 const struct drm_display_info *info = &connector->base.display_info;
2185
2186                 if (hdmi->dp_dual_mode.max_tmds_clock)
2187                         max_tmds_clock = min(max_tmds_clock,
2188                                              hdmi->dp_dual_mode.max_tmds_clock);
2189
2190                 if (info->max_tmds_clock)
2191                         max_tmds_clock = min(max_tmds_clock,
2192                                              info->max_tmds_clock);
2193                 else if (!has_hdmi_sink)
2194                         max_tmds_clock = min(max_tmds_clock, 165000);
2195         }
2196
2197         return max_tmds_clock;
2198 }
2199
2200 static enum drm_mode_status
2201 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
2202                       int clock, bool respect_downstream_limits,
2203                       bool has_hdmi_sink)
2204 {
2205         struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
2206
2207         if (clock < 25000)
2208                 return MODE_CLOCK_LOW;
2209         if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits,
2210                                           has_hdmi_sink))
2211                 return MODE_CLOCK_HIGH;
2212
2213         /* BXT DPLL can't generate 223-240 MHz */
2214         if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
2215                 return MODE_CLOCK_RANGE;
2216
2217         /* CHV DPLL can't generate 216-240 MHz */
2218         if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
2219                 return MODE_CLOCK_RANGE;
2220
2221         return MODE_OK;
2222 }
2223
2224 static enum drm_mode_status
2225 intel_hdmi_mode_valid(struct drm_connector *connector,
2226                       struct drm_display_mode *mode)
2227 {
2228         struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
2229         struct drm_device *dev = intel_hdmi_to_dev(hdmi);
2230         struct drm_i915_private *dev_priv = to_i915(dev);
2231         enum drm_mode_status status;
2232         int clock = mode->clock;
2233         int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
2234         bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state);
2235
2236         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
2237                 return MODE_NO_DBLESCAN;
2238
2239         if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
2240                 clock *= 2;
2241
2242         if (clock > max_dotclk)
2243                 return MODE_CLOCK_HIGH;
2244
2245         if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
2246                 if (!has_hdmi_sink)
2247                         return MODE_CLOCK_LOW;
2248                 clock *= 2;
2249         }
2250
2251         if (drm_mode_is_420_only(&connector->display_info, mode))
2252                 clock /= 2;
2253
2254         /* check if we can do 8bpc */
2255         status = hdmi_port_clock_valid(hdmi, clock, true, has_hdmi_sink);
2256
2257         if (has_hdmi_sink) {
2258                 /* if we can't do 8bpc we may still be able to do 12bpc */
2259                 if (status != MODE_OK && !HAS_GMCH(dev_priv))
2260                         status = hdmi_port_clock_valid(hdmi, clock * 3 / 2,
2261                                                        true, has_hdmi_sink);
2262
2263                 /* if we can't do 8,12bpc we may still be able to do 10bpc */
2264                 if (status != MODE_OK && INTEL_GEN(dev_priv) >= 11)
2265                         status = hdmi_port_clock_valid(hdmi, clock * 5 / 4,
2266                                                        true, has_hdmi_sink);
2267         }
2268         if (status != MODE_OK)
2269                 return status;
2270
2271         return intel_mode_valid_max_plane_size(dev_priv, mode);
2272 }
2273
2274 static bool hdmi_deep_color_possible(const struct intel_crtc_state *crtc_state,
2275                                      int bpc)
2276 {
2277         struct drm_i915_private *dev_priv =
2278                 to_i915(crtc_state->uapi.crtc->dev);
2279         struct drm_atomic_state *state = crtc_state->uapi.state;
2280         struct drm_connector_state *connector_state;
2281         struct drm_connector *connector;
2282         const struct drm_display_mode *adjusted_mode =
2283                 &crtc_state->hw.adjusted_mode;
2284         int i;
2285
2286         if (HAS_GMCH(dev_priv))
2287                 return false;
2288
2289         if (bpc == 10 && INTEL_GEN(dev_priv) < 11)
2290                 return false;
2291
2292         if (crtc_state->pipe_bpp < bpc * 3)
2293                 return false;
2294
2295         if (!crtc_state->has_hdmi_sink)
2296                 return false;
2297
2298         /*
2299          * HDMI deep color affects the clocks, so it's only possible
2300          * when not cloning with other encoder types.
2301          */
2302         if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
2303                 return false;
2304
2305         for_each_new_connector_in_state(state, connector, connector_state, i) {
2306                 const struct drm_display_info *info = &connector->display_info;
2307
2308                 if (connector_state->crtc != crtc_state->uapi.crtc)
2309                         continue;
2310
2311                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2312                         const struct drm_hdmi_info *hdmi = &info->hdmi;
2313
2314                         if (bpc == 12 && !(hdmi->y420_dc_modes &
2315                                            DRM_EDID_YCBCR420_DC_36))
2316                                 return false;
2317                         else if (bpc == 10 && !(hdmi->y420_dc_modes &
2318                                                 DRM_EDID_YCBCR420_DC_30))
2319                                 return false;
2320                 } else {
2321                         if (bpc == 12 && !(info->edid_hdmi_dc_modes &
2322                                            DRM_EDID_HDMI_DC_36))
2323                                 return false;
2324                         else if (bpc == 10 && !(info->edid_hdmi_dc_modes &
2325                                                 DRM_EDID_HDMI_DC_30))
2326                                 return false;
2327                 }
2328         }
2329
2330         /* Display Wa_1405510057:icl,ehl */
2331         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
2332             bpc == 10 && IS_GEN(dev_priv, 11) &&
2333             (adjusted_mode->crtc_hblank_end -
2334              adjusted_mode->crtc_hblank_start) % 8 == 2)
2335                 return false;
2336
2337         return true;
2338 }
2339
2340 static int
2341 intel_hdmi_ycbcr420_config(struct intel_crtc_state *crtc_state,
2342                            const struct drm_connector_state *conn_state)
2343 {
2344         struct drm_connector *connector = conn_state->connector;
2345         struct drm_i915_private *i915 = to_i915(connector->dev);
2346         const struct drm_display_mode *adjusted_mode =
2347                 &crtc_state->hw.adjusted_mode;
2348
2349         if (!drm_mode_is_420_only(&connector->display_info, adjusted_mode))
2350                 return 0;
2351
2352         if (!connector->ycbcr_420_allowed) {
2353                 drm_err(&i915->drm,
2354                         "Platform doesn't support YCBCR420 output\n");
2355                 return -EINVAL;
2356         }
2357
2358         crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2359
2360         return intel_pch_panel_fitting(crtc_state, conn_state);
2361 }
2362
2363 static int intel_hdmi_port_clock(int clock, int bpc)
2364 {
2365         /*
2366          * Need to adjust the port link by:
2367          *  1.5x for 12bpc
2368          *  1.25x for 10bpc
2369          */
2370         return clock * bpc / 8;
2371 }
2372
2373 static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2374                                   struct intel_crtc_state *crtc_state,
2375                                   int clock)
2376 {
2377         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2378         int bpc;
2379
2380         for (bpc = 12; bpc >= 10; bpc -= 2) {
2381                 if (hdmi_deep_color_possible(crtc_state, bpc) &&
2382                     hdmi_port_clock_valid(intel_hdmi,
2383                                           intel_hdmi_port_clock(clock, bpc),
2384                                           true, crtc_state->has_hdmi_sink) == MODE_OK)
2385                         return bpc;
2386         }
2387
2388         return 8;
2389 }
2390
2391 static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2392                                     struct intel_crtc_state *crtc_state)
2393 {
2394         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2395         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2396         const struct drm_display_mode *adjusted_mode =
2397                 &crtc_state->hw.adjusted_mode;
2398         int bpc, clock = adjusted_mode->crtc_clock;
2399
2400         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2401                 clock *= 2;
2402
2403         /* YCBCR420 TMDS rate requirement is half the pixel clock */
2404         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2405                 clock /= 2;
2406
2407         bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock);
2408
2409         crtc_state->port_clock = intel_hdmi_port_clock(clock, bpc);
2410
2411         /*
2412          * pipe_bpp could already be below 8bpc due to
2413          * FDI bandwidth constraints. We shouldn't bump it
2414          * back up to 8bpc in that case.
2415          */
2416         if (crtc_state->pipe_bpp > bpc * 3)
2417                 crtc_state->pipe_bpp = bpc * 3;
2418
2419         drm_dbg_kms(&i915->drm,
2420                     "picking %d bpc for HDMI output (pipe bpp: %d)\n",
2421                     bpc, crtc_state->pipe_bpp);
2422
2423         if (hdmi_port_clock_valid(intel_hdmi, crtc_state->port_clock,
2424                                   false, crtc_state->has_hdmi_sink) != MODE_OK) {
2425                 drm_dbg_kms(&i915->drm,
2426                             "unsupported HDMI clock (%d kHz), rejecting mode\n",
2427                             crtc_state->port_clock);
2428                 return -EINVAL;
2429         }
2430
2431         return 0;
2432 }
2433
2434 bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
2435                                     const struct drm_connector_state *conn_state)
2436 {
2437         const struct intel_digital_connector_state *intel_conn_state =
2438                 to_intel_digital_connector_state(conn_state);
2439         const struct drm_display_mode *adjusted_mode =
2440                 &crtc_state->hw.adjusted_mode;
2441
2442         /*
2443          * Our YCbCr output is always limited range.
2444          * crtc_state->limited_color_range only applies to RGB,
2445          * and it must never be set for YCbCr or we risk setting
2446          * some conflicting bits in PIPECONF which will mess up
2447          * the colors on the monitor.
2448          */
2449         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2450                 return false;
2451
2452         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2453                 /* See CEA-861-E - 5.1 Default Encoding Parameters */
2454                 return crtc_state->has_hdmi_sink &&
2455                         drm_default_rgb_quant_range(adjusted_mode) ==
2456                         HDMI_QUANTIZATION_RANGE_LIMITED;
2457         } else {
2458                 return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2459         }
2460 }
2461
2462 int intel_hdmi_compute_config(struct intel_encoder *encoder,
2463                               struct intel_crtc_state *pipe_config,
2464                               struct drm_connector_state *conn_state)
2465 {
2466         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2467         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2468         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2469         struct drm_connector *connector = conn_state->connector;
2470         struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2471         struct intel_digital_connector_state *intel_conn_state =
2472                 to_intel_digital_connector_state(conn_state);
2473         int ret;
2474
2475         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2476                 return -EINVAL;
2477
2478         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2479         pipe_config->has_hdmi_sink = intel_has_hdmi_sink(intel_hdmi,
2480                                                          conn_state);
2481
2482         if (pipe_config->has_hdmi_sink)
2483                 pipe_config->has_infoframe = true;
2484
2485         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2486                 pipe_config->pixel_multiplier = 2;
2487
2488         ret = intel_hdmi_ycbcr420_config(pipe_config, conn_state);
2489         if (ret)
2490                 return ret;
2491
2492         pipe_config->limited_color_range =
2493                 intel_hdmi_limited_color_range(pipe_config, conn_state);
2494
2495         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
2496                 pipe_config->has_pch_encoder = true;
2497
2498         if (pipe_config->has_hdmi_sink) {
2499                 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2500                         pipe_config->has_audio = intel_hdmi->has_audio;
2501                 else
2502                         pipe_config->has_audio =
2503                                 intel_conn_state->force_audio == HDMI_AUDIO_ON;
2504         }
2505
2506         ret = intel_hdmi_compute_clock(encoder, pipe_config);
2507         if (ret)
2508                 return ret;
2509
2510         if (conn_state->picture_aspect_ratio)
2511                 adjusted_mode->picture_aspect_ratio =
2512                         conn_state->picture_aspect_ratio;
2513
2514         pipe_config->lane_count = 4;
2515
2516         if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 ||
2517                                            IS_GEMINILAKE(dev_priv))) {
2518                 if (scdc->scrambling.low_rates)
2519                         pipe_config->hdmi_scrambling = true;
2520
2521                 if (pipe_config->port_clock > 340000) {
2522                         pipe_config->hdmi_scrambling = true;
2523                         pipe_config->hdmi_high_tmds_clock_ratio = true;
2524                 }
2525         }
2526
2527         intel_hdmi_compute_gcp_infoframe(encoder, pipe_config,
2528                                          conn_state);
2529
2530         if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2531                 drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n");
2532                 return -EINVAL;
2533         }
2534
2535         if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2536                 drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n");
2537                 return -EINVAL;
2538         }
2539
2540         if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2541                 drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n");
2542                 return -EINVAL;
2543         }
2544
2545         if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2546                 drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n");
2547                 return -EINVAL;
2548         }
2549
2550         return 0;
2551 }
2552
2553 static void
2554 intel_hdmi_unset_edid(struct drm_connector *connector)
2555 {
2556         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2557
2558         intel_hdmi->has_hdmi_sink = false;
2559         intel_hdmi->has_audio = false;
2560
2561         intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2562         intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2563
2564         kfree(to_intel_connector(connector)->detect_edid);
2565         to_intel_connector(connector)->detect_edid = NULL;
2566 }
2567
2568 static void
2569 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
2570 {
2571         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2572         struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
2573         enum port port = hdmi_to_dig_port(hdmi)->base.port;
2574         struct i2c_adapter *adapter =
2575                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
2576         enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
2577
2578         /*
2579          * Type 1 DVI adaptors are not required to implement any
2580          * registers, so we can't always detect their presence.
2581          * Ideally we should be able to check the state of the
2582          * CONFIG1 pin, but no such luck on our hardware.
2583          *
2584          * The only method left to us is to check the VBT to see
2585          * if the port is a dual mode capable DP port. But let's
2586          * only do that when we sucesfully read the EDID, to avoid
2587          * confusing log messages about DP dual mode adaptors when
2588          * there's nothing connected to the port.
2589          */
2590         if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2591                 /* An overridden EDID imply that we want this port for testing.
2592                  * Make sure not to set limits for that port.
2593                  */
2594                 if (has_edid && !connector->override_edid &&
2595                     intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
2596                         drm_dbg_kms(&dev_priv->drm,
2597                                     "Assuming DP dual mode adaptor presence based on VBT\n");
2598                         type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2599                 } else {
2600                         type = DRM_DP_DUAL_MODE_NONE;
2601                 }
2602         }
2603
2604         if (type == DRM_DP_DUAL_MODE_NONE)
2605                 return;
2606
2607         hdmi->dp_dual_mode.type = type;
2608         hdmi->dp_dual_mode.max_tmds_clock =
2609                 drm_dp_dual_mode_max_tmds_clock(type, adapter);
2610
2611         drm_dbg_kms(&dev_priv->drm,
2612                     "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2613                     drm_dp_get_dual_mode_type_name(type),
2614                     hdmi->dp_dual_mode.max_tmds_clock);
2615 }
2616
2617 static bool
2618 intel_hdmi_set_edid(struct drm_connector *connector)
2619 {
2620         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2621         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2622         intel_wakeref_t wakeref;
2623         struct edid *edid;
2624         bool connected = false;
2625         struct i2c_adapter *i2c;
2626
2627         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2628
2629         i2c = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2630
2631         edid = drm_get_edid(connector, i2c);
2632
2633         if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
2634                 drm_dbg_kms(&dev_priv->drm,
2635                             "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2636                 intel_gmbus_force_bit(i2c, true);
2637                 edid = drm_get_edid(connector, i2c);
2638                 intel_gmbus_force_bit(i2c, false);
2639         }
2640
2641         intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
2642
2643         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2644
2645         to_intel_connector(connector)->detect_edid = edid;
2646         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
2647                 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
2648                 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
2649
2650                 connected = true;
2651         }
2652
2653         cec_notifier_set_phys_addr_from_edid(intel_hdmi->cec_notifier, edid);
2654
2655         return connected;
2656 }
2657
2658 static enum drm_connector_status
2659 intel_hdmi_detect(struct drm_connector *connector, bool force)
2660 {
2661         enum drm_connector_status status = connector_status_disconnected;
2662         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2663         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2664         struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2665         intel_wakeref_t wakeref;
2666
2667         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
2668                     connector->base.id, connector->name);
2669
2670         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2671
2672         if (INTEL_GEN(dev_priv) >= 11 &&
2673             !intel_digital_port_connected(encoder))
2674                 goto out;
2675
2676         intel_hdmi_unset_edid(connector);
2677
2678         if (intel_hdmi_set_edid(connector))
2679                 status = connector_status_connected;
2680
2681 out:
2682         intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2683
2684         if (status != connector_status_connected)
2685                 cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2686
2687         /*
2688          * Make sure the refs for power wells enabled during detect are
2689          * dropped to avoid a new detect cycle triggered by HPD polling.
2690          */
2691         intel_display_power_flush_work(dev_priv);
2692
2693         return status;
2694 }
2695
2696 static void
2697 intel_hdmi_force(struct drm_connector *connector)
2698 {
2699         struct drm_i915_private *i915 = to_i915(connector->dev);
2700
2701         drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
2702                     connector->base.id, connector->name);
2703
2704         intel_hdmi_unset_edid(connector);
2705
2706         if (connector->status != connector_status_connected)
2707                 return;
2708
2709         intel_hdmi_set_edid(connector);
2710 }
2711
2712 static int intel_hdmi_get_modes(struct drm_connector *connector)
2713 {
2714         struct edid *edid;
2715
2716         edid = to_intel_connector(connector)->detect_edid;
2717         if (edid == NULL)
2718                 return 0;
2719
2720         return intel_connector_update_modes(connector, edid);
2721 }
2722
2723 static void intel_hdmi_pre_enable(struct intel_atomic_state *state,
2724                                   struct intel_encoder *encoder,
2725                                   const struct intel_crtc_state *pipe_config,
2726                                   const struct drm_connector_state *conn_state)
2727 {
2728         struct intel_digital_port *dig_port =
2729                 enc_to_dig_port(encoder);
2730
2731         intel_hdmi_prepare(encoder, pipe_config);
2732
2733         dig_port->set_infoframes(encoder,
2734                                        pipe_config->has_infoframe,
2735                                        pipe_config, conn_state);
2736 }
2737
2738 static void vlv_hdmi_pre_enable(struct intel_atomic_state *state,
2739                                 struct intel_encoder *encoder,
2740                                 const struct intel_crtc_state *pipe_config,
2741                                 const struct drm_connector_state *conn_state)
2742 {
2743         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2744         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2745
2746         vlv_phy_pre_encoder_enable(encoder, pipe_config);
2747
2748         /* HDMI 1.0V-2dB */
2749         vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
2750                                  0x2b247878);
2751
2752         dig_port->set_infoframes(encoder,
2753                               pipe_config->has_infoframe,
2754                               pipe_config, conn_state);
2755
2756         g4x_enable_hdmi(state, encoder, pipe_config, conn_state);
2757
2758         vlv_wait_port_ready(dev_priv, dig_port, 0x0);
2759 }
2760
2761 static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state,
2762                                     struct intel_encoder *encoder,
2763                                     const struct intel_crtc_state *pipe_config,
2764                                     const struct drm_connector_state *conn_state)
2765 {
2766         intel_hdmi_prepare(encoder, pipe_config);
2767
2768         vlv_phy_pre_pll_enable(encoder, pipe_config);
2769 }
2770
2771 static void chv_hdmi_pre_pll_enable(struct intel_atomic_state *state,
2772                                     struct intel_encoder *encoder,
2773                                     const struct intel_crtc_state *pipe_config,
2774                                     const struct drm_connector_state *conn_state)
2775 {
2776         intel_hdmi_prepare(encoder, pipe_config);
2777
2778         chv_phy_pre_pll_enable(encoder, pipe_config);
2779 }
2780
2781 static void chv_hdmi_post_pll_disable(struct intel_atomic_state *state,
2782                                       struct intel_encoder *encoder,
2783                                       const struct intel_crtc_state *old_crtc_state,
2784                                       const struct drm_connector_state *old_conn_state)
2785 {
2786         chv_phy_post_pll_disable(encoder, old_crtc_state);
2787 }
2788
2789 static void vlv_hdmi_post_disable(struct intel_atomic_state *state,
2790                                   struct intel_encoder *encoder,
2791                                   const struct intel_crtc_state *old_crtc_state,
2792                                   const struct drm_connector_state *old_conn_state)
2793 {
2794         /* Reset lanes to avoid HDMI flicker (VLV w/a) */
2795         vlv_phy_reset_lanes(encoder, old_crtc_state);
2796 }
2797
2798 static void chv_hdmi_post_disable(struct intel_atomic_state *state,
2799                                   struct intel_encoder *encoder,
2800                                   const struct intel_crtc_state *old_crtc_state,
2801                                   const struct drm_connector_state *old_conn_state)
2802 {
2803         struct drm_device *dev = encoder->base.dev;
2804         struct drm_i915_private *dev_priv = to_i915(dev);
2805
2806         vlv_dpio_get(dev_priv);
2807
2808         /* Assert data lane reset */
2809         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
2810
2811         vlv_dpio_put(dev_priv);
2812 }
2813
2814 static void chv_hdmi_pre_enable(struct intel_atomic_state *state,
2815                                 struct intel_encoder *encoder,
2816                                 const struct intel_crtc_state *pipe_config,
2817                                 const struct drm_connector_state *conn_state)
2818 {
2819         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2820         struct drm_device *dev = encoder->base.dev;
2821         struct drm_i915_private *dev_priv = to_i915(dev);
2822
2823         chv_phy_pre_encoder_enable(encoder, pipe_config);
2824
2825         /* FIXME: Program the support xxx V-dB */
2826         /* Use 800mV-0dB */
2827         chv_set_phy_signal_level(encoder, 128, 102, false);
2828
2829         dig_port->set_infoframes(encoder,
2830                               pipe_config->has_infoframe,
2831                               pipe_config, conn_state);
2832
2833         g4x_enable_hdmi(state, encoder, pipe_config, conn_state);
2834
2835         vlv_wait_port_ready(dev_priv, dig_port, 0x0);
2836
2837         /* Second common lane will stay alive on its own now */
2838         chv_phy_release_cl2_override(encoder);
2839 }
2840
2841 static struct i2c_adapter *
2842 intel_hdmi_get_i2c_adapter(struct drm_connector *connector)
2843 {
2844         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2845         struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2846
2847         return intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2848 }
2849
2850 static void intel_hdmi_create_i2c_symlink(struct drm_connector *connector)
2851 {
2852         struct drm_i915_private *i915 = to_i915(connector->dev);
2853         struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2854         struct kobject *i2c_kobj = &adapter->dev.kobj;
2855         struct kobject *connector_kobj = &connector->kdev->kobj;
2856         int ret;
2857
2858         ret = sysfs_create_link(connector_kobj, i2c_kobj, i2c_kobj->name);
2859         if (ret)
2860                 drm_err(&i915->drm, "Failed to create i2c symlink (%d)\n", ret);
2861 }
2862
2863 static void intel_hdmi_remove_i2c_symlink(struct drm_connector *connector)
2864 {
2865         struct i2c_adapter *adapter = intel_hdmi_get_i2c_adapter(connector);
2866         struct kobject *i2c_kobj = &adapter->dev.kobj;
2867         struct kobject *connector_kobj = &connector->kdev->kobj;
2868
2869         sysfs_remove_link(connector_kobj, i2c_kobj->name);
2870 }
2871
2872 static int
2873 intel_hdmi_connector_register(struct drm_connector *connector)
2874 {
2875         int ret;
2876
2877         ret = intel_connector_register(connector);
2878         if (ret)
2879                 return ret;
2880
2881         intel_hdmi_create_i2c_symlink(connector);
2882
2883         return ret;
2884 }
2885
2886 static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2887 {
2888         struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier;
2889
2890         cec_notifier_conn_unregister(n);
2891
2892         intel_hdmi_remove_i2c_symlink(connector);
2893         intel_connector_unregister(connector);
2894 }
2895
2896 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2897         .detect = intel_hdmi_detect,
2898         .force = intel_hdmi_force,
2899         .fill_modes = drm_helper_probe_single_connector_modes,
2900         .atomic_get_property = intel_digital_connector_atomic_get_property,
2901         .atomic_set_property = intel_digital_connector_atomic_set_property,
2902         .late_register = intel_hdmi_connector_register,
2903         .early_unregister = intel_hdmi_connector_unregister,
2904         .destroy = intel_connector_destroy,
2905         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2906         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
2907 };
2908
2909 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2910         .get_modes = intel_hdmi_get_modes,
2911         .mode_valid = intel_hdmi_mode_valid,
2912         .atomic_check = intel_digital_connector_atomic_check,
2913 };
2914
2915 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
2916         .destroy = intel_encoder_destroy,
2917 };
2918
2919 static void
2920 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2921 {
2922         struct drm_i915_private *dev_priv = to_i915(connector->dev);
2923         struct intel_digital_port *dig_port =
2924                                 hdmi_to_dig_port(intel_hdmi);
2925
2926         intel_attach_force_audio_property(connector);
2927         intel_attach_broadcast_rgb_property(connector);
2928         intel_attach_aspect_ratio_property(connector);
2929
2930         /*
2931          * Attach Colorspace property for Non LSPCON based device
2932          * ToDo: This needs to be extended for LSPCON implementation
2933          * as well. Will be implemented separately.
2934          */
2935         if (!dig_port->lspcon.active)
2936                 intel_attach_colorspace_property(connector);
2937
2938         drm_connector_attach_content_type_property(connector);
2939
2940         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
2941                 drm_object_attach_property(&connector->base,
2942                         connector->dev->mode_config.hdr_output_metadata_property, 0);
2943
2944         if (!HAS_GMCH(dev_priv))
2945                 drm_connector_attach_max_bpc_property(connector, 8, 12);
2946 }
2947
2948 /*
2949  * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2950  * @encoder: intel_encoder
2951  * @connector: drm_connector
2952  * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2953  *  or reset the high tmds clock ratio for scrambling
2954  * @scrambling: bool to Indicate if the function needs to set or reset
2955  *  sink scrambling
2956  *
2957  * This function handles scrambling on HDMI 2.0 capable sinks.
2958  * If required clock rate is > 340 Mhz && scrambling is supported by sink
2959  * it enables scrambling. This should be called before enabling the HDMI
2960  * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2961  * detect a scrambled clock within 100 ms.
2962  *
2963  * Returns:
2964  * True on success, false on failure.
2965  */
2966 bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2967                                        struct drm_connector *connector,
2968                                        bool high_tmds_clock_ratio,
2969                                        bool scrambling)
2970 {
2971         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2972         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2973         struct drm_scrambling *sink_scrambling =
2974                 &connector->display_info.hdmi.scdc.scrambling;
2975         struct i2c_adapter *adapter =
2976                 intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
2977
2978         if (!sink_scrambling->supported)
2979                 return true;
2980
2981         drm_dbg_kms(&dev_priv->drm,
2982                     "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2983                     connector->base.id, connector->name,
2984                     yesno(scrambling), high_tmds_clock_ratio ? 40 : 10);
2985
2986         /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2987         return drm_scdc_set_high_tmds_clock_ratio(adapter,
2988                                                   high_tmds_clock_ratio) &&
2989                 drm_scdc_set_scrambling(adapter, scrambling);
2990 }
2991
2992 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2993 {
2994         u8 ddc_pin;
2995
2996         switch (port) {
2997         case PORT_B:
2998                 ddc_pin = GMBUS_PIN_DPB;
2999                 break;
3000         case PORT_C:
3001                 ddc_pin = GMBUS_PIN_DPC;
3002                 break;
3003         case PORT_D:
3004                 ddc_pin = GMBUS_PIN_DPD_CHV;
3005                 break;
3006         default:
3007                 MISSING_CASE(port);
3008                 ddc_pin = GMBUS_PIN_DPB;
3009                 break;
3010         }
3011         return ddc_pin;
3012 }
3013
3014 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
3015 {
3016         u8 ddc_pin;
3017
3018         switch (port) {
3019         case PORT_B:
3020                 ddc_pin = GMBUS_PIN_1_BXT;
3021                 break;
3022         case PORT_C:
3023                 ddc_pin = GMBUS_PIN_2_BXT;
3024                 break;
3025         default:
3026                 MISSING_CASE(port);
3027                 ddc_pin = GMBUS_PIN_1_BXT;
3028                 break;
3029         }
3030         return ddc_pin;
3031 }
3032
3033 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
3034                               enum port port)
3035 {
3036         u8 ddc_pin;
3037
3038         switch (port) {
3039         case PORT_B:
3040                 ddc_pin = GMBUS_PIN_1_BXT;
3041                 break;
3042         case PORT_C:
3043                 ddc_pin = GMBUS_PIN_2_BXT;
3044                 break;
3045         case PORT_D:
3046                 ddc_pin = GMBUS_PIN_4_CNP;
3047                 break;
3048         case PORT_F:
3049                 ddc_pin = GMBUS_PIN_3_BXT;
3050                 break;
3051         default:
3052                 MISSING_CASE(port);
3053                 ddc_pin = GMBUS_PIN_1_BXT;
3054                 break;
3055         }
3056         return ddc_pin;
3057 }
3058
3059 static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
3060 {
3061         enum phy phy = intel_port_to_phy(dev_priv, port);
3062
3063         if (intel_phy_is_combo(dev_priv, phy))
3064                 return GMBUS_PIN_1_BXT + port;
3065         else if (intel_phy_is_tc(dev_priv, phy))
3066                 return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
3067
3068         drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port));
3069         return GMBUS_PIN_2_BXT;
3070 }
3071
3072 static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
3073 {
3074         enum phy phy = intel_port_to_phy(dev_priv, port);
3075         u8 ddc_pin;
3076
3077         switch (phy) {
3078         case PHY_A:
3079                 ddc_pin = GMBUS_PIN_1_BXT;
3080                 break;
3081         case PHY_B:
3082                 ddc_pin = GMBUS_PIN_2_BXT;
3083                 break;
3084         case PHY_C:
3085                 ddc_pin = GMBUS_PIN_9_TC1_ICP;
3086                 break;
3087         default:
3088                 MISSING_CASE(phy);
3089                 ddc_pin = GMBUS_PIN_1_BXT;
3090                 break;
3091         }
3092         return ddc_pin;
3093 }
3094
3095 static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
3096 {
3097         enum phy phy = intel_port_to_phy(dev_priv, port);
3098
3099         WARN_ON(port == PORT_C);
3100
3101         /*
3102          * Pin mapping for RKL depends on which PCH is present.  With TGP, the
3103          * final two outputs use type-c pins, even though they're actually
3104          * combo outputs.  With CMP, the traditional DDI A-D pins are used for
3105          * all outputs.
3106          */
3107         if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
3108                 return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
3109
3110         return GMBUS_PIN_1_BXT + phy;
3111 }
3112
3113 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
3114                               enum port port)
3115 {
3116         u8 ddc_pin;
3117
3118         switch (port) {
3119         case PORT_B:
3120                 ddc_pin = GMBUS_PIN_DPB;
3121                 break;
3122         case PORT_C:
3123                 ddc_pin = GMBUS_PIN_DPC;
3124                 break;
3125         case PORT_D:
3126                 ddc_pin = GMBUS_PIN_DPD;
3127                 break;
3128         default:
3129                 MISSING_CASE(port);
3130                 ddc_pin = GMBUS_PIN_DPB;
3131                 break;
3132         }
3133         return ddc_pin;
3134 }
3135
3136 static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
3137 {
3138         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3139         enum port port = encoder->port;
3140         u8 ddc_pin;
3141
3142         ddc_pin = intel_bios_alternate_ddc_pin(encoder);
3143         if (ddc_pin) {
3144                 drm_dbg_kms(&dev_priv->drm,
3145                             "Using DDC pin 0x%x for port %c (VBT)\n",
3146                             ddc_pin, port_name(port));
3147                 return ddc_pin;
3148         }
3149
3150         if (IS_ROCKETLAKE(dev_priv))
3151                 ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
3152         else if (HAS_PCH_MCC(dev_priv))
3153                 ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
3154         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3155                 ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
3156         else if (HAS_PCH_CNP(dev_priv))
3157                 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
3158         else if (IS_GEN9_LP(dev_priv))
3159                 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
3160         else if (IS_CHERRYVIEW(dev_priv))
3161                 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
3162         else
3163                 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
3164
3165         drm_dbg_kms(&dev_priv->drm,
3166                     "Using DDC pin 0x%x for port %c (platform default)\n",
3167                     ddc_pin, port_name(port));
3168
3169         return ddc_pin;
3170 }
3171
3172 void intel_infoframe_init(struct intel_digital_port *dig_port)
3173 {
3174         struct drm_i915_private *dev_priv =
3175                 to_i915(dig_port->base.base.dev);
3176
3177         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3178                 dig_port->write_infoframe = vlv_write_infoframe;
3179                 dig_port->read_infoframe = vlv_read_infoframe;
3180                 dig_port->set_infoframes = vlv_set_infoframes;
3181                 dig_port->infoframes_enabled = vlv_infoframes_enabled;
3182         } else if (IS_G4X(dev_priv)) {
3183                 dig_port->write_infoframe = g4x_write_infoframe;
3184                 dig_port->read_infoframe = g4x_read_infoframe;
3185                 dig_port->set_infoframes = g4x_set_infoframes;
3186                 dig_port->infoframes_enabled = g4x_infoframes_enabled;
3187         } else if (HAS_DDI(dev_priv)) {
3188                 if (dig_port->lspcon.active) {
3189                         dig_port->write_infoframe = lspcon_write_infoframe;
3190                         dig_port->read_infoframe = lspcon_read_infoframe;
3191                         dig_port->set_infoframes = lspcon_set_infoframes;
3192                         dig_port->infoframes_enabled = lspcon_infoframes_enabled;
3193                 } else {
3194                         dig_port->write_infoframe = hsw_write_infoframe;
3195                         dig_port->read_infoframe = hsw_read_infoframe;
3196                         dig_port->set_infoframes = hsw_set_infoframes;
3197                         dig_port->infoframes_enabled = hsw_infoframes_enabled;
3198                 }
3199         } else if (HAS_PCH_IBX(dev_priv)) {
3200                 dig_port->write_infoframe = ibx_write_infoframe;
3201                 dig_port->read_infoframe = ibx_read_infoframe;
3202                 dig_port->set_infoframes = ibx_set_infoframes;
3203                 dig_port->infoframes_enabled = ibx_infoframes_enabled;
3204         } else {
3205                 dig_port->write_infoframe = cpt_write_infoframe;
3206                 dig_port->read_infoframe = cpt_read_infoframe;
3207                 dig_port->set_infoframes = cpt_set_infoframes;
3208                 dig_port->infoframes_enabled = cpt_infoframes_enabled;
3209         }
3210 }
3211
3212 void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
3213                                struct intel_connector *intel_connector)
3214 {
3215         struct drm_connector *connector = &intel_connector->base;
3216         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3217         struct intel_encoder *intel_encoder = &dig_port->base;
3218         struct drm_device *dev = intel_encoder->base.dev;
3219         struct drm_i915_private *dev_priv = to_i915(dev);
3220         struct i2c_adapter *ddc;
3221         enum port port = intel_encoder->port;
3222         struct cec_connector_info conn_info;
3223
3224         drm_dbg_kms(&dev_priv->drm,
3225                     "Adding HDMI connector on [ENCODER:%d:%s]\n",
3226                     intel_encoder->base.base.id, intel_encoder->base.name);
3227
3228         if (INTEL_GEN(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A))
3229                 return;
3230
3231         if (drm_WARN(dev, dig_port->max_lanes < 4,
3232                      "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
3233                      dig_port->max_lanes, intel_encoder->base.base.id,
3234                      intel_encoder->base.name))
3235                 return;
3236
3237         intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder);
3238         ddc = intel_gmbus_get_adapter(dev_priv, intel_hdmi->ddc_bus);
3239
3240         drm_connector_init_with_ddc(dev, connector,
3241                                     &intel_hdmi_connector_funcs,
3242                                     DRM_MODE_CONNECTOR_HDMIA,
3243                                     ddc);
3244         drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
3245
3246         connector->interlace_allowed = 1;
3247         connector->doublescan_allowed = 0;
3248         connector->stereo_allowed = 1;
3249
3250         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
3251                 connector->ycbcr_420_allowed = true;
3252
3253         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
3254         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
3255
3256         if (HAS_DDI(dev_priv))
3257                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3258         else
3259                 intel_connector->get_hw_state = intel_connector_get_hw_state;
3260
3261         intel_hdmi_add_properties(intel_hdmi, connector);
3262
3263         intel_connector_attach_encoder(intel_connector, intel_encoder);
3264         intel_hdmi->attached_connector = intel_connector;
3265
3266         if (is_hdcp_supported(dev_priv, port)) {
3267                 int ret = intel_hdcp_init(intel_connector,
3268                                           &intel_hdmi_hdcp_shim);
3269                 if (ret)
3270                         drm_dbg_kms(&dev_priv->drm,
3271                                     "HDCP init failed, skipping.\n");
3272         }
3273
3274         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
3275          * 0xd.  Failure to do so will result in spurious interrupts being
3276          * generated on the port when a cable is not attached.
3277          */
3278         if (IS_G45(dev_priv)) {
3279                 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
3280                 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
3281                                (temp & ~0xf) | 0xd);
3282         }
3283
3284         cec_fill_conn_info_from_drm(&conn_info, connector);
3285
3286         intel_hdmi->cec_notifier =
3287                 cec_notifier_conn_register(dev->dev, port_identifier(port),
3288                                            &conn_info);
3289         if (!intel_hdmi->cec_notifier)
3290                 drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n");
3291 }
3292
3293 static enum intel_hotplug_state
3294 intel_hdmi_hotplug(struct intel_encoder *encoder,
3295                    struct intel_connector *connector)
3296 {
3297         enum intel_hotplug_state state;
3298
3299         state = intel_encoder_hotplug(encoder, connector);
3300
3301         /*
3302          * On many platforms the HDMI live state signal is known to be
3303          * unreliable, so we can't use it to detect if a sink is connected or
3304          * not. Instead we detect if it's connected based on whether we can
3305          * read the EDID or not. That in turn has a problem during disconnect,
3306          * since the HPD interrupt may be raised before the DDC lines get
3307          * disconnected (due to how the required length of DDC vs. HPD
3308          * connector pins are specified) and so we'll still be able to get a
3309          * valid EDID. To solve this schedule another detection cycle if this
3310          * time around we didn't detect any change in the sink's connection
3311          * status.
3312          */
3313         if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
3314                 state = INTEL_HOTPLUG_RETRY;
3315
3316         return state;
3317 }
3318
3319 void intel_hdmi_init(struct drm_i915_private *dev_priv,
3320                      i915_reg_t hdmi_reg, enum port port)
3321 {
3322         struct intel_digital_port *dig_port;
3323         struct intel_encoder *intel_encoder;
3324         struct intel_connector *intel_connector;
3325
3326         dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
3327         if (!dig_port)
3328                 return;
3329
3330         intel_connector = intel_connector_alloc();
3331         if (!intel_connector) {
3332                 kfree(dig_port);
3333                 return;
3334         }
3335
3336         intel_encoder = &dig_port->base;
3337
3338         drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3339                          &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
3340                          "HDMI %c", port_name(port));
3341
3342         intel_encoder->hotplug = intel_hdmi_hotplug;
3343         intel_encoder->compute_config = intel_hdmi_compute_config;
3344         if (HAS_PCH_SPLIT(dev_priv)) {
3345                 intel_encoder->disable = pch_disable_hdmi;
3346                 intel_encoder->post_disable = pch_post_disable_hdmi;
3347         } else {
3348                 intel_encoder->disable = g4x_disable_hdmi;
3349         }
3350         intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
3351         intel_encoder->get_config = intel_hdmi_get_config;
3352         if (IS_CHERRYVIEW(dev_priv)) {
3353                 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
3354                 intel_encoder->pre_enable = chv_hdmi_pre_enable;
3355                 intel_encoder->enable = vlv_enable_hdmi;
3356                 intel_encoder->post_disable = chv_hdmi_post_disable;
3357                 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
3358         } else if (IS_VALLEYVIEW(dev_priv)) {
3359                 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
3360                 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
3361                 intel_encoder->enable = vlv_enable_hdmi;
3362                 intel_encoder->post_disable = vlv_hdmi_post_disable;
3363         } else {
3364                 intel_encoder->pre_enable = intel_hdmi_pre_enable;
3365                 if (HAS_PCH_CPT(dev_priv))
3366                         intel_encoder->enable = cpt_enable_hdmi;
3367                 else if (HAS_PCH_IBX(dev_priv))
3368                         intel_encoder->enable = ibx_enable_hdmi;
3369                 else
3370                         intel_encoder->enable = g4x_enable_hdmi;
3371         }
3372
3373         intel_encoder->type = INTEL_OUTPUT_HDMI;
3374         intel_encoder->power_domain = intel_port_to_power_domain(port);
3375         intel_encoder->port = port;
3376         if (IS_CHERRYVIEW(dev_priv)) {
3377                 if (port == PORT_D)
3378                         intel_encoder->pipe_mask = BIT(PIPE_C);
3379                 else
3380                         intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
3381         } else {
3382                 intel_encoder->pipe_mask = ~0;
3383         }
3384         intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
3385         /*
3386          * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
3387          * to work on real hardware. And since g4x can send infoframes to
3388          * only one port anyway, nothing is lost by allowing it.
3389          */
3390         if (IS_G4X(dev_priv))
3391                 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
3392
3393         dig_port->hdmi.hdmi_reg = hdmi_reg;
3394         dig_port->dp.output_reg = INVALID_MMIO_REG;
3395         dig_port->max_lanes = 4;
3396
3397         intel_infoframe_init(dig_port);
3398
3399         dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
3400         intel_hdmi_init_connector(dig_port, intel_connector);
3401 }