drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #define SWSMU_CODE_LAYER_L1
  24
  25 #include <linux/firmware.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_smu.h"
  30 #include "smu_internal.h"
  31 #include "atom.h"
  32 #include "arcturus_ppt.h"
  33 #include "navi10_ppt.h"
  34 #include "sienna_cichlid_ppt.h"
  35 #include "renoir_ppt.h"
  36 #include "amd_pcie.h"
  37
  38 /*
  39  * DO NOT use these for err/warn/info/debug messages.
  40  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  41  * They are more MGPU friendly.
  42  */
  43 #undef pr_err
  44 #undef pr_warn
  45 #undef pr_info
  46 #undef pr_debug
  47
  48 size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
  49 {
  50         size_t size = 0;
  51
  52         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
  53                 return -EOPNOTSUPP;
  54
  55         mutex_lock(&smu->mutex);
  56
  57         size = smu_get_pp_feature_mask(smu, buf);
  58
  59         mutex_unlock(&smu->mutex);
  60
  61         return size;
  62 }
  63
  64 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
  65 {
  66         int ret = 0;
  67
  68         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
  69                 return -EOPNOTSUPP;
  70
  71         mutex_lock(&smu->mutex);
  72
  73         ret = smu_set_pp_feature_mask(smu, new_mask);
  74
  75         mutex_unlock(&smu->mutex);
  76
  77         return ret;
  78 }
  79
  80 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value)
  81 {
  82         int ret = 0;
  83         struct smu_context *smu = &adev->smu;
  84
  85         if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status)
  86                 *value = smu_get_gfx_off_status(smu);
  87         else
  88                 ret = -EINVAL;
  89
  90         return ret;
  91 }
  92
  93 int smu_set_soft_freq_range(struct smu_context *smu,
  94                             enum smu_clk_type clk_type,
  95                             uint32_t min,
  96                             uint32_t max)
  97 {
  98         int ret = 0;
  99
 100         mutex_lock(&smu->mutex);
 101
 102         if (smu->ppt_funcs->set_soft_freq_limited_range)
 103                 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,
 104                                                                   clk_type,
 105                                                                   min,
 106                                                                   max);
 107
 108         mutex_unlock(&smu->mutex);
 109
 110         return ret;
 111 }
 112
 113 int smu_get_dpm_freq_range(struct smu_context *smu,
 114                            enum smu_clk_type clk_type,
 115                            uint32_t *min,
 116                            uint32_t *max)
 117 {
 118         int ret = 0;
 119
 120         if (!min && !max)
 121                 return -EINVAL;
 122
 123         mutex_lock(&smu->mutex);
 124
 125         if (smu->ppt_funcs->get_dpm_ultimate_freq)
 126                 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu,
 127                                                             clk_type,
 128                                                             min,
 129                                                             max);
 130
 131         mutex_unlock(&smu->mutex);
 132
 133         return ret;
 134 }
 135
 136 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu,
 137                                          bool enable)
 138 {
 139         struct smu_power_context *smu_power = &smu->smu_power;
 140         struct smu_power_gate *power_gate = &smu_power->power_gate;
 141         int ret = 0;
 142
 143         if (!smu->ppt_funcs->dpm_set_vcn_enable)
 144                 return 0;
 145
 146         if (atomic_read(&power_gate->vcn_gated) ^ enable)
 147                 return 0;
 148
 149         ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
 150         if (!ret)
 151                 atomic_set(&power_gate->vcn_gated, !enable);
 152
 153         return ret;
 154 }
 155
 156 static int smu_dpm_set_vcn_enable(struct smu_context *smu,
 157                                   bool enable)
 158 {
 159         struct smu_power_context *smu_power = &smu->smu_power;
 160         struct smu_power_gate *power_gate = &smu_power->power_gate;
 161         int ret = 0;
 162
 163         mutex_lock(&power_gate->vcn_gate_lock);
 164
 165         ret = smu_dpm_set_vcn_enable_locked(smu, enable);
 166
 167         mutex_unlock(&power_gate->vcn_gate_lock);
 168
 169         return ret;
 170 }
 171
 172 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu,
 173                                           bool enable)
 174 {
 175         struct smu_power_context *smu_power = &smu->smu_power;
 176         struct smu_power_gate *power_gate = &smu_power->power_gate;
 177         int ret = 0;
 178
 179         if (!smu->ppt_funcs->dpm_set_jpeg_enable)
 180                 return 0;
 181
 182         if (atomic_read(&power_gate->jpeg_gated) ^ enable)
 183                 return 0;
 184
 185         ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
 186         if (!ret)
 187                 atomic_set(&power_gate->jpeg_gated, !enable);
 188
 189         return ret;
 190 }
 191
 192 static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
 193                                    bool enable)
 194 {
 195         struct smu_power_context *smu_power = &smu->smu_power;
 196         struct smu_power_gate *power_gate = &smu_power->power_gate;
 197         int ret = 0;
 198
 199         mutex_lock(&power_gate->jpeg_gate_lock);
 200
 201         ret = smu_dpm_set_jpeg_enable_locked(smu, enable);
 202
 203         mutex_unlock(&power_gate->jpeg_gate_lock);
 204
 205         return ret;
 206 }
 207
 208 /**
 209  * smu_dpm_set_power_gate - power gate/ungate the specific IP block
 210  *
 211  * @smu:        smu_context pointer
 212  * @block_type: the IP block to power gate/ungate
 213  * @gate:       to power gate if true, ungate otherwise
 214  *
 215  * This API uses no smu->mutex lock protection due to:
 216  * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
 217  *    This is guarded to be race condition free by the caller.
 218  * 2. Or get called on user setting request of power_dpm_force_performance_level.
 219  *    Under this case, the smu->mutex lock protection is already enforced on
 220  *    the parent API smu_force_performance_level of the call path.
 221  */
 222 int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
 223                            bool gate)
 224 {
 225         int ret = 0;
 226
 227         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 228                 return -EOPNOTSUPP;
 229
 230         switch (block_type) {
 231         /*
 232          * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
 233          * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
 234          */
 235         case AMD_IP_BLOCK_TYPE_UVD:
 236         case AMD_IP_BLOCK_TYPE_VCN:
 237                 ret = smu_dpm_set_vcn_enable(smu, !gate);
 238                 if (ret)
 239                         dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
 240                                 gate ? "gate" : "ungate");
 241                 break;
 242         case AMD_IP_BLOCK_TYPE_GFX:
 243                 ret = smu_gfx_off_control(smu, gate);
 244                 if (ret)
 245                         dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
 246                                 gate ? "enable" : "disable");
 247                 break;
 248         case AMD_IP_BLOCK_TYPE_SDMA:
 249                 ret = smu_powergate_sdma(smu, gate);
 250                 if (ret)
 251                         dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
 252                                 gate ? "gate" : "ungate");
 253                 break;
 254         case AMD_IP_BLOCK_TYPE_JPEG:
 255                 ret = smu_dpm_set_jpeg_enable(smu, !gate);
 256                 if (ret)
 257                         dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
 258                                 gate ? "gate" : "ungate");
 259                 break;
 260         default:
 261                 dev_err(smu->adev->dev, "Unsupported block type!\n");
 262                 return -EINVAL;
 263         }
 264
 265         return ret;
 266 }
 267
 268 int smu_get_power_num_states(struct smu_context *smu,
 269                              struct pp_states_info *state_info)
 270 {
 271         if (!state_info)
 272                 return -EINVAL;
 273
 274         /* not support power state */
 275         memset(state_info, 0, sizeof(struct pp_states_info));
 276         state_info->nums = 1;
 277         state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
 278
 279         return 0;
 280 }
 281
 282 bool is_support_sw_smu(struct amdgpu_device *adev)
 283 {
 284         if (adev->asic_type >= CHIP_ARCTURUS)
 285                 return true;
 286
 287         return false;
 288 }
 289
 290 int smu_sys_get_pp_table(struct smu_context *smu, void **table)
 291 {
 292         struct smu_table_context *smu_table = &smu->smu_table;
 293         uint32_t powerplay_table_size;
 294
 295         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 296                 return -EOPNOTSUPP;
 297
 298         if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
 299                 return -EINVAL;
 300
 301         mutex_lock(&smu->mutex);
 302
 303         if (smu_table->hardcode_pptable)
 304                 *table = smu_table->hardcode_pptable;
 305         else
 306                 *table = smu_table->power_play_table;
 307
 308         powerplay_table_size = smu_table->power_play_table_size;
 309
 310         mutex_unlock(&smu->mutex);
 311
 312         return powerplay_table_size;
 313 }
 314
 315 int smu_sys_set_pp_table(struct smu_context *smu,  void *buf, size_t size)
 316 {
 317         struct smu_table_context *smu_table = &smu->smu_table;
 318         ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
 319         int ret = 0;
 320
 321         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 322                 return -EOPNOTSUPP;
 323
 324         if (header->usStructureSize != size) {
 325                 dev_err(smu->adev->dev, "pp table size not matched !\n");
 326                 return -EIO;
 327         }
 328
 329         mutex_lock(&smu->mutex);
 330         if (!smu_table->hardcode_pptable)
 331                 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
 332         if (!smu_table->hardcode_pptable) {
 333                 ret = -ENOMEM;
 334                 goto failed;
 335         }
 336
 337         memcpy(smu_table->hardcode_pptable, buf, size);
 338         smu_table->power_play_table = smu_table->hardcode_pptable;
 339         smu_table->power_play_table_size = size;
 340
 341         /*
 342          * Special hw_fini action(for Navi1x, the DPMs disablement will be
 343          * skipped) may be needed for custom pptable uploading.
 344          */
 345         smu->uploading_custom_pp_table = true;
 346
 347         ret = smu_reset(smu);
 348         if (ret)
 349                 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
 350
 351         smu->uploading_custom_pp_table = false;
 352
 353 failed:
 354         mutex_unlock(&smu->mutex);
 355         return ret;
 356 }
 357
 358 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
 359 {
 360         struct smu_feature *feature = &smu->smu_feature;
 361         int ret = 0;
 362         uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
 363
 364         mutex_lock(&feature->mutex);
 365         bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
 366         mutex_unlock(&feature->mutex);
 367
 368         ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
 369                                              SMU_FEATURE_MAX/32);
 370         if (ret)
 371                 return ret;
 372
 373         mutex_lock(&feature->mutex);
 374         bitmap_or(feature->allowed, feature->allowed,
 375                       (unsigned long *)allowed_feature_mask,
 376                       feature->feature_num);
 377         mutex_unlock(&feature->mutex);
 378
 379         return ret;
 380 }
 381
 382 static int smu_set_funcs(struct amdgpu_device *adev)
 383 {
 384         struct smu_context *smu = &adev->smu;
 385
 386         if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
 387                 smu->od_enabled = true;
 388
 389         switch (adev->asic_type) {
 390         case CHIP_NAVI10:
 391         case CHIP_NAVI14:
 392         case CHIP_NAVI12:
 393                 navi10_set_ppt_funcs(smu);
 394                 break;
 395         case CHIP_ARCTURUS:
 396                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 397                 arcturus_set_ppt_funcs(smu);
 398                 /* OD is not supported on Arcturus */
 399                 smu->od_enabled =false;
 400                 break;
 401         case CHIP_SIENNA_CICHLID:
 402         case CHIP_NAVY_FLOUNDER:
 403                 sienna_cichlid_set_ppt_funcs(smu);
 404                 break;
 405         case CHIP_RENOIR:
 406                 renoir_set_ppt_funcs(smu);
 407                 break;
 408         default:
 409                 return -EINVAL;
 410         }
 411
 412         return 0;
 413 }
 414
 415 static int smu_early_init(void *handle)
 416 {
 417         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 418         struct smu_context *smu = &adev->smu;
 419
 420         smu->adev = adev;
 421         smu->pm_enabled = !!amdgpu_dpm;
 422         smu->is_apu = false;
 423         mutex_init(&smu->mutex);
 424
 425         return smu_set_funcs(adev);
 426 }
 427
 428 static int smu_set_default_dpm_table(struct smu_context *smu)
 429 {
 430         struct smu_power_context *smu_power = &smu->smu_power;
 431         struct smu_power_gate *power_gate = &smu_power->power_gate;
 432         int vcn_gate, jpeg_gate;
 433         int ret = 0;
 434
 435         if (!smu->ppt_funcs->set_default_dpm_table)
 436                 return 0;
 437
 438         mutex_lock(&power_gate->vcn_gate_lock);
 439         mutex_lock(&power_gate->jpeg_gate_lock);
 440
 441         vcn_gate = atomic_read(&power_gate->vcn_gated);
 442         jpeg_gate = atomic_read(&power_gate->jpeg_gated);
 443
 444         ret = smu_dpm_set_vcn_enable_locked(smu, true);
 445         if (ret)
 446                 goto err0_out;
 447
 448         ret = smu_dpm_set_jpeg_enable_locked(smu, true);
 449         if (ret)
 450                 goto err1_out;
 451
 452         ret = smu->ppt_funcs->set_default_dpm_table(smu);
 453         if (ret)
 454                 dev_err(smu->adev->dev,
 455                         "Failed to setup default dpm clock tables!\n");
 456
 457         smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate);
 458 err1_out:
 459         smu_dpm_set_vcn_enable_locked(smu, !vcn_gate);
 460 err0_out:
 461         mutex_unlock(&power_gate->jpeg_gate_lock);
 462         mutex_unlock(&power_gate->vcn_gate_lock);
 463
 464         return ret;
 465 }
 466
 467 static int smu_late_init(void *handle)
 468 {
 469         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 470         struct smu_context *smu = &adev->smu;
 471         int ret = 0;
 472
 473         if (!smu->pm_enabled)
 474                 return 0;
 475
 476         ret = smu_set_default_od_settings(smu);
 477         if (ret) {
 478                 dev_err(adev->dev, "Failed to setup default OD settings!\n");
 479                 return ret;
 480         }
 481
 482         /*
 483          * Set initialized values (get from vbios) to dpm tables context such as
 484          * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
 485          * type of clks.
 486          */
 487         ret = smu_set_default_dpm_table(smu);
 488         if (ret) {
 489                 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
 490                 return ret;
 491         }
 492
 493         ret = smu_populate_umd_state_clk(smu);
 494         if (ret) {
 495                 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
 496                 return ret;
 497         }
 498
 499         ret = smu_get_asic_power_limits(smu);
 500         if (ret) {
 501                 dev_err(adev->dev, "Failed to get asic power limits!\n");
 502                 return ret;
 503         }
 504
 505         smu_get_unique_id(smu);
 506
 507         smu_handle_task(&adev->smu,
 508                         smu->smu_dpm.dpm_level,
 509                         AMD_PP_TASK_COMPLETE_INIT,
 510                         false);
 511
 512         return 0;
 513 }
 514
 515 static int smu_init_fb_allocations(struct smu_context *smu)
 516 {
 517         struct amdgpu_device *adev = smu->adev;
 518         struct smu_table_context *smu_table = &smu->smu_table;
 519         struct smu_table *tables = smu_table->tables;
 520         struct smu_table *driver_table = &(smu_table->driver_table);
 521         uint32_t max_table_size = 0;
 522         int ret, i;
 523
 524         /* VRAM allocation for tool table */
 525         if (tables[SMU_TABLE_PMSTATUSLOG].size) {
 526                 ret = amdgpu_bo_create_kernel(adev,
 527                                               tables[SMU_TABLE_PMSTATUSLOG].size,
 528                                               tables[SMU_TABLE_PMSTATUSLOG].align,
 529                                               tables[SMU_TABLE_PMSTATUSLOG].domain,
 530                                               &tables[SMU_TABLE_PMSTATUSLOG].bo,
 531                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 532                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 533                 if (ret) {
 534                         dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
 535                         return ret;
 536                 }
 537         }
 538
 539         /* VRAM allocation for driver table */
 540         for (i = 0; i < SMU_TABLE_COUNT; i++) {
 541                 if (tables[i].size == 0)
 542                         continue;
 543
 544                 if (i == SMU_TABLE_PMSTATUSLOG)
 545                         continue;
 546
 547                 if (max_table_size < tables[i].size)
 548                         max_table_size = tables[i].size;
 549         }
 550
 551         driver_table->size = max_table_size;
 552         driver_table->align = PAGE_SIZE;
 553         driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
 554
 555         ret = amdgpu_bo_create_kernel(adev,
 556                                       driver_table->size,
 557                                       driver_table->align,
 558                                       driver_table->domain,
 559                                       &driver_table->bo,
 560                                       &driver_table->mc_address,
 561                                       &driver_table->cpu_addr);
 562         if (ret) {
 563                 dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
 564                 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 565                         amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 566                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 567                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 568         }
 569
 570         return ret;
 571 }
 572
 573 static int smu_fini_fb_allocations(struct smu_context *smu)
 574 {
 575         struct smu_table_context *smu_table = &smu->smu_table;
 576         struct smu_table *tables = smu_table->tables;
 577         struct smu_table *driver_table = &(smu_table->driver_table);
 578
 579         if (!tables)
 580                 return 0;
 581
 582         if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 583                 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 584                                       &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 585                                       &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 586
 587         amdgpu_bo_free_kernel(&driver_table->bo,
 588                               &driver_table->mc_address,
 589                               &driver_table->cpu_addr);
 590
 591         return 0;
 592 }
 593
 594 /**
 595  * smu_alloc_memory_pool - allocate memory pool in the system memory
 596  *
 597  * @smu: amdgpu_device pointer
 598  *
 599  * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
 600  * and DramLogSetDramAddr can notify it changed.
 601  *
 602  * Returns 0 on success, error on failure.
 603  */
 604 static int smu_alloc_memory_pool(struct smu_context *smu)
 605 {
 606         struct amdgpu_device *adev = smu->adev;
 607         struct smu_table_context *smu_table = &smu->smu_table;
 608         struct smu_table *memory_pool = &smu_table->memory_pool;
 609         uint64_t pool_size = smu->pool_size;
 610         int ret = 0;
 611
 612         if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
 613                 return ret;
 614
 615         memory_pool->size = pool_size;
 616         memory_pool->align = PAGE_SIZE;
 617         memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
 618
 619         switch (pool_size) {
 620         case SMU_MEMORY_POOL_SIZE_256_MB:
 621         case SMU_MEMORY_POOL_SIZE_512_MB:
 622         case SMU_MEMORY_POOL_SIZE_1_GB:
 623         case SMU_MEMORY_POOL_SIZE_2_GB:
 624                 ret = amdgpu_bo_create_kernel(adev,
 625                                               memory_pool->size,
 626                                               memory_pool->align,
 627                                               memory_pool->domain,
 628                                               &memory_pool->bo,
 629                                               &memory_pool->mc_address,
 630                                               &memory_pool->cpu_addr);
 631                 if (ret)
 632                         dev_err(adev->dev, "VRAM allocation for dramlog failed!\n");
 633                 break;
 634         default:
 635                 break;
 636         }
 637
 638         return ret;
 639 }
 640
 641 static int smu_free_memory_pool(struct smu_context *smu)
 642 {
 643         struct smu_table_context *smu_table = &smu->smu_table;
 644         struct smu_table *memory_pool = &smu_table->memory_pool;
 645
 646         if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
 647                 return 0;
 648
 649         amdgpu_bo_free_kernel(&memory_pool->bo,
 650                               &memory_pool->mc_address,
 651                               &memory_pool->cpu_addr);
 652
 653         memset(memory_pool, 0, sizeof(struct smu_table));
 654
 655         return 0;
 656 }
 657
 658 static int smu_smc_table_sw_init(struct smu_context *smu)
 659 {
 660         int ret;
 661
 662         /**
 663          * Create smu_table structure, and init smc tables such as
 664          * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
 665          */
 666         ret = smu_init_smc_tables(smu);
 667         if (ret) {
 668                 dev_err(smu->adev->dev, "Failed to init smc tables!\n");
 669                 return ret;
 670         }
 671
 672         /**
 673          * Create smu_power_context structure, and allocate smu_dpm_context and
 674          * context size to fill the smu_power_context data.
 675          */
 676         ret = smu_init_power(smu);
 677         if (ret) {
 678                 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
 679                 return ret;
 680         }
 681
 682         /*
 683          * allocate vram bos to store smc table contents.
 684          */
 685         ret = smu_init_fb_allocations(smu);
 686         if (ret)
 687                 return ret;
 688
 689         ret = smu_alloc_memory_pool(smu);
 690         if (ret)
 691                 return ret;
 692
 693         ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c);
 694         if (ret)
 695                 return ret;
 696
 697         return 0;
 698 }
 699
 700 static int smu_smc_table_sw_fini(struct smu_context *smu)
 701 {
 702         int ret;
 703
 704         smu_i2c_fini(smu, &smu->adev->pm.smu_i2c);
 705
 706         ret = smu_free_memory_pool(smu);
 707         if (ret)
 708                 return ret;
 709
 710         ret = smu_fini_fb_allocations(smu);
 711         if (ret)
 712                 return ret;
 713
 714         ret = smu_fini_power(smu);
 715         if (ret) {
 716                 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
 717                 return ret;
 718         }
 719
 720         ret = smu_fini_smc_tables(smu);
 721         if (ret) {
 722                 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
 723                 return ret;
 724         }
 725
 726         return 0;
 727 }
 728
 729 static void smu_throttling_logging_work_fn(struct work_struct *work)
 730 {
 731         struct smu_context *smu = container_of(work, struct smu_context,
 732                                                throttling_logging_work);
 733
 734         smu_log_thermal_throttling(smu);
 735 }
 736
 737 static int smu_sw_init(void *handle)
 738 {
 739         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 740         struct smu_context *smu = &adev->smu;
 741         int ret;
 742
 743         smu->pool_size = adev->pm.smu_prv_buffer_size;
 744         smu->smu_feature.feature_num = SMU_FEATURE_MAX;
 745         mutex_init(&smu->smu_feature.mutex);
 746         bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
 747         bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
 748         bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
 749
 750         mutex_init(&smu->smu_baco.mutex);
 751         smu->smu_baco.state = SMU_BACO_STATE_EXIT;
 752         smu->smu_baco.platform_support = false;
 753
 754         mutex_init(&smu->sensor_lock);
 755         mutex_init(&smu->metrics_lock);
 756         mutex_init(&smu->message_lock);
 757
 758         INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
 759         smu->watermarks_bitmap = 0;
 760         smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 761         smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 762
 763         atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
 764         atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
 765         mutex_init(&smu->smu_power.power_gate.vcn_gate_lock);
 766         mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock);
 767
 768         smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
 769         smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
 770         smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
 771         smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
 772         smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
 773         smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
 774         smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
 775         smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
 776
 777         smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
 778         smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
 779         smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
 780         smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
 781         smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
 782         smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
 783         smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
 784         smu->display_config = &adev->pm.pm_display_cfg;
 785
 786         smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 787         smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
 788         ret = smu_init_microcode(smu);
 789         if (ret) {
 790                 dev_err(adev->dev, "Failed to load smu firmware!\n");
 791                 return ret;
 792         }
 793
 794         ret = smu_smc_table_sw_init(smu);
 795         if (ret) {
 796                 dev_err(adev->dev, "Failed to sw init smc table!\n");
 797                 return ret;
 798         }
 799
 800         ret = smu_register_irq_handler(smu);
 801         if (ret) {
 802                 dev_err(adev->dev, "Failed to register smc irq handler!\n");
 803                 return ret;
 804         }
 805
 806         return 0;
 807 }
 808
 809 static int smu_sw_fini(void *handle)
 810 {
 811         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 812         struct smu_context *smu = &adev->smu;
 813         int ret;
 814
 815         ret = smu_smc_table_sw_fini(smu);
 816         if (ret) {
 817                 dev_err(adev->dev, "Failed to sw fini smc table!\n");
 818                 return ret;
 819         }
 820
 821         smu_fini_microcode(smu);
 822
 823         return 0;
 824 }
 825
 826 static int smu_get_thermal_temperature_range(struct smu_context *smu)
 827 {
 828         struct amdgpu_device *adev = smu->adev;
 829         struct smu_temperature_range *range =
 830                                 &smu->thermal_range;
 831         int ret = 0;
 832
 833         if (!smu->ppt_funcs->get_thermal_temperature_range)
 834                 return 0;
 835
 836         ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range);
 837         if (ret)
 838                 return ret;
 839
 840         adev->pm.dpm.thermal.min_temp = range->min;
 841         adev->pm.dpm.thermal.max_temp = range->max;
 842         adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max;
 843         adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min;
 844         adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max;
 845         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max;
 846         adev->pm.dpm.thermal.min_mem_temp = range->mem_min;
 847         adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max;
 848         adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max;
 849
 850         return ret;
 851 }
 852
 853 static int smu_smc_hw_setup(struct smu_context *smu)
 854 {
 855         struct amdgpu_device *adev = smu->adev;
 856         uint32_t pcie_gen = 0, pcie_width = 0;
 857         int ret;
 858
 859         if (adev->in_suspend && smu_is_dpm_running(smu)) {
 860                 dev_info(adev->dev, "dpm has been enabled\n");
 861                 return 0;
 862         }
 863
 864         ret = smu_init_display_count(smu, 0);
 865         if (ret) {
 866                 dev_info(adev->dev, "Failed to pre-set display count as 0!\n");
 867                 return ret;
 868         }
 869
 870         ret = smu_set_driver_table_location(smu);
 871         if (ret) {
 872                 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n");
 873                 return ret;
 874         }
 875
 876         /*
 877          * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
 878          */
 879         ret = smu_set_tool_table_location(smu);
 880         if (ret) {
 881                 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n");
 882                 return ret;
 883         }
 884
 885         /*
 886          * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
 887          * pool location.
 888          */
 889         ret = smu_notify_memory_pool_location(smu);
 890         if (ret) {
 891                 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n");
 892                 return ret;
 893         }
 894
 895         /* smu_dump_pptable(smu); */
 896         /*
 897          * Copy pptable bo in the vram to smc with SMU MSGs such as
 898          * SetDriverDramAddr and TransferTableDram2Smu.
 899          */
 900         ret = smu_write_pptable(smu);
 901         if (ret) {
 902                 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n");
 903                 return ret;
 904         }
 905
 906         /* issue Run*Btc msg */
 907         ret = smu_run_btc(smu);
 908         if (ret)
 909                 return ret;
 910
 911         ret = smu_feature_set_allowed_mask(smu);
 912         if (ret) {
 913                 dev_err(adev->dev, "Failed to set driver allowed features mask!\n");
 914                 return ret;
 915         }
 916
 917         ret = smu_system_features_control(smu, true);
 918         if (ret) {
 919                 dev_err(adev->dev, "Failed to enable requested dpm features!\n");
 920                 return ret;
 921         }
 922
 923         if (!smu_is_dpm_running(smu))
 924                 dev_info(adev->dev, "dpm has been disabled\n");
 925
 926         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
 927                 pcie_gen = 3;
 928         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
 929                 pcie_gen = 2;
 930         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
 931                 pcie_gen = 1;
 932         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
 933                 pcie_gen = 0;
 934
 935         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
 936          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
 937          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
 938          */
 939         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
 940                 pcie_width = 6;
 941         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
 942                 pcie_width = 5;
 943         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
 944                 pcie_width = 4;
 945         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
 946                 pcie_width = 3;
 947         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
 948                 pcie_width = 2;
 949         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
 950                 pcie_width = 1;
 951         ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
 952         if (ret) {
 953                 dev_err(adev->dev, "Attempt to override pcie params failed!\n");
 954                 return ret;
 955         }
 956
 957         ret = smu_get_thermal_temperature_range(smu);
 958         if (ret) {
 959                 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n");
 960                 return ret;
 961         }
 962
 963         ret = smu_enable_thermal_alert(smu);
 964         if (ret) {
 965                 dev_err(adev->dev, "Failed to enable thermal alert!\n");
 966                 return ret;
 967         }
 968
 969         ret = smu_disable_umc_cdr_12gbps_workaround(smu);
 970         if (ret) {
 971                 dev_err(adev->dev, "Workaround failed to disable UMC CDR feature on 12Gbps SKU!\n");
 972                 return ret;
 973         }
 974
 975         /*
 976          * For Navi1X, manually switch it to AC mode as PMFW
 977          * may boot it with DC mode.
 978          */
 979         ret = smu_set_power_source(smu,
 980                                    adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
 981                                    SMU_POWER_SOURCE_DC);
 982         if (ret) {
 983                 dev_err(adev->dev, "Failed to switch to %s mode!\n", adev->pm.ac_power ? "AC" : "DC");
 984                 return ret;
 985         }
 986
 987         ret = smu_notify_display_change(smu);
 988         if (ret)
 989                 return ret;
 990
 991         /*
 992          * Set min deep sleep dce fclk with bootup value from vbios via
 993          * SetMinDeepSleepDcefclk MSG.
 994          */
 995         ret = smu_set_min_dcef_deep_sleep(smu,
 996                                           smu->smu_table.boot_values.dcefclk / 100);
 997         if (ret)
 998                 return ret;
 999
1000         return ret;
1001 }
1002
1003 static int smu_start_smc_engine(struct smu_context *smu)
1004 {
1005         struct amdgpu_device *adev = smu->adev;
1006         int ret = 0;
1007
1008         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1009                 if (adev->asic_type < CHIP_NAVI10) {
1010                         if (smu->ppt_funcs->load_microcode) {
1011                                 ret = smu->ppt_funcs->load_microcode(smu);
1012                                 if (ret)
1013                                         return ret;
1014                         }
1015                 }
1016         }
1017
1018         if (smu->ppt_funcs->check_fw_status) {
1019                 ret = smu->ppt_funcs->check_fw_status(smu);
1020                 if (ret) {
1021                         dev_err(adev->dev, "SMC is not ready\n");
1022                         return ret;
1023                 }
1024         }
1025
1026         /*
1027          * Send msg GetDriverIfVersion to check if the return value is equal
1028          * with DRIVER_IF_VERSION of smc header.
1029          */
1030         ret = smu_check_fw_version(smu);
1031         if (ret)
1032                 return ret;
1033
1034         return ret;
1035 }
1036
1037 static int smu_hw_init(void *handle)
1038 {
1039         int ret;
1040         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1041         struct smu_context *smu = &adev->smu;
1042
1043         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
1044                 smu->pm_enabled = false;
1045                 return 0;
1046         }
1047
1048         ret = smu_start_smc_engine(smu);
1049         if (ret) {
1050                 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1051                 return ret;
1052         }
1053
1054         if (smu->is_apu) {
1055                 smu_powergate_sdma(&adev->smu, false);
1056                 smu_dpm_set_vcn_enable(smu, true);
1057                 smu_dpm_set_jpeg_enable(smu, true);
1058                 smu_set_gfx_cgpg(&adev->smu, true);
1059         }
1060
1061         if (!smu->pm_enabled)
1062                 return 0;
1063
1064         /* get boot_values from vbios to set revision, gfxclk, and etc. */
1065         ret = smu_get_vbios_bootup_values(smu);
1066         if (ret) {
1067                 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n");
1068                 return ret;
1069         }
1070
1071         ret = smu_setup_pptable(smu);
1072         if (ret) {
1073                 dev_err(adev->dev, "Failed to setup pptable!\n");
1074                 return ret;
1075         }
1076
1077         ret = smu_get_driver_allowed_feature_mask(smu);
1078         if (ret)
1079                 return ret;
1080
1081         ret = smu_smc_hw_setup(smu);
1082         if (ret) {
1083                 dev_err(adev->dev, "Failed to setup smc hw!\n");
1084                 return ret;
1085         }
1086
1087         /*
1088          * Move maximum sustainable clock retrieving here considering
1089          * 1. It is not needed on resume(from S3).
1090          * 2. DAL settings come between .hw_init and .late_init of SMU.
1091          *    And DAL needs to know the maximum sustainable clocks. Thus
1092          *    it cannot be put in .late_init().
1093          */
1094         ret = smu_init_max_sustainable_clocks(smu);
1095         if (ret) {
1096                 dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
1097                 return ret;
1098         }
1099
1100         adev->pm.dpm_enabled = true;
1101
1102         dev_info(adev->dev, "SMU is initialized successfully!\n");
1103
1104         return 0;
1105 }
1106
1107 static int smu_disable_dpms(struct smu_context *smu)
1108 {
1109         struct amdgpu_device *adev = smu->adev;
1110         int ret = 0;
1111         bool use_baco = !smu->is_apu &&
1112                 ((adev->in_gpu_reset &&
1113                   (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1114                  ((adev->in_runpm || adev->in_hibernate) && amdgpu_asic_supports_baco(adev)));
1115
1116         /*
1117          * For custom pptable uploading, skip the DPM features
1118          * disable process on Navi1x ASICs.
1119          *   - As the gfx related features are under control of
1120          *     RLC on those ASICs. RLC reinitialization will be
1121          *     needed to reenable them. That will cost much more
1122          *     efforts.
1123          *
1124          *   - SMU firmware can handle the DPM reenablement
1125          *     properly.
1126          */
1127         if (smu->uploading_custom_pp_table &&
1128             (adev->asic_type >= CHIP_NAVI10) &&
1129             (adev->asic_type <= CHIP_NAVI12))
1130                 return 0;
1131
1132         /*
1133          * For Sienna_Cichlid, PMFW will handle the features disablement properly
1134          * on BACO in. Driver involvement is unnecessary.
1135          */
1136         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1137              use_baco)
1138                 return 0;
1139
1140         /*
1141          * For gpu reset, runpm and hibernation through BACO,
1142          * BACO feature has to be kept enabled.
1143          */
1144         if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
1145                 ret = smu_disable_all_features_with_exception(smu,
1146                                                               SMU_FEATURE_BACO_BIT);
1147                 if (ret)
1148                         dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
1149         } else {
1150                 ret = smu_system_features_control(smu, false);
1151                 if (ret)
1152                         dev_err(adev->dev, "Failed to disable smu features.\n");
1153         }
1154
1155         if (adev->asic_type >= CHIP_NAVI10 &&
1156             adev->gfx.rlc.funcs->stop)
1157                 adev->gfx.rlc.funcs->stop(adev);
1158
1159         return ret;
1160 }
1161
1162 static int smu_smc_hw_cleanup(struct smu_context *smu)
1163 {
1164         struct amdgpu_device *adev = smu->adev;
1165         int ret = 0;
1166
1167         cancel_work_sync(&smu->throttling_logging_work);
1168
1169         ret = smu_disable_thermal_alert(smu);
1170         if (ret) {
1171                 dev_err(adev->dev, "Fail to disable thermal alert!\n");
1172                 return ret;
1173         }
1174
1175         ret = smu_disable_dpms(smu);
1176         if (ret) {
1177                 dev_err(adev->dev, "Fail to disable dpm features!\n");
1178                 return ret;
1179         }
1180
1181         return 0;
1182 }
1183
1184 static int smu_hw_fini(void *handle)
1185 {
1186         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1187         struct smu_context *smu = &adev->smu;
1188         int ret = 0;
1189
1190         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1191                 return 0;
1192
1193         if (smu->is_apu) {
1194                 smu_powergate_sdma(&adev->smu, true);
1195                 smu_dpm_set_vcn_enable(smu, false);
1196                 smu_dpm_set_jpeg_enable(smu, false);
1197         }
1198
1199         if (!smu->pm_enabled)
1200                 return 0;
1201
1202         adev->pm.dpm_enabled = false;
1203
1204         ret = smu_smc_hw_cleanup(smu);
1205         if (ret)
1206                 return ret;
1207
1208         return 0;
1209 }
1210
1211 int smu_reset(struct smu_context *smu)
1212 {
1213         struct amdgpu_device *adev = smu->adev;
1214         int ret = 0;
1215
1216         ret = smu_hw_fini(adev);
1217         if (ret)
1218                 return ret;
1219
1220         ret = smu_hw_init(adev);
1221         if (ret)
1222                 return ret;
1223
1224         ret = smu_late_init(adev);
1225
1226         return ret;
1227 }
1228
1229 static int smu_suspend(void *handle)
1230 {
1231         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1232         struct smu_context *smu = &adev->smu;
1233         int ret;
1234
1235         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1236                 return 0;
1237
1238         if (!smu->pm_enabled)
1239                 return 0;
1240
1241         adev->pm.dpm_enabled = false;
1242
1243         ret = smu_smc_hw_cleanup(smu);
1244         if (ret)
1245                 return ret;
1246
1247         smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1248
1249         if (smu->is_apu)
1250                 smu_set_gfx_cgpg(&adev->smu, false);
1251
1252         return 0;
1253 }
1254
1255 static int smu_resume(void *handle)
1256 {
1257         int ret;
1258         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1259         struct smu_context *smu = &adev->smu;
1260
1261         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1262                 return 0;
1263
1264         if (!smu->pm_enabled)
1265                 return 0;
1266
1267         dev_info(adev->dev, "SMU is resuming...\n");
1268
1269         ret = smu_start_smc_engine(smu);
1270         if (ret) {
1271                 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1272                 return ret;
1273         }
1274
1275         ret = smu_smc_hw_setup(smu);
1276         if (ret) {
1277                 dev_err(adev->dev, "Failed to setup smc hw!\n");
1278                 return ret;
1279         }
1280
1281         if (smu->is_apu)
1282                 smu_set_gfx_cgpg(&adev->smu, true);
1283
1284         smu->disable_uclk_switch = 0;
1285
1286         adev->pm.dpm_enabled = true;
1287
1288         dev_info(adev->dev, "SMU is resumed successfully!\n");
1289
1290         return 0;
1291 }
1292
1293 int smu_display_configuration_change(struct smu_context *smu,
1294                                      const struct amd_pp_display_configuration *display_config)
1295 {
1296         int index = 0;
1297         int num_of_active_display = 0;
1298
1299         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1300                 return -EOPNOTSUPP;
1301
1302         if (!display_config)
1303                 return -EINVAL;
1304
1305         mutex_lock(&smu->mutex);
1306
1307         smu_set_min_dcef_deep_sleep(smu,
1308                                     display_config->min_dcef_deep_sleep_set_clk / 100);
1309
1310         for (index = 0; index < display_config->num_path_including_non_display; index++) {
1311                 if (display_config->displays[index].controller_id != 0)
1312                         num_of_active_display++;
1313         }
1314
1315         smu_set_active_display_count(smu, num_of_active_display);
1316
1317         smu_store_cc6_data(smu, display_config->cpu_pstate_separation_time,
1318                            display_config->cpu_cc6_disable,
1319                            display_config->cpu_pstate_disable,
1320                            display_config->nb_pstate_switch_disable);
1321
1322         mutex_unlock(&smu->mutex);
1323
1324         return 0;
1325 }
1326
1327 static int smu_get_clock_info(struct smu_context *smu,
1328                               struct smu_clock_info *clk_info,
1329                               enum smu_perf_level_designation designation)
1330 {
1331         int ret;
1332         struct smu_performance_level level = {0};
1333
1334         if (!clk_info)
1335                 return -EINVAL;
1336
1337         ret = smu_get_perf_level(smu, PERF_LEVEL_ACTIVITY, &level);
1338         if (ret)
1339                 return -EINVAL;
1340
1341         clk_info->min_mem_clk = level.memory_clock;
1342         clk_info->min_eng_clk = level.core_clock;
1343         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1344
1345         ret = smu_get_perf_level(smu, designation, &level);
1346         if (ret)
1347                 return -EINVAL;
1348
1349         clk_info->min_mem_clk = level.memory_clock;
1350         clk_info->min_eng_clk = level.core_clock;
1351         clk_info->min_bus_bandwidth = level.non_local_mem_freq * level.non_local_mem_width;
1352
1353         return 0;
1354 }
1355
1356 int smu_get_current_clocks(struct smu_context *smu,
1357                            struct amd_pp_clock_info *clocks)
1358 {
1359         struct amd_pp_simple_clock_info simple_clocks = {0};
1360         struct smu_clock_info hw_clocks;
1361         int ret = 0;
1362
1363         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1364                 return -EOPNOTSUPP;
1365
1366         mutex_lock(&smu->mutex);
1367
1368         smu_get_dal_power_level(smu, &simple_clocks);
1369
1370         if (smu->support_power_containment)
1371                 ret = smu_get_clock_info(smu, &hw_clocks,
1372                                          PERF_LEVEL_POWER_CONTAINMENT);
1373         else
1374                 ret = smu_get_clock_info(smu, &hw_clocks, PERF_LEVEL_ACTIVITY);
1375
1376         if (ret) {
1377                 dev_err(smu->adev->dev, "Error in smu_get_clock_info\n");
1378                 goto failed;
1379         }
1380
1381         clocks->min_engine_clock = hw_clocks.min_eng_clk;
1382         clocks->max_engine_clock = hw_clocks.max_eng_clk;
1383         clocks->min_memory_clock = hw_clocks.min_mem_clk;
1384         clocks->max_memory_clock = hw_clocks.max_mem_clk;
1385         clocks->min_bus_bandwidth = hw_clocks.min_bus_bandwidth;
1386         clocks->max_bus_bandwidth = hw_clocks.max_bus_bandwidth;
1387         clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1388         clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1389
1390         if (simple_clocks.level == 0)
1391                 clocks->max_clocks_state = PP_DAL_POWERLEVEL_7;
1392         else
1393                 clocks->max_clocks_state = simple_clocks.level;
1394
1395         if (!smu_get_current_shallow_sleep_clocks(smu, &hw_clocks)) {
1396                 clocks->max_engine_clock_in_sr = hw_clocks.max_eng_clk;
1397                 clocks->min_engine_clock_in_sr = hw_clocks.min_eng_clk;
1398         }
1399
1400 failed:
1401         mutex_unlock(&smu->mutex);
1402         return ret;
1403 }
1404
1405 static int smu_set_clockgating_state(void *handle,
1406                                      enum amd_clockgating_state state)
1407 {
1408         return 0;
1409 }
1410
1411 static int smu_set_powergating_state(void *handle,
1412                                      enum amd_powergating_state state)
1413 {
1414         return 0;
1415 }
1416
1417 static int smu_enable_umd_pstate(void *handle,
1418                       enum amd_dpm_forced_level *level)
1419 {
1420         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1421                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1422                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1423                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1424
1425         struct smu_context *smu = (struct smu_context*)(handle);
1426         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1427
1428         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1429                 return -EINVAL;
1430
1431         if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1432                 /* enter umd pstate, save current level, disable gfx cg*/
1433                 if (*level & profile_mode_mask) {
1434                         smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1435                         smu_dpm_ctx->enable_umd_pstate = true;
1436                         amdgpu_device_ip_set_powergating_state(smu->adev,
1437                                                                AMD_IP_BLOCK_TYPE_GFX,
1438                                                                AMD_PG_STATE_UNGATE);
1439                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1440                                                                AMD_IP_BLOCK_TYPE_GFX,
1441                                                                AMD_CG_STATE_UNGATE);
1442                 }
1443         } else {
1444                 /* exit umd pstate, restore level, enable gfx cg*/
1445                 if (!(*level & profile_mode_mask)) {
1446                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1447                                 *level = smu_dpm_ctx->saved_dpm_level;
1448                         smu_dpm_ctx->enable_umd_pstate = false;
1449                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1450                                                                AMD_IP_BLOCK_TYPE_GFX,
1451                                                                AMD_CG_STATE_GATE);
1452                         amdgpu_device_ip_set_powergating_state(smu->adev,
1453                                                                AMD_IP_BLOCK_TYPE_GFX,
1454                                                                AMD_PG_STATE_GATE);
1455                 }
1456         }
1457
1458         return 0;
1459 }
1460
1461 static int smu_adjust_power_state_dynamic(struct smu_context *smu,
1462                                    enum amd_dpm_forced_level level,
1463                                    bool skip_display_settings)
1464 {
1465         int ret = 0;
1466         int index = 0;
1467         long workload;
1468         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1469
1470         if (!skip_display_settings) {
1471                 ret = smu_display_config_changed(smu);
1472                 if (ret) {
1473                         dev_err(smu->adev->dev, "Failed to change display config!");
1474                         return ret;
1475                 }
1476         }
1477
1478         ret = smu_apply_clocks_adjust_rules(smu);
1479         if (ret) {
1480                 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!");
1481                 return ret;
1482         }
1483
1484         if (!skip_display_settings) {
1485                 ret = smu_notify_smc_display_config(smu);
1486                 if (ret) {
1487                         dev_err(smu->adev->dev, "Failed to notify smc display config!");
1488                         return ret;
1489                 }
1490         }
1491
1492         if (smu_dpm_ctx->dpm_level != level) {
1493                 ret = smu_asic_set_performance_level(smu, level);
1494                 if (ret) {
1495                         dev_err(smu->adev->dev, "Failed to set performance level!");
1496                         return ret;
1497                 }
1498
1499                 /* update the saved copy */
1500                 smu_dpm_ctx->dpm_level = level;
1501         }
1502
1503         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1504                 index = fls(smu->workload_mask);
1505                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1506                 workload = smu->workload_setting[index];
1507
1508                 if (smu->power_profile_mode != workload)
1509                         smu_set_power_profile_mode(smu, &workload, 0, false);
1510         }
1511
1512         return ret;
1513 }
1514
1515 int smu_handle_task(struct smu_context *smu,
1516                     enum amd_dpm_forced_level level,
1517                     enum amd_pp_task task_id,
1518                     bool lock_needed)
1519 {
1520         int ret = 0;
1521
1522         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1523                 return -EOPNOTSUPP;
1524
1525         if (lock_needed)
1526                 mutex_lock(&smu->mutex);
1527
1528         switch (task_id) {
1529         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1530                 ret = smu_pre_display_config_changed(smu);
1531                 if (ret)
1532                         goto out;
1533                 ret = smu_set_cpu_power_state(smu);
1534                 if (ret)
1535                         goto out;
1536                 ret = smu_adjust_power_state_dynamic(smu, level, false);
1537                 break;
1538         case AMD_PP_TASK_COMPLETE_INIT:
1539         case AMD_PP_TASK_READJUST_POWER_STATE:
1540                 ret = smu_adjust_power_state_dynamic(smu, level, true);
1541                 break;
1542         default:
1543                 break;
1544         }
1545
1546 out:
1547         if (lock_needed)
1548                 mutex_unlock(&smu->mutex);
1549
1550         return ret;
1551 }
1552
1553 int smu_switch_power_profile(struct smu_context *smu,
1554                              enum PP_SMC_POWER_PROFILE type,
1555                              bool en)
1556 {
1557         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1558         long workload;
1559         uint32_t index;
1560
1561         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1562                 return -EOPNOTSUPP;
1563
1564         if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1565                 return -EINVAL;
1566
1567         mutex_lock(&smu->mutex);
1568
1569         if (!en) {
1570                 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1571                 index = fls(smu->workload_mask);
1572                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1573                 workload = smu->workload_setting[index];
1574         } else {
1575                 smu->workload_mask |= (1 << smu->workload_prority[type]);
1576                 index = fls(smu->workload_mask);
1577                 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1578                 workload = smu->workload_setting[index];
1579         }
1580
1581         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1582                 smu_set_power_profile_mode(smu, &workload, 0, false);
1583
1584         mutex_unlock(&smu->mutex);
1585
1586         return 0;
1587 }
1588
1589 enum amd_dpm_forced_level smu_get_performance_level(struct smu_context *smu)
1590 {
1591         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1592         enum amd_dpm_forced_level level;
1593
1594         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1595                 return -EOPNOTSUPP;
1596
1597         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1598                 return -EINVAL;
1599
1600         mutex_lock(&(smu->mutex));
1601         level = smu_dpm_ctx->dpm_level;
1602         mutex_unlock(&(smu->mutex));
1603
1604         return level;
1605 }
1606
1607 int smu_force_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
1608 {
1609         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1610         int ret = 0;
1611
1612         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1613                 return -EOPNOTSUPP;
1614
1615         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1616                 return -EINVAL;
1617
1618         mutex_lock(&smu->mutex);
1619
1620         ret = smu_enable_umd_pstate(smu, &level);
1621         if (ret) {
1622                 mutex_unlock(&smu->mutex);
1623                 return ret;
1624         }
1625
1626         ret = smu_handle_task(smu, level,
1627                               AMD_PP_TASK_READJUST_POWER_STATE,
1628                               false);
1629
1630         mutex_unlock(&smu->mutex);
1631
1632         return ret;
1633 }
1634
1635 int smu_set_display_count(struct smu_context *smu, uint32_t count)
1636 {
1637         int ret = 0;
1638
1639         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1640                 return -EOPNOTSUPP;
1641
1642         mutex_lock(&smu->mutex);
1643         ret = smu_init_display_count(smu, count);
1644         mutex_unlock(&smu->mutex);
1645
1646         return ret;
1647 }
1648
1649 int smu_force_clk_levels(struct smu_context *smu,
1650                          enum smu_clk_type clk_type,
1651                          uint32_t mask)
1652 {
1653         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1654         int ret = 0;
1655
1656         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1657                 return -EOPNOTSUPP;
1658
1659         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1660                 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n");
1661                 return -EINVAL;
1662         }
1663
1664         mutex_lock(&smu->mutex);
1665
1666         if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels)
1667                 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1668
1669         mutex_unlock(&smu->mutex);
1670
1671         return ret;
1672 }
1673
1674 /*
1675  * On system suspending or resetting, the dpm_enabled
1676  * flag will be cleared. So that those SMU services which
1677  * are not supported will be gated.
1678  * However, the mp1 state setting should still be granted
1679  * even if the dpm_enabled cleared.
1680  */
1681 int smu_set_mp1_state(struct smu_context *smu,
1682                       enum pp_mp1_state mp1_state)
1683 {
1684         uint16_t msg;
1685         int ret;
1686
1687         if (!smu->pm_enabled)
1688                 return -EOPNOTSUPP;
1689
1690         mutex_lock(&smu->mutex);
1691
1692         switch (mp1_state) {
1693         case PP_MP1_STATE_SHUTDOWN:
1694                 msg = SMU_MSG_PrepareMp1ForShutdown;
1695                 break;
1696         case PP_MP1_STATE_UNLOAD:
1697                 msg = SMU_MSG_PrepareMp1ForUnload;
1698                 break;
1699         case PP_MP1_STATE_RESET:
1700                 msg = SMU_MSG_PrepareMp1ForReset;
1701                 break;
1702         case PP_MP1_STATE_NONE:
1703         default:
1704                 mutex_unlock(&smu->mutex);
1705                 return 0;
1706         }
1707
1708         ret = smu_send_smc_msg(smu, msg, NULL);
1709         /* some asics may not support those messages */
1710         if (ret == -EINVAL)
1711                 ret = 0;
1712         if (ret)
1713                 dev_err(smu->adev->dev, "[PrepareMp1] Failed!\n");
1714
1715         mutex_unlock(&smu->mutex);
1716
1717         return ret;
1718 }
1719
1720 int smu_set_df_cstate(struct smu_context *smu,
1721                       enum pp_df_cstate state)
1722 {
1723         int ret = 0;
1724
1725         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1726                 return -EOPNOTSUPP;
1727
1728         if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
1729                 return 0;
1730
1731         mutex_lock(&smu->mutex);
1732
1733         ret = smu->ppt_funcs->set_df_cstate(smu, state);
1734         if (ret)
1735                 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
1736
1737         mutex_unlock(&smu->mutex);
1738
1739         return ret;
1740 }
1741
1742 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
1743 {
1744         int ret = 0;
1745
1746         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1747                 return -EOPNOTSUPP;
1748
1749         if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down)
1750                 return 0;
1751
1752         mutex_lock(&smu->mutex);
1753
1754         ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en);
1755         if (ret)
1756                 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n");
1757
1758         mutex_unlock(&smu->mutex);
1759
1760         return ret;
1761 }
1762
1763 int smu_write_watermarks_table(struct smu_context *smu)
1764 {
1765         int ret = 0;
1766
1767         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1768                 return -EOPNOTSUPP;
1769
1770         mutex_lock(&smu->mutex);
1771
1772         ret = smu_set_watermarks_table(smu, NULL);
1773
1774         mutex_unlock(&smu->mutex);
1775
1776         return ret;
1777 }
1778
1779 int smu_set_watermarks_for_clock_ranges(struct smu_context *smu,
1780                 struct dm_pp_wm_sets_with_clock_ranges_soc15 *clock_ranges)
1781 {
1782         int ret = 0;
1783
1784         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1785                 return -EOPNOTSUPP;
1786
1787         mutex_lock(&smu->mutex);
1788
1789         if (!smu->disable_watermark &&
1790                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1791                         smu_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1792                 ret = smu_set_watermarks_table(smu, clock_ranges);
1793
1794                 if (!(smu->watermarks_bitmap & WATERMARKS_EXIST)) {
1795                         smu->watermarks_bitmap |= WATERMARKS_EXIST;
1796                         smu->watermarks_bitmap &= ~WATERMARKS_LOADED;
1797                 }
1798         }
1799
1800         mutex_unlock(&smu->mutex);
1801
1802         return ret;
1803 }
1804
1805 int smu_set_ac_dc(struct smu_context *smu)
1806 {
1807         int ret = 0;
1808
1809         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1810                 return -EOPNOTSUPP;
1811
1812         /* controlled by firmware */
1813         if (smu->dc_controlled_by_gpio)
1814                 return 0;
1815
1816         mutex_lock(&smu->mutex);
1817         ret = smu_set_power_source(smu,
1818                                    smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
1819                                    SMU_POWER_SOURCE_DC);
1820         if (ret)
1821                 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",
1822                        smu->adev->pm.ac_power ? "AC" : "DC");
1823         mutex_unlock(&smu->mutex);
1824
1825         return ret;
1826 }
1827
1828 const struct amd_ip_funcs smu_ip_funcs = {
1829         .name = "smu",
1830         .early_init = smu_early_init,
1831         .late_init = smu_late_init,
1832         .sw_init = smu_sw_init,
1833         .sw_fini = smu_sw_fini,
1834         .hw_init = smu_hw_init,
1835         .hw_fini = smu_hw_fini,
1836         .suspend = smu_suspend,
1837         .resume = smu_resume,
1838         .is_idle = NULL,
1839         .check_soft_reset = NULL,
1840         .wait_for_idle = NULL,
1841         .soft_reset = NULL,
1842         .set_clockgating_state = smu_set_clockgating_state,
1843         .set_powergating_state = smu_set_powergating_state,
1844         .enable_umd_pstate = smu_enable_umd_pstate,
1845 };
1846
1847 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
1848 {
1849         .type = AMD_IP_BLOCK_TYPE_SMC,
1850         .major = 11,
1851         .minor = 0,
1852         .rev = 0,
1853         .funcs = &smu_ip_funcs,
1854 };
1855
1856 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
1857 {
1858         .type = AMD_IP_BLOCK_TYPE_SMC,
1859         .major = 12,
1860         .minor = 0,
1861         .rev = 0,
1862         .funcs = &smu_ip_funcs,
1863 };
1864
1865 int smu_load_microcode(struct smu_context *smu)
1866 {
1867         int ret = 0;
1868
1869         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1870                 return -EOPNOTSUPP;
1871
1872         mutex_lock(&smu->mutex);
1873
1874         if (smu->ppt_funcs->load_microcode)
1875                 ret = smu->ppt_funcs->load_microcode(smu);
1876
1877         mutex_unlock(&smu->mutex);
1878
1879         return ret;
1880 }
1881
1882 int smu_check_fw_status(struct smu_context *smu)
1883 {
1884         int ret = 0;
1885
1886         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1887                 return -EOPNOTSUPP;
1888
1889         mutex_lock(&smu->mutex);
1890
1891         if (smu->ppt_funcs->check_fw_status)
1892                 ret = smu->ppt_funcs->check_fw_status(smu);
1893
1894         mutex_unlock(&smu->mutex);
1895
1896         return ret;
1897 }
1898
1899 int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
1900 {
1901         int ret = 0;
1902
1903         mutex_lock(&smu->mutex);
1904
1905         if (smu->ppt_funcs->set_gfx_cgpg)
1906                 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
1907
1908         mutex_unlock(&smu->mutex);
1909
1910         return ret;
1911 }
1912
1913 int smu_set_fan_speed_rpm(struct smu_context *smu, uint32_t speed)
1914 {
1915         int ret = 0;
1916
1917         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1918                 return -EOPNOTSUPP;
1919
1920         mutex_lock(&smu->mutex);
1921
1922         if (smu->ppt_funcs->set_fan_speed_rpm)
1923                 ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
1924
1925         mutex_unlock(&smu->mutex);
1926
1927         return ret;
1928 }
1929
1930 int smu_get_power_limit(struct smu_context *smu,
1931                         uint32_t *limit,
1932                         bool max_setting)
1933 {
1934         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1935                 return -EOPNOTSUPP;
1936
1937         mutex_lock(&smu->mutex);
1938
1939         *limit = (max_setting ? smu->max_power_limit : smu->current_power_limit);
1940
1941         mutex_unlock(&smu->mutex);
1942
1943         return 0;
1944 }
1945
1946 int smu_set_power_limit(struct smu_context *smu, uint32_t limit)
1947 {
1948         int ret = 0;
1949
1950         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1951                 return -EOPNOTSUPP;
1952
1953         mutex_lock(&smu->mutex);
1954
1955         if (limit > smu->max_power_limit) {
1956                 dev_err(smu->adev->dev,
1957                         "New power limit (%d) is over the max allowed %d\n",
1958                         limit, smu->max_power_limit);
1959                 goto out;
1960         }
1961
1962         if (!limit)
1963                 limit = smu->current_power_limit;
1964
1965         if (smu->ppt_funcs->set_power_limit)
1966                 ret = smu->ppt_funcs->set_power_limit(smu, limit);
1967
1968 out:
1969         mutex_unlock(&smu->mutex);
1970
1971         return ret;
1972 }
1973
1974 int smu_print_clk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
1975 {
1976         int ret = 0;
1977
1978         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1979                 return -EOPNOTSUPP;
1980
1981         mutex_lock(&smu->mutex);
1982
1983         if (smu->ppt_funcs->print_clk_levels)
1984                 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
1985
1986         mutex_unlock(&smu->mutex);
1987
1988         return ret;
1989 }
1990
1991 int smu_get_od_percentage(struct smu_context *smu, enum smu_clk_type type)
1992 {
1993         int ret = 0;
1994
1995         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1996                 return -EOPNOTSUPP;
1997
1998         mutex_lock(&smu->mutex);
1999
2000         if (smu->ppt_funcs->get_od_percentage)
2001                 ret = smu->ppt_funcs->get_od_percentage(smu, type);
2002
2003         mutex_unlock(&smu->mutex);
2004
2005         return ret;
2006 }
2007
2008 int smu_set_od_percentage(struct smu_context *smu, enum smu_clk_type type, uint32_t value)
2009 {
2010         int ret = 0;
2011
2012         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2013                 return -EOPNOTSUPP;
2014
2015         mutex_lock(&smu->mutex);
2016
2017         if (smu->ppt_funcs->set_od_percentage)
2018                 ret = smu->ppt_funcs->set_od_percentage(smu, type, value);
2019
2020         mutex_unlock(&smu->mutex);
2021
2022         return ret;
2023 }
2024
2025 int smu_od_edit_dpm_table(struct smu_context *smu,
2026                           enum PP_OD_DPM_TABLE_COMMAND type,
2027                           long *input, uint32_t size)
2028 {
2029         int ret = 0;
2030
2031         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2032                 return -EOPNOTSUPP;
2033
2034         mutex_lock(&smu->mutex);
2035
2036         if (smu->ppt_funcs->od_edit_dpm_table) {
2037                 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2038                 if (!ret && (type == PP_OD_COMMIT_DPM_TABLE))
2039                         ret = smu_handle_task(smu,
2040                                               smu->smu_dpm.dpm_level,
2041                                               AMD_PP_TASK_READJUST_POWER_STATE,
2042                                               false);
2043         }
2044
2045         mutex_unlock(&smu->mutex);
2046
2047         return ret;
2048 }
2049
2050 int smu_read_sensor(struct smu_context *smu,
2051                     enum amd_pp_sensors sensor,
2052                     void *data, uint32_t *size)
2053 {
2054         struct smu_umd_pstate_table *pstate_table =
2055                                 &smu->pstate_table;
2056         int ret = 0;
2057
2058         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2059                 return -EOPNOTSUPP;
2060
2061         if (!data || !size)
2062                 return -EINVAL;
2063
2064         mutex_lock(&smu->mutex);
2065
2066         if (smu->ppt_funcs->read_sensor)
2067                 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
2068                         goto unlock;
2069
2070         switch (sensor) {
2071         case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
2072                 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;
2073                 *size = 4;
2074                 break;
2075         case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
2076                 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
2077                 *size = 4;
2078                 break;
2079         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2080                 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
2081                 *size = 8;
2082                 break;
2083         case AMDGPU_PP_SENSOR_UVD_POWER:
2084                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
2085                 *size = 4;
2086                 break;
2087         case AMDGPU_PP_SENSOR_VCE_POWER:
2088                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
2089                 *size = 4;
2090                 break;
2091         case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
2092                 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1;
2093                 *size = 4;
2094                 break;
2095         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
2096                 *(uint32_t *)data = 0;
2097                 *size = 4;
2098                 break;
2099         default:
2100                 *size = 0;
2101                 ret = -EOPNOTSUPP;
2102                 break;
2103         }
2104
2105 unlock:
2106         mutex_unlock(&smu->mutex);
2107
2108         return ret;
2109 }
2110
2111 int smu_get_power_profile_mode(struct smu_context *smu, char *buf)
2112 {
2113         int ret = 0;
2114
2115         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2116                 return -EOPNOTSUPP;
2117
2118         mutex_lock(&smu->mutex);
2119
2120         if (smu->ppt_funcs->get_power_profile_mode)
2121                 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
2122
2123         mutex_unlock(&smu->mutex);
2124
2125         return ret;
2126 }
2127
2128 int smu_set_power_profile_mode(struct smu_context *smu,
2129                                long *param,
2130                                uint32_t param_size,
2131                                bool lock_needed)
2132 {
2133         int ret = 0;
2134
2135         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2136                 return -EOPNOTSUPP;
2137
2138         if (lock_needed)
2139                 mutex_lock(&smu->mutex);
2140
2141         if (smu->ppt_funcs->set_power_profile_mode)
2142                 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
2143
2144         if (lock_needed)
2145                 mutex_unlock(&smu->mutex);
2146
2147         return ret;
2148 }
2149
2150
2151 int smu_get_fan_control_mode(struct smu_context *smu)
2152 {
2153         int ret = 0;
2154
2155         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2156                 return -EOPNOTSUPP;
2157
2158         mutex_lock(&smu->mutex);
2159
2160         if (smu->ppt_funcs->get_fan_control_mode)
2161                 ret = smu->ppt_funcs->get_fan_control_mode(smu);
2162
2163         mutex_unlock(&smu->mutex);
2164
2165         return ret;
2166 }
2167
2168 int smu_set_fan_control_mode(struct smu_context *smu, int value)
2169 {
2170         int ret = 0;
2171
2172         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2173                 return -EOPNOTSUPP;
2174
2175         mutex_lock(&smu->mutex);
2176
2177         if (smu->ppt_funcs->set_fan_control_mode)
2178                 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2179
2180         mutex_unlock(&smu->mutex);
2181
2182         return ret;
2183 }
2184
2185 int smu_get_fan_speed_percent(struct smu_context *smu, uint32_t *speed)
2186 {
2187         int ret = 0;
2188
2189         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2190                 return -EOPNOTSUPP;
2191
2192         mutex_lock(&smu->mutex);
2193
2194         if (smu->ppt_funcs->get_fan_speed_percent)
2195                 ret = smu->ppt_funcs->get_fan_speed_percent(smu, speed);
2196
2197         mutex_unlock(&smu->mutex);
2198
2199         return ret;
2200 }
2201
2202 int smu_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
2203 {
2204         int ret = 0;
2205
2206         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2207                 return -EOPNOTSUPP;
2208
2209         mutex_lock(&smu->mutex);
2210
2211         if (smu->ppt_funcs->set_fan_speed_percent)
2212                 ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
2213
2214         mutex_unlock(&smu->mutex);
2215
2216         return ret;
2217 }
2218
2219 int smu_get_fan_speed_rpm(struct smu_context *smu, uint32_t *speed)
2220 {
2221         int ret = 0;
2222
2223         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2224                 return -EOPNOTSUPP;
2225
2226         mutex_lock(&smu->mutex);
2227
2228         if (smu->ppt_funcs->get_fan_speed_rpm)
2229                 ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2230
2231         mutex_unlock(&smu->mutex);
2232
2233         return ret;
2234 }
2235
2236 int smu_set_deep_sleep_dcefclk(struct smu_context *smu, int clk)
2237 {
2238         int ret = 0;
2239
2240         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2241                 return -EOPNOTSUPP;
2242
2243         mutex_lock(&smu->mutex);
2244
2245         ret = smu_set_min_dcef_deep_sleep(smu, clk);
2246
2247         mutex_unlock(&smu->mutex);
2248
2249         return ret;
2250 }
2251
2252 int smu_set_active_display_count(struct smu_context *smu, uint32_t count)
2253 {
2254         int ret = 0;
2255
2256         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2257                 return -EOPNOTSUPP;
2258
2259         if (smu->ppt_funcs->set_active_display_count)
2260                 ret = smu->ppt_funcs->set_active_display_count(smu, count);
2261
2262         return ret;
2263 }
2264
2265 int smu_get_clock_by_type(struct smu_context *smu,
2266                           enum amd_pp_clock_type type,
2267                           struct amd_pp_clocks *clocks)
2268 {
2269         int ret = 0;
2270
2271         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2272                 return -EOPNOTSUPP;
2273
2274         mutex_lock(&smu->mutex);
2275
2276         if (smu->ppt_funcs->get_clock_by_type)
2277                 ret = smu->ppt_funcs->get_clock_by_type(smu, type, clocks);
2278
2279         mutex_unlock(&smu->mutex);
2280
2281         return ret;
2282 }
2283
2284 int smu_get_max_high_clocks(struct smu_context *smu,
2285                             struct amd_pp_simple_clock_info *clocks)
2286 {
2287         int ret = 0;
2288
2289         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2290                 return -EOPNOTSUPP;
2291
2292         mutex_lock(&smu->mutex);
2293
2294         if (smu->ppt_funcs->get_max_high_clocks)
2295                 ret = smu->ppt_funcs->get_max_high_clocks(smu, clocks);
2296
2297         mutex_unlock(&smu->mutex);
2298
2299         return ret;
2300 }
2301
2302 int smu_get_clock_by_type_with_latency(struct smu_context *smu,
2303                                        enum smu_clk_type clk_type,
2304                                        struct pp_clock_levels_with_latency *clocks)
2305 {
2306         int ret = 0;
2307
2308         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2309                 return -EOPNOTSUPP;
2310
2311         mutex_lock(&smu->mutex);
2312
2313         if (smu->ppt_funcs->get_clock_by_type_with_latency)
2314                 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2315
2316         mutex_unlock(&smu->mutex);
2317
2318         return ret;
2319 }
2320
2321 int smu_get_clock_by_type_with_voltage(struct smu_context *smu,
2322                                        enum amd_pp_clock_type type,
2323                                        struct pp_clock_levels_with_voltage *clocks)
2324 {
2325         int ret = 0;
2326
2327         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2328                 return -EOPNOTSUPP;
2329
2330         mutex_lock(&smu->mutex);
2331
2332         if (smu->ppt_funcs->get_clock_by_type_with_voltage)
2333                 ret = smu->ppt_funcs->get_clock_by_type_with_voltage(smu, type, clocks);
2334
2335         mutex_unlock(&smu->mutex);
2336
2337         return ret;
2338 }
2339
2340
2341 int smu_display_clock_voltage_request(struct smu_context *smu,
2342                                       struct pp_display_clock_request *clock_req)
2343 {
2344         int ret = 0;
2345
2346         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2347                 return -EOPNOTSUPP;
2348
2349         mutex_lock(&smu->mutex);
2350
2351         if (smu->ppt_funcs->display_clock_voltage_request)
2352                 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2353
2354         mutex_unlock(&smu->mutex);
2355
2356         return ret;
2357 }
2358
2359
2360 int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch)
2361 {
2362         int ret = -EINVAL;
2363
2364         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2365                 return -EOPNOTSUPP;
2366
2367         mutex_lock(&smu->mutex);
2368
2369         if (smu->ppt_funcs->display_disable_memory_clock_switch)
2370                 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2371
2372         mutex_unlock(&smu->mutex);
2373
2374         return ret;
2375 }
2376
2377 int smu_notify_smu_enable_pwe(struct smu_context *smu)
2378 {
2379         int ret = 0;
2380
2381         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2382                 return -EOPNOTSUPP;
2383
2384         mutex_lock(&smu->mutex);
2385
2386         if (smu->ppt_funcs->notify_smu_enable_pwe)
2387                 ret = smu->ppt_funcs->notify_smu_enable_pwe(smu);
2388
2389         mutex_unlock(&smu->mutex);
2390
2391         return ret;
2392 }
2393
2394 int smu_set_xgmi_pstate(struct smu_context *smu,
2395                         uint32_t pstate)
2396 {
2397         int ret = 0;
2398
2399         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2400                 return -EOPNOTSUPP;
2401
2402         mutex_lock(&smu->mutex);
2403
2404         if (smu->ppt_funcs->set_xgmi_pstate)
2405                 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2406
2407         mutex_unlock(&smu->mutex);
2408
2409         if(ret)
2410                 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n");
2411
2412         return ret;
2413 }
2414
2415 int smu_set_azalia_d3_pme(struct smu_context *smu)
2416 {
2417         int ret = 0;
2418
2419         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2420                 return -EOPNOTSUPP;
2421
2422         mutex_lock(&smu->mutex);
2423
2424         if (smu->ppt_funcs->set_azalia_d3_pme)
2425                 ret = smu->ppt_funcs->set_azalia_d3_pme(smu);
2426
2427         mutex_unlock(&smu->mutex);
2428
2429         return ret;
2430 }
2431
2432 /*
2433  * On system suspending or resetting, the dpm_enabled
2434  * flag will be cleared. So that those SMU services which
2435  * are not supported will be gated.
2436  *
2437  * However, the baco/mode1 reset should still be granted
2438  * as they are still supported and necessary.
2439  */
2440 bool smu_baco_is_support(struct smu_context *smu)
2441 {
2442         bool ret = false;
2443
2444         if (!smu->pm_enabled)
2445                 return false;
2446
2447         mutex_lock(&smu->mutex);
2448
2449         if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2450                 ret = smu->ppt_funcs->baco_is_support(smu);
2451
2452         mutex_unlock(&smu->mutex);
2453
2454         return ret;
2455 }
2456
2457 int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
2458 {
2459         if (smu->ppt_funcs->baco_get_state)
2460                 return -EINVAL;
2461
2462         mutex_lock(&smu->mutex);
2463         *state = smu->ppt_funcs->baco_get_state(smu);
2464         mutex_unlock(&smu->mutex);
2465
2466         return 0;
2467 }
2468
2469 int smu_baco_enter(struct smu_context *smu)
2470 {
2471         int ret = 0;
2472
2473         if (!smu->pm_enabled)
2474                 return -EOPNOTSUPP;
2475
2476         mutex_lock(&smu->mutex);
2477
2478         if (smu->ppt_funcs->baco_enter)
2479                 ret = smu->ppt_funcs->baco_enter(smu);
2480
2481         mutex_unlock(&smu->mutex);
2482
2483         if (ret)
2484                 dev_err(smu->adev->dev, "Failed to enter BACO state!\n");
2485
2486         return ret;
2487 }
2488
2489 int smu_baco_exit(struct smu_context *smu)
2490 {
2491         int ret = 0;
2492
2493         if (!smu->pm_enabled)
2494                 return -EOPNOTSUPP;
2495
2496         mutex_lock(&smu->mutex);
2497
2498         if (smu->ppt_funcs->baco_exit)
2499                 ret = smu->ppt_funcs->baco_exit(smu);
2500
2501         mutex_unlock(&smu->mutex);
2502
2503         if (ret)
2504                 dev_err(smu->adev->dev, "Failed to exit BACO state!\n");
2505
2506         return ret;
2507 }
2508
2509 bool smu_mode1_reset_is_support(struct smu_context *smu)
2510 {
2511         bool ret = false;
2512
2513         if (!smu->pm_enabled)
2514                 return false;
2515
2516         mutex_lock(&smu->mutex);
2517
2518         if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support)
2519                 ret = smu->ppt_funcs->mode1_reset_is_support(smu);
2520
2521         mutex_unlock(&smu->mutex);
2522
2523         return ret;
2524 }
2525
2526 int smu_mode1_reset(struct smu_context *smu)
2527 {
2528         int ret = 0;
2529
2530         if (!smu->pm_enabled)
2531                 return -EOPNOTSUPP;
2532
2533         mutex_lock(&smu->mutex);
2534
2535         if (smu->ppt_funcs->mode1_reset)
2536                 ret = smu->ppt_funcs->mode1_reset(smu);
2537
2538         mutex_unlock(&smu->mutex);
2539
2540         return ret;
2541 }
2542
2543 int smu_mode2_reset(struct smu_context *smu)
2544 {
2545         int ret = 0;
2546
2547         if (!smu->pm_enabled)
2548                 return -EOPNOTSUPP;
2549
2550         mutex_lock(&smu->mutex);
2551
2552         if (smu->ppt_funcs->mode2_reset)
2553                 ret = smu->ppt_funcs->mode2_reset(smu);
2554
2555         mutex_unlock(&smu->mutex);
2556
2557         if (ret)
2558                 dev_err(smu->adev->dev, "Mode2 reset failed!\n");
2559
2560         return ret;
2561 }
2562
2563 int smu_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
2564                                          struct pp_smu_nv_clock_table *max_clocks)
2565 {
2566         int ret = 0;
2567
2568         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2569                 return -EOPNOTSUPP;
2570
2571         mutex_lock(&smu->mutex);
2572
2573         if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2574                 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2575
2576         mutex_unlock(&smu->mutex);
2577
2578         return ret;
2579 }
2580
2581 int smu_get_uclk_dpm_states(struct smu_context *smu,
2582                             unsigned int *clock_values_in_khz,
2583                             unsigned int *num_states)
2584 {
2585         int ret = 0;
2586
2587         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2588                 return -EOPNOTSUPP;
2589
2590         mutex_lock(&smu->mutex);
2591
2592         if (smu->ppt_funcs->get_uclk_dpm_states)
2593                 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2594
2595         mutex_unlock(&smu->mutex);
2596
2597         return ret;
2598 }
2599
2600 enum amd_pm_state_type smu_get_current_power_state(struct smu_context *smu)
2601 {
2602         enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2603
2604         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2605                 return -EOPNOTSUPP;
2606
2607         mutex_lock(&smu->mutex);
2608
2609         if (smu->ppt_funcs->get_current_power_state)
2610                 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2611
2612         mutex_unlock(&smu->mutex);
2613
2614         return pm_state;
2615 }
2616
2617 int smu_get_dpm_clock_table(struct smu_context *smu,
2618                             struct dpm_clocks *clock_table)
2619 {
2620         int ret = 0;
2621
2622         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2623                 return -EOPNOTSUPP;
2624
2625         mutex_lock(&smu->mutex);
2626
2627         if (smu->ppt_funcs->get_dpm_clock_table)
2628                 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2629
2630         mutex_unlock(&smu->mutex);
2631
2632         return ret;
2633 }