drivers/gpu/drm/amd/amdgpu/nv.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_ih.h"
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "amdgpu_ucode.h"
  34 #include "amdgpu_psp.h"
  35 #include "amdgpu_smu.h"
  36 #include "atom.h"
  37 #include "amd_pcie.h"
  38
  39 #include "gc/gc_10_1_0_offset.h"
  40 #include "gc/gc_10_1_0_sh_mask.h"
  41 #include "hdp/hdp_5_0_0_offset.h"
  42 #include "hdp/hdp_5_0_0_sh_mask.h"
  43 #include "smuio/smuio_11_0_0_offset.h"
  44 #include "mp/mp_11_0_offset.h"
  45
  46 #include "soc15.h"
  47 #include "soc15_common.h"
  48 #include "gmc_v10_0.h"
  49 #include "gfxhub_v2_0.h"
  50 #include "mmhub_v2_0.h"
  51 #include "nbio_v2_3.h"
  52 #include "nv.h"
  53 #include "navi10_ih.h"
  54 #include "gfx_v10_0.h"
  55 #include "sdma_v5_0.h"
  56 #include "sdma_v5_2.h"
  57 #include "vcn_v2_0.h"
  58 #include "jpeg_v2_0.h"
  59 #include "vcn_v3_0.h"
  60 #include "jpeg_v3_0.h"
  61 #include "dce_virtual.h"
  62 #include "mes_v10_1.h"
  63 #include "mxgpu_nv.h"
  64
  65 static const struct amd_ip_funcs nv_common_ip_funcs;
  66
  67 /*
  68  * Indirect registers accessor
  69  */
  70 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
  71 {
  72         unsigned long flags, address, data;
  73         u32 r;
  74         address = adev->nbio.funcs->get_pcie_index_offset(adev);
  75         data = adev->nbio.funcs->get_pcie_data_offset(adev);
  76
  77         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  78         WREG32(address, reg);
  79         (void)RREG32(address);
  80         r = RREG32(data);
  81         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  82         return r;
  83 }
  84
  85 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
  86 {
  87         unsigned long flags, address, data;
  88
  89         address = adev->nbio.funcs->get_pcie_index_offset(adev);
  90         data = adev->nbio.funcs->get_pcie_data_offset(adev);
  91
  92         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
  93         WREG32(address, reg);
  94         (void)RREG32(address);
  95         WREG32(data, v);
  96         (void)RREG32(data);
  97         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
  98 }
  99
 100 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
 101 {
 102         unsigned long flags, address, data;
 103         u64 r;
 104         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 105         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 106
 107         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 108         /* read low 32 bit */
 109         WREG32(address, reg);
 110         (void)RREG32(address);
 111         r = RREG32(data);
 112
 113         /* read high 32 bit*/
 114         WREG32(address, reg + 4);
 115         (void)RREG32(address);
 116         r |= ((u64)RREG32(data) << 32);
 117         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 118         return r;
 119 }
 120
 121 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
 122 {
 123         unsigned long flags, address, data;
 124
 125         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 126         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 127
 128         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 129         /* write low 32 bit */
 130         WREG32(address, reg);
 131         (void)RREG32(address);
 132         WREG32(data, (u32)(v & 0xffffffffULL));
 133         (void)RREG32(data);
 134
 135         /* write high 32 bit */
 136         WREG32(address, reg + 4);
 137         (void)RREG32(address);
 138         WREG32(data, (u32)(v >> 32));
 139         (void)RREG32(data);
 140         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 141 }
 142
 143 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
 144 {
 145         unsigned long flags, address, data;
 146         u32 r;
 147
 148         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 149         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 150
 151         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 152         WREG32(address, (reg));
 153         r = RREG32(data);
 154         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 155         return r;
 156 }
 157
 158 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 159 {
 160         unsigned long flags, address, data;
 161
 162         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 163         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 164
 165         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 166         WREG32(address, (reg));
 167         WREG32(data, (v));
 168         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 169 }
 170
 171 static u32 nv_get_config_memsize(struct amdgpu_device *adev)
 172 {
 173         return adev->nbio.funcs->get_memsize(adev);
 174 }
 175
 176 static u32 nv_get_xclk(struct amdgpu_device *adev)
 177 {
 178         return adev->clock.spll.reference_freq;
 179 }
 180
 181
 182 void nv_grbm_select(struct amdgpu_device *adev,
 183                      u32 me, u32 pipe, u32 queue, u32 vmid)
 184 {
 185         u32 grbm_gfx_cntl = 0;
 186         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 187         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 188         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 189         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 190
 191         WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
 192 }
 193
 194 static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
 195 {
 196         /* todo */
 197 }
 198
 199 static bool nv_read_disabled_bios(struct amdgpu_device *adev)
 200 {
 201         /* todo */
 202         return false;
 203 }
 204
 205 static bool nv_read_bios_from_rom(struct amdgpu_device *adev,
 206                                   u8 *bios, u32 length_bytes)
 207 {
 208         u32 *dw_ptr;
 209         u32 i, length_dw;
 210
 211         if (bios == NULL)
 212                 return false;
 213         if (length_bytes == 0)
 214                 return false;
 215         /* APU vbios image is part of sbios image */
 216         if (adev->flags & AMD_IS_APU)
 217                 return false;
 218
 219         dw_ptr = (u32 *)bios;
 220         length_dw = ALIGN(length_bytes, 4) / 4;
 221
 222         /* set rom index to 0 */
 223         WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
 224         /* read out the rom data */
 225         for (i = 0; i < length_dw; i++)
 226                 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
 227
 228         return true;
 229 }
 230
 231 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
 232         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 233         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 234         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 235         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 236         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 237         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 238         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 239         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 240         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 241         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 242         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 243         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 244         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 245         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 246         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 247         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
 248         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 249         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 250         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 251 };
 252
 253 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 254                                          u32 sh_num, u32 reg_offset)
 255 {
 256         uint32_t val;
 257
 258         mutex_lock(&adev->grbm_idx_mutex);
 259         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 260                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 261
 262         val = RREG32(reg_offset);
 263
 264         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 265                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 266         mutex_unlock(&adev->grbm_idx_mutex);
 267         return val;
 268 }
 269
 270 static uint32_t nv_get_register_value(struct amdgpu_device *adev,
 271                                       bool indexed, u32 se_num,
 272                                       u32 sh_num, u32 reg_offset)
 273 {
 274         if (indexed) {
 275                 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
 276         } else {
 277                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 278                         return adev->gfx.config.gb_addr_config;
 279                 return RREG32(reg_offset);
 280         }
 281 }
 282
 283 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
 284                             u32 sh_num, u32 reg_offset, u32 *value)
 285 {
 286         uint32_t i;
 287         struct soc15_allowed_register_entry  *en;
 288
 289         *value = 0;
 290         for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
 291                 en = &nv_allowed_read_registers[i];
 292                 if (reg_offset !=
 293                     (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
 294                         continue;
 295
 296                 *value = nv_get_register_value(adev,
 297                                                nv_allowed_read_registers[i].grbm_indexed,
 298                                                se_num, sh_num, reg_offset);
 299                 return 0;
 300         }
 301         return -EINVAL;
 302 }
 303
 304 static int nv_asic_mode1_reset(struct amdgpu_device *adev)
 305 {
 306         u32 i;
 307         int ret = 0;
 308
 309         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 310
 311         /* disable BM */
 312         pci_clear_master(adev->pdev);
 313
 314         pci_save_state(adev->pdev);
 315
 316         if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
 317                 dev_info(adev->dev, "GPU smu mode1 reset\n");
 318                 ret = amdgpu_dpm_mode1_reset(adev);
 319         } else {
 320                 dev_info(adev->dev, "GPU psp mode1 reset\n");
 321                 ret = psp_gpu_reset(adev);
 322         }
 323
 324         if (ret)
 325                 dev_err(adev->dev, "GPU mode1 reset failed\n");
 326         pci_restore_state(adev->pdev);
 327
 328         /* wait for asic to come out of reset */
 329         for (i = 0; i < adev->usec_timeout; i++) {
 330                 u32 memsize = adev->nbio.funcs->get_memsize(adev);
 331
 332                 if (memsize != 0xffffffff)
 333                         break;
 334                 udelay(1);
 335         }
 336
 337         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 338
 339         return ret;
 340 }
 341
 342 static bool nv_asic_supports_baco(struct amdgpu_device *adev)
 343 {
 344         struct smu_context *smu = &adev->smu;
 345
 346         if (smu_baco_is_support(smu))
 347                 return true;
 348         else
 349                 return false;
 350 }
 351
 352 static enum amd_reset_method
 353 nv_asic_reset_method(struct amdgpu_device *adev)
 354 {
 355         struct smu_context *smu = &adev->smu;
 356
 357         if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
 358             amdgpu_reset_method == AMD_RESET_METHOD_BACO)
 359                 return amdgpu_reset_method;
 360
 361         if (amdgpu_reset_method != -1)
 362                 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
 363                                   amdgpu_reset_method);
 364
 365         switch (adev->asic_type) {
 366         case CHIP_SIENNA_CICHLID:
 367                 return AMD_RESET_METHOD_MODE1;
 368         default:
 369                 if (smu_baco_is_support(smu))
 370                         return AMD_RESET_METHOD_BACO;
 371                 else
 372                         return AMD_RESET_METHOD_MODE1;
 373         }
 374 }
 375
 376 static int nv_asic_reset(struct amdgpu_device *adev)
 377 {
 378         int ret = 0;
 379         struct smu_context *smu = &adev->smu;
 380
 381         if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
 382                 dev_info(adev->dev, "GPU BACO reset\n");
 383
 384                 ret = smu_baco_enter(smu);
 385                 if (ret)
 386                         return ret;
 387                 ret = smu_baco_exit(smu);
 388                 if (ret)
 389                         return ret;
 390         } else
 391                 ret = nv_asic_mode1_reset(adev);
 392
 393         return ret;
 394 }
 395
 396 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 397 {
 398         /* todo */
 399         return 0;
 400 }
 401
 402 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 403 {
 404         /* todo */
 405         return 0;
 406 }
 407
 408 static void nv_pcie_gen3_enable(struct amdgpu_device *adev)
 409 {
 410         if (pci_is_root_bus(adev->pdev->bus))
 411                 return;
 412
 413         if (amdgpu_pcie_gen2 == 0)
 414                 return;
 415
 416         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 417                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 418                 return;
 419
 420         /* todo */
 421 }
 422
 423 static void nv_program_aspm(struct amdgpu_device *adev)
 424 {
 425
 426         if (amdgpu_aspm == 0)
 427                 return;
 428
 429         /* todo */
 430 }
 431
 432 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
 433                                         bool enable)
 434 {
 435         adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
 436         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
 437 }
 438
 439 static const struct amdgpu_ip_block_version nv_common_ip_block =
 440 {
 441         .type = AMD_IP_BLOCK_TYPE_COMMON,
 442         .major = 1,
 443         .minor = 0,
 444         .rev = 0,
 445         .funcs = &nv_common_ip_funcs,
 446 };
 447
 448 static int nv_reg_base_init(struct amdgpu_device *adev)
 449 {
 450         int r;
 451
 452         if (amdgpu_discovery) {
 453                 r = amdgpu_discovery_reg_base_init(adev);
 454                 if (r) {
 455                         DRM_WARN("failed to init reg base from ip discovery table, "
 456                                         "fallback to legacy init method\n");
 457                         goto legacy_init;
 458                 }
 459
 460                 return 0;
 461         }
 462
 463 legacy_init:
 464         switch (adev->asic_type) {
 465         case CHIP_NAVI10:
 466                 navi10_reg_base_init(adev);
 467                 break;
 468         case CHIP_NAVI14:
 469                 navi14_reg_base_init(adev);
 470                 break;
 471         case CHIP_NAVI12:
 472                 navi12_reg_base_init(adev);
 473                 break;
 474         case CHIP_SIENNA_CICHLID:
 475         case CHIP_NAVY_FLOUNDER:
 476                 sienna_cichlid_reg_base_init(adev);
 477                 break;
 478         default:
 479                 return -EINVAL;
 480         }
 481
 482         return 0;
 483 }
 484
 485 void nv_set_virt_ops(struct amdgpu_device *adev)
 486 {
 487         adev->virt.ops = &xgpu_nv_virt_ops;
 488 }
 489
 490 int nv_set_ip_blocks(struct amdgpu_device *adev)
 491 {
 492         int r;
 493
 494         adev->nbio.funcs = &nbio_v2_3_funcs;
 495         adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
 496
 497         if (adev->asic_type == CHIP_SIENNA_CICHLID)
 498                 adev->gmc.xgmi.supported = true;
 499
 500         /* Set IP register base before any HW register access */
 501         r = nv_reg_base_init(adev);
 502         if (r)
 503                 return r;
 504
 505         switch (adev->asic_type) {
 506         case CHIP_NAVI10:
 507         case CHIP_NAVI14:
 508                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 509                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 510                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 511                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 512                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 513                     !amdgpu_sriov_vf(adev))
 514                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 515                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 516                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 517 #if defined(CONFIG_DRM_AMD_DC)
 518                 else if (amdgpu_device_has_dc_support(adev))
 519                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 520 #endif
 521                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 522                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 523                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 524                     !amdgpu_sriov_vf(adev))
 525                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 526                 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 527                 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 528                 if (adev->enable_mes)
 529                         amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
 530                 break;
 531         case CHIP_NAVI12:
 532                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 533                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 534                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 535                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 536                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
 537                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 538                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 539                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 540 #if defined(CONFIG_DRM_AMD_DC)
 541                 else if (amdgpu_device_has_dc_support(adev))
 542                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 543 #endif
 544                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 545                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 546                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 547                     !amdgpu_sriov_vf(adev))
 548                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 549                 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 550                 if (!amdgpu_sriov_vf(adev))
 551                         amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 552                 break;
 553         case CHIP_SIENNA_CICHLID:
 554                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 555                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 556                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 557                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 558                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 559                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 560                     is_support_sw_smu(adev) && !amdgpu_sriov_vf(adev))
 561                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 562                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 563                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 564 #if defined(CONFIG_DRM_AMD_DC)
 565                 else if (amdgpu_device_has_dc_support(adev))
 566                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 567 #endif
 568                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 569                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 570                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 571                 if (!amdgpu_sriov_vf(adev))
 572                         amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 573
 574                 if (adev->enable_mes)
 575                         amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
 576                 break;
 577         case CHIP_NAVY_FLOUNDER:
 578                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 579                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 580                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 581                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 582                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 583                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 584                     is_support_sw_smu(adev))
 585                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 586                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 587                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 588 #if defined(CONFIG_DRM_AMD_DC)
 589                 else if (amdgpu_device_has_dc_support(adev))
 590                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 591 #endif
 592                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 593                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 594                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 595                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 596                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 597                     is_support_sw_smu(adev))
 598                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 599                 break;
 600         default:
 601                 return -EINVAL;
 602         }
 603
 604         return 0;
 605 }
 606
 607 static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
 608 {
 609         return adev->nbio.funcs->get_rev_id(adev);
 610 }
 611
 612 static void nv_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
 613 {
 614         adev->nbio.funcs->hdp_flush(adev, ring);
 615 }
 616
 617 static void nv_invalidate_hdp(struct amdgpu_device *adev,
 618                                 struct amdgpu_ring *ring)
 619 {
 620         if (!ring || !ring->funcs->emit_wreg) {
 621                 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
 622         } else {
 623                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
 624                                         HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
 625         }
 626 }
 627
 628 static bool nv_need_full_reset(struct amdgpu_device *adev)
 629 {
 630         return true;
 631 }
 632
 633 static bool nv_need_reset_on_init(struct amdgpu_device *adev)
 634 {
 635         u32 sol_reg;
 636
 637         if (adev->flags & AMD_IS_APU)
 638                 return false;
 639
 640         /* Check sOS sign of life register to confirm sys driver and sOS
 641          * are already been loaded.
 642          */
 643         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 644         if (sol_reg)
 645                 return true;
 646
 647         return false;
 648 }
 649
 650 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev)
 651 {
 652
 653         /* TODO
 654          * dummy implement for pcie_replay_count sysfs interface
 655          * */
 656
 657         return 0;
 658 }
 659
 660 static void nv_init_doorbell_index(struct amdgpu_device *adev)
 661 {
 662         adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
 663         adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
 664         adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
 665         adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
 666         adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
 667         adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
 668         adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
 669         adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
 670         adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
 671         adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
 672         adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
 673         adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
 674         adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
 675         adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING;
 676         adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
 677         adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
 678         adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
 679         adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
 680         adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
 681         adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
 682         adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
 683         adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
 684         adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
 685         adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
 686         adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
 687
 688         adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
 689         adev->doorbell_index.sdma_doorbell_range = 20;
 690 }
 691
 692 static const struct amdgpu_asic_funcs nv_asic_funcs =
 693 {
 694         .read_disabled_bios = &nv_read_disabled_bios,
 695         .read_bios_from_rom = &nv_read_bios_from_rom,
 696         .read_register = &nv_read_register,
 697         .reset = &nv_asic_reset,
 698         .reset_method = &nv_asic_reset_method,
 699         .set_vga_state = &nv_vga_set_state,
 700         .get_xclk = &nv_get_xclk,
 701         .set_uvd_clocks = &nv_set_uvd_clocks,
 702         .set_vce_clocks = &nv_set_vce_clocks,
 703         .get_config_memsize = &nv_get_config_memsize,
 704         .flush_hdp = &nv_flush_hdp,
 705         .invalidate_hdp = &nv_invalidate_hdp,
 706         .init_doorbell_index = &nv_init_doorbell_index,
 707         .need_full_reset = &nv_need_full_reset,
 708         .need_reset_on_init = &nv_need_reset_on_init,
 709         .get_pcie_replay_count = &nv_get_pcie_replay_count,
 710         .supports_baco = &nv_asic_supports_baco,
 711 };
 712
 713 static int nv_common_early_init(void *handle)
 714 {
 715 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
 716         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 717
 718         adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
 719         adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
 720         adev->smc_rreg = NULL;
 721         adev->smc_wreg = NULL;
 722         adev->pcie_rreg = &nv_pcie_rreg;
 723         adev->pcie_wreg = &nv_pcie_wreg;
 724         adev->pcie_rreg64 = &nv_pcie_rreg64;
 725         adev->pcie_wreg64 = &nv_pcie_wreg64;
 726
 727         /* TODO: will add them during VCN v2 implementation */
 728         adev->uvd_ctx_rreg = NULL;
 729         adev->uvd_ctx_wreg = NULL;
 730
 731         adev->didt_rreg = &nv_didt_rreg;
 732         adev->didt_wreg = &nv_didt_wreg;
 733
 734         adev->asic_funcs = &nv_asic_funcs;
 735
 736         adev->rev_id = nv_get_rev_id(adev);
 737         adev->external_rev_id = 0xff;
 738         switch (adev->asic_type) {
 739         case CHIP_NAVI10:
 740                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 741                         AMD_CG_SUPPORT_GFX_CGCG |
 742                         AMD_CG_SUPPORT_IH_CG |
 743                         AMD_CG_SUPPORT_HDP_MGCG |
 744                         AMD_CG_SUPPORT_HDP_LS |
 745                         AMD_CG_SUPPORT_SDMA_MGCG |
 746                         AMD_CG_SUPPORT_SDMA_LS |
 747                         AMD_CG_SUPPORT_MC_MGCG |
 748                         AMD_CG_SUPPORT_MC_LS |
 749                         AMD_CG_SUPPORT_ATHUB_MGCG |
 750                         AMD_CG_SUPPORT_ATHUB_LS |
 751                         AMD_CG_SUPPORT_VCN_MGCG |
 752                         AMD_CG_SUPPORT_JPEG_MGCG |
 753                         AMD_CG_SUPPORT_BIF_MGCG |
 754                         AMD_CG_SUPPORT_BIF_LS;
 755                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 756                         AMD_PG_SUPPORT_VCN_DPG |
 757                         AMD_PG_SUPPORT_JPEG |
 758                         AMD_PG_SUPPORT_ATHUB;
 759                 adev->external_rev_id = adev->rev_id + 0x1;
 760                 break;
 761         case CHIP_NAVI14:
 762                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 763                         AMD_CG_SUPPORT_GFX_CGCG |
 764                         AMD_CG_SUPPORT_IH_CG |
 765                         AMD_CG_SUPPORT_HDP_MGCG |
 766                         AMD_CG_SUPPORT_HDP_LS |
 767                         AMD_CG_SUPPORT_SDMA_MGCG |
 768                         AMD_CG_SUPPORT_SDMA_LS |
 769                         AMD_CG_SUPPORT_MC_MGCG |
 770                         AMD_CG_SUPPORT_MC_LS |
 771                         AMD_CG_SUPPORT_ATHUB_MGCG |
 772                         AMD_CG_SUPPORT_ATHUB_LS |
 773                         AMD_CG_SUPPORT_VCN_MGCG |
 774                         AMD_CG_SUPPORT_JPEG_MGCG |
 775                         AMD_CG_SUPPORT_BIF_MGCG |
 776                         AMD_CG_SUPPORT_BIF_LS;
 777                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 778                         AMD_PG_SUPPORT_JPEG |
 779                         AMD_PG_SUPPORT_VCN_DPG;
 780                 adev->external_rev_id = adev->rev_id + 20;
 781                 break;
 782         case CHIP_NAVI12:
 783                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 784                         AMD_CG_SUPPORT_GFX_MGLS |
 785                         AMD_CG_SUPPORT_GFX_CGCG |
 786                         AMD_CG_SUPPORT_GFX_CP_LS |
 787                         AMD_CG_SUPPORT_GFX_RLC_LS |
 788                         AMD_CG_SUPPORT_IH_CG |
 789                         AMD_CG_SUPPORT_HDP_MGCG |
 790                         AMD_CG_SUPPORT_HDP_LS |
 791                         AMD_CG_SUPPORT_SDMA_MGCG |
 792                         AMD_CG_SUPPORT_SDMA_LS |
 793                         AMD_CG_SUPPORT_MC_MGCG |
 794                         AMD_CG_SUPPORT_MC_LS |
 795                         AMD_CG_SUPPORT_ATHUB_MGCG |
 796                         AMD_CG_SUPPORT_ATHUB_LS |
 797                         AMD_CG_SUPPORT_VCN_MGCG |
 798                         AMD_CG_SUPPORT_JPEG_MGCG;
 799                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 800                         AMD_PG_SUPPORT_VCN_DPG |
 801                         AMD_PG_SUPPORT_JPEG |
 802                         AMD_PG_SUPPORT_ATHUB;
 803                 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
 804                  * as a consequence, the rev_id and external_rev_id are wrong.
 805                  * workaround it by hardcoding rev_id to 0 (default value).
 806                  */
 807                 if (amdgpu_sriov_vf(adev))
 808                         adev->rev_id = 0;
 809                 adev->external_rev_id = adev->rev_id + 0xa;
 810                 break;
 811         case CHIP_SIENNA_CICHLID:
 812                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 813                         AMD_CG_SUPPORT_GFX_CGCG |
 814                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 815                         AMD_CG_SUPPORT_MC_MGCG |
 816                         AMD_CG_SUPPORT_VCN_MGCG |
 817                         AMD_CG_SUPPORT_JPEG_MGCG |
 818                         AMD_CG_SUPPORT_HDP_MGCG |
 819                         AMD_CG_SUPPORT_HDP_LS |
 820                         AMD_CG_SUPPORT_IH_CG |
 821                         AMD_CG_SUPPORT_MC_LS;
 822                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 823                         AMD_PG_SUPPORT_VCN_DPG |
 824                         AMD_PG_SUPPORT_JPEG |
 825                         AMD_PG_SUPPORT_ATHUB |
 826                         AMD_PG_SUPPORT_MMHUB;
 827                 if (amdgpu_sriov_vf(adev)) {
 828                         /* hypervisor control CG and PG enablement */
 829                         adev->cg_flags = 0;
 830                         adev->pg_flags = 0;
 831                 }
 832                 adev->external_rev_id = adev->rev_id + 0x28;
 833                 break;
 834         case CHIP_NAVY_FLOUNDER:
 835                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 836                         AMD_CG_SUPPORT_GFX_CGCG |
 837                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 838                         AMD_CG_SUPPORT_VCN_MGCG |
 839                         AMD_CG_SUPPORT_JPEG_MGCG |
 840                         AMD_CG_SUPPORT_MC_MGCG |
 841                         AMD_CG_SUPPORT_MC_LS |
 842                         AMD_CG_SUPPORT_HDP_MGCG |
 843                         AMD_CG_SUPPORT_HDP_LS |
 844                         AMD_CG_SUPPORT_IH_CG;
 845                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 846                         AMD_PG_SUPPORT_VCN_DPG |
 847                         AMD_PG_SUPPORT_JPEG |
 848                         AMD_PG_SUPPORT_ATHUB |
 849                         AMD_PG_SUPPORT_MMHUB;
 850                 adev->external_rev_id = adev->rev_id + 0x32;
 851                 break;
 852
 853         default:
 854                 /* FIXME: not supported yet */
 855                 return -EINVAL;
 856         }
 857
 858         if (amdgpu_sriov_vf(adev)) {
 859                 amdgpu_virt_init_setting(adev);
 860                 xgpu_nv_mailbox_set_irq_funcs(adev);
 861         }
 862
 863         return 0;
 864 }
 865
 866 static int nv_common_late_init(void *handle)
 867 {
 868         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 869
 870         if (amdgpu_sriov_vf(adev))
 871                 xgpu_nv_mailbox_get_irq(adev);
 872
 873         return 0;
 874 }
 875
 876 static int nv_common_sw_init(void *handle)
 877 {
 878         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 879
 880         if (amdgpu_sriov_vf(adev))
 881                 xgpu_nv_mailbox_add_irq_id(adev);
 882
 883         return 0;
 884 }
 885
 886 static int nv_common_sw_fini(void *handle)
 887 {
 888         return 0;
 889 }
 890
 891 static int nv_common_hw_init(void *handle)
 892 {
 893         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 894
 895         /* enable pcie gen2/3 link */
 896         nv_pcie_gen3_enable(adev);
 897         /* enable aspm */
 898         nv_program_aspm(adev);
 899         /* setup nbio registers */
 900         adev->nbio.funcs->init_registers(adev);
 901         /* remap HDP registers to a hole in mmio space,
 902          * for the purpose of expose those registers
 903          * to process space
 904          */
 905         if (adev->nbio.funcs->remap_hdp_registers)
 906                 adev->nbio.funcs->remap_hdp_registers(adev);
 907         /* enable the doorbell aperture */
 908         nv_enable_doorbell_aperture(adev, true);
 909
 910         return 0;
 911 }
 912
 913 static int nv_common_hw_fini(void *handle)
 914 {
 915         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 916
 917         /* disable the doorbell aperture */
 918         nv_enable_doorbell_aperture(adev, false);
 919
 920         return 0;
 921 }
 922
 923 static int nv_common_suspend(void *handle)
 924 {
 925         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 926
 927         return nv_common_hw_fini(adev);
 928 }
 929
 930 static int nv_common_resume(void *handle)
 931 {
 932         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 933
 934         return nv_common_hw_init(adev);
 935 }
 936
 937 static bool nv_common_is_idle(void *handle)
 938 {
 939         return true;
 940 }
 941
 942 static int nv_common_wait_for_idle(void *handle)
 943 {
 944         return 0;
 945 }
 946
 947 static int nv_common_soft_reset(void *handle)
 948 {
 949         return 0;
 950 }
 951
 952 static void nv_update_hdp_mem_power_gating(struct amdgpu_device *adev,
 953                                            bool enable)
 954 {
 955         uint32_t hdp_clk_cntl, hdp_clk_cntl1;
 956         uint32_t hdp_mem_pwr_cntl;
 957
 958         if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |
 959                                 AMD_CG_SUPPORT_HDP_DS |
 960                                 AMD_CG_SUPPORT_HDP_SD)))
 961                 return;
 962
 963         hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
 964         hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);
 965
 966         /* Before doing clock/power mode switch,
 967          * forced on IPH & RC clock */
 968         hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
 969                                      IPH_MEM_CLK_SOFT_OVERRIDE, 1);
 970         hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
 971                                      RC_MEM_CLK_SOFT_OVERRIDE, 1);
 972         WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
 973
 974         /* HDP 5.0 doesn't support dynamic power mode switch,
 975          * disable clock and power gating before any changing */
 976         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 977                                          IPH_MEM_POWER_CTRL_EN, 0);
 978         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 979                                          IPH_MEM_POWER_LS_EN, 0);
 980         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 981                                          IPH_MEM_POWER_DS_EN, 0);
 982         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 983                                          IPH_MEM_POWER_SD_EN, 0);
 984         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 985                                          RC_MEM_POWER_CTRL_EN, 0);
 986         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 987                                          RC_MEM_POWER_LS_EN, 0);
 988         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 989                                          RC_MEM_POWER_DS_EN, 0);
 990         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 991                                          RC_MEM_POWER_SD_EN, 0);
 992         WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
 993
 994         /* only one clock gating mode (LS/DS/SD) can be enabled */
 995         if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
 996                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 997                                                  HDP_MEM_POWER_CTRL,
 998                                                  IPH_MEM_POWER_LS_EN, enable);
 999                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
1000                                                  HDP_MEM_POWER_CTRL,
1001                                                  RC_MEM_POWER_LS_EN, enable);
1002         } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
1003                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
1004                                                  HDP_MEM_POWER_CTRL,
1005                                                  IPH_MEM_POWER_DS_EN, enable);
1006                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
1007                                                  HDP_MEM_POWER_CTRL,
1008                                                  RC_MEM_POWER_DS_EN, enable);
1009         } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
1010                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
1011                                                  HDP_MEM_POWER_CTRL,
1012                                                  IPH_MEM_POWER_SD_EN, enable);
1013                 /* RC should not use shut down mode, fallback to ds */
1014                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
1015                                                  HDP_MEM_POWER_CTRL,
1016                                                  RC_MEM_POWER_DS_EN, enable);
1017         }
1018
1019         /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to
1020          * be set for SRAM LS/DS/SD */
1021         if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS |
1022                                                         AMD_CG_SUPPORT_HDP_SD)) {
1023                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
1024                                                 IPH_MEM_POWER_CTRL_EN, 1);
1025                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
1026                                                 RC_MEM_POWER_CTRL_EN, 1);
1027         }
1028
1029         WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
1030
1031         /* restore IPH & RC clock override after clock/power mode changing */
1032         WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1);
1033 }
1034
1035 static void nv_update_hdp_clock_gating(struct amdgpu_device *adev,
1036                                        bool enable)
1037 {
1038         uint32_t hdp_clk_cntl;
1039
1040         if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
1041                 return;
1042
1043         hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
1044
1045         if (enable) {
1046                 hdp_clk_cntl &=
1047                         ~(uint32_t)
1048                           (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
1049                            HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
1050                            HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
1051                            HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
1052                            HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
1053                            HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK);
1054         } else {
1055                 hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
1056                         HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
1057                         HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
1058                         HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
1059                         HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
1060                         HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK;
1061         }
1062
1063         WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
1064 }
1065
1066 static int nv_common_set_clockgating_state(void *handle,
1067                                            enum amd_clockgating_state state)
1068 {
1069         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1070
1071         if (amdgpu_sriov_vf(adev))
1072                 return 0;
1073
1074         switch (adev->asic_type) {
1075         case CHIP_NAVI10:
1076         case CHIP_NAVI14:
1077         case CHIP_NAVI12:
1078         case CHIP_SIENNA_CICHLID:
1079         case CHIP_NAVY_FLOUNDER:
1080                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1081                                 state == AMD_CG_STATE_GATE);
1082                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1083                                 state == AMD_CG_STATE_GATE);
1084                 nv_update_hdp_mem_power_gating(adev,
1085                                    state == AMD_CG_STATE_GATE);
1086                 nv_update_hdp_clock_gating(adev,
1087                                 state == AMD_CG_STATE_GATE);
1088                 break;
1089         default:
1090                 break;
1091         }
1092         return 0;
1093 }
1094
1095 static int nv_common_set_powergating_state(void *handle,
1096                                            enum amd_powergating_state state)
1097 {
1098         /* TODO */
1099         return 0;
1100 }
1101
1102 static void nv_common_get_clockgating_state(void *handle, u32 *flags)
1103 {
1104         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1105         uint32_t tmp;
1106
1107         if (amdgpu_sriov_vf(adev))
1108                 *flags = 0;
1109
1110         adev->nbio.funcs->get_clockgating_state(adev, flags);
1111
1112         /* AMD_CG_SUPPORT_HDP_MGCG */
1113         tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
1114         if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
1115                      HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
1116                      HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
1117                      HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
1118                      HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
1119                      HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK)))
1120                 *flags |= AMD_CG_SUPPORT_HDP_MGCG;
1121
1122         /* AMD_CG_SUPPORT_HDP_LS/DS/SD */
1123         tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);
1124         if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK)
1125                 *flags |= AMD_CG_SUPPORT_HDP_LS;
1126         else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK)
1127                 *flags |= AMD_CG_SUPPORT_HDP_DS;
1128         else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK)
1129                 *flags |= AMD_CG_SUPPORT_HDP_SD;
1130
1131         return;
1132 }
1133
1134 static const struct amd_ip_funcs nv_common_ip_funcs = {
1135         .name = "nv_common",
1136         .early_init = nv_common_early_init,
1137         .late_init = nv_common_late_init,
1138         .sw_init = nv_common_sw_init,
1139         .sw_fini = nv_common_sw_fini,
1140         .hw_init = nv_common_hw_init,
1141         .hw_fini = nv_common_hw_fini,
1142         .suspend = nv_common_suspend,
1143         .resume = nv_common_resume,
1144         .is_idle = nv_common_is_idle,
1145         .wait_for_idle = nv_common_wait_for_idle,
1146         .soft_reset = nv_common_soft_reset,
1147         .set_clockgating_state = nv_common_set_clockgating_state,
1148         .set_powergating_state = nv_common_set_powergating_state,
1149         .get_clockgating_state = nv_common_get_clockgating_state,
1150 };