drivers/clk/socfpga/clk-agilex.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2019, Intel Corporation
   4  */
   5 #include <linux/slab.h>
   6 #include <linux/clk-provider.h>
   7 #include <linux/of_device.h>
   8 #include <linux/of_address.h>
   9 #include <linux/platform_device.h>
  10
  11 #include <dt-bindings/clock/agilex-clock.h>
  12
  13 #include "stratix10-clk.h"
  14
  15 static const struct clk_parent_data pll_mux[] = {
  16         { .fw_name = "osc1",
  17           .name = "osc1", },
  18         { .fw_name = "cb-intosc-hs-div2-clk",
  19           .name = "cb-intosc-hs-div2-clk", },
  20         { .fw_name = "f2s-free-clk",
  21           .name = "f2s-free-clk", },
  22 };
  23
  24 static const struct clk_parent_data cntr_mux[] = {
  25         { .fw_name = "main_pll",
  26           .name = "main_pll", },
  27         { .fw_name = "periph_pll",
  28           .name = "periph_pll", },
  29         { .fw_name = "osc1",
  30           .name = "osc1", },
  31         { .fw_name = "cb-intosc-hs-div2-clk",
  32           .name = "cb-intosc-hs-div2-clk", },
  33         { .fw_name = "f2s-free-clk",
  34           .name = "f2s-free-clk", },
  35 };
  36
  37 static const struct clk_parent_data boot_mux[] = {
  38         { .fw_name = "osc1",
  39           .name = "osc1", },
  40         { .fw_name = "cb-intosc-hs-div2-clk",
  41           .name = "cb-intosc-hs-div2-clk", },
  42 };
  43
  44 static const struct clk_parent_data mpu_free_mux[] = {
  45         { .fw_name = "main_pll_c0",
  46           .name = "main_pll_c0", },
  47         { .fw_name = "peri_pll_c0",
  48           .name = "peri_pll_c0", },
  49         { .fw_name = "osc1",
  50           .name = "osc1", },
  51         { .fw_name = "cb-intosc-hs-div2-clk",
  52           .name = "cb-intosc-hs-div2-clk", },
  53         { .fw_name = "f2s-free-clk",
  54           .name = "f2s-free-clk", },
  55 };
  56
  57 static const struct clk_parent_data noc_free_mux[] = {
  58         { .fw_name = "main_pll_c1",
  59           .name = "main_pll_c1", },
  60         { .fw_name = "peri_pll_c1",
  61           .name = "peri_pll_c1", },
  62         { .fw_name = "osc1",
  63           .name = "osc1", },
  64         { .fw_name = "cb-intosc-hs-div2-clk",
  65           .name = "cb-intosc-hs-div2-clk", },
  66         { .fw_name = "f2s-free-clk",
  67           .name = "f2s-free-clk", },
  68 };
  69
  70 static const struct clk_parent_data emaca_free_mux[] = {
  71         { .fw_name = "main_pll_c2",
  72           .name = "main_pll_c2", },
  73         { .fw_name = "peri_pll_c2",
  74           .name = "peri_pll_c2", },
  75         { .fw_name = "osc1",
  76           .name = "osc1", },
  77         { .fw_name = "cb-intosc-hs-div2-clk",
  78           .name = "cb-intosc-hs-div2-clk", },
  79         { .fw_name = "f2s-free-clk",
  80           .name = "f2s-free-clk", },
  81 };
  82
  83 static const struct clk_parent_data emacb_free_mux[] = {
  84         { .fw_name = "main_pll_c3",
  85           .name = "main_pll_c3", },
  86         { .fw_name = "peri_pll_c3",
  87           .name = "peri_pll_c3", },
  88         { .fw_name = "osc1",
  89           .name = "osc1", },
  90         { .fw_name = "cb-intosc-hs-div2-clk",
  91           .name = "cb-intosc-hs-div2-clk", },
  92         { .fw_name = "f2s-free-clk",
  93           .name = "f2s-free-clk", },
  94 };
  95
  96 static const struct clk_parent_data emac_ptp_free_mux[] = {
  97         { .fw_name = "main_pll_c3",
  98           .name = "main_pll_c3", },
  99         { .fw_name = "peri_pll_c3",
 100           .name = "peri_pll_c3", },
 101         { .fw_name = "osc1",
 102           .name = "osc1", },
 103         { .fw_name = "cb-intosc-hs-div2-clk",
 104           .name = "cb-intosc-hs-div2-clk", },
 105         { .fw_name = "f2s-free-clk",
 106           .name = "f2s-free-clk", },
 107 };
 108
 109 static const struct clk_parent_data gpio_db_free_mux[] = {
 110         { .fw_name = "main_pll_c3",
 111           .name = "main_pll_c3", },
 112         { .fw_name = "peri_pll_c3",
 113           .name = "peri_pll_c3", },
 114         { .fw_name = "osc1",
 115           .name = "osc1", },
 116         { .fw_name = "cb-intosc-hs-div2-clk",
 117           .name = "cb-intosc-hs-div2-clk", },
 118         { .fw_name = "f2s-free-clk",
 119           .name = "f2s-free-clk", },
 120 };
 121
 122 static const struct clk_parent_data psi_ref_free_mux[] = {
 123         { .fw_name = "main_pll_c3",
 124           .name = "main_pll_c3", },
 125         { .fw_name = "peri_pll_c3",
 126           .name = "peri_pll_c3", },
 127         { .fw_name = "osc1",
 128           .name = "osc1", },
 129         { .fw_name = "cb-intosc-hs-div2-clk",
 130           .name = "cb-intosc-hs-div2-clk", },
 131         { .fw_name = "f2s-free-clk",
 132           .name = "f2s-free-clk", },
 133 };
 134
 135 static const struct clk_parent_data sdmmc_free_mux[] = {
 136         { .fw_name = "main_pll_c3",
 137           .name = "main_pll_c3", },
 138         { .fw_name = "peri_pll_c3",
 139           .name = "peri_pll_c3", },
 140         { .fw_name = "osc1",
 141           .name = "osc1", },
 142         { .fw_name = "cb-intosc-hs-div2-clk",
 143           .name = "cb-intosc-hs-div2-clk", },
 144         { .fw_name = "f2s-free-clk",
 145           .name = "f2s-free-clk", },
 146 };
 147
 148 static const struct clk_parent_data s2f_usr0_free_mux[] = {
 149         { .fw_name = "main_pll_c2",
 150           .name = "main_pll_c2", },
 151         { .fw_name = "peri_pll_c2",
 152           .name = "peri_pll_c2", },
 153         { .fw_name = "osc1",
 154           .name = "osc1", },
 155         { .fw_name = "cb-intosc-hs-div2-clk",
 156           .name = "cb-intosc-hs-div2-clk", },
 157         { .fw_name = "f2s-free-clk",
 158           .name = "f2s-free-clk", },
 159 };
 160
 161 static const struct clk_parent_data s2f_usr1_free_mux[] = {
 162         { .fw_name = "main_pll_c2",
 163           .name = "main_pll_c2", },
 164         { .fw_name = "peri_pll_c2",
 165           .name = "peri_pll_c2", },
 166         { .fw_name = "osc1",
 167           .name = "osc1", },
 168         { .fw_name = "cb-intosc-hs-div2-clk",
 169           .name = "cb-intosc-hs-div2-clk", },
 170         { .fw_name = "f2s-free-clk",
 171           .name = "f2s-free-clk", },
 172 };
 173
 174 static const struct clk_parent_data mpu_mux[] = {
 175         { .fw_name = "mpu_free_clk",
 176           .name = "mpu_free_clk", },
 177         { .fw_name = "boot_clk",
 178           .name = "boot_clk", },
 179 };
 180
 181 static const struct clk_parent_data s2f_usr0_mux[] = {
 182         { .fw_name = "f2s-free-clk",
 183           .name = "f2s-free-clk", },
 184         { .fw_name = "boot_clk",
 185           .name = "boot_clk", },
 186 };
 187
 188 static const struct clk_parent_data emac_mux[] = {
 189         { .fw_name = "emaca_free_clk",
 190           .name = "emaca_free_clk", },
 191         { .fw_name = "emacb_free_clk",
 192           .name = "emacb_free_clk", },
 193 };
 194
 195 static const struct clk_parent_data noc_mux[] = {
 196         { .fw_name = "noc_free_clk",
 197           .name = "noc_free_clk", },
 198         { .fw_name = "boot_clk",
 199           .name = "boot_clk", },
 200 };
 201
 202 /* clocks in AO (always on) controller */
 203 static const struct stratix10_pll_clock agilex_pll_clks[] = {
 204         { AGILEX_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0,
 205           0x0},
 206         { AGILEX_MAIN_PLL_CLK, "main_pll", pll_mux, ARRAY_SIZE(pll_mux),
 207           0, 0x48},
 208         { AGILEX_PERIPH_PLL_CLK, "periph_pll", pll_mux, ARRAY_SIZE(pll_mux),
 209           0, 0x9c},
 210 };
 211
 212 static const struct stratix10_perip_c_clock agilex_main_perip_c_clks[] = {
 213         { AGILEX_MAIN_PLL_C0_CLK, "main_pll_c0", "main_pll", NULL, 1, 0, 0x58},
 214         { AGILEX_MAIN_PLL_C1_CLK, "main_pll_c1", "main_pll", NULL, 1, 0, 0x5C},
 215         { AGILEX_MAIN_PLL_C2_CLK, "main_pll_c2", "main_pll", NULL, 1, 0, 0x64},
 216         { AGILEX_MAIN_PLL_C3_CLK, "main_pll_c3", "main_pll", NULL, 1, 0, 0x68},
 217         { AGILEX_PERIPH_PLL_C0_CLK, "peri_pll_c0", "periph_pll", NULL, 1, 0, 0xAC},
 218         { AGILEX_PERIPH_PLL_C1_CLK, "peri_pll_c1", "periph_pll", NULL, 1, 0, 0xB0},
 219         { AGILEX_PERIPH_PLL_C2_CLK, "peri_pll_c2", "periph_pll", NULL, 1, 0, 0xB8},
 220         { AGILEX_PERIPH_PLL_C3_CLK, "peri_pll_c3", "periph_pll", NULL, 1, 0, 0xBC},
 221 };
 222
 223 static const struct stratix10_perip_cnt_clock agilex_main_perip_cnt_clks[] = {
 224         { AGILEX_MPU_FREE_CLK, "mpu_free_clk", NULL, mpu_free_mux, ARRAY_SIZE(mpu_free_mux),
 225            0, 0x3C, 0, 0, 0},
 226         { AGILEX_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux),
 227           0, 0x40, 0, 0, 1},
 228         { AGILEX_L4_SYS_FREE_CLK, "l4_sys_free_clk", "noc_free_clk", NULL, 1, 0,
 229           0, 4, 0, 0},
 230         { AGILEX_NOC_CLK, "noc_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux),
 231           0, 0, 0, 0x30, 1},
 232         { AGILEX_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux),
 233           0, 0xD4, 0, 0x88, 0},
 234         { AGILEX_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux),
 235           0, 0xD8, 0, 0x88, 1},
 236         { AGILEX_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, emac_ptp_free_mux,
 237           ARRAY_SIZE(emac_ptp_free_mux), 0, 0xDC, 0, 0x88, 2},
 238         { AGILEX_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux,
 239           ARRAY_SIZE(gpio_db_free_mux), 0, 0xE0, 0, 0x88, 3},
 240         { AGILEX_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux,
 241           ARRAY_SIZE(sdmmc_free_mux), 0, 0xE4, 0, 0x88, 4},
 242         { AGILEX_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", NULL, s2f_usr0_free_mux,
 243           ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0, 0},
 244         { AGILEX_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux,
 245           ARRAY_SIZE(s2f_usr1_free_mux), 0, 0xEC, 0, 0x88, 5},
 246         { AGILEX_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux,
 247           ARRAY_SIZE(psi_ref_free_mux), 0, 0xF0, 0, 0x88, 6},
 248 };
 249
 250 static const struct stratix10_gate_clock agilex_gate_clks[] = {
 251         { AGILEX_MPU_CLK, "mpu_clk", NULL, mpu_mux, ARRAY_SIZE(mpu_mux), 0, 0x24,
 252           0, 0, 0, 0, 0x30, 0, 0},
 253         { AGILEX_MPU_PERIPH_CLK, "mpu_periph_clk", "mpu_clk", NULL, 1, 0, 0x24,
 254           0, 0, 0, 0, 0, 0, 4},
 255         { AGILEX_MPU_CCU_CLK, "mpu_ccu_clk", "mpu_clk", NULL, 1, 0, 0x24,
 256           0, 0, 0, 0, 0, 0, 2},
 257         { AGILEX_L4_MAIN_CLK, "l4_main_clk", "noc_clk", NULL, 1, 0, 0x24,
 258           1, 0x44, 0, 2, 0, 0, 0},
 259         { AGILEX_L4_MP_CLK, "l4_mp_clk", "noc_clk", NULL, 1, 0, 0x24,
 260           2, 0x44, 8, 2, 0, 0, 0},
 261         /*
 262          * The l4_sp_clk feeds a 100 MHz clock to various peripherals, one of them
 263          * being the SP timers, thus cannot get gated.
 264          */
 265         { AGILEX_L4_SP_CLK, "l4_sp_clk", "noc_clk", NULL, 1, CLK_IS_CRITICAL, 0x24,
 266           3, 0x44, 16, 2, 0, 0, 0},
 267         { AGILEX_CS_AT_CLK, "cs_at_clk", "noc_clk", NULL, 1, 0, 0x24,
 268           4, 0x44, 24, 2, 0, 0, 0},
 269         { AGILEX_CS_TRACE_CLK, "cs_trace_clk", "noc_clk", NULL, 1, 0, 0x24,
 270           4, 0x44, 26, 2, 0, 0, 0},
 271         { AGILEX_CS_PDBG_CLK, "cs_pdbg_clk", "cs_at_clk", NULL, 1, 0, 0x24,
 272           4, 0x44, 28, 1, 0, 0, 0},
 273         { AGILEX_CS_TIMER_CLK, "cs_timer_clk", "noc_clk", NULL, 1, 0, 0x24,
 274           5, 0, 0, 0, 0, 0, 0},
 275         { AGILEX_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_usr0_mux, ARRAY_SIZE(s2f_usr0_mux), 0, 0x24,
 276           6, 0, 0, 0, 0, 0, 0},
 277         { AGILEX_EMAC0_CLK, "emac0_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
 278           0, 0, 0, 0, 0x94, 26, 0},
 279         { AGILEX_EMAC1_CLK, "emac1_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
 280           1, 0, 0, 0, 0x94, 27, 0},
 281         { AGILEX_EMAC2_CLK, "emac2_clk", NULL, emac_mux, ARRAY_SIZE(emac_mux), 0, 0x7C,
 282           2, 0, 0, 0, 0x94, 28, 0},
 283         { AGILEX_EMAC_PTP_CLK, "emac_ptp_clk", "emac_ptp_free_clk", NULL, 1, 0, 0x7C,
 284           3, 0, 0, 0, 0, 0, 0},
 285         { AGILEX_GPIO_DB_CLK, "gpio_db_clk", "gpio_db_free_clk", NULL, 1, 0, 0x7C,
 286           4, 0x98, 0, 16, 0, 0, 0},
 287         { AGILEX_SDMMC_CLK, "sdmmc_clk", "sdmmc_free_clk", NULL, 1, 0, 0x7C,
 288           5, 0, 0, 0, 0, 0, 4},
 289         { AGILEX_S2F_USER1_CLK, "s2f_user1_clk", "s2f_user1_free_clk", NULL, 1, 0, 0x7C,
 290           6, 0, 0, 0, 0, 0, 0},
 291         { AGILEX_PSI_REF_CLK, "psi_ref_clk", "psi_ref_free_clk", NULL, 1, 0, 0x7C,
 292           7, 0, 0, 0, 0, 0, 0},
 293         { AGILEX_USB_CLK, "usb_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
 294           8, 0, 0, 0, 0, 0, 0},
 295         { AGILEX_SPI_M_CLK, "spi_m_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
 296           9, 0, 0, 0, 0, 0, 0},
 297         { AGILEX_NAND_X_CLK, "nand_x_clk", "l4_mp_clk", NULL, 1, 0, 0x7C,
 298           10, 0, 0, 0, 0, 0, 0},
 299         { AGILEX_NAND_CLK, "nand_clk", "nand_x_clk", NULL, 1, 0, 0x7C,
 300           10, 0, 0, 0, 0, 0, 4},
 301         { AGILEX_NAND_ECC_CLK, "nand_ecc_clk", "nand_x_clk", NULL, 1, 0, 0x7C,
 302           10, 0, 0, 0, 0, 0, 4},
 303 };
 304
 305 static int agilex_clk_register_c_perip(const struct stratix10_perip_c_clock *clks,
 306                                        int nums, struct stratix10_clock_data *data)
 307 {
 308         struct clk *clk;
 309         void __iomem *base = data->base;
 310         int i;
 311
 312         for (i = 0; i < nums; i++) {
 313                 clk = s10_register_periph(&clks[i], base);
 314                 if (IS_ERR(clk)) {
 315                         pr_err("%s: failed to register clock %s\n",
 316                                __func__, clks[i].name);
 317                         continue;
 318                 }
 319                 data->clk_data.clks[clks[i].id] = clk;
 320         }
 321         return 0;
 322 }
 323
 324 static int agilex_clk_register_cnt_perip(const struct stratix10_perip_cnt_clock *clks,
 325                                          int nums, struct stratix10_clock_data *data)
 326 {
 327         struct clk *clk;
 328         void __iomem *base = data->base;
 329         int i;
 330
 331         for (i = 0; i < nums; i++) {
 332                 clk = s10_register_cnt_periph(&clks[i], base);
 333                 if (IS_ERR(clk)) {
 334                         pr_err("%s: failed to register clock %s\n",
 335                                __func__, clks[i].name);
 336                         continue;
 337                 }
 338                 data->clk_data.clks[clks[i].id] = clk;
 339         }
 340
 341         return 0;
 342 }
 343
 344 static int agilex_clk_register_gate(const struct stratix10_gate_clock *clks,                                        int nums, struct stratix10_clock_data *data)
 345 {
 346         struct clk *clk;
 347         void __iomem *base = data->base;
 348         int i;
 349
 350         for (i = 0; i < nums; i++) {
 351                 clk = s10_register_gate(&clks[i], base);
 352                 if (IS_ERR(clk)) {
 353                         pr_err("%s: failed to register clock %s\n",
 354                                __func__, clks[i].name);
 355                         continue;
 356                 }
 357                 data->clk_data.clks[clks[i].id] = clk;
 358         }
 359
 360         return 0;
 361 }
 362
 363 static int agilex_clk_register_pll(const struct stratix10_pll_clock *clks,
 364                                  int nums, struct stratix10_clock_data *data)
 365 {
 366         struct clk *clk;
 367         void __iomem *base = data->base;
 368         int i;
 369
 370         for (i = 0; i < nums; i++) {
 371                 clk = agilex_register_pll(&clks[i], base);
 372                 if (IS_ERR(clk)) {
 373                         pr_err("%s: failed to register clock %s\n",
 374                                __func__, clks[i].name);
 375                         continue;
 376                 }
 377                 data->clk_data.clks[clks[i].id] = clk;
 378         }
 379
 380         return 0;
 381 }
 382
 383 static struct stratix10_clock_data *__socfpga_agilex_clk_init(struct platform_device *pdev,
 384                                                     int nr_clks)
 385 {
 386         struct device_node *np = pdev->dev.of_node;
 387         struct device *dev = &pdev->dev;
 388         struct stratix10_clock_data *clk_data;
 389         struct clk **clk_table;
 390         struct resource *res;
 391         void __iomem *base;
 392         int ret;
 393
 394         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 395         base = devm_ioremap_resource(dev, res);
 396         if (IS_ERR(base))
 397                 return ERR_CAST(base);
 398
 399         clk_data = devm_kzalloc(dev, sizeof(*clk_data), GFP_KERNEL);
 400         if (!clk_data)
 401                 return ERR_PTR(-ENOMEM);
 402
 403         clk_data->base = base;
 404         clk_table = devm_kcalloc(dev, nr_clks, sizeof(*clk_table), GFP_KERNEL);
 405         if (!clk_table)
 406                 return ERR_PTR(-ENOMEM);
 407
 408         clk_data->clk_data.clks = clk_table;
 409         clk_data->clk_data.clk_num = nr_clks;
 410         ret = of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
 411         if (ret)
 412                 return ERR_PTR(ret);
 413
 414         return clk_data;
 415 }
 416
 417 static int agilex_clkmgr_probe(struct platform_device *pdev)
 418 {
 419         struct stratix10_clock_data *clk_data;
 420
 421         clk_data = __socfpga_agilex_clk_init(pdev, AGILEX_NUM_CLKS);
 422         if (IS_ERR(clk_data))
 423                 return PTR_ERR(clk_data);
 424
 425         agilex_clk_register_pll(agilex_pll_clks, ARRAY_SIZE(agilex_pll_clks), clk_data);
 426
 427         agilex_clk_register_c_perip(agilex_main_perip_c_clks,
 428                                  ARRAY_SIZE(agilex_main_perip_c_clks), clk_data);
 429
 430         agilex_clk_register_cnt_perip(agilex_main_perip_cnt_clks,
 431                                    ARRAY_SIZE(agilex_main_perip_cnt_clks),
 432                                    clk_data);
 433
 434         agilex_clk_register_gate(agilex_gate_clks, ARRAY_SIZE(agilex_gate_clks),
 435                               clk_data);
 436         return 0;
 437 }
 438
 439 static const struct of_device_id agilex_clkmgr_match_table[] = {
 440         { .compatible = "intel,agilex-clkmgr",
 441           .data = agilex_clkmgr_probe },
 442         { }
 443 };
 444
 445 static struct platform_driver agilex_clkmgr_driver = {
 446         .probe          = agilex_clkmgr_probe,
 447         .driver         = {
 448                 .name   = "agilex-clkmgr",
 449                 .suppress_bind_attrs = true,
 450                 .of_match_table = agilex_clkmgr_match_table,
 451         },
 452 };
 453
 454 static int __init agilex_clk_init(void)
 455 {
 456         return platform_driver_register(&agilex_clkmgr_driver);
 457 }
 458 core_initcall(agilex_clk_init);