drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "amdgpu.h"
  25 #include "mmhub_v2_0.h"
  26
  27 #include "mmhub/mmhub_2_0_0_offset.h"
  28 #include "mmhub/mmhub_2_0_0_sh_mask.h"
  29 #include "mmhub/mmhub_2_0_0_default.h"
  30 #include "navi10_enum.h"
  31
  32 #include "gc/gc_10_1_0_offset.h"
  33 #include "soc15_common.h"
  34
  35 #define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid                      0x064d
  36 #define mmMM_ATC_L2_MISC_CG_Sienna_Cichlid_BASE_IDX             0
  37 #define mmDAGB0_CNTL_MISC2_Sienna_Cichlid                       0x0070
  38 #define mmDAGB0_CNTL_MISC2_Sienna_Cichlid_BASE_IDX              0
  39
  40 static const char *mmhub_client_ids_navi1x[][2] = {
  41         [3][0] = "DCEDMC",
  42         [4][0] = "DCEVGA",
  43         [5][0] = "MP0",
  44         [6][0] = "MP1",
  45         [13][0] = "VMC",
  46         [14][0] = "HDP",
  47         [15][0] = "OSS",
  48         [16][0] = "VCNU",
  49         [17][0] = "JPEG",
  50         [18][0] = "VCN",
  51         [3][1] = "DCEDMC",
  52         [4][1] = "DCEXFC",
  53         [5][1] = "DCEVGA",
  54         [6][1] = "DCEDWB",
  55         [7][1] = "MP0",
  56         [8][1] = "MP1",
  57         [9][1] = "DBGU1",
  58         [10][1] = "DBGU0",
  59         [11][1] = "XDP",
  60         [14][1] = "HDP",
  61         [15][1] = "OSS",
  62         [16][1] = "VCNU",
  63         [17][1] = "JPEG",
  64         [18][1] = "VCN",
  65 };
  66
  67 static const char *mmhub_client_ids_sienna_cichlid[][2] = {
  68         [3][0] = "DCEDMC",
  69         [4][0] = "DCEVGA",
  70         [5][0] = "MP0",
  71         [6][0] = "MP1",
  72         [8][0] = "VMC",
  73         [9][0] = "VCNU0",
  74         [10][0] = "JPEG",
  75         [12][0] = "VCNU1",
  76         [13][0] = "VCN1",
  77         [14][0] = "HDP",
  78         [15][0] = "OSS",
  79         [32+11][0] = "VCN0",
  80         [0][1] = "DBGU0",
  81         [1][1] = "DBGU1",
  82         [2][1] = "DCEDWB",
  83         [3][1] = "DCEDMC",
  84         [4][1] = "DCEVGA",
  85         [5][1] = "MP0",
  86         [6][1] = "MP1",
  87         [7][1] = "XDP",
  88         [9][1] = "VCNU0",
  89         [10][1] = "JPEG",
  90         [11][1] = "VCN0",
  91         [12][1] = "VCNU1",
  92         [13][1] = "VCN1",
  93         [14][1] = "HDP",
  94         [15][1] = "OSS",
  95 };
  96
  97 static const char *mmhub_client_ids_beige_goby[][2] = {
  98         [3][0] = "DCEDMC",
  99         [4][0] = "DCEVGA",
 100         [5][0] = "MP0",
 101         [6][0] = "MP1",
 102         [8][0] = "VMC",
 103         [9][0] = "VCNU0",
 104         [11][0] = "VCN0",
 105         [14][0] = "HDP",
 106         [15][0] = "OSS",
 107         [0][1] = "DBGU0",
 108         [1][1] = "DBGU1",
 109         [2][1] = "DCEDWB",
 110         [3][1] = "DCEDMC",
 111         [4][1] = "DCEVGA",
 112         [5][1] = "MP0",
 113         [6][1] = "MP1",
 114         [7][1] = "XDP",
 115         [9][1] = "VCNU0",
 116         [11][1] = "VCN0",
 117         [14][1] = "HDP",
 118         [15][1] = "OSS",
 119 };
 120
 121 static uint32_t mmhub_v2_0_get_invalidate_req(unsigned int vmid,
 122                                               uint32_t flush_type)
 123 {
 124         u32 req = 0;
 125
 126         /* invalidate using legacy mode on vmid*/
 127         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
 128                             PER_VMID_INVALIDATE_REQ, 1 << vmid);
 129         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
 130         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
 131         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
 132         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
 133         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
 134         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
 135         req = REG_SET_FIELD(req, MMVM_INVALIDATE_ENG0_REQ,
 136                             CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
 137
 138         return req;
 139 }
 140
 141 static void
 142 mmhub_v2_0_print_l2_protection_fault_status(struct amdgpu_device *adev,
 143                                              uint32_t status)
 144 {
 145         uint32_t cid, rw;
 146         const char *mmhub_cid = NULL;
 147
 148         cid = REG_GET_FIELD(status,
 149                             MMVM_L2_PROTECTION_FAULT_STATUS, CID);
 150         rw = REG_GET_FIELD(status,
 151                            MMVM_L2_PROTECTION_FAULT_STATUS, RW);
 152
 153         dev_err(adev->dev,
 154                 "MMVM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
 155                 status);
 156         switch (adev->ip_versions[MMHUB_HWIP][0]) {
 157         case IP_VERSION(2, 0, 0):
 158         case IP_VERSION(2, 0, 2):
 159                 mmhub_cid = mmhub_client_ids_navi1x[cid][rw];
 160                 break;
 161         case IP_VERSION(2, 1, 0):
 162         case IP_VERSION(2, 1, 1):
 163                 mmhub_cid = mmhub_client_ids_sienna_cichlid[cid][rw];
 164                 break;
 165         case IP_VERSION(2, 1, 2):
 166                 mmhub_cid = mmhub_client_ids_beige_goby[cid][rw];
 167                 break;
 168         default:
 169                 mmhub_cid = NULL;
 170                 break;
 171         }
 172         dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
 173                 mmhub_cid ? mmhub_cid : "unknown", cid);
 174         dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
 175                 REG_GET_FIELD(status,
 176                 MMVM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
 177         dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
 178                 REG_GET_FIELD(status,
 179                 MMVM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
 180         dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
 181                 REG_GET_FIELD(status,
 182                 MMVM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
 183         dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
 184                 REG_GET_FIELD(status,
 185                 MMVM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
 186         dev_err(adev->dev, "\t RW: 0x%x\n", rw);
 187 }
 188
 189 static void mmhub_v2_0_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
 190                                 uint64_t page_table_base)
 191 {
 192         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 193
 194         WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
 195                             hub->ctx_addr_distance * vmid,
 196                             lower_32_bits(page_table_base));
 197
 198         WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
 199                             hub->ctx_addr_distance * vmid,
 200                             upper_32_bits(page_table_base));
 201 }
 202
 203 static void mmhub_v2_0_init_gart_aperture_regs(struct amdgpu_device *adev)
 204 {
 205         uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
 206
 207         mmhub_v2_0_setup_vm_pt_regs(adev, 0, pt_base);
 208
 209         WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
 210                      (u32)(adev->gmc.gart_start >> 12));
 211         WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
 212                      (u32)(adev->gmc.gart_start >> 44));
 213
 214         WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
 215                      (u32)(adev->gmc.gart_end >> 12));
 216         WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
 217                      (u32)(adev->gmc.gart_end >> 44));
 218 }
 219
 220 static void mmhub_v2_0_init_system_aperture_regs(struct amdgpu_device *adev)
 221 {
 222         uint64_t value;
 223         uint32_t tmp;
 224
 225         if (!amdgpu_sriov_vf(adev)) {
 226                 /* Program the AGP BAR */
 227                 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BASE, 0);
 228                 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
 229                 WREG32_SOC15_RLC(MMHUB, 0, mmMMMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
 230
 231                 /* Program the system aperture low logical page number. */
 232                 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 233                              min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 234                 WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 235                              max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 236         }
 237
 238         /* Set default page address. */
 239         value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
 240         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 241                      (u32)(value >> 12));
 242         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 243                      (u32)(value >> 44));
 244
 245         /* Program "protection fault". */
 246         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 247                      (u32)(adev->dummy_page_addr >> 12));
 248         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 249                      (u32)((u64)adev->dummy_page_addr >> 44));
 250
 251         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2);
 252         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL2,
 253                             ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 254         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL2, tmp);
 255 }
 256
 257 static void mmhub_v2_0_init_tlb_regs(struct amdgpu_device *adev)
 258 {
 259         uint32_t tmp;
 260
 261         /* Setup TLB control */
 262         tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
 263
 264         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 265         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 266         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 267                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 268         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 269                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 270         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 271         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 272                             MTYPE, MTYPE_UC); /* UC, uncached */
 273
 274         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
 275 }
 276
 277 static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
 278 {
 279         uint32_t tmp;
 280
 281         /* These registers are not accessible to VF-SRIOV.
 282          * The PF will program them instead.
 283          */
 284         if (amdgpu_sriov_vf(adev))
 285                 return;
 286
 287         /* Setup L2 cache */
 288         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
 289         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
 290         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 0);
 291         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL,
 292                             ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY, 1);
 293         /* XXX for emulation, Refer to closed source code.*/
 294         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
 295                             0);
 296         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
 297         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 298         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 299         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
 300
 301         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2);
 302         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 303         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 304         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL2, tmp);
 305
 306         tmp = mmMMVM_L2_CNTL3_DEFAULT;
 307         if (adev->gmc.translate_further) {
 308                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 12);
 309                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
 310                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 311         } else {
 312                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3, BANK_SELECT, 9);
 313                 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL3,
 314                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 315         }
 316         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, tmp);
 317
 318         tmp = mmMMVM_L2_CNTL4_DEFAULT;
 319         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 320         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 321         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL4, tmp);
 322
 323         tmp = mmMMVM_L2_CNTL5_DEFAULT;
 324         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL5, L2_CACHE_SMALLK_FRAGMENT_SIZE, 0);
 325         WREG32_SOC15(GC, 0, mmMMVM_L2_CNTL5, tmp);
 326 }
 327
 328 static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
 329 {
 330         uint32_t tmp;
 331
 332         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
 333         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 334         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 335         tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT0_CNTL,
 336                             RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 337         WREG32_SOC15_RLC(MMHUB, 0, mmMMVM_CONTEXT0_CNTL, tmp);
 338 }
 339
 340 static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
 341 {
 342         /* These registers are not accessible to VF-SRIOV.
 343          * The PF will program them instead.
 344          */
 345         if (amdgpu_sriov_vf(adev))
 346                 return;
 347
 348         WREG32_SOC15(MMHUB, 0,
 349                      mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 350                      0xFFFFFFFF);
 351         WREG32_SOC15(MMHUB, 0,
 352                      mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 353                      0x0000000F);
 354
 355         WREG32_SOC15(MMHUB, 0,
 356                      mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
 357         WREG32_SOC15(MMHUB, 0,
 358                      mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
 359
 360         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
 361                      0);
 362         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
 363                      0);
 364 }
 365
 366 static void mmhub_v2_0_setup_vmid_config(struct amdgpu_device *adev)
 367 {
 368         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 369         int i;
 370         uint32_t tmp;
 371
 372         for (i = 0; i <= 14; i++) {
 373                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT1_CNTL, i);
 374                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 375                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 376                                     adev->vm_manager.num_level);
 377                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 378                                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 379                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 380                                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 381                                     1);
 382                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 383                                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 384                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 385                                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 386                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 387                                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 388                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 389                                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 390                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 391                                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 392                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 393                                     PAGE_TABLE_BLOCK_SIZE,
 394                                     adev->vm_manager.block_size - 9);
 395                 /* Send no-retry XNACK on fault to suppress VM fault storm. */
 396                 tmp = REG_SET_FIELD(tmp, MMVM_CONTEXT1_CNTL,
 397                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 398                                     !adev->gmc.noretry);
 399                 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_CNTL,
 400                                     i * hub->ctx_distance, tmp);
 401                 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
 402                                     i * hub->ctx_addr_distance, 0);
 403                 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
 404                                     i * hub->ctx_addr_distance, 0);
 405                 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
 406                                     i * hub->ctx_addr_distance,
 407                                     lower_32_bits(adev->vm_manager.max_pfn - 1));
 408                 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
 409                                     i * hub->ctx_addr_distance,
 410                                     upper_32_bits(adev->vm_manager.max_pfn - 1));
 411         }
 412 }
 413
 414 static void mmhub_v2_0_program_invalidation(struct amdgpu_device *adev)
 415 {
 416         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 417         unsigned i;
 418
 419         for (i = 0; i < 18; ++i) {
 420                 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 421                                     i * hub->eng_addr_distance, 0xffffffff);
 422                 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 423                                     i * hub->eng_addr_distance, 0x1f);
 424         }
 425 }
 426
 427 static int mmhub_v2_0_gart_enable(struct amdgpu_device *adev)
 428 {
 429         /* GART Enable. */
 430         mmhub_v2_0_init_gart_aperture_regs(adev);
 431         mmhub_v2_0_init_system_aperture_regs(adev);
 432         mmhub_v2_0_init_tlb_regs(adev);
 433         mmhub_v2_0_init_cache_regs(adev);
 434
 435         mmhub_v2_0_enable_system_domain(adev);
 436         mmhub_v2_0_disable_identity_aperture(adev);
 437         mmhub_v2_0_setup_vmid_config(adev);
 438         mmhub_v2_0_program_invalidation(adev);
 439
 440         return 0;
 441 }
 442
 443 static void mmhub_v2_0_gart_disable(struct amdgpu_device *adev)
 444 {
 445         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 446         u32 tmp;
 447         u32 i;
 448
 449         /* Disable all tables */
 450         for (i = 0; i < AMDGPU_NUM_VMID; i++)
 451                 WREG32_SOC15_OFFSET_RLC(MMHUB, 0, mmMMVM_CONTEXT0_CNTL,
 452                                     i * hub->ctx_distance, 0);
 453
 454         /* Setup TLB control */
 455         tmp = RREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL);
 456         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 457         tmp = REG_SET_FIELD(tmp, MMMC_VM_MX_L1_TLB_CNTL,
 458                             ENABLE_ADVANCED_DRIVER_MODEL, 0);
 459         WREG32_SOC15(MMHUB, 0, mmMMMC_VM_MX_L1_TLB_CNTL, tmp);
 460
 461         /* Setup L2 cache */
 462         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
 463         tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0);
 464         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL, tmp);
 465         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL3, 0);
 466 }
 467
 468 /**
 469  * mmhub_v2_0_set_fault_enable_default - update GART/VM fault handling
 470  *
 471  * @adev: amdgpu_device pointer
 472  * @value: true redirects VM faults to the default page
 473  */
 474 static void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
 475 {
 476         u32 tmp;
 477
 478         /* These registers are not accessible to VF-SRIOV.
 479          * The PF will program them instead.
 480          */
 481         if (amdgpu_sriov_vf(adev))
 482                 return;
 483
 484         tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
 485         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 486                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 487         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 488                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 489         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 490                             PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 491         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 492                             PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 493         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 494                             TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 495                             value);
 496         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 497                             NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 498         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 499                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 500         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 501                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 502         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 503                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 504         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 505                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 506         tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 507                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 508         if (!value) {
 509                 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 510                                 CRASH_ON_NO_RETRY_FAULT, 1);
 511                 tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
 512                                 CRASH_ON_RETRY_FAULT, 1);
 513         }
 514         WREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL, tmp);
 515 }
 516
 517 static const struct amdgpu_vmhub_funcs mmhub_v2_0_vmhub_funcs = {
 518         .print_l2_protection_fault_status = mmhub_v2_0_print_l2_protection_fault_status,
 519         .get_invalidate_req = mmhub_v2_0_get_invalidate_req,
 520 };
 521
 522 static void mmhub_v2_0_init(struct amdgpu_device *adev)
 523 {
 524         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 525
 526         hub->ctx0_ptb_addr_lo32 =
 527                 SOC15_REG_OFFSET(MMHUB, 0,
 528                                  mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 529         hub->ctx0_ptb_addr_hi32 =
 530                 SOC15_REG_OFFSET(MMHUB, 0,
 531                                  mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 532         hub->vm_inv_eng0_sem =
 533                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_SEM);
 534         hub->vm_inv_eng0_req =
 535                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_REQ);
 536         hub->vm_inv_eng0_ack =
 537                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_INVALIDATE_ENG0_ACK);
 538         hub->vm_context0_cntl =
 539                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL);
 540         hub->vm_l2_pro_fault_status =
 541                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_STATUS);
 542         hub->vm_l2_pro_fault_cntl =
 543                 SOC15_REG_OFFSET(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
 544
 545         hub->ctx_distance = mmMMVM_CONTEXT1_CNTL - mmMMVM_CONTEXT0_CNTL;
 546         hub->ctx_addr_distance = mmMMVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
 547                 mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
 548         hub->eng_distance = mmMMVM_INVALIDATE_ENG1_REQ -
 549                 mmMMVM_INVALIDATE_ENG0_REQ;
 550         hub->eng_addr_distance = mmMMVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
 551                 mmMMVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
 552
 553         hub->vm_cntx_cntl_vm_fault = MMVM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 554                 MMVM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 555                 MMVM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 556                 MMVM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 557                 MMVM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 558                 MMVM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 559                 MMVM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
 560
 561         hub->vmhub_funcs = &mmhub_v2_0_vmhub_funcs;
 562 }
 563
 564 static void mmhub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 565                                                         bool enable)
 566 {
 567         uint32_t def, data, def1, data1;
 568
 569         if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
 570                 return;
 571
 572         switch (adev->ip_versions[MMHUB_HWIP][0]) {
 573         case IP_VERSION(2, 1, 0):
 574         case IP_VERSION(2, 1, 1):
 575         case IP_VERSION(2, 1, 2):
 576                 def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
 577                 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
 578                 break;
 579         default:
 580                 def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
 581                 def1 = data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
 582                 break;
 583         }
 584
 585         if (enable) {
 586                 data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;
 587
 588                 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 589                            DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 590                            DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 591                            DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 592                            DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 593                            DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 594
 595         } else {
 596                 data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK;
 597
 598                 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 599                           DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 600                           DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 601                           DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 602                           DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 603                           DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 604         }
 605
 606         switch (adev->ip_versions[MMHUB_HWIP][0]) {
 607         case IP_VERSION(2, 1, 0):
 608         case IP_VERSION(2, 1, 1):
 609         case IP_VERSION(2, 1, 2):
 610                 if (def != data)
 611                         WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);
 612                 if (def1 != data1)
 613                         WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid, data1);
 614                 break;
 615         default:
 616                 if (def != data)
 617                         WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
 618                 if (def1 != data1)
 619                         WREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2, data1);
 620                 break;
 621         }
 622 }
 623
 624 static void mmhub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 625                                                        bool enable)
 626 {
 627         uint32_t def, data;
 628
 629         if (!(adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
 630                 return;
 631
 632         switch (adev->ip_versions[MMHUB_HWIP][0]) {
 633         case IP_VERSION(2, 1, 0):
 634         case IP_VERSION(2, 1, 1):
 635         case IP_VERSION(2, 1, 2):
 636                 def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
 637                 break;
 638         default:
 639                 def  = data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
 640                 break;
 641         }
 642
 643         if (enable)
 644                 data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 645         else
 646                 data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 647
 648         if (def != data) {
 649                 switch (adev->ip_versions[MMHUB_HWIP][0]) {
 650                 case IP_VERSION(2, 1, 0):
 651                 case IP_VERSION(2, 1, 1):
 652                 case IP_VERSION(2, 1, 2):
 653                         WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid, data);
 654                         break;
 655                 default:
 656                         WREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG, data);
 657                         break;
 658                 }
 659         }
 660 }
 661
 662 static int mmhub_v2_0_set_clockgating(struct amdgpu_device *adev,
 663                                enum amd_clockgating_state state)
 664 {
 665         if (amdgpu_sriov_vf(adev))
 666                 return 0;
 667
 668         switch (adev->ip_versions[MMHUB_HWIP][0]) {
 669         case IP_VERSION(2, 0, 0):
 670         case IP_VERSION(2, 0, 2):
 671         case IP_VERSION(2, 1, 0):
 672         case IP_VERSION(2, 1, 1):
 673         case IP_VERSION(2, 1, 2):
 674                 mmhub_v2_0_update_medium_grain_clock_gating(adev,
 675                                 state == AMD_CG_STATE_GATE);
 676                 mmhub_v2_0_update_medium_grain_light_sleep(adev,
 677                                 state == AMD_CG_STATE_GATE);
 678                 break;
 679         default:
 680                 break;
 681         }
 682
 683         return 0;
 684 }
 685
 686 static void mmhub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
 687 {
 688         int data, data1;
 689
 690         if (amdgpu_sriov_vf(adev))
 691                 *flags = 0;
 692
 693         switch (adev->ip_versions[MMHUB_HWIP][0]) {
 694         case IP_VERSION(2, 1, 0):
 695         case IP_VERSION(2, 1, 1):
 696         case IP_VERSION(2, 1, 2):
 697                 data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG_Sienna_Cichlid);
 698                 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2_Sienna_Cichlid);
 699                 break;
 700         default:
 701                 data  = RREG32_SOC15(MMHUB, 0, mmMM_ATC_L2_MISC_CG);
 702                 data1 = RREG32_SOC15(MMHUB, 0, mmDAGB0_CNTL_MISC2);
 703                 break;
 704         }
 705
 706         /* AMD_CG_SUPPORT_MC_MGCG */
 707         if ((data & MM_ATC_L2_MISC_CG__ENABLE_MASK) &&
 708             !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 709                        DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 710                        DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 711                        DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 712                        DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 713                        DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
 714                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
 715
 716         /* AMD_CG_SUPPORT_MC_LS */
 717         if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
 718                 *flags |= AMD_CG_SUPPORT_MC_LS;
 719 }
 720
 721 const struct amdgpu_mmhub_funcs mmhub_v2_0_funcs = {
 722         .init = mmhub_v2_0_init,
 723         .gart_enable = mmhub_v2_0_gart_enable,
 724         .set_fault_enable_default = mmhub_v2_0_set_fault_enable_default,
 725         .gart_disable = mmhub_v2_0_gart_disable,
 726         .set_clockgating = mmhub_v2_0_set_clockgating,
 727         .get_clockgating = mmhub_v2_0_get_clockgating,
 728         .setup_vm_pt_regs = mmhub_v2_0_setup_vm_pt_regs,
 729 };