drivers/gpu/drm/mediatek/mtk_dsi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015 MediaTek Inc.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/component.h>
   8 #include <linux/iopoll.h>
   9 #include <linux/irq.h>
  10 #include <linux/of.h>
  11 #include <linux/of_platform.h>
  12 #include <linux/phy/phy.h>
  13 #include <linux/platform_device.h>
  14
  15 #include <video/mipi_display.h>
  16 #include <video/videomode.h>
  17
  18 #include <drm/drm_atomic_helper.h>
  19 #include <drm/drm_bridge.h>
  20 #include <drm/drm_mipi_dsi.h>
  21 #include <drm/drm_of.h>
  22 #include <drm/drm_panel.h>
  23 #include <drm/drm_print.h>
  24 #include <drm/drm_probe_helper.h>
  25 #include <drm/drm_simple_kms_helper.h>
  26
  27 #include "mtk_drm_ddp_comp.h"
  28
  29 #define DSI_START               0x00
  30
  31 #define DSI_INTEN               0x08
  32
  33 #define DSI_INTSTA              0x0c
  34 #define LPRX_RD_RDY_INT_FLAG            BIT(0)
  35 #define CMD_DONE_INT_FLAG               BIT(1)
  36 #define TE_RDY_INT_FLAG                 BIT(2)
  37 #define VM_DONE_INT_FLAG                BIT(3)
  38 #define EXT_TE_RDY_INT_FLAG             BIT(4)
  39 #define DSI_BUSY                        BIT(31)
  40
  41 #define DSI_CON_CTRL            0x10
  42 #define DSI_RESET                       BIT(0)
  43 #define DSI_EN                          BIT(1)
  44 #define DPHY_RESET                      BIT(2)
  45
  46 #define DSI_MODE_CTRL           0x14
  47 #define MODE                            (3)
  48 #define CMD_MODE                        0
  49 #define SYNC_PULSE_MODE                 1
  50 #define SYNC_EVENT_MODE                 2
  51 #define BURST_MODE                      3
  52 #define FRM_MODE                        BIT(16)
  53 #define MIX_MODE                        BIT(17)
  54
  55 #define DSI_TXRX_CTRL           0x18
  56 #define VC_NUM                          BIT(1)
  57 #define LANE_NUM                        (0xf << 2)
  58 #define DIS_EOT                         BIT(6)
  59 #define NULL_EN                         BIT(7)
  60 #define TE_FREERUN                      BIT(8)
  61 #define EXT_TE_EN                       BIT(9)
  62 #define EXT_TE_EDGE                     BIT(10)
  63 #define MAX_RTN_SIZE                    (0xf << 12)
  64 #define HSTX_CKLP_EN                    BIT(16)
  65
  66 #define DSI_PSCTRL              0x1c
  67 #define DSI_PS_WC                       0x3fff
  68 #define DSI_PS_SEL                      (3 << 16)
  69 #define PACKED_PS_16BIT_RGB565          (0 << 16)
  70 #define LOOSELY_PS_18BIT_RGB666         (1 << 16)
  71 #define PACKED_PS_18BIT_RGB666          (2 << 16)
  72 #define PACKED_PS_24BIT_RGB888          (3 << 16)
  73
  74 #define DSI_VSA_NL              0x20
  75 #define DSI_VBP_NL              0x24
  76 #define DSI_VFP_NL              0x28
  77 #define DSI_VACT_NL             0x2C
  78 #define DSI_SIZE_CON            0x38
  79 #define DSI_HSA_WC              0x50
  80 #define DSI_HBP_WC              0x54
  81 #define DSI_HFP_WC              0x58
  82
  83 #define DSI_CMDQ_SIZE           0x60
  84 #define CMDQ_SIZE                       0x3f
  85
  86 #define DSI_HSTX_CKL_WC         0x64
  87
  88 #define DSI_RX_DATA0            0x74
  89 #define DSI_RX_DATA1            0x78
  90 #define DSI_RX_DATA2            0x7c
  91 #define DSI_RX_DATA3            0x80
  92
  93 #define DSI_RACK                0x84
  94 #define RACK                            BIT(0)
  95
  96 #define DSI_PHY_LCCON           0x104
  97 #define LC_HS_TX_EN                     BIT(0)
  98 #define LC_ULPM_EN                      BIT(1)
  99 #define LC_WAKEUP_EN                    BIT(2)
 100
 101 #define DSI_PHY_LD0CON          0x108
 102 #define LD0_HS_TX_EN                    BIT(0)
 103 #define LD0_ULPM_EN                     BIT(1)
 104 #define LD0_WAKEUP_EN                   BIT(2)
 105
 106 #define DSI_PHY_TIMECON0        0x110
 107 #define LPX                             (0xff << 0)
 108 #define HS_PREP                         (0xff << 8)
 109 #define HS_ZERO                         (0xff << 16)
 110 #define HS_TRAIL                        (0xff << 24)
 111
 112 #define DSI_PHY_TIMECON1        0x114
 113 #define TA_GO                           (0xff << 0)
 114 #define TA_SURE                         (0xff << 8)
 115 #define TA_GET                          (0xff << 16)
 116 #define DA_HS_EXIT                      (0xff << 24)
 117
 118 #define DSI_PHY_TIMECON2        0x118
 119 #define CONT_DET                        (0xff << 0)
 120 #define CLK_ZERO                        (0xff << 16)
 121 #define CLK_TRAIL                       (0xff << 24)
 122
 123 #define DSI_PHY_TIMECON3        0x11c
 124 #define CLK_HS_PREP                     (0xff << 0)
 125 #define CLK_HS_POST                     (0xff << 8)
 126 #define CLK_HS_EXIT                     (0xff << 16)
 127
 128 #define DSI_VM_CMD_CON          0x130
 129 #define VM_CMD_EN                       BIT(0)
 130 #define TS_VFP_EN                       BIT(5)
 131
 132 #define DSI_SHADOW_DEBUG        0x190U
 133 #define FORCE_COMMIT                    BIT(0)
 134 #define BYPASS_SHADOW                   BIT(1)
 135
 136 #define CONFIG                          (0xff << 0)
 137 #define SHORT_PACKET                    0
 138 #define LONG_PACKET                     2
 139 #define BTA                             BIT(2)
 140 #define DATA_ID                         (0xff << 8)
 141 #define DATA_0                          (0xff << 16)
 142 #define DATA_1                          (0xff << 24)
 143
 144 #define NS_TO_CYCLE(n, c)    ((n) / (c) + (((n) % (c)) ? 1 : 0))
 145
 146 #define MTK_DSI_HOST_IS_READ(type) \
 147         ((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
 148         (type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
 149         (type == MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM) || \
 150         (type == MIPI_DSI_DCS_READ))
 151
 152 struct mtk_phy_timing {
 153         u32 lpx;
 154         u32 da_hs_prepare;
 155         u32 da_hs_zero;
 156         u32 da_hs_trail;
 157
 158         u32 ta_go;
 159         u32 ta_sure;
 160         u32 ta_get;
 161         u32 da_hs_exit;
 162
 163         u32 clk_hs_zero;
 164         u32 clk_hs_trail;
 165
 166         u32 clk_hs_prepare;
 167         u32 clk_hs_post;
 168         u32 clk_hs_exit;
 169 };
 170
 171 struct phy;
 172
 173 struct mtk_dsi_driver_data {
 174         const u32 reg_cmdq_off;
 175         bool has_shadow_ctl;
 176         bool has_size_ctl;
 177 };
 178
 179 struct mtk_dsi {
 180         struct mtk_ddp_comp ddp_comp;
 181         struct device *dev;
 182         struct mipi_dsi_host host;
 183         struct drm_encoder encoder;
 184         struct drm_connector conn;
 185         struct drm_panel *panel;
 186         struct drm_bridge *bridge;
 187         struct phy *phy;
 188
 189         void __iomem *regs;
 190
 191         struct clk *engine_clk;
 192         struct clk *digital_clk;
 193         struct clk *hs_clk;
 194
 195         u32 data_rate;
 196
 197         unsigned long mode_flags;
 198         enum mipi_dsi_pixel_format format;
 199         unsigned int lanes;
 200         struct videomode vm;
 201         struct mtk_phy_timing phy_timing;
 202         int refcount;
 203         bool enabled;
 204         u32 irq_data;
 205         wait_queue_head_t irq_wait_queue;
 206         const struct mtk_dsi_driver_data *driver_data;
 207 };
 208
 209 static inline struct mtk_dsi *encoder_to_dsi(struct drm_encoder *e)
 210 {
 211         return container_of(e, struct mtk_dsi, encoder);
 212 }
 213
 214 static inline struct mtk_dsi *connector_to_dsi(struct drm_connector *c)
 215 {
 216         return container_of(c, struct mtk_dsi, conn);
 217 }
 218
 219 static inline struct mtk_dsi *host_to_dsi(struct mipi_dsi_host *h)
 220 {
 221         return container_of(h, struct mtk_dsi, host);
 222 }
 223
 224 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data)
 225 {
 226         u32 temp = readl(dsi->regs + offset);
 227
 228         writel((temp & ~mask) | (data & mask), dsi->regs + offset);
 229 }
 230
 231 static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
 232 {
 233         u32 timcon0, timcon1, timcon2, timcon3;
 234         u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, 1000000);
 235         struct mtk_phy_timing *timing = &dsi->phy_timing;
 236
 237         timing->lpx = (60 * data_rate_mhz / (8 * 1000)) + 1;
 238         timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;
 239         timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -
 240                              timing->da_hs_prepare;
 241         timing->da_hs_trail = timing->da_hs_prepare + 1;
 242
 243         timing->ta_go = 4 * timing->lpx - 2;
 244         timing->ta_sure = timing->lpx + 2;
 245         timing->ta_get = 4 * timing->lpx;
 246         timing->da_hs_exit = 2 * timing->lpx + 1;
 247
 248         timing->clk_hs_prepare = 70 * data_rate_mhz / (8 * 1000);
 249         timing->clk_hs_post = timing->clk_hs_prepare + 8;
 250         timing->clk_hs_trail = timing->clk_hs_prepare;
 251         timing->clk_hs_zero = timing->clk_hs_trail * 4;
 252         timing->clk_hs_exit = 2 * timing->clk_hs_trail;
 253
 254         timcon0 = timing->lpx | timing->da_hs_prepare << 8 |
 255                   timing->da_hs_zero << 16 | timing->da_hs_trail << 24;
 256         timcon1 = timing->ta_go | timing->ta_sure << 8 |
 257                   timing->ta_get << 16 | timing->da_hs_exit << 24;
 258         timcon2 = 1 << 8 | timing->clk_hs_zero << 16 |
 259                   timing->clk_hs_trail << 24;
 260         timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 |
 261                   timing->clk_hs_exit << 16;
 262
 263         writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
 264         writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
 265         writel(timcon2, dsi->regs + DSI_PHY_TIMECON2);
 266         writel(timcon3, dsi->regs + DSI_PHY_TIMECON3);
 267 }
 268
 269 static void mtk_dsi_enable(struct mtk_dsi *dsi)
 270 {
 271         mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN);
 272 }
 273
 274 static void mtk_dsi_disable(struct mtk_dsi *dsi)
 275 {
 276         mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);
 277 }
 278
 279 static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
 280 {
 281         mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
 282         mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
 283 }
 284
 285 static void mtk_dsi_reset_dphy(struct mtk_dsi *dsi)
 286 {
 287         mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, DPHY_RESET);
 288         mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, 0);
 289 }
 290
 291 static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
 292 {
 293         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
 294         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
 295 }
 296
 297 static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
 298 {
 299         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
 300         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN);
 301         mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0);
 302 }
 303
 304 static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
 305 {
 306         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0);
 307         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
 308 }
 309
 310 static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
 311 {
 312         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
 313         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN);
 314         mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0);
 315 }
 316
 317 static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi)
 318 {
 319         u32 tmp_reg1;
 320
 321         tmp_reg1 = readl(dsi->regs + DSI_PHY_LCCON);
 322         return ((tmp_reg1 & LC_HS_TX_EN) == 1) ? true : false;
 323 }
 324
 325 static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
 326 {
 327         if (enter && !mtk_dsi_clk_hs_state(dsi))
 328                 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN);
 329         else if (!enter && mtk_dsi_clk_hs_state(dsi))
 330                 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
 331 }
 332
 333 static void mtk_dsi_set_mode(struct mtk_dsi *dsi)
 334 {
 335         u32 vid_mode = CMD_MODE;
 336
 337         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
 338                 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
 339                         vid_mode = BURST_MODE;
 340                 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 341                         vid_mode = SYNC_PULSE_MODE;
 342                 else
 343                         vid_mode = SYNC_EVENT_MODE;
 344         }
 345
 346         writel(vid_mode, dsi->regs + DSI_MODE_CTRL);
 347 }
 348
 349 static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi)
 350 {
 351         mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN);
 352         mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN);
 353 }
 354
 355 static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi)
 356 {
 357         struct videomode *vm = &dsi->vm;
 358         u32 dsi_buf_bpp, ps_wc;
 359         u32 ps_bpp_mode;
 360
 361         if (dsi->format == MIPI_DSI_FMT_RGB565)
 362                 dsi_buf_bpp = 2;
 363         else
 364                 dsi_buf_bpp = 3;
 365
 366         ps_wc = vm->hactive * dsi_buf_bpp;
 367         ps_bpp_mode = ps_wc;
 368
 369         switch (dsi->format) {
 370         case MIPI_DSI_FMT_RGB888:
 371                 ps_bpp_mode |= PACKED_PS_24BIT_RGB888;
 372                 break;
 373         case MIPI_DSI_FMT_RGB666:
 374                 ps_bpp_mode |= PACKED_PS_18BIT_RGB666;
 375                 break;
 376         case MIPI_DSI_FMT_RGB666_PACKED:
 377                 ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666;
 378                 break;
 379         case MIPI_DSI_FMT_RGB565:
 380                 ps_bpp_mode |= PACKED_PS_16BIT_RGB565;
 381                 break;
 382         }
 383
 384         writel(vm->vactive, dsi->regs + DSI_VACT_NL);
 385         writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL);
 386         writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
 387 }
 388
 389 static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
 390 {
 391         u32 tmp_reg;
 392
 393         switch (dsi->lanes) {
 394         case 1:
 395                 tmp_reg = 1 << 2;
 396                 break;
 397         case 2:
 398                 tmp_reg = 3 << 2;
 399                 break;
 400         case 3:
 401                 tmp_reg = 7 << 2;
 402                 break;
 403         case 4:
 404                 tmp_reg = 0xf << 2;
 405                 break;
 406         default:
 407                 tmp_reg = 0xf << 2;
 408                 break;
 409         }
 410
 411         tmp_reg |= (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6;
 412         tmp_reg |= (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3;
 413
 414         writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL);
 415 }
 416
 417 static void mtk_dsi_ps_control(struct mtk_dsi *dsi)
 418 {
 419         u32 dsi_tmp_buf_bpp;
 420         u32 tmp_reg;
 421
 422         switch (dsi->format) {
 423         case MIPI_DSI_FMT_RGB888:
 424                 tmp_reg = PACKED_PS_24BIT_RGB888;
 425                 dsi_tmp_buf_bpp = 3;
 426                 break;
 427         case MIPI_DSI_FMT_RGB666:
 428                 tmp_reg = LOOSELY_PS_18BIT_RGB666;
 429                 dsi_tmp_buf_bpp = 3;
 430                 break;
 431         case MIPI_DSI_FMT_RGB666_PACKED:
 432                 tmp_reg = PACKED_PS_18BIT_RGB666;
 433                 dsi_tmp_buf_bpp = 3;
 434                 break;
 435         case MIPI_DSI_FMT_RGB565:
 436                 tmp_reg = PACKED_PS_16BIT_RGB565;
 437                 dsi_tmp_buf_bpp = 2;
 438                 break;
 439         default:
 440                 tmp_reg = PACKED_PS_24BIT_RGB888;
 441                 dsi_tmp_buf_bpp = 3;
 442                 break;
 443         }
 444
 445         tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC;
 446         writel(tmp_reg, dsi->regs + DSI_PSCTRL);
 447 }
 448
 449 static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
 450 {
 451         u32 horizontal_sync_active_byte;
 452         u32 horizontal_backporch_byte;
 453         u32 horizontal_frontporch_byte;
 454         u32 dsi_tmp_buf_bpp, data_phy_cycles;
 455         struct mtk_phy_timing *timing = &dsi->phy_timing;
 456
 457         struct videomode *vm = &dsi->vm;
 458
 459         if (dsi->format == MIPI_DSI_FMT_RGB565)
 460                 dsi_tmp_buf_bpp = 2;
 461         else
 462                 dsi_tmp_buf_bpp = 3;
 463
 464         writel(vm->vsync_len, dsi->regs + DSI_VSA_NL);
 465         writel(vm->vback_porch, dsi->regs + DSI_VBP_NL);
 466         writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
 467         writel(vm->vactive, dsi->regs + DSI_VACT_NL);
 468
 469         if (dsi->driver_data->has_size_ctl)
 470                 writel(vm->vactive << 16 | vm->hactive,
 471                        dsi->regs + DSI_SIZE_CON);
 472
 473         horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10);
 474
 475         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
 476                 horizontal_backporch_byte =
 477                         (vm->hback_porch * dsi_tmp_buf_bpp - 10);
 478         else
 479                 horizontal_backporch_byte = ((vm->hback_porch + vm->hsync_len) *
 480                         dsi_tmp_buf_bpp - 10);
 481
 482         data_phy_cycles = timing->lpx + timing->da_hs_prepare +
 483                           timing->da_hs_zero + timing->da_hs_exit + 3;
 484
 485         if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
 486                 if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
 487                     data_phy_cycles * dsi->lanes + 18) {
 488                         horizontal_frontporch_byte =
 489                                 vm->hfront_porch * dsi_tmp_buf_bpp -
 490                                 (data_phy_cycles * dsi->lanes + 18) *
 491                                 vm->hfront_porch /
 492                                 (vm->hfront_porch + vm->hback_porch);
 493
 494                         horizontal_backporch_byte =
 495                                 horizontal_backporch_byte -
 496                                 (data_phy_cycles * dsi->lanes + 18) *
 497                                 vm->hback_porch /
 498                                 (vm->hfront_porch + vm->hback_porch);
 499                 } else {
 500                         DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
 501                         horizontal_frontporch_byte = vm->hfront_porch *
 502                                                      dsi_tmp_buf_bpp;
 503                 }
 504         } else {
 505                 if ((vm->hfront_porch + vm->hback_porch) * dsi_tmp_buf_bpp >
 506                     data_phy_cycles * dsi->lanes + 12) {
 507                         horizontal_frontporch_byte =
 508                                 vm->hfront_porch * dsi_tmp_buf_bpp -
 509                                 (data_phy_cycles * dsi->lanes + 12) *
 510                                 vm->hfront_porch /
 511                                 (vm->hfront_porch + vm->hback_porch);
 512                         horizontal_backporch_byte = horizontal_backporch_byte -
 513                                 (data_phy_cycles * dsi->lanes + 12) *
 514                                 vm->hback_porch /
 515                                 (vm->hfront_porch + vm->hback_porch);
 516                 } else {
 517                         DRM_WARN("HFP less than d-phy, FPS will under 60Hz\n");
 518                         horizontal_frontporch_byte = vm->hfront_porch *
 519                                                      dsi_tmp_buf_bpp;
 520                 }
 521         }
 522
 523         writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
 524         writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
 525         writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
 526
 527         mtk_dsi_ps_control(dsi);
 528 }
 529
 530 static void mtk_dsi_start(struct mtk_dsi *dsi)
 531 {
 532         writel(0, dsi->regs + DSI_START);
 533         writel(1, dsi->regs + DSI_START);
 534 }
 535
 536 static void mtk_dsi_stop(struct mtk_dsi *dsi)
 537 {
 538         writel(0, dsi->regs + DSI_START);
 539 }
 540
 541 static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi)
 542 {
 543         writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL);
 544 }
 545
 546 static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)
 547 {
 548         u32 inten = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
 549
 550         writel(inten, dsi->regs + DSI_INTEN);
 551 }
 552
 553 static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit)
 554 {
 555         dsi->irq_data |= irq_bit;
 556 }
 557
 558 static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
 559 {
 560         dsi->irq_data &= ~irq_bit;
 561 }
 562
 563 static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
 564                                      unsigned int timeout)
 565 {
 566         s32 ret = 0;
 567         unsigned long jiffies = msecs_to_jiffies(timeout);
 568
 569         ret = wait_event_interruptible_timeout(dsi->irq_wait_queue,
 570                                                dsi->irq_data & irq_flag,
 571                                                jiffies);
 572         if (ret == 0) {
 573                 DRM_WARN("Wait DSI IRQ(0x%08x) Timeout\n", irq_flag);
 574
 575                 mtk_dsi_enable(dsi);
 576                 mtk_dsi_reset_engine(dsi);
 577         }
 578
 579         return ret;
 580 }
 581
 582 static irqreturn_t mtk_dsi_irq(int irq, void *dev_id)
 583 {
 584         struct mtk_dsi *dsi = dev_id;
 585         u32 status, tmp;
 586         u32 flag = LPRX_RD_RDY_INT_FLAG | CMD_DONE_INT_FLAG | VM_DONE_INT_FLAG;
 587
 588         status = readl(dsi->regs + DSI_INTSTA) & flag;
 589
 590         if (status) {
 591                 do {
 592                         mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);
 593                         tmp = readl(dsi->regs + DSI_INTSTA);
 594                 } while (tmp & DSI_BUSY);
 595
 596                 mtk_dsi_mask(dsi, DSI_INTSTA, status, 0);
 597                 mtk_dsi_irq_data_set(dsi, status);
 598                 wake_up_interruptible(&dsi->irq_wait_queue);
 599         }
 600
 601         return IRQ_HANDLED;
 602 }
 603
 604 static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t)
 605 {
 606         mtk_dsi_irq_data_clear(dsi, irq_flag);
 607         mtk_dsi_set_cmd_mode(dsi);
 608
 609         if (!mtk_dsi_wait_for_irq_done(dsi, irq_flag, t)) {
 610                 DRM_ERROR("failed to switch cmd mode\n");
 611                 return -ETIME;
 612         } else {
 613                 return 0;
 614         }
 615 }
 616
 617 static int mtk_dsi_poweron(struct mtk_dsi *dsi)
 618 {
 619         struct device *dev = dsi->host.dev;
 620         int ret;
 621         u32 bit_per_pixel;
 622
 623         if (++dsi->refcount != 1)
 624                 return 0;
 625
 626         switch (dsi->format) {
 627         case MIPI_DSI_FMT_RGB565:
 628                 bit_per_pixel = 16;
 629                 break;
 630         case MIPI_DSI_FMT_RGB666_PACKED:
 631                 bit_per_pixel = 18;
 632                 break;
 633         case MIPI_DSI_FMT_RGB666:
 634         case MIPI_DSI_FMT_RGB888:
 635         default:
 636                 bit_per_pixel = 24;
 637                 break;
 638         }
 639
 640         dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,
 641                                           dsi->lanes);
 642
 643         ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
 644         if (ret < 0) {
 645                 dev_err(dev, "Failed to set data rate: %d\n", ret);
 646                 goto err_refcount;
 647         }
 648
 649         phy_power_on(dsi->phy);
 650
 651         ret = clk_prepare_enable(dsi->engine_clk);
 652         if (ret < 0) {
 653                 dev_err(dev, "Failed to enable engine clock: %d\n", ret);
 654                 goto err_phy_power_off;
 655         }
 656
 657         ret = clk_prepare_enable(dsi->digital_clk);
 658         if (ret < 0) {
 659                 dev_err(dev, "Failed to enable digital clock: %d\n", ret);
 660                 goto err_disable_engine_clk;
 661         }
 662
 663         mtk_dsi_enable(dsi);
 664
 665         if (dsi->driver_data->has_shadow_ctl)
 666                 writel(FORCE_COMMIT | BYPASS_SHADOW,
 667                        dsi->regs + DSI_SHADOW_DEBUG);
 668
 669         mtk_dsi_reset_engine(dsi);
 670         mtk_dsi_phy_timconfig(dsi);
 671
 672         mtk_dsi_rxtx_control(dsi);
 673         usleep_range(30, 100);
 674         mtk_dsi_reset_dphy(dsi);
 675         mtk_dsi_ps_control_vact(dsi);
 676         mtk_dsi_set_vm_cmd(dsi);
 677         mtk_dsi_config_vdo_timing(dsi);
 678         mtk_dsi_set_interrupt_enable(dsi);
 679
 680         mtk_dsi_clk_ulp_mode_leave(dsi);
 681         mtk_dsi_lane0_ulp_mode_leave(dsi);
 682         mtk_dsi_clk_hs_mode(dsi, 0);
 683
 684         if (dsi->panel) {
 685                 if (drm_panel_prepare(dsi->panel)) {
 686                         DRM_ERROR("failed to prepare the panel\n");
 687                         goto err_disable_digital_clk;
 688                 }
 689         }
 690
 691         return 0;
 692 err_disable_digital_clk:
 693         clk_disable_unprepare(dsi->digital_clk);
 694 err_disable_engine_clk:
 695         clk_disable_unprepare(dsi->engine_clk);
 696 err_phy_power_off:
 697         phy_power_off(dsi->phy);
 698 err_refcount:
 699         dsi->refcount--;
 700         return ret;
 701 }
 702
 703 static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
 704 {
 705         if (WARN_ON(dsi->refcount == 0))
 706                 return;
 707
 708         if (--dsi->refcount != 0)
 709                 return;
 710
 711         /*
 712          * mtk_dsi_stop() and mtk_dsi_start() is asymmetric, since
 713          * mtk_dsi_stop() should be called after mtk_drm_crtc_atomic_disable(),
 714          * which needs irq for vblank, and mtk_dsi_stop() will disable irq.
 715          * mtk_dsi_start() needs to be called in mtk_output_dsi_enable(),
 716          * after dsi is fully set.
 717          */
 718         mtk_dsi_stop(dsi);
 719
 720         if (!mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500)) {
 721                 if (dsi->panel) {
 722                         if (drm_panel_unprepare(dsi->panel)) {
 723                                 DRM_ERROR("failed to unprepare the panel\n");
 724                                 return;
 725                         }
 726                 }
 727         }
 728
 729         mtk_dsi_reset_engine(dsi);
 730         mtk_dsi_lane0_ulp_mode_enter(dsi);
 731         mtk_dsi_clk_ulp_mode_enter(dsi);
 732
 733         mtk_dsi_disable(dsi);
 734
 735         clk_disable_unprepare(dsi->engine_clk);
 736         clk_disable_unprepare(dsi->digital_clk);
 737
 738         phy_power_off(dsi->phy);
 739 }
 740
 741 static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
 742 {
 743         int ret;
 744
 745         if (dsi->enabled)
 746                 return;
 747
 748         ret = mtk_dsi_poweron(dsi);
 749         if (ret < 0) {
 750                 DRM_ERROR("failed to power on dsi\n");
 751                 return;
 752         }
 753
 754         mtk_dsi_set_mode(dsi);
 755         mtk_dsi_clk_hs_mode(dsi, 1);
 756
 757         mtk_dsi_start(dsi);
 758
 759         if (dsi->panel) {
 760                 if (drm_panel_enable(dsi->panel)) {
 761                         DRM_ERROR("failed to enable the panel\n");
 762                         goto err_dsi_power_off;
 763                 }
 764         }
 765
 766         dsi->enabled = true;
 767
 768         return;
 769 err_dsi_power_off:
 770         mtk_dsi_stop(dsi);
 771         mtk_dsi_poweroff(dsi);
 772 }
 773
 774 static void mtk_output_dsi_disable(struct mtk_dsi *dsi)
 775 {
 776         if (!dsi->enabled)
 777                 return;
 778
 779         if (dsi->panel) {
 780                 if (drm_panel_disable(dsi->panel)) {
 781                         DRM_ERROR("failed to disable the panel\n");
 782                         return;
 783                 }
 784         }
 785
 786         mtk_dsi_poweroff(dsi);
 787
 788         dsi->enabled = false;
 789 }
 790
 791 static bool mtk_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
 792                                        const struct drm_display_mode *mode,
 793                                        struct drm_display_mode *adjusted_mode)
 794 {
 795         return true;
 796 }
 797
 798 static void mtk_dsi_encoder_mode_set(struct drm_encoder *encoder,
 799                                      struct drm_display_mode *mode,
 800                                      struct drm_display_mode *adjusted)
 801 {
 802         struct mtk_dsi *dsi = encoder_to_dsi(encoder);
 803
 804         drm_display_mode_to_videomode(adjusted, &dsi->vm);
 805 }
 806
 807 static void mtk_dsi_encoder_disable(struct drm_encoder *encoder)
 808 {
 809         struct mtk_dsi *dsi = encoder_to_dsi(encoder);
 810
 811         mtk_output_dsi_disable(dsi);
 812 }
 813
 814 static void mtk_dsi_encoder_enable(struct drm_encoder *encoder)
 815 {
 816         struct mtk_dsi *dsi = encoder_to_dsi(encoder);
 817
 818         mtk_output_dsi_enable(dsi);
 819 }
 820
 821 static int mtk_dsi_connector_get_modes(struct drm_connector *connector)
 822 {
 823         struct mtk_dsi *dsi = connector_to_dsi(connector);
 824
 825         return drm_panel_get_modes(dsi->panel, connector);
 826 }
 827
 828 static const struct drm_encoder_helper_funcs mtk_dsi_encoder_helper_funcs = {
 829         .mode_fixup = mtk_dsi_encoder_mode_fixup,
 830         .mode_set = mtk_dsi_encoder_mode_set,
 831         .disable = mtk_dsi_encoder_disable,
 832         .enable = mtk_dsi_encoder_enable,
 833 };
 834
 835 static const struct drm_connector_funcs mtk_dsi_connector_funcs = {
 836         .fill_modes = drm_helper_probe_single_connector_modes,
 837         .destroy = drm_connector_cleanup,
 838         .reset = drm_atomic_helper_connector_reset,
 839         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 840         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 841 };
 842
 843 static const struct drm_connector_helper_funcs
 844         mtk_dsi_connector_helper_funcs = {
 845         .get_modes = mtk_dsi_connector_get_modes,
 846 };
 847
 848 static int mtk_dsi_create_connector(struct drm_device *drm, struct mtk_dsi *dsi)
 849 {
 850         int ret;
 851
 852         ret = drm_connector_init(drm, &dsi->conn, &mtk_dsi_connector_funcs,
 853                                  DRM_MODE_CONNECTOR_DSI);
 854         if (ret) {
 855                 DRM_ERROR("Failed to connector init to drm\n");
 856                 return ret;
 857         }
 858
 859         drm_connector_helper_add(&dsi->conn, &mtk_dsi_connector_helper_funcs);
 860
 861         dsi->conn.dpms = DRM_MODE_DPMS_OFF;
 862         drm_connector_attach_encoder(&dsi->conn, &dsi->encoder);
 863
 864         if (dsi->panel) {
 865                 ret = drm_panel_attach(dsi->panel, &dsi->conn);
 866                 if (ret) {
 867                         DRM_ERROR("Failed to attach panel to drm\n");
 868                         goto err_connector_cleanup;
 869                 }
 870         }
 871
 872         return 0;
 873
 874 err_connector_cleanup:
 875         drm_connector_cleanup(&dsi->conn);
 876         return ret;
 877 }
 878
 879 static int mtk_dsi_create_conn_enc(struct drm_device *drm, struct mtk_dsi *dsi)
 880 {
 881         int ret;
 882
 883         ret = drm_simple_encoder_init(drm, &dsi->encoder,
 884                                       DRM_MODE_ENCODER_DSI);
 885         if (ret) {
 886                 DRM_ERROR("Failed to encoder init to drm\n");
 887                 return ret;
 888         }
 889         drm_encoder_helper_add(&dsi->encoder, &mtk_dsi_encoder_helper_funcs);
 890
 891         /*
 892          * Currently display data paths are statically assigned to a crtc each.
 893          * crtc 0 is OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0
 894          */
 895         dsi->encoder.possible_crtcs = 1;
 896
 897         /* If there's a bridge, attach to it and let it create the connector */
 898         if (dsi->bridge) {
 899                 ret = drm_bridge_attach(&dsi->encoder, dsi->bridge, NULL, 0);
 900                 if (ret) {
 901                         DRM_ERROR("Failed to attach bridge to drm\n");
 902                         goto err_encoder_cleanup;
 903                 }
 904         } else {
 905                 /* Otherwise create our own connector and attach to a panel */
 906                 ret = mtk_dsi_create_connector(drm, dsi);
 907                 if (ret)
 908                         goto err_encoder_cleanup;
 909         }
 910
 911         return 0;
 912
 913 err_encoder_cleanup:
 914         drm_encoder_cleanup(&dsi->encoder);
 915         return ret;
 916 }
 917
 918 static void mtk_dsi_destroy_conn_enc(struct mtk_dsi *dsi)
 919 {
 920         drm_encoder_cleanup(&dsi->encoder);
 921         /* Skip connector cleanup if creation was delegated to the bridge */
 922         if (dsi->conn.dev)
 923                 drm_connector_cleanup(&dsi->conn);
 924         if (dsi->panel)
 925                 drm_panel_detach(dsi->panel);
 926 }
 927
 928 static void mtk_dsi_ddp_start(struct mtk_ddp_comp *comp)
 929 {
 930         struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
 931
 932         mtk_dsi_poweron(dsi);
 933 }
 934
 935 static void mtk_dsi_ddp_stop(struct mtk_ddp_comp *comp)
 936 {
 937         struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
 938
 939         mtk_dsi_poweroff(dsi);
 940 }
 941
 942 static const struct mtk_ddp_comp_funcs mtk_dsi_funcs = {
 943         .start = mtk_dsi_ddp_start,
 944         .stop = mtk_dsi_ddp_stop,
 945 };
 946
 947 static int mtk_dsi_host_attach(struct mipi_dsi_host *host,
 948                                struct mipi_dsi_device *device)
 949 {
 950         struct mtk_dsi *dsi = host_to_dsi(host);
 951
 952         dsi->lanes = device->lanes;
 953         dsi->format = device->format;
 954         dsi->mode_flags = device->mode_flags;
 955
 956         if (dsi->conn.dev)
 957                 drm_helper_hpd_irq_event(dsi->conn.dev);
 958
 959         return 0;
 960 }
 961
 962 static int mtk_dsi_host_detach(struct mipi_dsi_host *host,
 963                                struct mipi_dsi_device *device)
 964 {
 965         struct mtk_dsi *dsi = host_to_dsi(host);
 966
 967         if (dsi->conn.dev)
 968                 drm_helper_hpd_irq_event(dsi->conn.dev);
 969
 970         return 0;
 971 }
 972
 973 static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
 974 {
 975         int ret;
 976         u32 val;
 977
 978         ret = readl_poll_timeout(dsi->regs + DSI_INTSTA, val, !(val & DSI_BUSY),
 979                                  4, 2000000);
 980         if (ret) {
 981                 DRM_WARN("polling dsi wait not busy timeout!\n");
 982
 983                 mtk_dsi_enable(dsi);
 984                 mtk_dsi_reset_engine(dsi);
 985         }
 986 }
 987
 988 static u32 mtk_dsi_recv_cnt(u8 type, u8 *read_data)
 989 {
 990         switch (type) {
 991         case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
 992         case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
 993                 return 1;
 994         case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
 995         case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
 996                 return 2;
 997         case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
 998         case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
 999                 return read_data[1] + read_data[2] * 16;
1000         case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1001                 DRM_INFO("type is 0x02, try again\n");
1002                 break;
1003         default:
1004                 DRM_INFO("type(0x%x) not recognized\n", type);
1005                 break;
1006         }
1007
1008         return 0;
1009 }
1010
1011 static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
1012 {
1013         const char *tx_buf = msg->tx_buf;
1014         u8 config, cmdq_size, cmdq_off, type = msg->type;
1015         u32 reg_val, cmdq_mask, i;
1016         u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off;
1017
1018         if (MTK_DSI_HOST_IS_READ(type))
1019                 config = BTA;
1020         else
1021                 config = (msg->tx_len > 2) ? LONG_PACKET : SHORT_PACKET;
1022
1023         if (msg->tx_len > 2) {
1024                 cmdq_size = 1 + (msg->tx_len + 3) / 4;
1025                 cmdq_off = 4;
1026                 cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1;
1027                 reg_val = (msg->tx_len << 16) | (type << 8) | config;
1028         } else {
1029                 cmdq_size = 1;
1030                 cmdq_off = 2;
1031                 cmdq_mask = CONFIG | DATA_ID;
1032                 reg_val = (type << 8) | config;
1033         }
1034
1035         for (i = 0; i < msg->tx_len; i++)
1036                 mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U),
1037                              (0xffUL << (((i + cmdq_off) & 3U) * 8U)),
1038                              tx_buf[i] << (((i + cmdq_off) & 3U) * 8U));
1039
1040         mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
1041         mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
1042 }
1043
1044 static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi,
1045                                      const struct mipi_dsi_msg *msg, u8 flag)
1046 {
1047         mtk_dsi_wait_for_idle(dsi);
1048         mtk_dsi_irq_data_clear(dsi, flag);
1049         mtk_dsi_cmdq(dsi, msg);
1050         mtk_dsi_start(dsi);
1051
1052         if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000))
1053                 return -ETIME;
1054         else
1055                 return 0;
1056 }
1057
1058 static ssize_t mtk_dsi_host_transfer(struct mipi_dsi_host *host,
1059                                      const struct mipi_dsi_msg *msg)
1060 {
1061         struct mtk_dsi *dsi = host_to_dsi(host);
1062         u32 recv_cnt, i;
1063         u8 read_data[16];
1064         void *src_addr;
1065         u8 irq_flag = CMD_DONE_INT_FLAG;
1066
1067         if (readl(dsi->regs + DSI_MODE_CTRL) & MODE) {
1068                 DRM_ERROR("dsi engine is not command mode\n");
1069                 return -EINVAL;
1070         }
1071
1072         if (MTK_DSI_HOST_IS_READ(msg->type))
1073                 irq_flag |= LPRX_RD_RDY_INT_FLAG;
1074
1075         if (mtk_dsi_host_send_cmd(dsi, msg, irq_flag) < 0)
1076                 return -ETIME;
1077
1078         if (!MTK_DSI_HOST_IS_READ(msg->type))
1079                 return 0;
1080
1081         if (!msg->rx_buf) {
1082                 DRM_ERROR("dsi receive buffer size may be NULL\n");
1083                 return -EINVAL;
1084         }
1085
1086         for (i = 0; i < 16; i++)
1087                 *(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i);
1088
1089         recv_cnt = mtk_dsi_recv_cnt(read_data[0], read_data);
1090
1091         if (recv_cnt > 2)
1092                 src_addr = &read_data[4];
1093         else
1094                 src_addr = &read_data[1];
1095
1096         if (recv_cnt > 10)
1097                 recv_cnt = 10;
1098
1099         if (recv_cnt > msg->rx_len)
1100                 recv_cnt = msg->rx_len;
1101
1102         if (recv_cnt)
1103                 memcpy(msg->rx_buf, src_addr, recv_cnt);
1104
1105         DRM_INFO("dsi get %d byte data from the panel address(0x%x)\n",
1106                  recv_cnt, *((u8 *)(msg->tx_buf)));
1107
1108         return recv_cnt;
1109 }
1110
1111 static const struct mipi_dsi_host_ops mtk_dsi_ops = {
1112         .attach = mtk_dsi_host_attach,
1113         .detach = mtk_dsi_host_detach,
1114         .transfer = mtk_dsi_host_transfer,
1115 };
1116
1117 static int mtk_dsi_bind(struct device *dev, struct device *master, void *data)
1118 {
1119         int ret;
1120         struct drm_device *drm = data;
1121         struct mtk_dsi *dsi = dev_get_drvdata(dev);
1122
1123         ret = mtk_ddp_comp_register(drm, &dsi->ddp_comp);
1124         if (ret < 0) {
1125                 dev_err(dev, "Failed to register component %pOF: %d\n",
1126                         dev->of_node, ret);
1127                 return ret;
1128         }
1129
1130         ret = mtk_dsi_create_conn_enc(drm, dsi);
1131         if (ret) {
1132                 DRM_ERROR("Encoder create failed with %d\n", ret);
1133                 goto err_unregister;
1134         }
1135
1136         return 0;
1137
1138 err_unregister:
1139         mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
1140         return ret;
1141 }
1142
1143 static void mtk_dsi_unbind(struct device *dev, struct device *master,
1144                            void *data)
1145 {
1146         struct drm_device *drm = data;
1147         struct mtk_dsi *dsi = dev_get_drvdata(dev);
1148
1149         mtk_dsi_destroy_conn_enc(dsi);
1150         mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
1151 }
1152
1153 static const struct component_ops mtk_dsi_component_ops = {
1154         .bind = mtk_dsi_bind,
1155         .unbind = mtk_dsi_unbind,
1156 };
1157
1158 static int mtk_dsi_probe(struct platform_device *pdev)
1159 {
1160         struct mtk_dsi *dsi;
1161         struct device *dev = &pdev->dev;
1162         struct resource *regs;
1163         int irq_num;
1164         int comp_id;
1165         int ret;
1166
1167         dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1168         if (!dsi)
1169                 return -ENOMEM;
1170
1171         dsi->host.ops = &mtk_dsi_ops;
1172         dsi->host.dev = dev;
1173         ret = mipi_dsi_host_register(&dsi->host);
1174         if (ret < 0) {
1175                 dev_err(dev, "failed to register DSI host: %d\n", ret);
1176                 return ret;
1177         }
1178
1179         ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
1180                                           &dsi->panel, &dsi->bridge);
1181         if (ret)
1182                 goto err_unregister_host;
1183
1184         dsi->driver_data = of_device_get_match_data(dev);
1185
1186         dsi->engine_clk = devm_clk_get(dev, "engine");
1187         if (IS_ERR(dsi->engine_clk)) {
1188                 ret = PTR_ERR(dsi->engine_clk);
1189                 dev_err(dev, "Failed to get engine clock: %d\n", ret);
1190                 goto err_unregister_host;
1191         }
1192
1193         dsi->digital_clk = devm_clk_get(dev, "digital");
1194         if (IS_ERR(dsi->digital_clk)) {
1195                 ret = PTR_ERR(dsi->digital_clk);
1196                 dev_err(dev, "Failed to get digital clock: %d\n", ret);
1197                 goto err_unregister_host;
1198         }
1199
1200         dsi->hs_clk = devm_clk_get(dev, "hs");
1201         if (IS_ERR(dsi->hs_clk)) {
1202                 ret = PTR_ERR(dsi->hs_clk);
1203                 dev_err(dev, "Failed to get hs clock: %d\n", ret);
1204                 goto err_unregister_host;
1205         }
1206
1207         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1208         dsi->regs = devm_ioremap_resource(dev, regs);
1209         if (IS_ERR(dsi->regs)) {
1210                 ret = PTR_ERR(dsi->regs);
1211                 dev_err(dev, "Failed to ioremap memory: %d\n", ret);
1212                 goto err_unregister_host;
1213         }
1214
1215         dsi->phy = devm_phy_get(dev, "dphy");
1216         if (IS_ERR(dsi->phy)) {
1217                 ret = PTR_ERR(dsi->phy);
1218                 dev_err(dev, "Failed to get MIPI-DPHY: %d\n", ret);
1219                 goto err_unregister_host;
1220         }
1221
1222         comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
1223         if (comp_id < 0) {
1224                 dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
1225                 ret = comp_id;
1226                 goto err_unregister_host;
1227         }
1228
1229         ret = mtk_ddp_comp_init(dev, dev->of_node, &dsi->ddp_comp, comp_id,
1230                                 &mtk_dsi_funcs);
1231         if (ret) {
1232                 dev_err(dev, "Failed to initialize component: %d\n", ret);
1233                 goto err_unregister_host;
1234         }
1235
1236         irq_num = platform_get_irq(pdev, 0);
1237         if (irq_num < 0) {
1238                 dev_err(&pdev->dev, "failed to get dsi irq_num: %d\n", irq_num);
1239                 ret = irq_num;
1240                 goto err_unregister_host;
1241         }
1242
1243         irq_set_status_flags(irq_num, IRQ_TYPE_LEVEL_LOW);
1244         ret = devm_request_irq(&pdev->dev, irq_num, mtk_dsi_irq,
1245                                IRQF_TRIGGER_LOW, dev_name(&pdev->dev), dsi);
1246         if (ret) {
1247                 dev_err(&pdev->dev, "failed to request mediatek dsi irq\n");
1248                 goto err_unregister_host;
1249         }
1250
1251         init_waitqueue_head(&dsi->irq_wait_queue);
1252
1253         platform_set_drvdata(pdev, dsi);
1254
1255         ret = component_add(&pdev->dev, &mtk_dsi_component_ops);
1256         if (ret) {
1257                 dev_err(&pdev->dev, "failed to add component: %d\n", ret);
1258                 goto err_unregister_host;
1259         }
1260
1261         return 0;
1262
1263 err_unregister_host:
1264         mipi_dsi_host_unregister(&dsi->host);
1265         return ret;
1266 }
1267
1268 static int mtk_dsi_remove(struct platform_device *pdev)
1269 {
1270         struct mtk_dsi *dsi = platform_get_drvdata(pdev);
1271
1272         mtk_output_dsi_disable(dsi);
1273         component_del(&pdev->dev, &mtk_dsi_component_ops);
1274         mipi_dsi_host_unregister(&dsi->host);
1275
1276         return 0;
1277 }
1278
1279 static const struct mtk_dsi_driver_data mt8173_dsi_driver_data = {
1280         .reg_cmdq_off = 0x200,
1281 };
1282
1283 static const struct mtk_dsi_driver_data mt2701_dsi_driver_data = {
1284         .reg_cmdq_off = 0x180,
1285 };
1286
1287 static const struct mtk_dsi_driver_data mt8183_dsi_driver_data = {
1288         .reg_cmdq_off = 0x200,
1289         .has_shadow_ctl = true,
1290         .has_size_ctl = true,
1291 };
1292
1293 static const struct of_device_id mtk_dsi_of_match[] = {
1294         { .compatible = "mediatek,mt2701-dsi",
1295           .data = &mt2701_dsi_driver_data },
1296         { .compatible = "mediatek,mt8173-dsi",
1297           .data = &mt8173_dsi_driver_data },
1298         { .compatible = "mediatek,mt8183-dsi",
1299           .data = &mt8183_dsi_driver_data },
1300         { },
1301 };
1302
1303 struct platform_driver mtk_dsi_driver = {
1304         .probe = mtk_dsi_probe,
1305         .remove = mtk_dsi_remove,
1306         .driver = {
1307                 .name = "mtk-dsi",
1308                 .of_match_table = mtk_dsi_of_match,
1309         },
1310 };