drivers/gpu/drm/bridge/ti-sn65dsi86.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4  * datasheet: http://www.ti.com/lit/ds/symlink/sn65dsi86.pdf
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/debugfs.h>
   9 #include <linux/gpio/consumer.h>
  10 #include <linux/i2c.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/module.h>
  13 #include <linux/of_graph.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/regmap.h>
  16 #include <linux/regulator/consumer.h>
  17
  18 #include <drm/drm_atomic.h>
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_bridge.h>
  21 #include <drm/drm_dp_helper.h>
  22 #include <drm/drm_mipi_dsi.h>
  23 #include <drm/drm_of.h>
  24 #include <drm/drm_panel.h>
  25 #include <drm/drm_print.h>
  26 #include <drm/drm_probe_helper.h>
  27
  28 #define SN_DEVICE_REV_REG                       0x08
  29 #define SN_DPPLL_SRC_REG                        0x0A
  30 #define  DPPLL_CLK_SRC_DSICLK                   BIT(0)
  31 #define  REFCLK_FREQ_MASK                       GENMASK(3, 1)
  32 #define  REFCLK_FREQ(x)                         ((x) << 1)
  33 #define  DPPLL_SRC_DP_PLL_LOCK                  BIT(7)
  34 #define SN_PLL_ENABLE_REG                       0x0D
  35 #define SN_DSI_LANES_REG                        0x10
  36 #define  CHA_DSI_LANES_MASK                     GENMASK(4, 3)
  37 #define  CHA_DSI_LANES(x)                       ((x) << 3)
  38 #define SN_DSIA_CLK_FREQ_REG                    0x12
  39 #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG       0x20
  40 #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG    0x24
  41 #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG        0x2C
  42 #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG       0x2D
  43 #define  CHA_HSYNC_POLARITY                     BIT(7)
  44 #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG        0x30
  45 #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG       0x31
  46 #define  CHA_VSYNC_POLARITY                     BIT(7)
  47 #define SN_CHA_HORIZONTAL_BACK_PORCH_REG        0x34
  48 #define SN_CHA_VERTICAL_BACK_PORCH_REG          0x36
  49 #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG       0x38
  50 #define SN_CHA_VERTICAL_FRONT_PORCH_REG         0x3A
  51 #define SN_ENH_FRAME_REG                        0x5A
  52 #define  VSTREAM_ENABLE                         BIT(3)
  53 #define SN_DATA_FORMAT_REG                      0x5B
  54 #define  BPP_18_RGB                             BIT(0)
  55 #define SN_HPD_DISABLE_REG                      0x5C
  56 #define  HPD_DISABLE                            BIT(0)
  57 #define SN_AUX_WDATA_REG(x)                     (0x64 + (x))
  58 #define SN_AUX_ADDR_19_16_REG                   0x74
  59 #define SN_AUX_ADDR_15_8_REG                    0x75
  60 #define SN_AUX_ADDR_7_0_REG                     0x76
  61 #define SN_AUX_LENGTH_REG                       0x77
  62 #define SN_AUX_CMD_REG                          0x78
  63 #define  AUX_CMD_SEND                           BIT(0)
  64 #define  AUX_CMD_REQ(x)                         ((x) << 4)
  65 #define SN_AUX_RDATA_REG(x)                     (0x79 + (x))
  66 #define SN_SSC_CONFIG_REG                       0x93
  67 #define  DP_NUM_LANES_MASK                      GENMASK(5, 4)
  68 #define  DP_NUM_LANES(x)                        ((x) << 4)
  69 #define SN_DATARATE_CONFIG_REG                  0x94
  70 #define  DP_DATARATE_MASK                       GENMASK(7, 5)
  71 #define  DP_DATARATE(x)                         ((x) << 5)
  72 #define SN_ML_TX_MODE_REG                       0x96
  73 #define  ML_TX_MAIN_LINK_OFF                    0
  74 #define  ML_TX_NORMAL_MODE                      BIT(0)
  75 #define SN_AUX_CMD_STATUS_REG                   0xF4
  76 #define  AUX_IRQ_STATUS_AUX_RPLY_TOUT           BIT(3)
  77 #define  AUX_IRQ_STATUS_AUX_SHORT               BIT(5)
  78 #define  AUX_IRQ_STATUS_NAT_I2C_FAIL            BIT(6)
  79
  80 #define MIN_DSI_CLK_FREQ_MHZ    40
  81
  82 /* fudge factor required to account for 8b/10b encoding */
  83 #define DP_CLK_FUDGE_NUM        10
  84 #define DP_CLK_FUDGE_DEN        8
  85
  86 /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */
  87 #define SN_AUX_MAX_PAYLOAD_BYTES        16
  88
  89 #define SN_REGULATOR_SUPPLY_NUM         4
  90
  91 struct ti_sn_bridge {
  92         struct device                   *dev;
  93         struct regmap                   *regmap;
  94         struct drm_dp_aux               aux;
  95         struct drm_bridge               bridge;
  96         struct drm_connector            connector;
  97         struct dentry                   *debugfs;
  98         struct device_node              *host_node;
  99         struct mipi_dsi_device          *dsi;
 100         struct clk                      *refclk;
 101         struct drm_panel                *panel;
 102         struct gpio_desc                *enable_gpio;
 103         struct regulator_bulk_data      supplies[SN_REGULATOR_SUPPLY_NUM];
 104         int                             dp_lanes;
 105 };
 106
 107 static const struct regmap_range ti_sn_bridge_volatile_ranges[] = {
 108         { .range_min = 0, .range_max = 0xFF },
 109 };
 110
 111 static const struct regmap_access_table ti_sn_bridge_volatile_table = {
 112         .yes_ranges = ti_sn_bridge_volatile_ranges,
 113         .n_yes_ranges = ARRAY_SIZE(ti_sn_bridge_volatile_ranges),
 114 };
 115
 116 static const struct regmap_config ti_sn_bridge_regmap_config = {
 117         .reg_bits = 8,
 118         .val_bits = 8,
 119         .volatile_table = &ti_sn_bridge_volatile_table,
 120         .cache_type = REGCACHE_NONE,
 121 };
 122
 123 static void ti_sn_bridge_write_u16(struct ti_sn_bridge *pdata,
 124                                    unsigned int reg, u16 val)
 125 {
 126         regmap_write(pdata->regmap, reg, val & 0xFF);
 127         regmap_write(pdata->regmap, reg + 1, val >> 8);
 128 }
 129
 130 static int __maybe_unused ti_sn_bridge_resume(struct device *dev)
 131 {
 132         struct ti_sn_bridge *pdata = dev_get_drvdata(dev);
 133         int ret;
 134
 135         ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
 136         if (ret) {
 137                 DRM_ERROR("failed to enable supplies %d\n", ret);
 138                 return ret;
 139         }
 140
 141         gpiod_set_value(pdata->enable_gpio, 1);
 142
 143         return ret;
 144 }
 145
 146 static int __maybe_unused ti_sn_bridge_suspend(struct device *dev)
 147 {
 148         struct ti_sn_bridge *pdata = dev_get_drvdata(dev);
 149         int ret;
 150
 151         gpiod_set_value(pdata->enable_gpio, 0);
 152
 153         ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
 154         if (ret)
 155                 DRM_ERROR("failed to disable supplies %d\n", ret);
 156
 157         return ret;
 158 }
 159
 160 static const struct dev_pm_ops ti_sn_bridge_pm_ops = {
 161         SET_RUNTIME_PM_OPS(ti_sn_bridge_suspend, ti_sn_bridge_resume, NULL)
 162 };
 163
 164 static int status_show(struct seq_file *s, void *data)
 165 {
 166         struct ti_sn_bridge *pdata = s->private;
 167         unsigned int reg, val;
 168
 169         seq_puts(s, "STATUS REGISTERS:\n");
 170
 171         pm_runtime_get_sync(pdata->dev);
 172
 173         /* IRQ Status Registers, see Table 31 in datasheet */
 174         for (reg = 0xf0; reg <= 0xf8; reg++) {
 175                 regmap_read(pdata->regmap, reg, &val);
 176                 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val);
 177         }
 178
 179         pm_runtime_put(pdata->dev);
 180
 181         return 0;
 182 }
 183
 184 DEFINE_SHOW_ATTRIBUTE(status);
 185
 186 static void ti_sn_debugfs_init(struct ti_sn_bridge *pdata)
 187 {
 188         pdata->debugfs = debugfs_create_dir(dev_name(pdata->dev), NULL);
 189
 190         debugfs_create_file("status", 0600, pdata->debugfs, pdata,
 191                         &status_fops);
 192 }
 193
 194 static void ti_sn_debugfs_remove(struct ti_sn_bridge *pdata)
 195 {
 196         debugfs_remove_recursive(pdata->debugfs);
 197         pdata->debugfs = NULL;
 198 }
 199
 200 /* Connector funcs */
 201 static struct ti_sn_bridge *
 202 connector_to_ti_sn_bridge(struct drm_connector *connector)
 203 {
 204         return container_of(connector, struct ti_sn_bridge, connector);
 205 }
 206
 207 static int ti_sn_bridge_connector_get_modes(struct drm_connector *connector)
 208 {
 209         struct ti_sn_bridge *pdata = connector_to_ti_sn_bridge(connector);
 210
 211         return drm_panel_get_modes(pdata->panel, connector);
 212 }
 213
 214 static enum drm_mode_status
 215 ti_sn_bridge_connector_mode_valid(struct drm_connector *connector,
 216                                   struct drm_display_mode *mode)
 217 {
 218         /* maximum supported resolution is 4K at 60 fps */
 219         if (mode->clock > 594000)
 220                 return MODE_CLOCK_HIGH;
 221
 222         return MODE_OK;
 223 }
 224
 225 static struct drm_connector_helper_funcs ti_sn_bridge_connector_helper_funcs = {
 226         .get_modes = ti_sn_bridge_connector_get_modes,
 227         .mode_valid = ti_sn_bridge_connector_mode_valid,
 228 };
 229
 230 static enum drm_connector_status
 231 ti_sn_bridge_connector_detect(struct drm_connector *connector, bool force)
 232 {
 233         /**
 234          * TODO: Currently if drm_panel is present, then always
 235          * return the status as connected. Need to add support to detect
 236          * device state for hot pluggable scenarios.
 237          */
 238         return connector_status_connected;
 239 }
 240
 241 static const struct drm_connector_funcs ti_sn_bridge_connector_funcs = {
 242         .fill_modes = drm_helper_probe_single_connector_modes,
 243         .detect = ti_sn_bridge_connector_detect,
 244         .destroy = drm_connector_cleanup,
 245         .reset = drm_atomic_helper_connector_reset,
 246         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 247         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 248 };
 249
 250 static struct ti_sn_bridge *bridge_to_ti_sn_bridge(struct drm_bridge *bridge)
 251 {
 252         return container_of(bridge, struct ti_sn_bridge, bridge);
 253 }
 254
 255 static int ti_sn_bridge_parse_regulators(struct ti_sn_bridge *pdata)
 256 {
 257         unsigned int i;
 258         const char * const ti_sn_bridge_supply_names[] = {
 259                 "vcca", "vcc", "vccio", "vpll",
 260         };
 261
 262         for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++)
 263                 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i];
 264
 265         return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM,
 266                                        pdata->supplies);
 267 }
 268
 269 static int ti_sn_bridge_attach(struct drm_bridge *bridge,
 270                                enum drm_bridge_attach_flags flags)
 271 {
 272         int ret, val;
 273         struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
 274         struct mipi_dsi_host *host;
 275         struct mipi_dsi_device *dsi;
 276         const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge",
 277                                                    .channel = 0,
 278                                                    .node = NULL,
 279                                                  };
 280
 281         if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) {
 282                 DRM_ERROR("Fix bridge driver to make connector optional!");
 283                 return -EINVAL;
 284         }
 285
 286         ret = drm_connector_init(bridge->dev, &pdata->connector,
 287                                  &ti_sn_bridge_connector_funcs,
 288                                  DRM_MODE_CONNECTOR_eDP);
 289         if (ret) {
 290                 DRM_ERROR("Failed to initialize connector with drm\n");
 291                 return ret;
 292         }
 293
 294         drm_connector_helper_add(&pdata->connector,
 295                                  &ti_sn_bridge_connector_helper_funcs);
 296         drm_connector_attach_encoder(&pdata->connector, bridge->encoder);
 297
 298         /*
 299          * TODO: ideally finding host resource and dsi dev registration needs
 300          * to be done in bridge probe. But some existing DSI host drivers will
 301          * wait for any of the drm_bridge/drm_panel to get added to the global
 302          * bridge/panel list, before completing their probe. So if we do the
 303          * dsi dev registration part in bridge probe, before populating in
 304          * the global bridge list, then it will cause deadlock as dsi host probe
 305          * will never complete, neither our bridge probe. So keeping it here
 306          * will satisfy most of the existing host drivers. Once the host driver
 307          * is fixed we can move the below code to bridge probe safely.
 308          */
 309         host = of_find_mipi_dsi_host_by_node(pdata->host_node);
 310         if (!host) {
 311                 DRM_ERROR("failed to find dsi host\n");
 312                 ret = -ENODEV;
 313                 goto err_dsi_host;
 314         }
 315
 316         dsi = mipi_dsi_device_register_full(host, &info);
 317         if (IS_ERR(dsi)) {
 318                 DRM_ERROR("failed to create dsi device\n");
 319                 ret = PTR_ERR(dsi);
 320                 goto err_dsi_host;
 321         }
 322
 323         /* TODO: setting to 4 MIPI lanes always for now */
 324         dsi->lanes = 4;
 325         dsi->format = MIPI_DSI_FMT_RGB888;
 326         dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
 327
 328         /* check if continuous dsi clock is required or not */
 329         pm_runtime_get_sync(pdata->dev);
 330         regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val);
 331         pm_runtime_put(pdata->dev);
 332         if (!(val & DPPLL_CLK_SRC_DSICLK))
 333                 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS;
 334
 335         ret = mipi_dsi_attach(dsi);
 336         if (ret < 0) {
 337                 DRM_ERROR("failed to attach dsi to host\n");
 338                 goto err_dsi_attach;
 339         }
 340         pdata->dsi = dsi;
 341
 342         /* attach panel to bridge */
 343         drm_panel_attach(pdata->panel, &pdata->connector);
 344
 345         return 0;
 346
 347 err_dsi_attach:
 348         mipi_dsi_device_unregister(dsi);
 349 err_dsi_host:
 350         drm_connector_cleanup(&pdata->connector);
 351         return ret;
 352 }
 353
 354 static void ti_sn_bridge_disable(struct drm_bridge *bridge)
 355 {
 356         struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
 357
 358         drm_panel_disable(pdata->panel);
 359
 360         /* disable video stream */
 361         regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0);
 362         /* semi auto link training mode OFF */
 363         regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
 364         /* disable DP PLL */
 365         regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
 366
 367         drm_panel_unprepare(pdata->panel);
 368 }
 369
 370 static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn_bridge *pdata)
 371 {
 372         u32 bit_rate_khz, clk_freq_khz;
 373         struct drm_display_mode *mode =
 374                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 375
 376         bit_rate_khz = mode->clock *
 377                         mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
 378         clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2);
 379
 380         return clk_freq_khz;
 381 }
 382
 383 /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
 384 static const u32 ti_sn_bridge_refclk_lut[] = {
 385         12000000,
 386         19200000,
 387         26000000,
 388         27000000,
 389         38400000,
 390 };
 391
 392 /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
 393 static const u32 ti_sn_bridge_dsiclk_lut[] = {
 394         468000000,
 395         384000000,
 396         416000000,
 397         486000000,
 398         460800000,
 399 };
 400
 401 static void ti_sn_bridge_set_refclk_freq(struct ti_sn_bridge *pdata)
 402 {
 403         int i;
 404         u32 refclk_rate;
 405         const u32 *refclk_lut;
 406         size_t refclk_lut_size;
 407
 408         if (pdata->refclk) {
 409                 refclk_rate = clk_get_rate(pdata->refclk);
 410                 refclk_lut = ti_sn_bridge_refclk_lut;
 411                 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut);
 412                 clk_prepare_enable(pdata->refclk);
 413         } else {
 414                 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000;
 415                 refclk_lut = ti_sn_bridge_dsiclk_lut;
 416                 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut);
 417         }
 418
 419         /* for i equals to refclk_lut_size means default frequency */
 420         for (i = 0; i < refclk_lut_size; i++)
 421                 if (refclk_lut[i] == refclk_rate)
 422                         break;
 423
 424         regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
 425                            REFCLK_FREQ(i));
 426 }
 427
 428 static void ti_sn_bridge_set_dsi_rate(struct ti_sn_bridge *pdata)
 429 {
 430         unsigned int bit_rate_mhz, clk_freq_mhz;
 431         unsigned int val;
 432         struct drm_display_mode *mode =
 433                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 434
 435         /* set DSIA clk frequency */
 436         bit_rate_mhz = (mode->clock / 1000) *
 437                         mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
 438         clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
 439
 440         /* for each increment in val, frequency increases by 5MHz */
 441         val = (MIN_DSI_CLK_FREQ_MHZ / 5) +
 442                 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
 443         regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
 444 }
 445
 446 static unsigned int ti_sn_bridge_get_bpp(struct ti_sn_bridge *pdata)
 447 {
 448         if (pdata->connector.display_info.bpc <= 6)
 449                 return 18;
 450         else
 451                 return 24;
 452 }
 453
 454 /**
 455  * LUT index corresponds to register value and
 456  * LUT values corresponds to dp data rate supported
 457  * by the bridge in Mbps unit.
 458  */
 459 static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
 460         0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
 461 };
 462
 463 static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn_bridge *pdata)
 464 {
 465         unsigned int bit_rate_khz, dp_rate_mhz;
 466         unsigned int i;
 467         struct drm_display_mode *mode =
 468                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 469
 470         /* Calculate minimum bit rate based on our pixel clock. */
 471         bit_rate_khz = mode->clock * ti_sn_bridge_get_bpp(pdata);
 472
 473         /* Calculate minimum DP data rate, taking 80% as per DP spec */
 474         dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM,
 475                                    1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN);
 476
 477         for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
 478                 if (ti_sn_bridge_dp_rate_lut[i] > dp_rate_mhz)
 479                         break;
 480
 481         return i;
 482 }
 483
 484 static void ti_sn_bridge_read_valid_rates(struct ti_sn_bridge *pdata,
 485                                           bool rate_valid[])
 486 {
 487         unsigned int rate_per_200khz;
 488         unsigned int rate_mhz;
 489         u8 dpcd_val;
 490         int ret;
 491         int i, j;
 492
 493         ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val);
 494         if (ret != 1) {
 495                 DRM_DEV_ERROR(pdata->dev,
 496                               "Can't read eDP rev (%d), assuming 1.1\n", ret);
 497                 dpcd_val = DP_EDP_11;
 498         }
 499
 500         if (dpcd_val >= DP_EDP_14) {
 501                 /* eDP 1.4 devices must provide a custom table */
 502                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
 503
 504                 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES,
 505                                        sink_rates, sizeof(sink_rates));
 506
 507                 if (ret != sizeof(sink_rates)) {
 508                         DRM_DEV_ERROR(pdata->dev,
 509                                 "Can't read supported rate table (%d)\n", ret);
 510
 511                         /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */
 512                         memset(sink_rates, 0, sizeof(sink_rates));
 513                 }
 514
 515                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
 516                         rate_per_200khz = le16_to_cpu(sink_rates[i]);
 517
 518                         if (!rate_per_200khz)
 519                                 break;
 520
 521                         rate_mhz = rate_per_200khz * 200 / 1000;
 522                         for (j = 0;
 523                              j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
 524                              j++) {
 525                                 if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz)
 526                                         rate_valid[j] = true;
 527                         }
 528                 }
 529
 530                 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) {
 531                         if (rate_valid[i])
 532                                 return;
 533                 }
 534                 DRM_DEV_ERROR(pdata->dev,
 535                               "No matching eDP rates in table; falling back\n");
 536         }
 537
 538         /* On older versions best we can do is use DP_MAX_LINK_RATE */
 539         ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val);
 540         if (ret != 1) {
 541                 DRM_DEV_ERROR(pdata->dev,
 542                               "Can't read max rate (%d); assuming 5.4 GHz\n",
 543                               ret);
 544                 dpcd_val = DP_LINK_BW_5_4;
 545         }
 546
 547         switch (dpcd_val) {
 548         default:
 549                 DRM_DEV_ERROR(pdata->dev,
 550                               "Unexpected max rate (%#x); assuming 5.4 GHz\n",
 551                               (int)dpcd_val);
 552                 /* fall through */
 553         case DP_LINK_BW_5_4:
 554                 rate_valid[7] = 1;
 555                 /* fall through */
 556         case DP_LINK_BW_2_7:
 557                 rate_valid[4] = 1;
 558                 /* fall through */
 559         case DP_LINK_BW_1_62:
 560                 rate_valid[1] = 1;
 561                 break;
 562         }
 563 }
 564
 565 static void ti_sn_bridge_set_video_timings(struct ti_sn_bridge *pdata)
 566 {
 567         struct drm_display_mode *mode =
 568                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 569         u8 hsync_polarity = 0, vsync_polarity = 0;
 570
 571         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 572                 hsync_polarity = CHA_HSYNC_POLARITY;
 573         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 574                 vsync_polarity = CHA_VSYNC_POLARITY;
 575
 576         ti_sn_bridge_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
 577                                mode->hdisplay);
 578         ti_sn_bridge_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG,
 579                                mode->vdisplay);
 580         regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG,
 581                      (mode->hsync_end - mode->hsync_start) & 0xFF);
 582         regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG,
 583                      (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) |
 584                      hsync_polarity);
 585         regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG,
 586                      (mode->vsync_end - mode->vsync_start) & 0xFF);
 587         regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG,
 588                      (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) |
 589                      vsync_polarity);
 590
 591         regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG,
 592                      (mode->htotal - mode->hsync_end) & 0xFF);
 593         regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG,
 594                      (mode->vtotal - mode->vsync_end) & 0xFF);
 595
 596         regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG,
 597                      (mode->hsync_start - mode->hdisplay) & 0xFF);
 598         regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG,
 599                      (mode->vsync_start - mode->vdisplay) & 0xFF);
 600
 601         usleep_range(10000, 10500); /* 10ms delay recommended by spec */
 602 }
 603
 604 static unsigned int ti_sn_get_max_lanes(struct ti_sn_bridge *pdata)
 605 {
 606         u8 data;
 607         int ret;
 608
 609         ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data);
 610         if (ret != 1) {
 611                 DRM_DEV_ERROR(pdata->dev,
 612                               "Can't read lane count (%d); assuming 4\n", ret);
 613                 return 4;
 614         }
 615
 616         return data & DP_LANE_COUNT_MASK;
 617 }
 618
 619 static int ti_sn_link_training(struct ti_sn_bridge *pdata, int dp_rate_idx,
 620                                const char **last_err_str)
 621 {
 622         unsigned int val;
 623         int ret;
 624
 625         /* set dp clk frequency value */
 626         regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
 627                            DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx));
 628
 629         /* enable DP PLL */
 630         regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);
 631
 632         ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val,
 633                                        val & DPPLL_SRC_DP_PLL_LOCK, 1000,
 634                                        50 * 1000);
 635         if (ret) {
 636                 *last_err_str = "DP_PLL_LOCK polling failed";
 637                 goto exit;
 638         }
 639
 640         /* Semi auto link training mode */
 641         regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A);
 642         ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val,
 643                                        val == ML_TX_MAIN_LINK_OFF ||
 644                                        val == ML_TX_NORMAL_MODE, 1000,
 645                                        500 * 1000);
 646         if (ret) {
 647                 *last_err_str = "Training complete polling failed";
 648         } else if (val == ML_TX_MAIN_LINK_OFF) {
 649                 *last_err_str = "Link training failed, link is off";
 650                 ret = -EIO;
 651         }
 652
 653 exit:
 654         /* Disable the PLL if we failed */
 655         if (ret)
 656                 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
 657
 658         return ret;
 659 }
 660
 661 static void ti_sn_bridge_enable(struct drm_bridge *bridge)
 662 {
 663         struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
 664         bool rate_valid[ARRAY_SIZE(ti_sn_bridge_dp_rate_lut)] = { };
 665         const char *last_err_str = "No supported DP rate";
 666         int dp_rate_idx;
 667         unsigned int val;
 668         int ret = -EINVAL;
 669
 670         /*
 671          * Run with the maximum number of lanes that the DP sink supports.
 672          *
 673          * Depending use cases, we might want to revisit this later because:
 674          * - It's plausible that someone may have run fewer lines to the
 675          *   sink than the sink actually supports, assuming that the lines
 676          *   will just be driven at a higher rate.
 677          * - The DP spec seems to indicate that it's more important to minimize
 678          *   the number of lanes than the link rate.
 679          *
 680          * If we do revisit, it would be important to measure the power impact.
 681          */
 682         pdata->dp_lanes = ti_sn_get_max_lanes(pdata);
 683
 684         /* DSI_A lane config */
 685         val = CHA_DSI_LANES(4 - pdata->dsi->lanes);
 686         regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
 687                            CHA_DSI_LANES_MASK, val);
 688
 689         /* set dsi clk frequency value */
 690         ti_sn_bridge_set_dsi_rate(pdata);
 691
 692         /**
 693          * The SN65DSI86 only supports ASSR Display Authentication method and
 694          * this method is enabled by default. An eDP panel must support this
 695          * authentication method. We need to enable this method in the eDP panel
 696          * at DisplayPort address 0x0010A prior to link training.
 697          */
 698         drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET,
 699                            DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
 700
 701         /* Set the DP output format (18 bpp or 24 bpp) */
 702         val = (ti_sn_bridge_get_bpp(pdata) == 18) ? BPP_18_RGB : 0;
 703         regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val);
 704
 705         /* DP lane config */
 706         val = DP_NUM_LANES(min(pdata->dp_lanes, 3));
 707         regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
 708                            val);
 709
 710         ti_sn_bridge_read_valid_rates(pdata, rate_valid);
 711
 712         /* Train until we run out of rates */
 713         for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata);
 714              dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
 715              dp_rate_idx++) {
 716                 if (!rate_valid[dp_rate_idx])
 717                         continue;
 718
 719                 ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str);
 720                 if (!ret)
 721                         break;
 722         }
 723         if (ret) {
 724                 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret);
 725                 return;
 726         }
 727
 728         /* config video parameters */
 729         ti_sn_bridge_set_video_timings(pdata);
 730
 731         /* enable video stream */
 732         regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE,
 733                            VSTREAM_ENABLE);
 734
 735         drm_panel_enable(pdata->panel);
 736 }
 737
 738 static void ti_sn_bridge_pre_enable(struct drm_bridge *bridge)
 739 {
 740         struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
 741
 742         pm_runtime_get_sync(pdata->dev);
 743
 744         /* configure bridge ref_clk */
 745         ti_sn_bridge_set_refclk_freq(pdata);
 746
 747         /*
 748          * HPD on this bridge chip is a bit useless.  This is an eDP bridge
 749          * so the HPD is an internal signal that's only there to signal that
 750          * the panel is done powering up.  ...but the bridge chip debounces
 751          * this signal by between 100 ms and 400 ms (depending on process,
 752          * voltage, and temperate--I measured it at about 200 ms).  One
 753          * particular panel asserted HPD 84 ms after it was powered on meaning
 754          * that we saw HPD 284 ms after power on.  ...but the same panel said
 755          * that instead of looking at HPD you could just hardcode a delay of
 756          * 200 ms.  We'll assume that the panel driver will have the hardcoded
 757          * delay in its prepare and always disable HPD.
 758          *
 759          * If HPD somehow makes sense on some future panel we'll have to
 760          * change this to be conditional on someone specifying that HPD should
 761          * be used.
 762          */
 763         regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
 764                            HPD_DISABLE);
 765
 766         drm_panel_prepare(pdata->panel);
 767 }
 768
 769 static void ti_sn_bridge_post_disable(struct drm_bridge *bridge)
 770 {
 771         struct ti_sn_bridge *pdata = bridge_to_ti_sn_bridge(bridge);
 772
 773         if (pdata->refclk)
 774                 clk_disable_unprepare(pdata->refclk);
 775
 776         pm_runtime_put_sync(pdata->dev);
 777 }
 778
 779 static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
 780         .attach = ti_sn_bridge_attach,
 781         .pre_enable = ti_sn_bridge_pre_enable,
 782         .enable = ti_sn_bridge_enable,
 783         .disable = ti_sn_bridge_disable,
 784         .post_disable = ti_sn_bridge_post_disable,
 785 };
 786
 787 static struct ti_sn_bridge *aux_to_ti_sn_bridge(struct drm_dp_aux *aux)
 788 {
 789         return container_of(aux, struct ti_sn_bridge, aux);
 790 }
 791
 792 static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,
 793                                   struct drm_dp_aux_msg *msg)
 794 {
 795         struct ti_sn_bridge *pdata = aux_to_ti_sn_bridge(aux);
 796         u32 request = msg->request & ~DP_AUX_I2C_MOT;
 797         u32 request_val = AUX_CMD_REQ(msg->request);
 798         u8 *buf = (u8 *)msg->buffer;
 799         unsigned int val;
 800         int ret, i;
 801
 802         if (msg->size > SN_AUX_MAX_PAYLOAD_BYTES)
 803                 return -EINVAL;
 804
 805         switch (request) {
 806         case DP_AUX_NATIVE_WRITE:
 807         case DP_AUX_I2C_WRITE:
 808         case DP_AUX_NATIVE_READ:
 809         case DP_AUX_I2C_READ:
 810                 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val);
 811                 break;
 812         default:
 813                 return -EINVAL;
 814         }
 815
 816         regmap_write(pdata->regmap, SN_AUX_ADDR_19_16_REG,
 817                      (msg->address >> 16) & 0xF);
 818         regmap_write(pdata->regmap, SN_AUX_ADDR_15_8_REG,
 819                      (msg->address >> 8) & 0xFF);
 820         regmap_write(pdata->regmap, SN_AUX_ADDR_7_0_REG, msg->address & 0xFF);
 821
 822         regmap_write(pdata->regmap, SN_AUX_LENGTH_REG, msg->size);
 823
 824         if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE) {
 825                 for (i = 0; i < msg->size; i++)
 826                         regmap_write(pdata->regmap, SN_AUX_WDATA_REG(i),
 827                                      buf[i]);
 828         }
 829
 830         regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND);
 831
 832         ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val,
 833                                        !(val & AUX_CMD_SEND), 200,
 834                                        50 * 1000);
 835         if (ret)
 836                 return ret;
 837
 838         ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val);
 839         if (ret)
 840                 return ret;
 841         else if ((val & AUX_IRQ_STATUS_NAT_I2C_FAIL)
 842                  || (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT)
 843                  || (val & AUX_IRQ_STATUS_AUX_SHORT))
 844                 return -ENXIO;
 845
 846         if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE)
 847                 return msg->size;
 848
 849         for (i = 0; i < msg->size; i++) {
 850                 unsigned int val;
 851                 ret = regmap_read(pdata->regmap, SN_AUX_RDATA_REG(i),
 852                                   &val);
 853                 if (ret)
 854                         return ret;
 855
 856                 WARN_ON(val & ~0xFF);
 857                 buf[i] = (u8)(val & 0xFF);
 858         }
 859
 860         return msg->size;
 861 }
 862
 863 static int ti_sn_bridge_parse_dsi_host(struct ti_sn_bridge *pdata)
 864 {
 865         struct device_node *np = pdata->dev->of_node;
 866
 867         pdata->host_node = of_graph_get_remote_node(np, 0, 0);
 868
 869         if (!pdata->host_node) {
 870                 DRM_ERROR("remote dsi host node not found\n");
 871                 return -ENODEV;
 872         }
 873
 874         return 0;
 875 }
 876
 877 static int ti_sn_bridge_probe(struct i2c_client *client,
 878                               const struct i2c_device_id *id)
 879 {
 880         struct ti_sn_bridge *pdata;
 881         int ret;
 882
 883         if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
 884                 DRM_ERROR("device doesn't support I2C\n");
 885                 return -ENODEV;
 886         }
 887
 888         pdata = devm_kzalloc(&client->dev, sizeof(struct ti_sn_bridge),
 889                              GFP_KERNEL);
 890         if (!pdata)
 891                 return -ENOMEM;
 892
 893         pdata->regmap = devm_regmap_init_i2c(client,
 894                                              &ti_sn_bridge_regmap_config);
 895         if (IS_ERR(pdata->regmap)) {
 896                 DRM_ERROR("regmap i2c init failed\n");
 897                 return PTR_ERR(pdata->regmap);
 898         }
 899
 900         pdata->dev = &client->dev;
 901
 902         ret = drm_of_find_panel_or_bridge(pdata->dev->of_node, 1, 0,
 903                                           &pdata->panel, NULL);
 904         if (ret) {
 905                 DRM_ERROR("could not find any panel node\n");
 906                 return ret;
 907         }
 908
 909         dev_set_drvdata(&client->dev, pdata);
 910
 911         pdata->enable_gpio = devm_gpiod_get(pdata->dev, "enable",
 912                                             GPIOD_OUT_LOW);
 913         if (IS_ERR(pdata->enable_gpio)) {
 914                 DRM_ERROR("failed to get enable gpio from DT\n");
 915                 ret = PTR_ERR(pdata->enable_gpio);
 916                 return ret;
 917         }
 918
 919         ret = ti_sn_bridge_parse_regulators(pdata);
 920         if (ret) {
 921                 DRM_ERROR("failed to parse regulators\n");
 922                 return ret;
 923         }
 924
 925         pdata->refclk = devm_clk_get(pdata->dev, "refclk");
 926         if (IS_ERR(pdata->refclk)) {
 927                 ret = PTR_ERR(pdata->refclk);
 928                 if (ret == -EPROBE_DEFER)
 929                         return ret;
 930                 DRM_DEBUG_KMS("refclk not found\n");
 931                 pdata->refclk = NULL;
 932         }
 933
 934         ret = ti_sn_bridge_parse_dsi_host(pdata);
 935         if (ret)
 936                 return ret;
 937
 938         pm_runtime_enable(pdata->dev);
 939
 940         i2c_set_clientdata(client, pdata);
 941
 942         pdata->aux.name = "ti-sn65dsi86-aux";
 943         pdata->aux.dev = pdata->dev;
 944         pdata->aux.transfer = ti_sn_aux_transfer;
 945         drm_dp_aux_register(&pdata->aux);
 946
 947         pdata->bridge.funcs = &ti_sn_bridge_funcs;
 948         pdata->bridge.of_node = client->dev.of_node;
 949
 950         drm_bridge_add(&pdata->bridge);
 951
 952         ti_sn_debugfs_init(pdata);
 953
 954         return 0;
 955 }
 956
 957 static int ti_sn_bridge_remove(struct i2c_client *client)
 958 {
 959         struct ti_sn_bridge *pdata = i2c_get_clientdata(client);
 960
 961         if (!pdata)
 962                 return -EINVAL;
 963
 964         ti_sn_debugfs_remove(pdata);
 965
 966         of_node_put(pdata->host_node);
 967
 968         pm_runtime_disable(pdata->dev);
 969
 970         if (pdata->dsi) {
 971                 mipi_dsi_detach(pdata->dsi);
 972                 mipi_dsi_device_unregister(pdata->dsi);
 973         }
 974
 975         drm_bridge_remove(&pdata->bridge);
 976
 977         return 0;
 978 }
 979
 980 static struct i2c_device_id ti_sn_bridge_id[] = {
 981         { "ti,sn65dsi86", 0},
 982         {},
 983 };
 984 MODULE_DEVICE_TABLE(i2c, ti_sn_bridge_id);
 985
 986 static const struct of_device_id ti_sn_bridge_match_table[] = {
 987         {.compatible = "ti,sn65dsi86"},
 988         {},
 989 };
 990 MODULE_DEVICE_TABLE(of, ti_sn_bridge_match_table);
 991
 992 static struct i2c_driver ti_sn_bridge_driver = {
 993         .driver = {
 994                 .name = "ti_sn65dsi86",
 995                 .of_match_table = ti_sn_bridge_match_table,
 996                 .pm = &ti_sn_bridge_pm_ops,
 997         },
 998         .probe = ti_sn_bridge_probe,
 999         .remove = ti_sn_bridge_remove,
1000         .id_table = ti_sn_bridge_id,
1001 };
1002 module_i2c_driver(ti_sn_bridge_driver);
1003
1004 MODULE_AUTHOR("Sandeep Panda <[email protected]>");
1005 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");
1006 MODULE_LICENSE("GPL v2");