drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __AMDGPU_MES_H__
  25 #define __AMDGPU_MES_H__
  26
  27 #include "amdgpu_irq.h"
  28 #include "kgd_kfd_interface.h"
  29 #include "amdgpu_gfx.h"
  30 #include <linux/sched/mm.h>
  31
  32 #define AMDGPU_MES_MAX_COMPUTE_PIPES        8
  33 #define AMDGPU_MES_MAX_GFX_PIPES            2
  34 #define AMDGPU_MES_MAX_SDMA_PIPES           2
  35
  36 #define AMDGPU_MES_API_VERSION_SHIFT    12
  37 #define AMDGPU_MES_FEAT_VERSION_SHIFT   24
  38
  39 #define AMDGPU_MES_VERSION_MASK         0x00000fff
  40 #define AMDGPU_MES_API_VERSION_MASK     0x00fff000
  41 #define AMDGPU_MES_FEAT_VERSION_MASK    0xff000000
  42
  43 enum amdgpu_mes_priority_level {
  44         AMDGPU_MES_PRIORITY_LEVEL_LOW       = 0,
  45         AMDGPU_MES_PRIORITY_LEVEL_NORMAL    = 1,
  46         AMDGPU_MES_PRIORITY_LEVEL_MEDIUM    = 2,
  47         AMDGPU_MES_PRIORITY_LEVEL_HIGH      = 3,
  48         AMDGPU_MES_PRIORITY_LEVEL_REALTIME  = 4,
  49         AMDGPU_MES_PRIORITY_NUM_LEVELS
  50 };
  51
  52 #define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */
  53 #define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */
  54
  55 struct amdgpu_mes_funcs;
  56
  57 enum admgpu_mes_pipe {
  58         AMDGPU_MES_SCHED_PIPE = 0,
  59         AMDGPU_MES_KIQ_PIPE,
  60         AMDGPU_MAX_MES_PIPES = 2,
  61 };
  62
  63 struct amdgpu_mes {
  64         struct amdgpu_device            *adev;
  65
  66         struct mutex                    mutex_hidden;
  67
  68         struct idr                      pasid_idr;
  69         struct idr                      gang_id_idr;
  70         struct idr                      queue_id_idr;
  71         struct ida                      doorbell_ida;
  72
  73         spinlock_t                      queue_id_lock;
  74
  75         uint32_t                        sched_version;
  76         uint32_t                        kiq_version;
  77
  78         uint32_t                        total_max_queue;
  79         uint32_t                        doorbell_id_offset;
  80         uint32_t                        max_doorbell_slices;
  81
  82         uint64_t                        default_process_quantum;
  83         uint64_t                        default_gang_quantum;
  84
  85         struct amdgpu_ring              ring;
  86         spinlock_t                      ring_lock;
  87
  88         const struct firmware           *fw[AMDGPU_MAX_MES_PIPES];
  89
  90         /* mes ucode */
  91         struct amdgpu_bo                *ucode_fw_obj[AMDGPU_MAX_MES_PIPES];
  92         uint64_t                        ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES];
  93         uint32_t                        *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES];
  94         uint64_t                        uc_start_addr[AMDGPU_MAX_MES_PIPES];
  95
  96         /* mes ucode data */
  97         struct amdgpu_bo                *data_fw_obj[AMDGPU_MAX_MES_PIPES];
  98         uint64_t                        data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES];
  99         uint32_t                        *data_fw_ptr[AMDGPU_MAX_MES_PIPES];
 100         uint64_t                        data_start_addr[AMDGPU_MAX_MES_PIPES];
 101
 102         /* eop gpu obj */
 103         struct amdgpu_bo                *eop_gpu_obj[AMDGPU_MAX_MES_PIPES];
 104         uint64_t                        eop_gpu_addr[AMDGPU_MAX_MES_PIPES];
 105
 106         void                            *mqd_backup[AMDGPU_MAX_MES_PIPES];
 107         struct amdgpu_irq_src           irq[AMDGPU_MAX_MES_PIPES];
 108
 109         uint32_t                        vmid_mask_gfxhub;
 110         uint32_t                        vmid_mask_mmhub;
 111         uint32_t                        compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES];
 112         uint32_t                        gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES];
 113         uint32_t                        sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES];
 114         uint32_t                        aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS];
 115         uint32_t                        sch_ctx_offs;
 116         uint64_t                        sch_ctx_gpu_addr;
 117         uint64_t                        *sch_ctx_ptr;
 118         uint32_t                        query_status_fence_offs;
 119         uint64_t                        query_status_fence_gpu_addr;
 120         uint64_t                        *query_status_fence_ptr;
 121         uint32_t                        read_val_offs;
 122         uint64_t                        read_val_gpu_addr;
 123         uint32_t                        *read_val_ptr;
 124
 125         uint32_t                        saved_flags;
 126
 127         /* initialize kiq pipe */
 128         int                             (*kiq_hw_init)(struct amdgpu_device *adev);
 129         int                             (*kiq_hw_fini)(struct amdgpu_device *adev);
 130
 131         /* ip specific functions */
 132         const struct amdgpu_mes_funcs   *funcs;
 133 };
 134
 135 struct amdgpu_mes_process {
 136         int                     pasid;
 137         struct                  amdgpu_vm *vm;
 138         uint64_t                pd_gpu_addr;
 139         struct amdgpu_bo        *proc_ctx_bo;
 140         uint64_t                proc_ctx_gpu_addr;
 141         void                    *proc_ctx_cpu_ptr;
 142         uint64_t                process_quantum;
 143         struct                  list_head gang_list;
 144         uint32_t                doorbell_index;
 145         unsigned long           *doorbell_bitmap;
 146         struct mutex            doorbell_lock;
 147 };
 148
 149 struct amdgpu_mes_gang {
 150         int                             gang_id;
 151         int                             priority;
 152         int                             inprocess_gang_priority;
 153         int                             global_priority_level;
 154         struct list_head                list;
 155         struct amdgpu_mes_process       *process;
 156         struct amdgpu_bo                *gang_ctx_bo;
 157         uint64_t                        gang_ctx_gpu_addr;
 158         void                            *gang_ctx_cpu_ptr;
 159         uint64_t                        gang_quantum;
 160         struct list_head                queue_list;
 161 };
 162
 163 struct amdgpu_mes_queue {
 164         struct list_head                list;
 165         struct amdgpu_mes_gang          *gang;
 166         int                             queue_id;
 167         uint64_t                        doorbell_off;
 168         struct amdgpu_bo                *mqd_obj;
 169         void                            *mqd_cpu_ptr;
 170         uint64_t                        mqd_gpu_addr;
 171         uint64_t                        wptr_gpu_addr;
 172         int                             queue_type;
 173         int                             paging;
 174         struct amdgpu_ring              *ring;
 175 };
 176
 177 struct amdgpu_mes_queue_properties {
 178         int                     queue_type;
 179         uint64_t                hqd_base_gpu_addr;
 180         uint64_t                rptr_gpu_addr;
 181         uint64_t                wptr_gpu_addr;
 182         uint64_t                wptr_mc_addr;
 183         uint32_t                queue_size;
 184         uint64_t                eop_gpu_addr;
 185         uint32_t                hqd_pipe_priority;
 186         uint32_t                hqd_queue_priority;
 187         bool                    paging;
 188         struct amdgpu_ring      *ring;
 189         /* out */
 190         uint64_t                doorbell_off;
 191 };
 192
 193 struct amdgpu_mes_gang_properties {
 194         uint32_t        priority;
 195         uint32_t        gang_quantum;
 196         uint32_t        inprocess_gang_priority;
 197         uint32_t        priority_level;
 198         int             global_priority_level;
 199 };
 200
 201 struct mes_add_queue_input {
 202         uint32_t        process_id;
 203         uint64_t        page_table_base_addr;
 204         uint64_t        process_va_start;
 205         uint64_t        process_va_end;
 206         uint64_t        process_quantum;
 207         uint64_t        process_context_addr;
 208         uint64_t        gang_quantum;
 209         uint64_t        gang_context_addr;
 210         uint32_t        inprocess_gang_priority;
 211         uint32_t        gang_global_priority_level;
 212         uint32_t        doorbell_offset;
 213         uint64_t        mqd_addr;
 214         uint64_t        wptr_addr;
 215         uint64_t        wptr_mc_addr;
 216         uint32_t        queue_type;
 217         uint32_t        paging;
 218         uint32_t        gws_base;
 219         uint32_t        gws_size;
 220         uint64_t        tba_addr;
 221         uint64_t        tma_addr;
 222         uint32_t        trap_en;
 223         uint32_t        skip_process_ctx_clear;
 224         uint32_t        is_kfd_process;
 225         uint32_t        is_aql_queue;
 226         uint32_t        queue_size;
 227         uint32_t        exclusively_scheduled;
 228 };
 229
 230 struct mes_remove_queue_input {
 231         uint32_t        doorbell_offset;
 232         uint64_t        gang_context_addr;
 233 };
 234
 235 struct mes_unmap_legacy_queue_input {
 236         enum amdgpu_unmap_queues_action    action;
 237         uint32_t                           queue_type;
 238         uint32_t                           doorbell_offset;
 239         uint32_t                           pipe_id;
 240         uint32_t                           queue_id;
 241         uint64_t                           trail_fence_addr;
 242         uint64_t                           trail_fence_data;
 243 };
 244
 245 struct mes_suspend_gang_input {
 246         bool            suspend_all_gangs;
 247         uint64_t        gang_context_addr;
 248         uint64_t        suspend_fence_addr;
 249         uint32_t        suspend_fence_value;
 250 };
 251
 252 struct mes_resume_gang_input {
 253         bool            resume_all_gangs;
 254         uint64_t        gang_context_addr;
 255 };
 256
 257 enum mes_misc_opcode {
 258         MES_MISC_OP_WRITE_REG,
 259         MES_MISC_OP_READ_REG,
 260         MES_MISC_OP_WRM_REG_WAIT,
 261         MES_MISC_OP_WRM_REG_WR_WAIT,
 262         MES_MISC_OP_SET_SHADER_DEBUGGER,
 263 };
 264
 265 struct mes_misc_op_input {
 266         enum mes_misc_opcode op;
 267
 268         union {
 269                 struct {
 270                         uint32_t                  reg_offset;
 271                         uint64_t                  buffer_addr;
 272                 } read_reg;
 273
 274                 struct {
 275                         uint32_t                  reg_offset;
 276                         uint32_t                  reg_value;
 277                 } write_reg;
 278
 279                 struct {
 280                         uint32_t                   ref;
 281                         uint32_t                   mask;
 282                         uint32_t                   reg0;
 283                         uint32_t                   reg1;
 284                 } wrm_reg;
 285
 286                 struct {
 287                         uint64_t process_context_addr;
 288                         union {
 289                                 struct {
 290                                         uint64_t single_memop : 1;
 291                                         uint64_t single_alu_op : 1;
 292                                         uint64_t reserved: 30;
 293                                 };
 294                                 uint32_t u32all;
 295                         } flags;
 296                         uint32_t spi_gdbg_per_vmid_cntl;
 297                         uint32_t tcp_watch_cntl[4];
 298                         uint32_t trap_en;
 299                 } set_shader_debugger;
 300         };
 301 };
 302
 303 struct amdgpu_mes_funcs {
 304         int (*add_hw_queue)(struct amdgpu_mes *mes,
 305                             struct mes_add_queue_input *input);
 306
 307         int (*remove_hw_queue)(struct amdgpu_mes *mes,
 308                                struct mes_remove_queue_input *input);
 309
 310         int (*unmap_legacy_queue)(struct amdgpu_mes *mes,
 311                                   struct mes_unmap_legacy_queue_input *input);
 312
 313         int (*suspend_gang)(struct amdgpu_mes *mes,
 314                             struct mes_suspend_gang_input *input);
 315
 316         int (*resume_gang)(struct amdgpu_mes *mes,
 317                            struct mes_resume_gang_input *input);
 318
 319         int (*misc_op)(struct amdgpu_mes *mes,
 320                        struct mes_misc_op_input *input);
 321 };
 322
 323 #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev))
 324 #define amdgpu_mes_kiq_hw_fini(adev) (adev)->mes.kiq_hw_fini((adev))
 325
 326 int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs);
 327
 328 int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe);
 329 int amdgpu_mes_init(struct amdgpu_device *adev);
 330 void amdgpu_mes_fini(struct amdgpu_device *adev);
 331
 332 int amdgpu_mes_create_process(struct amdgpu_device *adev, int pasid,
 333                               struct amdgpu_vm *vm);
 334 void amdgpu_mes_destroy_process(struct amdgpu_device *adev, int pasid);
 335
 336 int amdgpu_mes_add_gang(struct amdgpu_device *adev, int pasid,
 337                         struct amdgpu_mes_gang_properties *gprops,
 338                         int *gang_id);
 339 int amdgpu_mes_remove_gang(struct amdgpu_device *adev, int gang_id);
 340
 341 int amdgpu_mes_suspend(struct amdgpu_device *adev);
 342 int amdgpu_mes_resume(struct amdgpu_device *adev);
 343
 344 int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id,
 345                             struct amdgpu_mes_queue_properties *qprops,
 346                             int *queue_id);
 347 int amdgpu_mes_remove_hw_queue(struct amdgpu_device *adev, int queue_id);
 348
 349 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev,
 350                                   struct amdgpu_ring *ring,
 351                                   enum amdgpu_unmap_queues_action action,
 352                                   u64 gpu_addr, u64 seq);
 353
 354 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg);
 355 int amdgpu_mes_wreg(struct amdgpu_device *adev,
 356                     uint32_t reg, uint32_t val);
 357 int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg,
 358                         uint32_t val, uint32_t mask);
 359 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev,
 360                                   uint32_t reg0, uint32_t reg1,
 361                                   uint32_t ref, uint32_t mask);
 362 int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev,
 363                                 uint64_t process_context_addr,
 364                                 uint32_t spi_gdbg_per_vmid_cntl,
 365                                 const uint32_t *tcp_watch_cntl,
 366                                 uint32_t flags,
 367                                 bool trap_en);
 368
 369 int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id,
 370                         int queue_type, int idx,
 371                         struct amdgpu_mes_ctx_data *ctx_data,
 372                         struct amdgpu_ring **out);
 373 void amdgpu_mes_remove_ring(struct amdgpu_device *adev,
 374                             struct amdgpu_ring *ring);
 375
 376 uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev,
 377                                                    enum amdgpu_mes_priority_level prio);
 378
 379 int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev,
 380                                    struct amdgpu_mes_ctx_data *ctx_data);
 381 void amdgpu_mes_ctx_free_meta_data(struct amdgpu_mes_ctx_data *ctx_data);
 382 int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device *adev,
 383                                  struct amdgpu_vm *vm,
 384                                  struct amdgpu_mes_ctx_data *ctx_data);
 385 int amdgpu_mes_ctx_unmap_meta_data(struct amdgpu_device *adev,
 386                                    struct amdgpu_mes_ctx_data *ctx_data);
 387
 388 int amdgpu_mes_self_test(struct amdgpu_device *adev);
 389
 390 int amdgpu_mes_alloc_process_doorbells(struct amdgpu_device *adev,
 391                                         unsigned int *doorbell_index);
 392 void amdgpu_mes_free_process_doorbells(struct amdgpu_device *adev,
 393                                         unsigned int doorbell_index);
 394 unsigned int amdgpu_mes_get_doorbell_dw_offset_in_bar(
 395                                         struct amdgpu_device *adev,
 396                                         uint32_t doorbell_index,
 397                                         unsigned int doorbell_id);
 398 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev);
 399
 400 /*
 401  * MES lock can be taken in MMU notifiers.
 402  *
 403  * A bit more detail about why to set no-FS reclaim with MES lock:
 404  *
 405  * The purpose of the MMU notifier is to stop GPU access to memory so
 406  * that the Linux VM subsystem can move pages around safely. This is
 407  * done by preempting user mode queues for the affected process. When
 408  * MES is used, MES lock needs to be taken to preempt the queues.
 409  *
 410  * The MMU notifier callback entry point in the driver is
 411  * amdgpu_mn_invalidate_range_start_hsa. The relevant call chain from
 412  * there is:
 413  * amdgpu_amdkfd_evict_userptr -> kgd2kfd_quiesce_mm ->
 414  * kfd_process_evict_queues -> pdd->dev->dqm->ops.evict_process_queues
 415  *
 416  * The last part of the chain is a function pointer where we take the
 417  * MES lock.
 418  *
 419  * The problem with taking locks in the MMU notifier is, that MMU
 420  * notifiers can be called in reclaim-FS context. That's where the
 421  * kernel frees up pages to make room for new page allocations under
 422  * memory pressure. While we are running in reclaim-FS context, we must
 423  * not trigger another memory reclaim operation because that would
 424  * recursively reenter the reclaim code and cause a deadlock. The
 425  * memalloc_nofs_save/restore calls guarantee that.
 426  *
 427  * In addition we also need to avoid lock dependencies on other locks taken
 428  * under the MES lock, for example reservation locks. Here is a possible
 429  * scenario of a deadlock:
 430  * Thread A: takes and holds reservation lock | triggers reclaim-FS |
 431  * MMU notifier | blocks trying to take MES lock
 432  * Thread B: takes and holds MES lock | blocks trying to take reservation lock
 433  *
 434  * In this scenario Thread B gets involved in a deadlock even without
 435  * triggering a reclaim-FS operation itself.
 436  * To fix this and break the lock dependency chain you'd need to either:
 437  * 1. protect reservation locks with memalloc_nofs_save/restore, or
 438  * 2. avoid taking reservation locks under the MES lock.
 439  *
 440  * Reservation locks are taken all over the kernel in different subsystems, we
 441  * have no control over them and their lock dependencies.So the only workable
 442  * solution is to avoid taking other locks under the MES lock.
 443  * As a result, make sure no reclaim-FS happens while holding this lock anywhere
 444  * to prevent deadlocks when an MMU notifier runs in reclaim-FS context.
 445  */
 446 static inline void amdgpu_mes_lock(struct amdgpu_mes *mes)
 447 {
 448         mutex_lock(&mes->mutex_hidden);
 449         mes->saved_flags = memalloc_noreclaim_save();
 450 }
 451
 452 static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes)
 453 {
 454         memalloc_noreclaim_restore(mes->saved_flags);
 455         mutex_unlock(&mes->mutex_hidden);
 456 }
 457 #endif /* __AMDGPU_MES_H__ */