drivers/staging/wilc1000/wilc_spi.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) Atmel Corporation.  All rights reserved.
   4  *
   5  * Module Name:  wilc_spi.c
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/init.h>
  10 #include <linux/kernel.h>
  11 #include <linux/fs.h>
  12 #include <linux/slab.h>
  13 #include <linux/types.h>
  14 #include <linux/cdev.h>
  15 #include <linux/uaccess.h>
  16 #include <linux/device.h>
  17 #include <linux/spi/spi.h>
  18 #include <linux/of_gpio.h>
  19
  20 #include <linux/string.h>
  21 #include "wilc_wlan_if.h"
  22 #include "wilc_wlan.h"
  23 #include "wilc_wfi_netdevice.h"
  24
  25 struct wilc_spi {
  26         int crc_off;
  27         int nint;
  28         int has_thrpt_enh;
  29 };
  30
  31 static struct wilc_spi g_spi;
  32 static const struct wilc_hif_func wilc_hif_spi;
  33
  34 static int wilc_spi_read(struct wilc *wilc, u32, u8 *, u32);
  35 static int wilc_spi_write(struct wilc *wilc, u32, u8 *, u32);
  36
  37 /********************************************
  38  *
  39  *      Crc7
  40  *
  41  ********************************************/
  42
  43 static const u8 crc7_syndrome_table[256] = {
  44         0x00, 0x09, 0x12, 0x1b, 0x24, 0x2d, 0x36, 0x3f,
  45         0x48, 0x41, 0x5a, 0x53, 0x6c, 0x65, 0x7e, 0x77,
  46         0x19, 0x10, 0x0b, 0x02, 0x3d, 0x34, 0x2f, 0x26,
  47         0x51, 0x58, 0x43, 0x4a, 0x75, 0x7c, 0x67, 0x6e,
  48         0x32, 0x3b, 0x20, 0x29, 0x16, 0x1f, 0x04, 0x0d,
  49         0x7a, 0x73, 0x68, 0x61, 0x5e, 0x57, 0x4c, 0x45,
  50         0x2b, 0x22, 0x39, 0x30, 0x0f, 0x06, 0x1d, 0x14,
  51         0x63, 0x6a, 0x71, 0x78, 0x47, 0x4e, 0x55, 0x5c,
  52         0x64, 0x6d, 0x76, 0x7f, 0x40, 0x49, 0x52, 0x5b,
  53         0x2c, 0x25, 0x3e, 0x37, 0x08, 0x01, 0x1a, 0x13,
  54         0x7d, 0x74, 0x6f, 0x66, 0x59, 0x50, 0x4b, 0x42,
  55         0x35, 0x3c, 0x27, 0x2e, 0x11, 0x18, 0x03, 0x0a,
  56         0x56, 0x5f, 0x44, 0x4d, 0x72, 0x7b, 0x60, 0x69,
  57         0x1e, 0x17, 0x0c, 0x05, 0x3a, 0x33, 0x28, 0x21,
  58         0x4f, 0x46, 0x5d, 0x54, 0x6b, 0x62, 0x79, 0x70,
  59         0x07, 0x0e, 0x15, 0x1c, 0x23, 0x2a, 0x31, 0x38,
  60         0x41, 0x48, 0x53, 0x5a, 0x65, 0x6c, 0x77, 0x7e,
  61         0x09, 0x00, 0x1b, 0x12, 0x2d, 0x24, 0x3f, 0x36,
  62         0x58, 0x51, 0x4a, 0x43, 0x7c, 0x75, 0x6e, 0x67,
  63         0x10, 0x19, 0x02, 0x0b, 0x34, 0x3d, 0x26, 0x2f,
  64         0x73, 0x7a, 0x61, 0x68, 0x57, 0x5e, 0x45, 0x4c,
  65         0x3b, 0x32, 0x29, 0x20, 0x1f, 0x16, 0x0d, 0x04,
  66         0x6a, 0x63, 0x78, 0x71, 0x4e, 0x47, 0x5c, 0x55,
  67         0x22, 0x2b, 0x30, 0x39, 0x06, 0x0f, 0x14, 0x1d,
  68         0x25, 0x2c, 0x37, 0x3e, 0x01, 0x08, 0x13, 0x1a,
  69         0x6d, 0x64, 0x7f, 0x76, 0x49, 0x40, 0x5b, 0x52,
  70         0x3c, 0x35, 0x2e, 0x27, 0x18, 0x11, 0x0a, 0x03,
  71         0x74, 0x7d, 0x66, 0x6f, 0x50, 0x59, 0x42, 0x4b,
  72         0x17, 0x1e, 0x05, 0x0c, 0x33, 0x3a, 0x21, 0x28,
  73         0x5f, 0x56, 0x4d, 0x44, 0x7b, 0x72, 0x69, 0x60,
  74         0x0e, 0x07, 0x1c, 0x15, 0x2a, 0x23, 0x38, 0x31,
  75         0x46, 0x4f, 0x54, 0x5d, 0x62, 0x6b, 0x70, 0x79
  76 };
  77
  78 static u8 crc7_byte(u8 crc, u8 data)
  79 {
  80         return crc7_syndrome_table[(crc << 1) ^ data];
  81 }
  82
  83 static u8 crc7(u8 crc, const u8 *buffer, u32 len)
  84 {
  85         while (len--)
  86                 crc = crc7_byte(crc, *buffer++);
  87         return crc;
  88 }
  89
  90 /********************************************
  91  *
  92  *      Spi protocol Function
  93  *
  94  ********************************************/
  95
  96 #define CMD_DMA_WRITE                           0xc1
  97 #define CMD_DMA_READ                            0xc2
  98 #define CMD_INTERNAL_WRITE              0xc3
  99 #define CMD_INTERNAL_READ               0xc4
 100 #define CMD_TERMINATE                           0xc5
 101 #define CMD_REPEAT                                      0xc6
 102 #define CMD_DMA_EXT_WRITE               0xc7
 103 #define CMD_DMA_EXT_READ                0xc8
 104 #define CMD_SINGLE_WRITE                        0xc9
 105 #define CMD_SINGLE_READ                 0xca
 106 #define CMD_RESET                                               0xcf
 107
 108 #define N_OK                                                            1
 109 #define N_FAIL                                                          0
 110 #define N_RESET                                                 -1
 111 #define N_RETRY                                                 -2
 112
 113 #define DATA_PKT_SZ_256                         256
 114 #define DATA_PKT_SZ_512                 512
 115 #define DATA_PKT_SZ_1K                          1024
 116 #define DATA_PKT_SZ_4K                          (4 * 1024)
 117 #define DATA_PKT_SZ_8K                          (8 * 1024)
 118 #define DATA_PKT_SZ                                     DATA_PKT_SZ_8K
 119
 120 #define USE_SPI_DMA     0
 121
 122 static int wilc_bus_probe(struct spi_device *spi)
 123 {
 124         int ret, gpio;
 125         struct wilc *wilc;
 126
 127         gpio = of_get_gpio(spi->dev.of_node, 0);
 128         if (gpio < 0)
 129                 gpio = GPIO_NUM;
 130
 131         ret = wilc_netdev_init(&wilc, NULL, HIF_SPI, GPIO_NUM, &wilc_hif_spi);
 132         if (ret)
 133                 return ret;
 134
 135         spi_set_drvdata(spi, wilc);
 136         wilc->dev = &spi->dev;
 137
 138         return 0;
 139 }
 140
 141 static int wilc_bus_remove(struct spi_device *spi)
 142 {
 143         wilc_netdev_cleanup(spi_get_drvdata(spi));
 144         return 0;
 145 }
 146
 147 static const struct of_device_id wilc1000_of_match[] = {
 148         { .compatible = "atmel,wilc_spi", },
 149         {}
 150 };
 151 MODULE_DEVICE_TABLE(of, wilc1000_of_match);
 152
 153 static struct spi_driver wilc1000_spi_driver = {
 154         .driver = {
 155                 .name = MODALIAS,
 156                 .of_match_table = wilc1000_of_match,
 157         },
 158         .probe =  wilc_bus_probe,
 159         .remove = wilc_bus_remove,
 160 };
 161 module_spi_driver(wilc1000_spi_driver);
 162 MODULE_LICENSE("GPL");
 163
 164 static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len)
 165 {
 166         struct spi_device *spi = to_spi_device(wilc->dev);
 167         int ret;
 168         struct spi_message msg;
 169
 170         if (len > 0 && b) {
 171                 struct spi_transfer tr = {
 172                         .tx_buf = b,
 173                         .len = len,
 174                         .delay_usecs = 0,
 175                 };
 176                 char *r_buffer = kzalloc(len, GFP_KERNEL);
 177
 178                 if (!r_buffer)
 179                         return -ENOMEM;
 180
 181                 tr.rx_buf = r_buffer;
 182                 dev_dbg(&spi->dev, "Request writing %d bytes\n", len);
 183
 184                 memset(&msg, 0, sizeof(msg));
 185                 spi_message_init(&msg);
 186                 msg.spi = spi;
 187                 msg.is_dma_mapped = USE_SPI_DMA;
 188                 spi_message_add_tail(&tr, &msg);
 189
 190                 ret = spi_sync(spi, &msg);
 191                 if (ret < 0)
 192                         dev_err(&spi->dev, "SPI transaction failed\n");
 193
 194                 kfree(r_buffer);
 195         } else {
 196                 dev_err(&spi->dev,
 197                         "can't write data with the following length: %d\n",
 198                         len);
 199                 ret = -EINVAL;
 200         }
 201
 202         return ret;
 203 }
 204
 205 static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen)
 206 {
 207         struct spi_device *spi = to_spi_device(wilc->dev);
 208         int ret;
 209
 210         if (rlen > 0) {
 211                 struct spi_message msg;
 212                 struct spi_transfer tr = {
 213                         .rx_buf = rb,
 214                         .len = rlen,
 215                         .delay_usecs = 0,
 216
 217                 };
 218                 char *t_buffer = kzalloc(rlen, GFP_KERNEL);
 219
 220                 if (!t_buffer)
 221                         return -ENOMEM;
 222
 223                 tr.tx_buf = t_buffer;
 224
 225                 memset(&msg, 0, sizeof(msg));
 226                 spi_message_init(&msg);
 227                 msg.spi = spi;
 228                 msg.is_dma_mapped = USE_SPI_DMA;
 229                 spi_message_add_tail(&tr, &msg);
 230
 231                 ret = spi_sync(spi, &msg);
 232                 if (ret < 0)
 233                         dev_err(&spi->dev, "SPI transaction failed\n");
 234                 kfree(t_buffer);
 235         } else {
 236                 dev_err(&spi->dev,
 237                         "can't read data with the following length: %u\n",
 238                         rlen);
 239                 ret = -EINVAL;
 240         }
 241
 242         return ret;
 243 }
 244
 245 static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen)
 246 {
 247         struct spi_device *spi = to_spi_device(wilc->dev);
 248         int ret;
 249
 250         if (rlen > 0) {
 251                 struct spi_message msg;
 252                 struct spi_transfer tr = {
 253                         .rx_buf = rb,
 254                         .tx_buf = wb,
 255                         .len = rlen,
 256                         .bits_per_word = 8,
 257                         .delay_usecs = 0,
 258
 259                 };
 260
 261                 memset(&msg, 0, sizeof(msg));
 262                 spi_message_init(&msg);
 263                 msg.spi = spi;
 264                 msg.is_dma_mapped = USE_SPI_DMA;
 265
 266                 spi_message_add_tail(&tr, &msg);
 267                 ret = spi_sync(spi, &msg);
 268                 if (ret < 0)
 269                         dev_err(&spi->dev, "SPI transaction failed\n");
 270         } else {
 271                 dev_err(&spi->dev,
 272                         "can't read data with the following length: %u\n",
 273                         rlen);
 274                 ret = -EINVAL;
 275         }
 276
 277         return ret;
 278 }
 279
 280 static int spi_cmd_complete(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz,
 281                             u8 clockless)
 282 {
 283         struct spi_device *spi = to_spi_device(wilc->dev);
 284         u8 wb[32], rb[32];
 285         u8 wix, rix;
 286         u32 len2;
 287         u8 rsp;
 288         int len = 0;
 289         int result = N_OK;
 290         int retry;
 291         u8 crc[2];
 292
 293         wb[0] = cmd;
 294         switch (cmd) {
 295         case CMD_SINGLE_READ: /* single word (4 bytes) read */
 296                 wb[1] = (u8)(adr >> 16);
 297                 wb[2] = (u8)(adr >> 8);
 298                 wb[3] = (u8)adr;
 299                 len = 5;
 300                 break;
 301
 302         case CMD_INTERNAL_READ: /* internal register read */
 303                 wb[1] = (u8)(adr >> 8);
 304                 if (clockless == 1)
 305                         wb[1] |= BIT(7);
 306                 wb[2] = (u8)adr;
 307                 wb[3] = 0x00;
 308                 len = 5;
 309                 break;
 310
 311         case CMD_TERMINATE:
 312                 wb[1] = 0x00;
 313                 wb[2] = 0x00;
 314                 wb[3] = 0x00;
 315                 len = 5;
 316                 break;
 317
 318         case CMD_REPEAT:
 319                 wb[1] = 0x00;
 320                 wb[2] = 0x00;
 321                 wb[3] = 0x00;
 322                 len = 5;
 323                 break;
 324
 325         case CMD_RESET:
 326                 wb[1] = 0xff;
 327                 wb[2] = 0xff;
 328                 wb[3] = 0xff;
 329                 len = 5;
 330                 break;
 331
 332         case CMD_DMA_WRITE: /* dma write */
 333         case CMD_DMA_READ:  /* dma read */
 334                 wb[1] = (u8)(adr >> 16);
 335                 wb[2] = (u8)(adr >> 8);
 336                 wb[3] = (u8)adr;
 337                 wb[4] = (u8)(sz >> 8);
 338                 wb[5] = (u8)(sz);
 339                 len = 7;
 340                 break;
 341
 342         case CMD_DMA_EXT_WRITE: /* dma extended write */
 343         case CMD_DMA_EXT_READ:  /* dma extended read */
 344                 wb[1] = (u8)(adr >> 16);
 345                 wb[2] = (u8)(adr >> 8);
 346                 wb[3] = (u8)adr;
 347                 wb[4] = (u8)(sz >> 16);
 348                 wb[5] = (u8)(sz >> 8);
 349                 wb[6] = (u8)(sz);
 350                 len = 8;
 351                 break;
 352
 353         case CMD_INTERNAL_WRITE: /* internal register write */
 354                 wb[1] = (u8)(adr >> 8);
 355                 if (clockless == 1)
 356                         wb[1] |= BIT(7);
 357                 wb[2] = (u8)(adr);
 358                 wb[3] = b[3];
 359                 wb[4] = b[2];
 360                 wb[5] = b[1];
 361                 wb[6] = b[0];
 362                 len = 8;
 363                 break;
 364
 365         case CMD_SINGLE_WRITE: /* single word write */
 366                 wb[1] = (u8)(adr >> 16);
 367                 wb[2] = (u8)(adr >> 8);
 368                 wb[3] = (u8)(adr);
 369                 wb[4] = b[3];
 370                 wb[5] = b[2];
 371                 wb[6] = b[1];
 372                 wb[7] = b[0];
 373                 len = 9;
 374                 break;
 375
 376         default:
 377                 result = N_FAIL;
 378                 break;
 379         }
 380
 381         if (result != N_OK)
 382                 return result;
 383
 384         if (!g_spi.crc_off)
 385                 wb[len - 1] = (crc7(0x7f, (const u8 *)&wb[0], len - 1)) << 1;
 386         else
 387                 len -= 1;
 388
 389 #define NUM_SKIP_BYTES (1)
 390 #define NUM_RSP_BYTES (2)
 391 #define NUM_DATA_HDR_BYTES (1)
 392 #define NUM_DATA_BYTES (4)
 393 #define NUM_CRC_BYTES (2)
 394 #define NUM_DUMMY_BYTES (3)
 395         if (cmd == CMD_RESET ||
 396             cmd == CMD_TERMINATE ||
 397             cmd == CMD_REPEAT) {
 398                 len2 = len + (NUM_SKIP_BYTES + NUM_RSP_BYTES + NUM_DUMMY_BYTES);
 399         } else if (cmd == CMD_INTERNAL_READ || cmd == CMD_SINGLE_READ) {
 400                 int tmp = NUM_RSP_BYTES + NUM_DATA_HDR_BYTES + NUM_DATA_BYTES
 401                         + NUM_DUMMY_BYTES;
 402                 if (!g_spi.crc_off)
 403                         len2 = len + tmp + NUM_CRC_BYTES;
 404                 else
 405                         len2 = len + tmp;
 406         } else {
 407                 len2 = len + (NUM_RSP_BYTES + NUM_DUMMY_BYTES);
 408         }
 409 #undef NUM_DUMMY_BYTES
 410
 411         if (len2 > ARRAY_SIZE(wb)) {
 412                 dev_err(&spi->dev, "spi buffer size too small (%d) (%zu)\n",
 413                         len2, ARRAY_SIZE(wb));
 414                 return N_FAIL;
 415         }
 416         /* zero spi write buffers. */
 417         for (wix = len; wix < len2; wix++)
 418                 wb[wix] = 0;
 419         rix = len;
 420
 421         if (wilc_spi_tx_rx(wilc, wb, rb, len2)) {
 422                 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
 423                 return N_FAIL;
 424         }
 425
 426         /*
 427          * Command/Control response
 428          */
 429         if (cmd == CMD_RESET || cmd == CMD_TERMINATE || cmd == CMD_REPEAT)
 430                 rix++; /* skip 1 byte */
 431
 432         rsp = rb[rix++];
 433
 434         if (rsp != cmd) {
 435                 dev_err(&spi->dev,
 436                         "Failed cmd response, cmd (%02x), resp (%02x)\n",
 437                         cmd, rsp);
 438                 return N_FAIL;
 439         }
 440
 441         /*
 442          * State response
 443          */
 444         rsp = rb[rix++];
 445         if (rsp != 0x00) {
 446                 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
 447                         rsp);
 448                 return N_FAIL;
 449         }
 450
 451         if (cmd == CMD_INTERNAL_READ || cmd == CMD_SINGLE_READ ||
 452             cmd == CMD_DMA_READ || cmd == CMD_DMA_EXT_READ) {
 453                 /*
 454                  * Data Respnose header
 455                  */
 456                 retry = 100;
 457                 do {
 458                         /*
 459                          * ensure there is room in buffer later
 460                          * to read data and crc
 461                          */
 462                         if (rix < len2) {
 463                                 rsp = rb[rix++];
 464                         } else {
 465                                 retry = 0;
 466                                 break;
 467                         }
 468                         if (((rsp >> 4) & 0xf) == 0xf)
 469                                 break;
 470                 } while (retry--);
 471
 472                 if (retry <= 0) {
 473                         dev_err(&spi->dev,
 474                                 "Error, data read response (%02x)\n", rsp);
 475                         return N_RESET;
 476                 }
 477         }
 478
 479         if (cmd == CMD_INTERNAL_READ || cmd == CMD_SINGLE_READ) {
 480                 /*
 481                  * Read bytes
 482                  */
 483                 if ((rix + 3) < len2) {
 484                         b[0] = rb[rix++];
 485                         b[1] = rb[rix++];
 486                         b[2] = rb[rix++];
 487                         b[3] = rb[rix++];
 488                 } else {
 489                         dev_err(&spi->dev,
 490                                 "buffer overrun when reading data.\n");
 491                         return N_FAIL;
 492                 }
 493
 494                 if (!g_spi.crc_off) {
 495                         /*
 496                          * Read Crc
 497                          */
 498                         if ((rix + 1) < len2) {
 499                                 crc[0] = rb[rix++];
 500                                 crc[1] = rb[rix++];
 501                         } else {
 502                                 dev_err(&spi->dev,
 503                                         "buffer overrun when reading crc.\n");
 504                                 return N_FAIL;
 505                         }
 506                 }
 507         } else if ((cmd == CMD_DMA_READ) || (cmd == CMD_DMA_EXT_READ)) {
 508                 int ix;
 509
 510                 /* some data may be read in response to dummy bytes. */
 511                 for (ix = 0; (rix < len2) && (ix < sz); )
 512                         b[ix++] = rb[rix++];
 513
 514                 sz -= ix;
 515
 516                 if (sz > 0) {
 517                         int nbytes;
 518
 519                         if (sz <= (DATA_PKT_SZ - ix))
 520                                 nbytes = sz;
 521                         else
 522                                 nbytes = DATA_PKT_SZ - ix;
 523
 524                         /*
 525                          * Read bytes
 526                          */
 527                         if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
 528                                 dev_err(&spi->dev,
 529                                         "Failed block read, bus err\n");
 530                                 result = N_FAIL;
 531                                 goto _error_;
 532                         }
 533
 534                         /*
 535                          * Read Crc
 536                          */
 537                         if (!g_spi.crc_off && wilc_spi_rx(wilc, crc, 2)) {
 538                                 dev_err(&spi->dev,
 539                                         "Failed block crc read, bus err\n");
 540                                 result = N_FAIL;
 541                                 goto _error_;
 542                         }
 543
 544                         ix += nbytes;
 545                         sz -= nbytes;
 546                 }
 547
 548                 /*
 549                  * if any data in left unread,
 550                  * then read the rest using normal DMA code.
 551                  */
 552                 while (sz > 0) {
 553                         int nbytes;
 554
 555                         if (sz <= DATA_PKT_SZ)
 556                                 nbytes = sz;
 557                         else
 558                                 nbytes = DATA_PKT_SZ;
 559
 560                         /*
 561                          * read data response only on the next DMA cycles not
 562                          * the first DMA since data response header is already
 563                          * handled above for the first DMA.
 564                          */
 565                         /*
 566                          * Data Respnose header
 567                          */
 568                         retry = 10;
 569                         do {
 570                                 if (wilc_spi_rx(wilc, &rsp, 1)) {
 571                                         dev_err(&spi->dev,
 572                                                 "Failed resp read, bus err\n");
 573                                         result = N_FAIL;
 574                                         break;
 575                                 }
 576                                 if (((rsp >> 4) & 0xf) == 0xf)
 577                                         break;
 578                         } while (retry--);
 579
 580                         if (result == N_FAIL)
 581                                 break;
 582
 583                         /*
 584                          * Read bytes
 585                          */
 586                         if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
 587                                 dev_err(&spi->dev,
 588                                         "Failed block read, bus err\n");
 589                                 result = N_FAIL;
 590                                 break;
 591                         }
 592
 593                         /*
 594                          * Read Crc
 595                          */
 596                         if (!g_spi.crc_off && wilc_spi_rx(wilc, crc, 2)) {
 597                                 dev_err(&spi->dev,
 598                                         "Failed block crc read, bus err\n");
 599                                 result = N_FAIL;
 600                                 break;
 601                         }
 602
 603                         ix += nbytes;
 604                         sz -= nbytes;
 605                 }
 606         }
 607 _error_:
 608         return result;
 609 }
 610
 611 static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz)
 612 {
 613         struct spi_device *spi = to_spi_device(wilc->dev);
 614         int ix, nbytes;
 615         int result = 1;
 616         u8 cmd, order, crc[2] = {0};
 617
 618         /*
 619          * Data
 620          */
 621         ix = 0;
 622         do {
 623                 if (sz <= DATA_PKT_SZ)
 624                         nbytes = sz;
 625                 else
 626                         nbytes = DATA_PKT_SZ;
 627
 628                 /*
 629                  * Write command
 630                  */
 631                 cmd = 0xf0;
 632                 if (ix == 0) {
 633                         if (sz <= DATA_PKT_SZ)
 634
 635                                 order = 0x3;
 636                         else
 637                                 order = 0x1;
 638                 } else {
 639                         if (sz <= DATA_PKT_SZ)
 640                                 order = 0x3;
 641                         else
 642                                 order = 0x2;
 643                 }
 644                 cmd |= order;
 645                 if (wilc_spi_tx(wilc, &cmd, 1)) {
 646                         dev_err(&spi->dev,
 647                                 "Failed data block cmd write, bus error...\n");
 648                         result = N_FAIL;
 649                         break;
 650                 }
 651
 652                 /*
 653                  * Write data
 654                  */
 655                 if (wilc_spi_tx(wilc, &b[ix], nbytes)) {
 656                         dev_err(&spi->dev,
 657                                 "Failed data block write, bus error...\n");
 658                         result = N_FAIL;
 659                         break;
 660                 }
 661
 662                 /*
 663                  * Write Crc
 664                  */
 665                 if (!g_spi.crc_off) {
 666                         if (wilc_spi_tx(wilc, crc, 2)) {
 667                                 dev_err(&spi->dev, "Failed data block crc write, bus error...\n");
 668                                 result = N_FAIL;
 669                                 break;
 670                         }
 671                 }
 672
 673                 /*
 674                  * No need to wait for response
 675                  */
 676                 ix += nbytes;
 677                 sz -= nbytes;
 678         } while (sz);
 679
 680         return result;
 681 }
 682
 683 /********************************************
 684  *
 685  *      Spi Internal Read/Write Function
 686  *
 687  ********************************************/
 688
 689 static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat)
 690 {
 691         struct spi_device *spi = to_spi_device(wilc->dev);
 692         int result;
 693
 694         dat = cpu_to_le32(dat);
 695         result = spi_cmd_complete(wilc, CMD_INTERNAL_WRITE, adr, (u8 *)&dat, 4,
 696                                   0);
 697         if (result != N_OK)
 698                 dev_err(&spi->dev, "Failed internal write cmd...\n");
 699
 700         return result;
 701 }
 702
 703 static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data)
 704 {
 705         struct spi_device *spi = to_spi_device(wilc->dev);
 706         int result;
 707
 708         result = spi_cmd_complete(wilc, CMD_INTERNAL_READ, adr, (u8 *)data, 4,
 709                                   0);
 710         if (result != N_OK) {
 711                 dev_err(&spi->dev, "Failed internal read cmd...\n");
 712                 return 0;
 713         }
 714
 715         *data = cpu_to_le32(*data);
 716
 717         return 1;
 718 }
 719
 720 /********************************************
 721  *
 722  *      Spi interfaces
 723  *
 724  ********************************************/
 725
 726 static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data)
 727 {
 728         struct spi_device *spi = to_spi_device(wilc->dev);
 729         int result = N_OK;
 730         u8 cmd = CMD_SINGLE_WRITE;
 731         u8 clockless = 0;
 732
 733         data = cpu_to_le32(data);
 734         if (addr < 0x30) {
 735                 /* Clockless register */
 736                 cmd = CMD_INTERNAL_WRITE;
 737                 clockless = 1;
 738         }
 739
 740         result = spi_cmd_complete(wilc, cmd, addr, (u8 *)&data, 4, clockless);
 741         if (result != N_OK)
 742                 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr);
 743
 744         return result;
 745 }
 746
 747 static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
 748 {
 749         struct spi_device *spi = to_spi_device(wilc->dev);
 750         int result;
 751         u8 cmd = CMD_DMA_EXT_WRITE;
 752
 753         /*
 754          * has to be greated than 4
 755          */
 756         if (size <= 4)
 757                 return 0;
 758
 759         result = spi_cmd_complete(wilc, cmd, addr, NULL, size, 0);
 760         if (result != N_OK) {
 761                 dev_err(&spi->dev,
 762                         "Failed cmd, write block (%08x)...\n", addr);
 763                 return 0;
 764         }
 765
 766         /*
 767          * Data
 768          */
 769         result = spi_data_write(wilc, buf, size);
 770         if (result != N_OK)
 771                 dev_err(&spi->dev, "Failed block data write...\n");
 772
 773         return 1;
 774 }
 775
 776 static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data)
 777 {
 778         struct spi_device *spi = to_spi_device(wilc->dev);
 779         int result = N_OK;
 780         u8 cmd = CMD_SINGLE_READ;
 781         u8 clockless = 0;
 782
 783         if (addr < 0x30) {
 784                 /* dev_err(&spi->dev, "***** read addr %d\n\n", addr); */
 785                 /* Clockless register */
 786                 cmd = CMD_INTERNAL_READ;
 787                 clockless = 1;
 788         }
 789
 790         result = spi_cmd_complete(wilc, cmd, addr, (u8 *)data, 4, clockless);
 791         if (result != N_OK) {
 792                 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr);
 793                 return 0;
 794         }
 795
 796         *data = cpu_to_le32(*data);
 797
 798         return 1;
 799 }
 800
 801 static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
 802 {
 803         struct spi_device *spi = to_spi_device(wilc->dev);
 804         u8 cmd = CMD_DMA_EXT_READ;
 805         int result;
 806
 807         if (size <= 4)
 808                 return 0;
 809
 810         result = spi_cmd_complete(wilc, cmd, addr, buf, size, 0);
 811         if (result != N_OK) {
 812                 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr);
 813                 return 0;
 814         }
 815
 816         return 1;
 817 }
 818
 819 /********************************************
 820  *
 821  *      Bus interfaces
 822  *
 823  ********************************************/
 824
 825 static int _wilc_spi_deinit(struct wilc *wilc)
 826 {
 827         /*
 828          * TODO:
 829          */
 830         return 1;
 831 }
 832
 833 static int wilc_spi_init(struct wilc *wilc, bool resume)
 834 {
 835         struct spi_device *spi = to_spi_device(wilc->dev);
 836         u32 reg;
 837         u32 chipid;
 838         static int isinit;
 839
 840         if (isinit) {
 841                 if (!wilc_spi_read_reg(wilc, 0x1000, &chipid)) {
 842                         dev_err(&spi->dev, "Fail cmd read chip id...\n");
 843                         return 0;
 844                 }
 845                 return 1;
 846         }
 847
 848         memset(&g_spi, 0, sizeof(struct wilc_spi));
 849
 850         /*
 851          * configure protocol
 852          */
 853         g_spi.crc_off = 0;
 854
 855         /*
 856          * TODO: We can remove the CRC trials if there is a definite
 857          * way to reset
 858          */
 859         /* the SPI to it's initial value. */
 860         if (!spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, &reg)) {
 861                 /*
 862                  * Read failed. Try with CRC off. This might happen when module
 863                  * is removed but chip isn't reset
 864                  */
 865                 g_spi.crc_off = 1;
 866                 dev_err(&spi->dev,
 867                         "Failed read with CRC on, retrying with CRC off\n");
 868                 if (!spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, &reg)) {
 869                         /*
 870                          * Read failed with both CRC on and off,
 871                          * something went bad
 872                          */
 873                         dev_err(&spi->dev, "Failed internal read protocol\n");
 874                         return 0;
 875                 }
 876         }
 877         if (g_spi.crc_off == 0) {
 878                 reg &= ~0xc; /* disable crc checking */
 879                 reg &= ~0x70;
 880                 reg |= (0x5 << 4);
 881                 if (!spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg)) {
 882                         dev_err(&spi->dev,
 883                                 "[wilc spi %d]: Failed internal write reg\n",
 884                                 __LINE__);
 885                         return 0;
 886                 }
 887                 g_spi.crc_off = 1;
 888         }
 889
 890         /*
 891          * make sure can read back chip id correctly
 892          */
 893         if (!wilc_spi_read_reg(wilc, 0x1000, &chipid)) {
 894                 dev_err(&spi->dev, "Fail cmd read chip id...\n");
 895                 return 0;
 896         }
 897
 898         g_spi.has_thrpt_enh = 1;
 899
 900         isinit = 1;
 901
 902         return 1;
 903 }
 904
 905 static int wilc_spi_read_size(struct wilc *wilc, u32 *size)
 906 {
 907         struct spi_device *spi = to_spi_device(wilc->dev);
 908         int ret;
 909
 910         if (g_spi.has_thrpt_enh) {
 911                 ret = spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE,
 912                                         size);
 913                 *size = *size  & IRQ_DMA_WD_CNT_MASK;
 914         } else {
 915                 u32 tmp;
 916                 u32 byte_cnt;
 917
 918                 ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE,
 919                                         &byte_cnt);
 920                 if (!ret) {
 921                         dev_err(&spi->dev,
 922                                 "Failed read WILC_VMM_TO_HOST_SIZE ...\n");
 923                         goto _fail_;
 924                 }
 925                 tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
 926                 *size = tmp;
 927         }
 928
 929 _fail_:
 930         return ret;
 931 }
 932
 933 static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status)
 934 {
 935         struct spi_device *spi = to_spi_device(wilc->dev);
 936         int ret;
 937         u32 tmp;
 938         u32 byte_cnt;
 939         int happened, j;
 940         u32 unknown_mask;
 941         u32 irq_flags;
 942         int k = IRG_FLAGS_OFFSET + 5;
 943
 944         if (g_spi.has_thrpt_enh) {
 945                 ret = spi_internal_read(wilc, 0xe840 - WILC_SPI_REG_BASE,
 946                                         int_status);
 947                 return ret;
 948         }
 949         ret = wilc_spi_read_reg(wilc, WILC_VMM_TO_HOST_SIZE, &byte_cnt);
 950         if (!ret) {
 951                 dev_err(&spi->dev,
 952                         "Failed read WILC_VMM_TO_HOST_SIZE ...\n");
 953                 goto _fail_;
 954         }
 955         tmp = (byte_cnt >> 2) & IRQ_DMA_WD_CNT_MASK;
 956
 957         j = 0;
 958         do {
 959                 happened = 0;
 960
 961                 wilc_spi_read_reg(wilc, 0x1a90, &irq_flags);
 962                 tmp |= ((irq_flags >> 27) << IRG_FLAGS_OFFSET);
 963
 964                 if (g_spi.nint > 5) {
 965                         wilc_spi_read_reg(wilc, 0x1a94, &irq_flags);
 966                         tmp |= (((irq_flags >> 0) & 0x7) << k);
 967                 }
 968
 969                 unknown_mask = ~((1ul << g_spi.nint) - 1);
 970
 971                 if ((tmp >> IRG_FLAGS_OFFSET) & unknown_mask) {
 972                         dev_err(&spi->dev,
 973                                 "Unexpected interrupt(2):j=%d,tmp=%x,mask=%x\n",
 974                                 j, tmp, unknown_mask);
 975                                 happened = 1;
 976                 }
 977
 978                 j++;
 979         } while (happened);
 980
 981         *int_status = tmp;
 982
 983 _fail_:
 984         return ret;
 985 }
 986
 987 static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val)
 988 {
 989         struct spi_device *spi = to_spi_device(wilc->dev);
 990         int ret;
 991         u32 flags;
 992         u32 tbl_ctl;
 993
 994         if (g_spi.has_thrpt_enh) {
 995                 ret = spi_internal_write(wilc, 0xe844 - WILC_SPI_REG_BASE,
 996                                          val);
 997                 return ret;
 998         }
 999
1000         flags = val & (BIT(MAX_NUM_INT) - 1);
1001         if (flags) {
1002                 int i;
1003
1004                 ret = 1;
1005                 for (i = 0; i < g_spi.nint; i++) {
1006                         /*
1007                          * No matter what you write 1 or 0,
1008                          * it will clear interrupt.
1009                          */
1010                         if (flags & 1)
1011                                 ret = wilc_spi_write_reg(wilc,
1012                                                          0x10c8 + i * 4, 1);
1013                         if (!ret)
1014                                 break;
1015                         flags >>= 1;
1016                 }
1017                 if (!ret) {
1018                         dev_err(&spi->dev,
1019                                 "Failed wilc_spi_write_reg, set reg %x ...\n",
1020                                 0x10c8 + i * 4);
1021                         goto _fail_;
1022                 }
1023                 for (i = g_spi.nint; i < MAX_NUM_INT; i++) {
1024                         if (flags & 1)
1025                                 dev_err(&spi->dev,
1026                                         "Unexpected interrupt cleared %d...\n",
1027                                         i);
1028                         flags >>= 1;
1029                 }
1030         }
1031
1032         tbl_ctl = 0;
1033         /* select VMM table 0 */
1034         if ((val & SEL_VMM_TBL0) == SEL_VMM_TBL0)
1035                 tbl_ctl |= BIT(0);
1036         /* select VMM table 1 */
1037         if ((val & SEL_VMM_TBL1) == SEL_VMM_TBL1)
1038                 tbl_ctl |= BIT(1);
1039
1040         ret = wilc_spi_write_reg(wilc, WILC_VMM_TBL_CTL, tbl_ctl);
1041         if (!ret) {
1042                 dev_err(&spi->dev, "fail write reg vmm_tbl_ctl...\n");
1043                 goto _fail_;
1044         }
1045
1046         if ((val & EN_VMM) == EN_VMM) {
1047                 /*
1048                  * enable vmm transfer.
1049                  */
1050                 ret = wilc_spi_write_reg(wilc, WILC_VMM_CORE_CTL, 1);
1051                 if (!ret) {
1052                         dev_err(&spi->dev, "fail write reg vmm_core_ctl...\n");
1053                         goto _fail_;
1054                 }
1055         }
1056 _fail_:
1057         return ret;
1058 }
1059
1060 static int wilc_spi_sync_ext(struct wilc *wilc, int nint)
1061 {
1062         struct spi_device *spi = to_spi_device(wilc->dev);
1063         u32 reg;
1064         int ret, i;
1065
1066         if (nint > MAX_NUM_INT) {
1067                 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint);
1068                 return 0;
1069         }
1070
1071         g_spi.nint = nint;
1072
1073         /*
1074          * interrupt pin mux select
1075          */
1076         ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, &reg);
1077         if (!ret) {
1078                 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1079                         WILC_PIN_MUX_0);
1080                 return 0;
1081         }
1082         reg |= BIT(8);
1083         ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg);
1084         if (!ret) {
1085                 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1086                         WILC_PIN_MUX_0);
1087                 return 0;
1088         }
1089
1090         /*
1091          * interrupt enable
1092          */
1093         ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, &reg);
1094         if (!ret) {
1095                 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1096                         WILC_INTR_ENABLE);
1097                 return 0;
1098         }
1099
1100         for (i = 0; (i < 5) && (nint > 0); i++, nint--)
1101                 reg |= (BIT((27 + i)));
1102
1103         ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg);
1104         if (!ret) {
1105                 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1106                         WILC_INTR_ENABLE);
1107                 return 0;
1108         }
1109         if (nint) {
1110                 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, &reg);
1111                 if (!ret) {
1112                         dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1113                                 WILC_INTR2_ENABLE);
1114                         return 0;
1115                 }
1116
1117                 for (i = 0; (i < 3) && (nint > 0); i++, nint--)
1118                         reg |= BIT(i);
1119
1120                 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, &reg);
1121                 if (!ret) {
1122                         dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1123                                 WILC_INTR2_ENABLE);
1124                         return 0;
1125                 }
1126         }
1127
1128         return 1;
1129 }
1130
1131 /* Global spi HIF function table */
1132 static const struct wilc_hif_func wilc_hif_spi = {
1133         .hif_init = wilc_spi_init,
1134         .hif_deinit = _wilc_spi_deinit,
1135         .hif_read_reg = wilc_spi_read_reg,
1136         .hif_write_reg = wilc_spi_write_reg,
1137         .hif_block_rx = wilc_spi_read,
1138         .hif_block_tx = wilc_spi_write,
1139         .hif_read_int = wilc_spi_read_int,
1140         .hif_clear_int_ext = wilc_spi_clear_int_ext,
1141         .hif_read_size = wilc_spi_read_size,
1142         .hif_block_tx_ext = wilc_spi_write,
1143         .hif_block_rx_ext = wilc_spi_read,
1144         .hif_sync_ext = wilc_spi_sync_ext,
1145 };