drivers/spi/spi-imx.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 // Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3 // Copyright (C) 2008 Juergen Beisert
   4
   5 #include <linux/clk.h>
   6 #include <linux/completion.h>
   7 #include <linux/delay.h>
   8 #include <linux/dmaengine.h>
   9 #include <linux/dma-mapping.h>
  10 #include <linux/err.h>
  11 #include <linux/gpio.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/irq.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/slab.h>
  19 #include <linux/spi/spi.h>
  20 #include <linux/spi/spi_bitbang.h>
  21 #include <linux/types.h>
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include <linux/of_gpio.h>
  25
  26 #include <linux/platform_data/dma-imx.h>
  27 #include <linux/platform_data/spi-imx.h>
  28
  29 #define DRIVER_NAME "spi_imx"
  30
  31 #define MXC_CSPIRXDATA          0x00
  32 #define MXC_CSPITXDATA          0x04
  33 #define MXC_CSPICTRL            0x08
  34 #define MXC_CSPIINT             0x0c
  35 #define MXC_RESET               0x1c
  36
  37 /* generic defines to abstract from the different register layouts */
  38 #define MXC_INT_RR      (1 << 0) /* Receive data ready interrupt */
  39 #define MXC_INT_TE      (1 << 1) /* Transmit FIFO empty interrupt */
  40 #define MXC_INT_RDR     BIT(4) /* Receive date threshold interrupt */
  41
  42 /* The maximum  bytes that a sdma BD can transfer.*/
  43 #define MAX_SDMA_BD_BYTES  (1 << 15)
  44 #define MX51_ECSPI_CTRL_MAX_BURST       512
  45 /* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/
  46 #define MX53_MAX_TRANSFER_BYTES         512
  47
  48 enum spi_imx_devtype {
  49         IMX1_CSPI,
  50         IMX21_CSPI,
  51         IMX27_CSPI,
  52         IMX31_CSPI,
  53         IMX35_CSPI,     /* CSPI on all i.mx except above */
  54         IMX51_ECSPI,    /* ECSPI on i.mx51 */
  55         IMX53_ECSPI,    /* ECSPI on i.mx53 and later */
  56 };
  57
  58 struct spi_imx_data;
  59
  60 struct spi_imx_devtype_data {
  61         void (*intctrl)(struct spi_imx_data *, int);
  62         int (*config)(struct spi_device *);
  63         void (*trigger)(struct spi_imx_data *);
  64         int (*rx_available)(struct spi_imx_data *);
  65         void (*reset)(struct spi_imx_data *);
  66         void (*disable)(struct spi_imx_data *);
  67         bool has_dmamode;
  68         bool has_slavemode;
  69         unsigned int fifo_size;
  70         bool dynamic_burst;
  71         enum spi_imx_devtype devtype;
  72 };
  73
  74 struct spi_imx_data {
  75         struct spi_bitbang bitbang;
  76         struct device *dev;
  77
  78         struct completion xfer_done;
  79         void __iomem *base;
  80         unsigned long base_phys;
  81
  82         struct clk *clk_per;
  83         struct clk *clk_ipg;
  84         unsigned long spi_clk;
  85         unsigned int spi_bus_clk;
  86
  87         unsigned int speed_hz;
  88         unsigned int bits_per_word;
  89         unsigned int spi_drctl;
  90
  91         unsigned int count, remainder;
  92         void (*tx)(struct spi_imx_data *);
  93         void (*rx)(struct spi_imx_data *);
  94         void *rx_buf;
  95         const void *tx_buf;
  96         unsigned int txfifo; /* number of words pushed in tx FIFO */
  97         unsigned int dynamic_burst, read_u32;
  98         unsigned int word_mask;
  99
 100         /* Slave mode */
 101         bool slave_mode;
 102         bool slave_aborted;
 103         unsigned int slave_burst;
 104
 105         /* DMA */
 106         bool usedma;
 107         u32 wml;
 108         struct completion dma_rx_completion;
 109         struct completion dma_tx_completion;
 110
 111         const struct spi_imx_devtype_data *devtype_data;
 112 };
 113
 114 static inline int is_imx27_cspi(struct spi_imx_data *d)
 115 {
 116         return d->devtype_data->devtype == IMX27_CSPI;
 117 }
 118
 119 static inline int is_imx35_cspi(struct spi_imx_data *d)
 120 {
 121         return d->devtype_data->devtype == IMX35_CSPI;
 122 }
 123
 124 static inline int is_imx51_ecspi(struct spi_imx_data *d)
 125 {
 126         return d->devtype_data->devtype == IMX51_ECSPI;
 127 }
 128
 129 static inline int is_imx53_ecspi(struct spi_imx_data *d)
 130 {
 131         return d->devtype_data->devtype == IMX53_ECSPI;
 132 }
 133
 134 #define MXC_SPI_BUF_RX(type)                                            \
 135 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx)         \
 136 {                                                                       \
 137         unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);       \
 138                                                                         \
 139         if (spi_imx->rx_buf) {                                          \
 140                 *(type *)spi_imx->rx_buf = val;                         \
 141                 spi_imx->rx_buf += sizeof(type);                        \
 142         }                                                               \
 143 }
 144
 145 #define MXC_SPI_BUF_TX(type)                                            \
 146 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx)         \
 147 {                                                                       \
 148         type val = 0;                                                   \
 149                                                                         \
 150         if (spi_imx->tx_buf) {                                          \
 151                 val = *(type *)spi_imx->tx_buf;                         \
 152                 spi_imx->tx_buf += sizeof(type);                        \
 153         }                                                               \
 154                                                                         \
 155         spi_imx->count -= sizeof(type);                                 \
 156                                                                         \
 157         writel(val, spi_imx->base + MXC_CSPITXDATA);                    \
 158 }
 159
 160 MXC_SPI_BUF_RX(u8)
 161 MXC_SPI_BUF_TX(u8)
 162 MXC_SPI_BUF_RX(u16)
 163 MXC_SPI_BUF_TX(u16)
 164 MXC_SPI_BUF_RX(u32)
 165 MXC_SPI_BUF_TX(u32)
 166
 167 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
 168  * (which is currently not the case in this driver)
 169  */
 170 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
 171         256, 384, 512, 768, 1024};
 172
 173 /* MX21, MX27 */
 174 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
 175                 unsigned int fspi, unsigned int max, unsigned int *fres)
 176 {
 177         int i;
 178
 179         for (i = 2; i < max; i++)
 180                 if (fspi * mxc_clkdivs[i] >= fin)
 181                         break;
 182
 183         *fres = fin / mxc_clkdivs[i];
 184         return i;
 185 }
 186
 187 /* MX1, MX31, MX35, MX51 CSPI */
 188 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
 189                 unsigned int fspi, unsigned int *fres)
 190 {
 191         int i, div = 4;
 192
 193         for (i = 0; i < 7; i++) {
 194                 if (fspi * div >= fin)
 195                         goto out;
 196                 div <<= 1;
 197         }
 198
 199 out:
 200         *fres = fin / div;
 201         return i;
 202 }
 203
 204 static int spi_imx_bytes_per_word(const int bits_per_word)
 205 {
 206         return DIV_ROUND_UP(bits_per_word, BITS_PER_BYTE);
 207 }
 208
 209 static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
 210                          struct spi_transfer *transfer)
 211 {
 212         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
 213         unsigned int bytes_per_word, i;
 214
 215         if (!master->dma_rx)
 216                 return false;
 217
 218         if (spi_imx->slave_mode)
 219                 return false;
 220
 221         bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
 222
 223         if (bytes_per_word != 1 && bytes_per_word != 2 && bytes_per_word != 4)
 224                 return false;
 225
 226         for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
 227                 if (!(transfer->len % (i * bytes_per_word)))
 228                         break;
 229         }
 230
 231         if (i == 0)
 232                 return false;
 233
 234         spi_imx->wml = i;
 235         spi_imx->dynamic_burst = 0;
 236
 237         return true;
 238 }
 239
 240 #define MX51_ECSPI_CTRL         0x08
 241 #define MX51_ECSPI_CTRL_ENABLE          (1 <<  0)
 242 #define MX51_ECSPI_CTRL_XCH             (1 <<  2)
 243 #define MX51_ECSPI_CTRL_SMC             (1 << 3)
 244 #define MX51_ECSPI_CTRL_MODE_MASK       (0xf << 4)
 245 #define MX51_ECSPI_CTRL_DRCTL(drctl)    ((drctl) << 16)
 246 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET  8
 247 #define MX51_ECSPI_CTRL_PREDIV_OFFSET   12
 248 #define MX51_ECSPI_CTRL_CS(cs)          ((cs) << 18)
 249 #define MX51_ECSPI_CTRL_BL_OFFSET       20
 250 #define MX51_ECSPI_CTRL_BL_MASK         (0xfff << 20)
 251
 252 #define MX51_ECSPI_CONFIG       0x0c
 253 #define MX51_ECSPI_CONFIG_SCLKPHA(cs)   (1 << ((cs) +  0))
 254 #define MX51_ECSPI_CONFIG_SCLKPOL(cs)   (1 << ((cs) +  4))
 255 #define MX51_ECSPI_CONFIG_SBBCTRL(cs)   (1 << ((cs) +  8))
 256 #define MX51_ECSPI_CONFIG_SSBPOL(cs)    (1 << ((cs) + 12))
 257 #define MX51_ECSPI_CONFIG_SCLKCTL(cs)   (1 << ((cs) + 20))
 258
 259 #define MX51_ECSPI_INT          0x10
 260 #define MX51_ECSPI_INT_TEEN             (1 <<  0)
 261 #define MX51_ECSPI_INT_RREN             (1 <<  3)
 262 #define MX51_ECSPI_INT_RDREN            (1 <<  4)
 263
 264 #define MX51_ECSPI_DMA      0x14
 265 #define MX51_ECSPI_DMA_TX_WML(wml)      ((wml) & 0x3f)
 266 #define MX51_ECSPI_DMA_RX_WML(wml)      (((wml) & 0x3f) << 16)
 267 #define MX51_ECSPI_DMA_RXT_WML(wml)     (((wml) & 0x3f) << 24)
 268
 269 #define MX51_ECSPI_DMA_TEDEN            (1 << 7)
 270 #define MX51_ECSPI_DMA_RXDEN            (1 << 23)
 271 #define MX51_ECSPI_DMA_RXTDEN           (1 << 31)
 272
 273 #define MX51_ECSPI_STAT         0x18
 274 #define MX51_ECSPI_STAT_RR              (1 <<  3)
 275
 276 #define MX51_ECSPI_TESTREG      0x20
 277 #define MX51_ECSPI_TESTREG_LBC  BIT(31)
 278
 279 static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx)
 280 {
 281         unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);
 282 #ifdef __LITTLE_ENDIAN
 283         unsigned int bytes_per_word;
 284 #endif
 285
 286         if (spi_imx->rx_buf) {
 287 #ifdef __LITTLE_ENDIAN
 288                 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
 289                 if (bytes_per_word == 1)
 290                         val = cpu_to_be32(val);
 291                 else if (bytes_per_word == 2)
 292                         val = (val << 16) | (val >> 16);
 293 #endif
 294                 val &= spi_imx->word_mask;
 295                 *(u32 *)spi_imx->rx_buf = val;
 296                 spi_imx->rx_buf += sizeof(u32);
 297         }
 298 }
 299
 300 static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx)
 301 {
 302         unsigned int bytes_per_word;
 303
 304         bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
 305         if (spi_imx->read_u32) {
 306                 spi_imx_buf_rx_swap_u32(spi_imx);
 307                 return;
 308         }
 309
 310         if (bytes_per_word == 1)
 311                 spi_imx_buf_rx_u8(spi_imx);
 312         else if (bytes_per_word == 2)
 313                 spi_imx_buf_rx_u16(spi_imx);
 314 }
 315
 316 static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx)
 317 {
 318         u32 val = 0;
 319 #ifdef __LITTLE_ENDIAN
 320         unsigned int bytes_per_word;
 321 #endif
 322
 323         if (spi_imx->tx_buf) {
 324                 val = *(u32 *)spi_imx->tx_buf;
 325                 val &= spi_imx->word_mask;
 326                 spi_imx->tx_buf += sizeof(u32);
 327         }
 328
 329         spi_imx->count -= sizeof(u32);
 330 #ifdef __LITTLE_ENDIAN
 331         bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
 332
 333         if (bytes_per_word == 1)
 334                 val = cpu_to_be32(val);
 335         else if (bytes_per_word == 2)
 336                 val = (val << 16) | (val >> 16);
 337 #endif
 338         writel(val, spi_imx->base + MXC_CSPITXDATA);
 339 }
 340
 341 static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx)
 342 {
 343         u32 ctrl, val;
 344         unsigned int bytes_per_word;
 345
 346         if (spi_imx->count == spi_imx->remainder) {
 347                 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
 348                 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
 349                 if (spi_imx->count > MX51_ECSPI_CTRL_MAX_BURST) {
 350                         spi_imx->remainder = spi_imx->count %
 351                                              MX51_ECSPI_CTRL_MAX_BURST;
 352                         val = MX51_ECSPI_CTRL_MAX_BURST * 8 - 1;
 353                 } else if (spi_imx->count >= sizeof(u32)) {
 354                         spi_imx->remainder = spi_imx->count % sizeof(u32);
 355                         val = (spi_imx->count - spi_imx->remainder) * 8 - 1;
 356                 } else {
 357                         spi_imx->remainder = 0;
 358                         val = spi_imx->bits_per_word - 1;
 359                         spi_imx->read_u32 = 0;
 360                 }
 361
 362                 ctrl |= (val << MX51_ECSPI_CTRL_BL_OFFSET);
 363                 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
 364         }
 365
 366         if (spi_imx->count >= sizeof(u32)) {
 367                 spi_imx_buf_tx_swap_u32(spi_imx);
 368                 return;
 369         }
 370
 371         bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
 372
 373         if (bytes_per_word == 1)
 374                 spi_imx_buf_tx_u8(spi_imx);
 375         else if (bytes_per_word == 2)
 376                 spi_imx_buf_tx_u16(spi_imx);
 377 }
 378
 379 static void mx53_ecspi_rx_slave(struct spi_imx_data *spi_imx)
 380 {
 381         u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA));
 382
 383         if (spi_imx->rx_buf) {
 384                 int n_bytes = spi_imx->slave_burst % sizeof(val);
 385
 386                 if (!n_bytes)
 387                         n_bytes = sizeof(val);
 388
 389                 memcpy(spi_imx->rx_buf,
 390                        ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes);
 391
 392                 spi_imx->rx_buf += n_bytes;
 393                 spi_imx->slave_burst -= n_bytes;
 394         }
 395 }
 396
 397 static void mx53_ecspi_tx_slave(struct spi_imx_data *spi_imx)
 398 {
 399         u32 val = 0;
 400         int n_bytes = spi_imx->count % sizeof(val);
 401
 402         if (!n_bytes)
 403                 n_bytes = sizeof(val);
 404
 405         if (spi_imx->tx_buf) {
 406                 memcpy(((u8 *)&val) + sizeof(val) - n_bytes,
 407                        spi_imx->tx_buf, n_bytes);
 408                 val = cpu_to_be32(val);
 409                 spi_imx->tx_buf += n_bytes;
 410         }
 411
 412         spi_imx->count -= n_bytes;
 413
 414         writel(val, spi_imx->base + MXC_CSPITXDATA);
 415 }
 416
 417 /* MX51 eCSPI */
 418 static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
 419                                       unsigned int fspi, unsigned int *fres)
 420 {
 421         /*
 422          * there are two 4-bit dividers, the pre-divider divides by
 423          * $pre, the post-divider by 2^$post
 424          */
 425         unsigned int pre, post;
 426         unsigned int fin = spi_imx->spi_clk;
 427
 428         if (unlikely(fspi > fin))
 429                 return 0;
 430
 431         post = fls(fin) - fls(fspi);
 432         if (fin > fspi << post)
 433                 post++;
 434
 435         /* now we have: (fin <= fspi << post) with post being minimal */
 436
 437         post = max(4U, post) - 4;
 438         if (unlikely(post > 0xf)) {
 439                 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
 440                                 fspi, fin);
 441                 return 0xff;
 442         }
 443
 444         pre = DIV_ROUND_UP(fin, fspi << post) - 1;
 445
 446         dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
 447                         __func__, fin, fspi, post, pre);
 448
 449         /* Resulting frequency for the SCLK line. */
 450         *fres = (fin / (pre + 1)) >> post;
 451
 452         return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
 453                 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
 454 }
 455
 456 static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
 457 {
 458         unsigned val = 0;
 459
 460         if (enable & MXC_INT_TE)
 461                 val |= MX51_ECSPI_INT_TEEN;
 462
 463         if (enable & MXC_INT_RR)
 464                 val |= MX51_ECSPI_INT_RREN;
 465
 466         if (enable & MXC_INT_RDR)
 467                 val |= MX51_ECSPI_INT_RDREN;
 468
 469         writel(val, spi_imx->base + MX51_ECSPI_INT);
 470 }
 471
 472 static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
 473 {
 474         u32 reg;
 475
 476         reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
 477         reg |= MX51_ECSPI_CTRL_XCH;
 478         writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
 479 }
 480
 481 static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
 482 {
 483         u32 ctrl;
 484
 485         ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
 486         ctrl &= ~MX51_ECSPI_CTRL_ENABLE;
 487         writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
 488 }
 489
 490 static int mx51_ecspi_config(struct spi_device *spi)
 491 {
 492         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 493         u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
 494         u32 clk = spi_imx->speed_hz, delay, reg;
 495         u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
 496
 497         /* set Master or Slave mode */
 498         if (spi_imx->slave_mode)
 499                 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK;
 500         else
 501                 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
 502
 503         /*
 504          * Enable SPI_RDY handling (falling edge/level triggered).
 505          */
 506         if (spi->mode & SPI_READY)
 507                 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
 508
 509         /* set clock speed */
 510         ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->speed_hz, &clk);
 511         spi_imx->spi_bus_clk = clk;
 512
 513         /* set chip select to use */
 514         ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
 515
 516         if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
 517                 ctrl |= (spi_imx->slave_burst * 8 - 1)
 518                         << MX51_ECSPI_CTRL_BL_OFFSET;
 519         else
 520                 ctrl |= (spi_imx->bits_per_word - 1)
 521                         << MX51_ECSPI_CTRL_BL_OFFSET;
 522
 523         /*
 524          * eCSPI burst completion by Chip Select signal in Slave mode
 525          * is not functional for imx53 Soc, config SPI burst completed when
 526          * BURST_LENGTH + 1 bits are received
 527          */
 528         if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
 529                 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
 530         else
 531                 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
 532
 533         if (spi->mode & SPI_CPHA)
 534                 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
 535         else
 536                 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
 537
 538         if (spi->mode & SPI_CPOL) {
 539                 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
 540                 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
 541         } else {
 542                 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
 543                 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
 544         }
 545         if (spi->mode & SPI_CS_HIGH)
 546                 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
 547         else
 548                 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
 549
 550         if (spi_imx->usedma)
 551                 ctrl |= MX51_ECSPI_CTRL_SMC;
 552
 553         /* CTRL register always go first to bring out controller from reset */
 554         writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
 555
 556         reg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
 557         if (spi->mode & SPI_LOOP)
 558                 reg |= MX51_ECSPI_TESTREG_LBC;
 559         else
 560                 reg &= ~MX51_ECSPI_TESTREG_LBC;
 561         writel(reg, spi_imx->base + MX51_ECSPI_TESTREG);
 562
 563         writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
 564
 565         /*
 566          * Wait until the changes in the configuration register CONFIGREG
 567          * propagate into the hardware. It takes exactly one tick of the
 568          * SCLK clock, but we will wait two SCLK clock just to be sure. The
 569          * effect of the delay it takes for the hardware to apply changes
 570          * is noticable if the SCLK clock run very slow. In such a case, if
 571          * the polarity of SCLK should be inverted, the GPIO ChipSelect might
 572          * be asserted before the SCLK polarity changes, which would disrupt
 573          * the SPI communication as the device on the other end would consider
 574          * the change of SCLK polarity as a clock tick already.
 575          */
 576         delay = (2 * 1000000) / clk;
 577         if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
 578                 udelay(delay);
 579         else                    /* SCLK is _very_ slow */
 580                 usleep_range(delay, delay + 10);
 581
 582         /*
 583          * Configure the DMA register: setup the watermark
 584          * and enable DMA request.
 585          */
 586
 587         writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml) |
 588                 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
 589                 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
 590                 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
 591                 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
 592
 593         return 0;
 594 }
 595
 596 static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
 597 {
 598         return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
 599 }
 600
 601 static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
 602 {
 603         /* drain receive buffer */
 604         while (mx51_ecspi_rx_available(spi_imx))
 605                 readl(spi_imx->base + MXC_CSPIRXDATA);
 606 }
 607
 608 #define MX31_INTREG_TEEN        (1 << 0)
 609 #define MX31_INTREG_RREN        (1 << 3)
 610
 611 #define MX31_CSPICTRL_ENABLE    (1 << 0)
 612 #define MX31_CSPICTRL_MASTER    (1 << 1)
 613 #define MX31_CSPICTRL_XCH       (1 << 2)
 614 #define MX31_CSPICTRL_SMC       (1 << 3)
 615 #define MX31_CSPICTRL_POL       (1 << 4)
 616 #define MX31_CSPICTRL_PHA       (1 << 5)
 617 #define MX31_CSPICTRL_SSCTL     (1 << 6)
 618 #define MX31_CSPICTRL_SSPOL     (1 << 7)
 619 #define MX31_CSPICTRL_BC_SHIFT  8
 620 #define MX35_CSPICTRL_BL_SHIFT  20
 621 #define MX31_CSPICTRL_CS_SHIFT  24
 622 #define MX35_CSPICTRL_CS_SHIFT  12
 623 #define MX31_CSPICTRL_DR_SHIFT  16
 624
 625 #define MX31_CSPI_DMAREG        0x10
 626 #define MX31_DMAREG_RH_DEN      (1<<4)
 627 #define MX31_DMAREG_TH_DEN      (1<<1)
 628
 629 #define MX31_CSPISTATUS         0x14
 630 #define MX31_STATUS_RR          (1 << 3)
 631
 632 #define MX31_CSPI_TESTREG       0x1C
 633 #define MX31_TEST_LBC           (1 << 14)
 634
 635 /* These functions also work for the i.MX35, but be aware that
 636  * the i.MX35 has a slightly different register layout for bits
 637  * we do not use here.
 638  */
 639 static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
 640 {
 641         unsigned int val = 0;
 642
 643         if (enable & MXC_INT_TE)
 644                 val |= MX31_INTREG_TEEN;
 645         if (enable & MXC_INT_RR)
 646                 val |= MX31_INTREG_RREN;
 647
 648         writel(val, spi_imx->base + MXC_CSPIINT);
 649 }
 650
 651 static void mx31_trigger(struct spi_imx_data *spi_imx)
 652 {
 653         unsigned int reg;
 654
 655         reg = readl(spi_imx->base + MXC_CSPICTRL);
 656         reg |= MX31_CSPICTRL_XCH;
 657         writel(reg, spi_imx->base + MXC_CSPICTRL);
 658 }
 659
 660 static int mx31_config(struct spi_device *spi)
 661 {
 662         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 663         unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
 664         unsigned int clk;
 665
 666         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->speed_hz, &clk) <<
 667                 MX31_CSPICTRL_DR_SHIFT;
 668         spi_imx->spi_bus_clk = clk;
 669
 670         if (is_imx35_cspi(spi_imx)) {
 671                 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT;
 672                 reg |= MX31_CSPICTRL_SSCTL;
 673         } else {
 674                 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT;
 675         }
 676
 677         if (spi->mode & SPI_CPHA)
 678                 reg |= MX31_CSPICTRL_PHA;
 679         if (spi->mode & SPI_CPOL)
 680                 reg |= MX31_CSPICTRL_POL;
 681         if (spi->mode & SPI_CS_HIGH)
 682                 reg |= MX31_CSPICTRL_SSPOL;
 683         if (!gpio_is_valid(spi->cs_gpio))
 684                 reg |= (spi->chip_select) <<
 685                         (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
 686                                                   MX31_CSPICTRL_CS_SHIFT);
 687
 688         if (spi_imx->usedma)
 689                 reg |= MX31_CSPICTRL_SMC;
 690
 691         writel(reg, spi_imx->base + MXC_CSPICTRL);
 692
 693         reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
 694         if (spi->mode & SPI_LOOP)
 695                 reg |= MX31_TEST_LBC;
 696         else
 697                 reg &= ~MX31_TEST_LBC;
 698         writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
 699
 700         if (spi_imx->usedma) {
 701                 /* configure DMA requests when RXFIFO is half full and
 702                    when TXFIFO is half empty */
 703                 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
 704                         spi_imx->base + MX31_CSPI_DMAREG);
 705         }
 706
 707         return 0;
 708 }
 709
 710 static int mx31_rx_available(struct spi_imx_data *spi_imx)
 711 {
 712         return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
 713 }
 714
 715 static void mx31_reset(struct spi_imx_data *spi_imx)
 716 {
 717         /* drain receive buffer */
 718         while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
 719                 readl(spi_imx->base + MXC_CSPIRXDATA);
 720 }
 721
 722 #define MX21_INTREG_RR          (1 << 4)
 723 #define MX21_INTREG_TEEN        (1 << 9)
 724 #define MX21_INTREG_RREN        (1 << 13)
 725
 726 #define MX21_CSPICTRL_POL       (1 << 5)
 727 #define MX21_CSPICTRL_PHA       (1 << 6)
 728 #define MX21_CSPICTRL_SSPOL     (1 << 8)
 729 #define MX21_CSPICTRL_XCH       (1 << 9)
 730 #define MX21_CSPICTRL_ENABLE    (1 << 10)
 731 #define MX21_CSPICTRL_MASTER    (1 << 11)
 732 #define MX21_CSPICTRL_DR_SHIFT  14
 733 #define MX21_CSPICTRL_CS_SHIFT  19
 734
 735 static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
 736 {
 737         unsigned int val = 0;
 738
 739         if (enable & MXC_INT_TE)
 740                 val |= MX21_INTREG_TEEN;
 741         if (enable & MXC_INT_RR)
 742                 val |= MX21_INTREG_RREN;
 743
 744         writel(val, spi_imx->base + MXC_CSPIINT);
 745 }
 746
 747 static void mx21_trigger(struct spi_imx_data *spi_imx)
 748 {
 749         unsigned int reg;
 750
 751         reg = readl(spi_imx->base + MXC_CSPICTRL);
 752         reg |= MX21_CSPICTRL_XCH;
 753         writel(reg, spi_imx->base + MXC_CSPICTRL);
 754 }
 755
 756 static int mx21_config(struct spi_device *spi)
 757 {
 758         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 759         unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
 760         unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
 761         unsigned int clk;
 762
 763         reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->speed_hz, max, &clk)
 764                 << MX21_CSPICTRL_DR_SHIFT;
 765         spi_imx->spi_bus_clk = clk;
 766
 767         reg |= spi_imx->bits_per_word - 1;
 768
 769         if (spi->mode & SPI_CPHA)
 770                 reg |= MX21_CSPICTRL_PHA;
 771         if (spi->mode & SPI_CPOL)
 772                 reg |= MX21_CSPICTRL_POL;
 773         if (spi->mode & SPI_CS_HIGH)
 774                 reg |= MX21_CSPICTRL_SSPOL;
 775         if (!gpio_is_valid(spi->cs_gpio))
 776                 reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT;
 777
 778         writel(reg, spi_imx->base + MXC_CSPICTRL);
 779
 780         return 0;
 781 }
 782
 783 static int mx21_rx_available(struct spi_imx_data *spi_imx)
 784 {
 785         return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
 786 }
 787
 788 static void mx21_reset(struct spi_imx_data *spi_imx)
 789 {
 790         writel(1, spi_imx->base + MXC_RESET);
 791 }
 792
 793 #define MX1_INTREG_RR           (1 << 3)
 794 #define MX1_INTREG_TEEN         (1 << 8)
 795 #define MX1_INTREG_RREN         (1 << 11)
 796
 797 #define MX1_CSPICTRL_POL        (1 << 4)
 798 #define MX1_CSPICTRL_PHA        (1 << 5)
 799 #define MX1_CSPICTRL_XCH        (1 << 8)
 800 #define MX1_CSPICTRL_ENABLE     (1 << 9)
 801 #define MX1_CSPICTRL_MASTER     (1 << 10)
 802 #define MX1_CSPICTRL_DR_SHIFT   13
 803
 804 static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
 805 {
 806         unsigned int val = 0;
 807
 808         if (enable & MXC_INT_TE)
 809                 val |= MX1_INTREG_TEEN;
 810         if (enable & MXC_INT_RR)
 811                 val |= MX1_INTREG_RREN;
 812
 813         writel(val, spi_imx->base + MXC_CSPIINT);
 814 }
 815
 816 static void mx1_trigger(struct spi_imx_data *spi_imx)
 817 {
 818         unsigned int reg;
 819
 820         reg = readl(spi_imx->base + MXC_CSPICTRL);
 821         reg |= MX1_CSPICTRL_XCH;
 822         writel(reg, spi_imx->base + MXC_CSPICTRL);
 823 }
 824
 825 static int mx1_config(struct spi_device *spi)
 826 {
 827         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
 828         unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
 829         unsigned int clk;
 830
 831         reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->speed_hz, &clk) <<
 832                 MX1_CSPICTRL_DR_SHIFT;
 833         spi_imx->spi_bus_clk = clk;
 834
 835         reg |= spi_imx->bits_per_word - 1;
 836
 837         if (spi->mode & SPI_CPHA)
 838                 reg |= MX1_CSPICTRL_PHA;
 839         if (spi->mode & SPI_CPOL)
 840                 reg |= MX1_CSPICTRL_POL;
 841
 842         writel(reg, spi_imx->base + MXC_CSPICTRL);
 843
 844         return 0;
 845 }
 846
 847 static int mx1_rx_available(struct spi_imx_data *spi_imx)
 848 {
 849         return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
 850 }
 851
 852 static void mx1_reset(struct spi_imx_data *spi_imx)
 853 {
 854         writel(1, spi_imx->base + MXC_RESET);
 855 }
 856
 857 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
 858         .intctrl = mx1_intctrl,
 859         .config = mx1_config,
 860         .trigger = mx1_trigger,
 861         .rx_available = mx1_rx_available,
 862         .reset = mx1_reset,
 863         .fifo_size = 8,
 864         .has_dmamode = false,
 865         .dynamic_burst = false,
 866         .has_slavemode = false,
 867         .devtype = IMX1_CSPI,
 868 };
 869
 870 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
 871         .intctrl = mx21_intctrl,
 872         .config = mx21_config,
 873         .trigger = mx21_trigger,
 874         .rx_available = mx21_rx_available,
 875         .reset = mx21_reset,
 876         .fifo_size = 8,
 877         .has_dmamode = false,
 878         .dynamic_burst = false,
 879         .has_slavemode = false,
 880         .devtype = IMX21_CSPI,
 881 };
 882
 883 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
 884         /* i.mx27 cspi shares the functions with i.mx21 one */
 885         .intctrl = mx21_intctrl,
 886         .config = mx21_config,
 887         .trigger = mx21_trigger,
 888         .rx_available = mx21_rx_available,
 889         .reset = mx21_reset,
 890         .fifo_size = 8,
 891         .has_dmamode = false,
 892         .dynamic_burst = false,
 893         .has_slavemode = false,
 894         .devtype = IMX27_CSPI,
 895 };
 896
 897 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
 898         .intctrl = mx31_intctrl,
 899         .config = mx31_config,
 900         .trigger = mx31_trigger,
 901         .rx_available = mx31_rx_available,
 902         .reset = mx31_reset,
 903         .fifo_size = 8,
 904         .has_dmamode = false,
 905         .dynamic_burst = false,
 906         .has_slavemode = false,
 907         .devtype = IMX31_CSPI,
 908 };
 909
 910 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
 911         /* i.mx35 and later cspi shares the functions with i.mx31 one */
 912         .intctrl = mx31_intctrl,
 913         .config = mx31_config,
 914         .trigger = mx31_trigger,
 915         .rx_available = mx31_rx_available,
 916         .reset = mx31_reset,
 917         .fifo_size = 8,
 918         .has_dmamode = true,
 919         .dynamic_burst = false,
 920         .has_slavemode = false,
 921         .devtype = IMX35_CSPI,
 922 };
 923
 924 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
 925         .intctrl = mx51_ecspi_intctrl,
 926         .config = mx51_ecspi_config,
 927         .trigger = mx51_ecspi_trigger,
 928         .rx_available = mx51_ecspi_rx_available,
 929         .reset = mx51_ecspi_reset,
 930         .fifo_size = 64,
 931         .has_dmamode = true,
 932         .dynamic_burst = true,
 933         .has_slavemode = true,
 934         .disable = mx51_ecspi_disable,
 935         .devtype = IMX51_ECSPI,
 936 };
 937
 938 static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
 939         .intctrl = mx51_ecspi_intctrl,
 940         .config = mx51_ecspi_config,
 941         .trigger = mx51_ecspi_trigger,
 942         .rx_available = mx51_ecspi_rx_available,
 943         .reset = mx51_ecspi_reset,
 944         .fifo_size = 64,
 945         .has_dmamode = true,
 946         .has_slavemode = true,
 947         .disable = mx51_ecspi_disable,
 948         .devtype = IMX53_ECSPI,
 949 };
 950
 951 static const struct platform_device_id spi_imx_devtype[] = {
 952         {
 953                 .name = "imx1-cspi",
 954                 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
 955         }, {
 956                 .name = "imx21-cspi",
 957                 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
 958         }, {
 959                 .name = "imx27-cspi",
 960                 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
 961         }, {
 962                 .name = "imx31-cspi",
 963                 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
 964         }, {
 965                 .name = "imx35-cspi",
 966                 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
 967         }, {
 968                 .name = "imx51-ecspi",
 969                 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
 970         }, {
 971                 .name = "imx53-ecspi",
 972                 .driver_data = (kernel_ulong_t) &imx53_ecspi_devtype_data,
 973         }, {
 974                 /* sentinel */
 975         }
 976 };
 977
 978 static const struct of_device_id spi_imx_dt_ids[] = {
 979         { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
 980         { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
 981         { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
 982         { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
 983         { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
 984         { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
 985         { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
 986         { /* sentinel */ }
 987 };
 988 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
 989
 990 static void spi_imx_chipselect(struct spi_device *spi, int is_active)
 991 {
 992         int active = is_active != BITBANG_CS_INACTIVE;
 993         int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
 994
 995         if (spi->mode & SPI_NO_CS)
 996                 return;
 997
 998         if (!gpio_is_valid(spi->cs_gpio))
 999                 return;
1000
1001         gpio_set_value(spi->cs_gpio, dev_is_lowactive ^ active);
1002 }
1003
1004 static void spi_imx_push(struct spi_imx_data *spi_imx)
1005 {
1006         while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) {
1007                 if (!spi_imx->count)
1008                         break;
1009                 if (spi_imx->txfifo && (spi_imx->count == spi_imx->remainder))
1010                         break;
1011                 spi_imx->tx(spi_imx);
1012                 spi_imx->txfifo++;
1013         }
1014
1015         if (!spi_imx->slave_mode)
1016                 spi_imx->devtype_data->trigger(spi_imx);
1017 }
1018
1019 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
1020 {
1021         struct spi_imx_data *spi_imx = dev_id;
1022
1023         while (spi_imx->txfifo &&
1024                spi_imx->devtype_data->rx_available(spi_imx)) {
1025                 spi_imx->rx(spi_imx);
1026                 spi_imx->txfifo--;
1027         }
1028
1029         if (spi_imx->count) {
1030                 spi_imx_push(spi_imx);
1031                 return IRQ_HANDLED;
1032         }
1033
1034         if (spi_imx->txfifo) {
1035                 /* No data left to push, but still waiting for rx data,
1036                  * enable receive data available interrupt.
1037                  */
1038                 spi_imx->devtype_data->intctrl(
1039                                 spi_imx, MXC_INT_RR);
1040                 return IRQ_HANDLED;
1041         }
1042
1043         spi_imx->devtype_data->intctrl(spi_imx, 0);
1044         complete(&spi_imx->xfer_done);
1045
1046         return IRQ_HANDLED;
1047 }
1048
1049 static int spi_imx_dma_configure(struct spi_master *master)
1050 {
1051         int ret;
1052         enum dma_slave_buswidth buswidth;
1053         struct dma_slave_config rx = {}, tx = {};
1054         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1055
1056         switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) {
1057         case 4:
1058                 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1059                 break;
1060         case 2:
1061                 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1062                 break;
1063         case 1:
1064                 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1065                 break;
1066         default:
1067                 return -EINVAL;
1068         }
1069
1070         tx.direction = DMA_MEM_TO_DEV;
1071         tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
1072         tx.dst_addr_width = buswidth;
1073         tx.dst_maxburst = spi_imx->wml;
1074         ret = dmaengine_slave_config(master->dma_tx, &tx);
1075         if (ret) {
1076                 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
1077                 return ret;
1078         }
1079
1080         rx.direction = DMA_DEV_TO_MEM;
1081         rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
1082         rx.src_addr_width = buswidth;
1083         rx.src_maxburst = spi_imx->wml;
1084         ret = dmaengine_slave_config(master->dma_rx, &rx);
1085         if (ret) {
1086                 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
1087                 return ret;
1088         }
1089
1090         return 0;
1091 }
1092
1093 static int spi_imx_setupxfer(struct spi_device *spi,
1094                                  struct spi_transfer *t)
1095 {
1096         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1097         int ret;
1098
1099         if (!t)
1100                 return 0;
1101
1102         spi_imx->bits_per_word = t->bits_per_word;
1103         spi_imx->speed_hz  = t->speed_hz;
1104
1105         /* Initialize the functions for transfer */
1106         if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode) {
1107                 u32 mask;
1108
1109                 spi_imx->dynamic_burst = 0;
1110                 spi_imx->remainder = 0;
1111                 spi_imx->read_u32  = 1;
1112
1113                 mask = (1 << spi_imx->bits_per_word) - 1;
1114                 spi_imx->rx = spi_imx_buf_rx_swap;
1115                 spi_imx->tx = spi_imx_buf_tx_swap;
1116                 spi_imx->dynamic_burst = 1;
1117                 spi_imx->remainder = t->len;
1118
1119                 if (spi_imx->bits_per_word <= 8)
1120                         spi_imx->word_mask = mask << 24 | mask << 16
1121                                              | mask << 8 | mask;
1122                 else if (spi_imx->bits_per_word <= 16)
1123                         spi_imx->word_mask = mask << 16 | mask;
1124                 else
1125                         spi_imx->word_mask = mask;
1126         } else {
1127                 if (spi_imx->bits_per_word <= 8) {
1128                         spi_imx->rx = spi_imx_buf_rx_u8;
1129                         spi_imx->tx = spi_imx_buf_tx_u8;
1130                 } else if (spi_imx->bits_per_word <= 16) {
1131                         spi_imx->rx = spi_imx_buf_rx_u16;
1132                         spi_imx->tx = spi_imx_buf_tx_u16;
1133                 } else {
1134                         spi_imx->rx = spi_imx_buf_rx_u32;
1135                         spi_imx->tx = spi_imx_buf_tx_u32;
1136                 }
1137         }
1138
1139         if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
1140                 spi_imx->usedma = 1;
1141         else
1142                 spi_imx->usedma = 0;
1143
1144         if (spi_imx->usedma) {
1145                 ret = spi_imx_dma_configure(spi->master);
1146                 if (ret)
1147                         return ret;
1148         }
1149
1150         if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) {
1151                 spi_imx->rx = mx53_ecspi_rx_slave;
1152                 spi_imx->tx = mx53_ecspi_tx_slave;
1153                 spi_imx->slave_burst = t->len;
1154         }
1155
1156         spi_imx->devtype_data->config(spi);
1157
1158         return 0;
1159 }
1160
1161 static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
1162 {
1163         struct spi_master *master = spi_imx->bitbang.master;
1164
1165         if (master->dma_rx) {
1166                 dma_release_channel(master->dma_rx);
1167                 master->dma_rx = NULL;
1168         }
1169
1170         if (master->dma_tx) {
1171                 dma_release_channel(master->dma_tx);
1172                 master->dma_tx = NULL;
1173         }
1174 }
1175
1176 static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
1177                              struct spi_master *master)
1178 {
1179         int ret;
1180
1181         /* use pio mode for i.mx6dl chip TKT238285 */
1182         if (of_machine_is_compatible("fsl,imx6dl"))
1183                 return 0;
1184
1185         spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
1186
1187         /* Prepare for TX DMA: */
1188         master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
1189         if (IS_ERR(master->dma_tx)) {
1190                 ret = PTR_ERR(master->dma_tx);
1191                 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
1192                 master->dma_tx = NULL;
1193                 goto err;
1194         }
1195
1196         /* Prepare for RX : */
1197         master->dma_rx = dma_request_slave_channel_reason(dev, "rx");
1198         if (IS_ERR(master->dma_rx)) {
1199                 ret = PTR_ERR(master->dma_rx);
1200                 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
1201                 master->dma_rx = NULL;
1202                 goto err;
1203         }
1204
1205         init_completion(&spi_imx->dma_rx_completion);
1206         init_completion(&spi_imx->dma_tx_completion);
1207         master->can_dma = spi_imx_can_dma;
1208         master->max_dma_len = MAX_SDMA_BD_BYTES;
1209         spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
1210                                          SPI_MASTER_MUST_TX;
1211
1212         return 0;
1213 err:
1214         spi_imx_sdma_exit(spi_imx);
1215         return ret;
1216 }
1217
1218 static void spi_imx_dma_rx_callback(void *cookie)
1219 {
1220         struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1221
1222         complete(&spi_imx->dma_rx_completion);
1223 }
1224
1225 static void spi_imx_dma_tx_callback(void *cookie)
1226 {
1227         struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1228
1229         complete(&spi_imx->dma_tx_completion);
1230 }
1231
1232 static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
1233 {
1234         unsigned long timeout = 0;
1235
1236         /* Time with actual data transfer and CS change delay related to HW */
1237         timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
1238
1239         /* Add extra second for scheduler related activities */
1240         timeout += 1;
1241
1242         /* Double calculated timeout */
1243         return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
1244 }
1245
1246 static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
1247                                 struct spi_transfer *transfer)
1248 {
1249         struct dma_async_tx_descriptor *desc_tx, *desc_rx;
1250         unsigned long transfer_timeout;
1251         unsigned long timeout;
1252         struct spi_master *master = spi_imx->bitbang.master;
1253         struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1254
1255         /*
1256          * The TX DMA setup starts the transfer, so make sure RX is configured
1257          * before TX.
1258          */
1259         desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
1260                                 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
1261                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1262         if (!desc_rx)
1263                 return -EINVAL;
1264
1265         desc_rx->callback = spi_imx_dma_rx_callback;
1266         desc_rx->callback_param = (void *)spi_imx;
1267         dmaengine_submit(desc_rx);
1268         reinit_completion(&spi_imx->dma_rx_completion);
1269         dma_async_issue_pending(master->dma_rx);
1270
1271         desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
1272                                 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1273                                 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1274         if (!desc_tx) {
1275                 dmaengine_terminate_all(master->dma_tx);
1276                 return -EINVAL;
1277         }
1278
1279         desc_tx->callback = spi_imx_dma_tx_callback;
1280         desc_tx->callback_param = (void *)spi_imx;
1281         dmaengine_submit(desc_tx);
1282         reinit_completion(&spi_imx->dma_tx_completion);
1283         dma_async_issue_pending(master->dma_tx);
1284
1285         transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1286
1287         /* Wait SDMA to finish the data transfer.*/
1288         timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1289                                                 transfer_timeout);
1290         if (!timeout) {
1291                 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1292                 dmaengine_terminate_all(master->dma_tx);
1293                 dmaengine_terminate_all(master->dma_rx);
1294                 return -ETIMEDOUT;
1295         }
1296
1297         timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1298                                               transfer_timeout);
1299         if (!timeout) {
1300                 dev_err(&master->dev, "I/O Error in DMA RX\n");
1301                 spi_imx->devtype_data->reset(spi_imx);
1302                 dmaengine_terminate_all(master->dma_rx);
1303                 return -ETIMEDOUT;
1304         }
1305
1306         return transfer->len;
1307 }
1308
1309 static int spi_imx_pio_transfer(struct spi_device *spi,
1310                                 struct spi_transfer *transfer)
1311 {
1312         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1313         unsigned long transfer_timeout;
1314         unsigned long timeout;
1315
1316         spi_imx->tx_buf = transfer->tx_buf;
1317         spi_imx->rx_buf = transfer->rx_buf;
1318         spi_imx->count = transfer->len;
1319         spi_imx->txfifo = 0;
1320
1321         reinit_completion(&spi_imx->xfer_done);
1322
1323         spi_imx_push(spi_imx);
1324
1325         spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1326
1327         transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1328
1329         timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
1330                                               transfer_timeout);
1331         if (!timeout) {
1332                 dev_err(&spi->dev, "I/O Error in PIO\n");
1333                 spi_imx->devtype_data->reset(spi_imx);
1334                 return -ETIMEDOUT;
1335         }
1336
1337         return transfer->len;
1338 }
1339
1340 static int spi_imx_pio_transfer_slave(struct spi_device *spi,
1341                                       struct spi_transfer *transfer)
1342 {
1343         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1344         int ret = transfer->len;
1345
1346         if (is_imx53_ecspi(spi_imx) &&
1347             transfer->len > MX53_MAX_TRANSFER_BYTES) {
1348                 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n",
1349                         MX53_MAX_TRANSFER_BYTES);
1350                 return -EMSGSIZE;
1351         }
1352
1353         spi_imx->tx_buf = transfer->tx_buf;
1354         spi_imx->rx_buf = transfer->rx_buf;
1355         spi_imx->count = transfer->len;
1356         spi_imx->txfifo = 0;
1357
1358         reinit_completion(&spi_imx->xfer_done);
1359         spi_imx->slave_aborted = false;
1360
1361         spi_imx_push(spi_imx);
1362
1363         spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR);
1364
1365         if (wait_for_completion_interruptible(&spi_imx->xfer_done) ||
1366             spi_imx->slave_aborted) {
1367                 dev_dbg(&spi->dev, "interrupted\n");
1368                 ret = -EINTR;
1369         }
1370
1371         /* ecspi has a HW issue when works in Slave mode,
1372          * after 64 words writtern to TXFIFO, even TXFIFO becomes empty,
1373          * ECSPI_TXDATA keeps shift out the last word data,
1374          * so we have to disable ECSPI when in slave mode after the
1375          * transfer completes
1376          */
1377         if (spi_imx->devtype_data->disable)
1378                 spi_imx->devtype_data->disable(spi_imx);
1379
1380         return ret;
1381 }
1382
1383 static int spi_imx_transfer(struct spi_device *spi,
1384                                 struct spi_transfer *transfer)
1385 {
1386         struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1387
1388         /* flush rxfifo before transfer */
1389         while (spi_imx->devtype_data->rx_available(spi_imx))
1390                 spi_imx->rx(spi_imx);
1391
1392         if (spi_imx->slave_mode)
1393                 return spi_imx_pio_transfer_slave(spi, transfer);
1394
1395         if (spi_imx->usedma)
1396                 return spi_imx_dma_transfer(spi_imx, transfer);
1397         else
1398                 return spi_imx_pio_transfer(spi, transfer);
1399 }
1400
1401 static int spi_imx_setup(struct spi_device *spi)
1402 {
1403         dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1404                  spi->mode, spi->bits_per_word, spi->max_speed_hz);
1405
1406         if (spi->mode & SPI_NO_CS)
1407                 return 0;
1408
1409         if (gpio_is_valid(spi->cs_gpio))
1410                 gpio_direction_output(spi->cs_gpio,
1411                                       spi->mode & SPI_CS_HIGH ? 0 : 1);
1412
1413         spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
1414
1415         return 0;
1416 }
1417
1418 static void spi_imx_cleanup(struct spi_device *spi)
1419 {
1420 }
1421
1422 static int
1423 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1424 {
1425         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1426         int ret;
1427
1428         ret = clk_enable(spi_imx->clk_per);
1429         if (ret)
1430                 return ret;
1431
1432         ret = clk_enable(spi_imx->clk_ipg);
1433         if (ret) {
1434                 clk_disable(spi_imx->clk_per);
1435                 return ret;
1436         }
1437
1438         return 0;
1439 }
1440
1441 static int
1442 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1443 {
1444         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1445
1446         clk_disable(spi_imx->clk_ipg);
1447         clk_disable(spi_imx->clk_per);
1448         return 0;
1449 }
1450
1451 static int spi_imx_slave_abort(struct spi_master *master)
1452 {
1453         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1454
1455         spi_imx->slave_aborted = true;
1456         complete(&spi_imx->xfer_done);
1457
1458         return 0;
1459 }
1460
1461 static int spi_imx_probe(struct platform_device *pdev)
1462 {
1463         struct device_node *np = pdev->dev.of_node;
1464         const struct of_device_id *of_id =
1465                         of_match_device(spi_imx_dt_ids, &pdev->dev);
1466         struct spi_imx_master *mxc_platform_info =
1467                         dev_get_platdata(&pdev->dev);
1468         struct spi_master *master;
1469         struct spi_imx_data *spi_imx;
1470         struct resource *res;
1471         int i, ret, irq, spi_drctl;
1472         const struct spi_imx_devtype_data *devtype_data = of_id ? of_id->data :
1473                 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
1474         bool slave_mode;
1475
1476         if (!np && !mxc_platform_info) {
1477                 dev_err(&pdev->dev, "can't get the platform data\n");
1478                 return -EINVAL;
1479         }
1480
1481         slave_mode = devtype_data->has_slavemode &&
1482                         of_property_read_bool(np, "spi-slave");
1483         if (slave_mode)
1484                 master = spi_alloc_slave(&pdev->dev,
1485                                          sizeof(struct spi_imx_data));
1486         else
1487                 master = spi_alloc_master(&pdev->dev,
1488                                           sizeof(struct spi_imx_data));
1489         if (!master)
1490                 return -ENOMEM;
1491
1492         ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl);
1493         if ((ret < 0) || (spi_drctl >= 0x3)) {
1494                 /* '11' is reserved */
1495                 spi_drctl = 0;
1496         }
1497
1498         platform_set_drvdata(pdev, master);
1499
1500         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1501         master->bus_num = np ? -1 : pdev->id;
1502
1503         spi_imx = spi_master_get_devdata(master);
1504         spi_imx->bitbang.master = master;
1505         spi_imx->dev = &pdev->dev;
1506         spi_imx->slave_mode = slave_mode;
1507
1508         spi_imx->devtype_data = devtype_data;
1509
1510         /* Get number of chip selects, either platform data or OF */
1511         if (mxc_platform_info) {
1512                 master->num_chipselect = mxc_platform_info->num_chipselect;
1513                 if (mxc_platform_info->chipselect) {
1514                         master->cs_gpios = devm_kzalloc(&master->dev,
1515                                 sizeof(int) * master->num_chipselect, GFP_KERNEL);
1516                         if (!master->cs_gpios)
1517                                 return -ENOMEM;
1518
1519                         for (i = 0; i < master->num_chipselect; i++)
1520                                 master->cs_gpios[i] = mxc_platform_info->chipselect[i];
1521                 }
1522         } else {
1523                 u32 num_cs;
1524
1525                 if (!of_property_read_u32(np, "num-cs", &num_cs))
1526                         master->num_chipselect = num_cs;
1527                 /* If not preset, default value of 1 is used */
1528         }
1529
1530         spi_imx->bitbang.chipselect = spi_imx_chipselect;
1531         spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1532         spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1533         spi_imx->bitbang.master->setup = spi_imx_setup;
1534         spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1535         spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1536         spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1537         spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort;
1538         spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
1539                                              | SPI_NO_CS;
1540         if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
1541             is_imx53_ecspi(spi_imx))
1542                 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;
1543
1544         spi_imx->spi_drctl = spi_drctl;
1545
1546         init_completion(&spi_imx->xfer_done);
1547
1548         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1549         spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1550         if (IS_ERR(spi_imx->base)) {
1551                 ret = PTR_ERR(spi_imx->base);
1552                 goto out_master_put;
1553         }
1554         spi_imx->base_phys = res->start;
1555
1556         irq = platform_get_irq(pdev, 0);
1557         if (irq < 0) {
1558                 ret = irq;
1559                 goto out_master_put;
1560         }
1561
1562         ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1563                                dev_name(&pdev->dev), spi_imx);
1564         if (ret) {
1565                 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1566                 goto out_master_put;
1567         }
1568
1569         spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1570         if (IS_ERR(spi_imx->clk_ipg)) {
1571                 ret = PTR_ERR(spi_imx->clk_ipg);
1572                 goto out_master_put;
1573         }
1574
1575         spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1576         if (IS_ERR(spi_imx->clk_per)) {
1577                 ret = PTR_ERR(spi_imx->clk_per);
1578                 goto out_master_put;
1579         }
1580
1581         ret = clk_prepare_enable(spi_imx->clk_per);
1582         if (ret)
1583                 goto out_master_put;
1584
1585         ret = clk_prepare_enable(spi_imx->clk_ipg);
1586         if (ret)
1587                 goto out_put_per;
1588
1589         spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1590         /*
1591          * Only validated on i.mx35 and i.mx6 now, can remove the constraint
1592          * if validated on other chips.
1593          */
1594         if (spi_imx->devtype_data->has_dmamode) {
1595                 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
1596                 if (ret == -EPROBE_DEFER)
1597                         goto out_clk_put;
1598
1599                 if (ret < 0)
1600                         dev_err(&pdev->dev, "dma setup error %d, use pio\n",
1601                                 ret);
1602         }
1603
1604         spi_imx->devtype_data->reset(spi_imx);
1605
1606         spi_imx->devtype_data->intctrl(spi_imx, 0);
1607
1608         master->dev.of_node = pdev->dev.of_node;
1609         ret = spi_bitbang_start(&spi_imx->bitbang);
1610         if (ret) {
1611                 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
1612                 goto out_clk_put;
1613         }
1614
1615         /* Request GPIO CS lines, if any */
1616         if (!spi_imx->slave_mode && master->cs_gpios) {
1617                 for (i = 0; i < master->num_chipselect; i++) {
1618                         if (!gpio_is_valid(master->cs_gpios[i]))
1619                                 continue;
1620
1621                         ret = devm_gpio_request(&pdev->dev,
1622                                                 master->cs_gpios[i],
1623                                                 DRIVER_NAME);
1624                         if (ret) {
1625                                 dev_err(&pdev->dev, "Can't get CS GPIO %i\n",
1626                                         master->cs_gpios[i]);
1627                                 goto out_spi_bitbang;
1628                         }
1629                 }
1630         }
1631
1632         dev_info(&pdev->dev, "probed\n");
1633
1634         clk_disable(spi_imx->clk_ipg);
1635         clk_disable(spi_imx->clk_per);
1636         return ret;
1637
1638 out_spi_bitbang:
1639         spi_bitbang_stop(&spi_imx->bitbang);
1640 out_clk_put:
1641         clk_disable_unprepare(spi_imx->clk_ipg);
1642 out_put_per:
1643         clk_disable_unprepare(spi_imx->clk_per);
1644 out_master_put:
1645         spi_master_put(master);
1646
1647         return ret;
1648 }
1649
1650 static int spi_imx_remove(struct platform_device *pdev)
1651 {
1652         struct spi_master *master = platform_get_drvdata(pdev);
1653         struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1654         int ret;
1655
1656         spi_bitbang_stop(&spi_imx->bitbang);
1657
1658         ret = clk_enable(spi_imx->clk_per);
1659         if (ret)
1660                 return ret;
1661
1662         ret = clk_enable(spi_imx->clk_ipg);
1663         if (ret) {
1664                 clk_disable(spi_imx->clk_per);
1665                 return ret;
1666         }
1667
1668         writel(0, spi_imx->base + MXC_CSPICTRL);
1669         clk_disable_unprepare(spi_imx->clk_ipg);
1670         clk_disable_unprepare(spi_imx->clk_per);
1671         spi_imx_sdma_exit(spi_imx);
1672         spi_master_put(master);
1673
1674         return 0;
1675 }
1676
1677 static struct platform_driver spi_imx_driver = {
1678         .driver = {
1679                    .name = DRIVER_NAME,
1680                    .of_match_table = spi_imx_dt_ids,
1681                    },
1682         .id_table = spi_imx_devtype,
1683         .probe = spi_imx_probe,
1684         .remove = spi_imx_remove,
1685 };
1686 module_platform_driver(spi_imx_driver);
1687
1688 MODULE_DESCRIPTION("SPI Controller driver");
1689 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1690 MODULE_LICENSE("GPL");
1691 MODULE_ALIAS("platform:" DRIVER_NAME);