drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <drm/drmP.h>
  24 #include <drm/amdgpu_drm.h>
  25 #include "amdgpu.h"
  26 #include "atomfirmware.h"
  27 #include "amdgpu_atomfirmware.h"
  28 #include "atom.h"
  29 #include "atombios.h"
  30
  31 bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev)
  32 {
  33         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  34                                                 firmwareinfo);
  35         uint16_t data_offset;
  36
  37         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
  38                                           NULL, NULL, &data_offset)) {
  39                 struct atom_firmware_info_v3_1 *firmware_info =
  40                         (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
  41                                                            data_offset);
  42
  43                 if (le32_to_cpu(firmware_info->firmware_capability) &
  44                     ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION)
  45                         return true;
  46         }
  47         return false;
  48 }
  49
  50 void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev)
  51 {
  52         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  53                                                 firmwareinfo);
  54         uint16_t data_offset;
  55
  56         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
  57                                           NULL, NULL, &data_offset)) {
  58                 struct atom_firmware_info_v3_1 *firmware_info =
  59                         (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
  60                                                            data_offset);
  61
  62                 adev->bios_scratch_reg_offset =
  63                         le32_to_cpu(firmware_info->bios_scratch_reg_startaddr);
  64         }
  65 }
  66
  67 int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
  68 {
  69         struct atom_context *ctx = adev->mode_info.atom_context;
  70         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
  71                                                 vram_usagebyfirmware);
  72         struct vram_usagebyfirmware_v2_1 *      firmware_usage;
  73         uint32_t start_addr, size;
  74         uint16_t data_offset;
  75         int usage_bytes = 0;
  76
  77         if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
  78                 firmware_usage = (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
  79                 DRM_DEBUG("atom firmware requested %08x %dkb fw %dkb drv\n",
  80                           le32_to_cpu(firmware_usage->start_address_in_kb),
  81                           le16_to_cpu(firmware_usage->used_by_firmware_in_kb),
  82                           le16_to_cpu(firmware_usage->used_by_driver_in_kb));
  83
  84                 start_addr = le32_to_cpu(firmware_usage->start_address_in_kb);
  85                 size = le16_to_cpu(firmware_usage->used_by_firmware_in_kb);
  86
  87                 if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) ==
  88                         (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION <<
  89                         ATOM_VRAM_OPERATION_FLAGS_SHIFT)) {
  90                         /* Firmware request VRAM reservation for SR-IOV */
  91                         adev->fw_vram_usage.start_offset = (start_addr &
  92                                 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10;
  93                         adev->fw_vram_usage.size = size << 10;
  94                         /* Use the default scratch size */
  95                         usage_bytes = 0;
  96                 } else {
  97                         usage_bytes = le16_to_cpu(firmware_usage->used_by_driver_in_kb) << 10;
  98                 }
  99         }
 100         ctx->scratch_size_bytes = 0;
 101         if (usage_bytes == 0)
 102                 usage_bytes = 20 * 1024;
 103         /* allocate some scratch memory */
 104         ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
 105         if (!ctx->scratch)
 106                 return -ENOMEM;
 107         ctx->scratch_size_bytes = usage_bytes;
 108         return 0;
 109 }
 110
 111 union igp_info {
 112         struct atom_integrated_system_info_v1_11 v11;
 113 };
 114
 115 union umc_info {
 116         struct atom_umc_info_v3_1 v31;
 117 };
 118
 119 union vram_info {
 120         struct atom_vram_info_header_v2_3 v23;
 121 };
 122 /*
 123  * Return vram width from integrated system info table, if available,
 124  * or 0 if not.
 125  */
 126 int amdgpu_atomfirmware_get_vram_width(struct amdgpu_device *adev)
 127 {
 128         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 129         int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 130                                                 integratedsysteminfo);
 131         u16 data_offset, size;
 132         union igp_info *igp_info;
 133         u8 frev, crev;
 134
 135         /* get any igp specific overrides */
 136         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size,
 137                                    &frev, &crev, &data_offset)) {
 138                 igp_info = (union igp_info *)
 139                         (mode_info->atom_context->bios + data_offset);
 140                 switch (crev) {
 141                 case 11:
 142                         return igp_info->v11.umachannelnumber * 64;
 143                 default:
 144                         return 0;
 145                 }
 146         }
 147
 148         return 0;
 149 }
 150
 151 static int convert_atom_mem_type_to_vram_type (struct amdgpu_device *adev,
 152                                                int atom_mem_type)
 153 {
 154         int vram_type;
 155
 156         if (adev->flags & AMD_IS_APU) {
 157                 switch (atom_mem_type) {
 158                 case Ddr2MemType:
 159                 case LpDdr2MemType:
 160                         vram_type = AMDGPU_VRAM_TYPE_DDR2;
 161                         break;
 162                 case Ddr3MemType:
 163                 case LpDdr3MemType:
 164                         vram_type = AMDGPU_VRAM_TYPE_DDR3;
 165                         break;
 166                 case Ddr4MemType:
 167                 case LpDdr4MemType:
 168                         vram_type = AMDGPU_VRAM_TYPE_DDR4;
 169                         break;
 170                 default:
 171                         vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 172                         break;
 173                 }
 174         } else {
 175                 switch (atom_mem_type) {
 176                 case ATOM_DGPU_VRAM_TYPE_GDDR5:
 177                         vram_type = AMDGPU_VRAM_TYPE_GDDR5;
 178                         break;
 179                 case ATOM_DGPU_VRAM_TYPE_HBM2:
 180                         vram_type = AMDGPU_VRAM_TYPE_HBM;
 181                         break;
 182                 default:
 183                         vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
 184                         break;
 185                 }
 186         }
 187
 188         return vram_type;
 189 }
 190 /*
 191  * Return vram type from either integrated system info table
 192  * or umc info table, if available, or 0 (TYPE_UNKNOWN) if not
 193  */
 194 int amdgpu_atomfirmware_get_vram_type(struct amdgpu_device *adev)
 195 {
 196         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 197         int index;
 198         u16 data_offset, size;
 199         union igp_info *igp_info;
 200         union vram_info *vram_info;
 201         u8 frev, crev;
 202         u8 mem_type;
 203
 204         if (adev->flags & AMD_IS_APU)
 205                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 206                                                     integratedsysteminfo);
 207         else
 208                 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 209                                                     vram_info);
 210         if (amdgpu_atom_parse_data_header(mode_info->atom_context,
 211                                           index, &size,
 212                                           &frev, &crev, &data_offset)) {
 213                 if (adev->flags & AMD_IS_APU) {
 214                         igp_info = (union igp_info *)
 215                                 (mode_info->atom_context->bios + data_offset);
 216                         switch (crev) {
 217                         case 11:
 218                                 mem_type = igp_info->v11.memorytype;
 219                                 return convert_atom_mem_type_to_vram_type(adev, mem_type);
 220                         default:
 221                                 return 0;
 222                         }
 223                 } else {
 224                         vram_info = (union vram_info *)
 225                                 (mode_info->atom_context->bios + data_offset);
 226                         switch (crev) {
 227                         case 3:
 228                                 mem_type = vram_info->v23.vram_module[0].memory_type;
 229                                 return convert_atom_mem_type_to_vram_type(adev, mem_type);
 230                         default:
 231                                 return 0;
 232                         }
 233                 }
 234         }
 235
 236         return 0;
 237 }
 238
 239 /*
 240  * Return true if vbios enabled ecc by default, if umc info table is available
 241  * or false if ecc is not enabled or umc info table is not available
 242  */
 243 bool amdgpu_atomfirmware_mem_ecc_supported(struct amdgpu_device *adev)
 244 {
 245         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 246         int index;
 247         u16 data_offset, size;
 248         union umc_info *umc_info;
 249         u8 frev, crev;
 250         bool ecc_default_enabled = false;
 251
 252         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 253                         umc_info);
 254
 255         if (amdgpu_atom_parse_data_header(mode_info->atom_context,
 256                                 index, &size, &frev, &crev, &data_offset)) {
 257                 /* support umc_info 3.1+ */
 258                 if ((frev == 3 && crev >= 1) || (frev > 3)) {
 259                         umc_info = (union umc_info *)
 260                                 (mode_info->atom_context->bios + data_offset);
 261                         ecc_default_enabled =
 262                                 (le32_to_cpu(umc_info->v31.umc_config) &
 263                                  UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE) ? true : false;
 264                 }
 265         }
 266
 267         return ecc_default_enabled;
 268 }
 269
 270 union firmware_info {
 271         struct atom_firmware_info_v3_1 v31;
 272 };
 273
 274 /*
 275  * Return true if vbios supports sram ecc or false if not
 276  */
 277 bool amdgpu_atomfirmware_sram_ecc_supported(struct amdgpu_device *adev)
 278 {
 279         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 280         int index;
 281         u16 data_offset, size;
 282         union firmware_info *firmware_info;
 283         u8 frev, crev;
 284         bool sram_ecc_supported = false;
 285
 286         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 287                         firmwareinfo);
 288
 289         if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context,
 290                                 index, &size, &frev, &crev, &data_offset)) {
 291                 /* support firmware_info 3.1 + */
 292                 if ((frev == 3 && crev >=1) || (frev > 3)) {
 293                         firmware_info = (union firmware_info *)
 294                                 (mode_info->atom_context->bios + data_offset);
 295                         sram_ecc_supported =
 296                                 (le32_to_cpu(firmware_info->v31.firmware_capability) &
 297                                  ATOM_FIRMWARE_CAP_SRAM_ECC) ? true : false;
 298                 }
 299         }
 300
 301         return sram_ecc_supported;
 302 }
 303
 304 union smu_info {
 305         struct atom_smu_info_v3_1 v31;
 306 };
 307
 308 int amdgpu_atomfirmware_get_clock_info(struct amdgpu_device *adev)
 309 {
 310         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 311         struct amdgpu_pll *spll = &adev->clock.spll;
 312         struct amdgpu_pll *mpll = &adev->clock.mpll;
 313         uint8_t frev, crev;
 314         uint16_t data_offset;
 315         int ret = -EINVAL, index;
 316
 317         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 318                                             firmwareinfo);
 319         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 320                                    &frev, &crev, &data_offset)) {
 321                 union firmware_info *firmware_info =
 322                         (union firmware_info *)(mode_info->atom_context->bios +
 323                                                 data_offset);
 324
 325                 adev->clock.default_sclk =
 326                         le32_to_cpu(firmware_info->v31.bootup_sclk_in10khz);
 327                 adev->clock.default_mclk =
 328                         le32_to_cpu(firmware_info->v31.bootup_mclk_in10khz);
 329
 330                 adev->pm.current_sclk = adev->clock.default_sclk;
 331                 adev->pm.current_mclk = adev->clock.default_mclk;
 332
 333                 /* not technically a clock, but... */
 334                 adev->mode_info.firmware_flags =
 335                         le32_to_cpu(firmware_info->v31.firmware_capability);
 336
 337                 ret = 0;
 338         }
 339
 340         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 341                                             smu_info);
 342         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 343                                    &frev, &crev, &data_offset)) {
 344                 union smu_info *smu_info =
 345                         (union smu_info *)(mode_info->atom_context->bios +
 346                                            data_offset);
 347
 348                 /* system clock */
 349                 spll->reference_freq = le32_to_cpu(smu_info->v31.core_refclk_10khz);
 350
 351                 spll->reference_div = 0;
 352                 spll->min_post_div = 1;
 353                 spll->max_post_div = 1;
 354                 spll->min_ref_div = 2;
 355                 spll->max_ref_div = 0xff;
 356                 spll->min_feedback_div = 4;
 357                 spll->max_feedback_div = 0xff;
 358                 spll->best_vco = 0;
 359
 360                 ret = 0;
 361         }
 362
 363         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 364                                             umc_info);
 365         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 366                                    &frev, &crev, &data_offset)) {
 367                 union umc_info *umc_info =
 368                         (union umc_info *)(mode_info->atom_context->bios +
 369                                            data_offset);
 370
 371                 /* memory clock */
 372                 mpll->reference_freq = le32_to_cpu(umc_info->v31.mem_refclk_10khz);
 373
 374                 mpll->reference_div = 0;
 375                 mpll->min_post_div = 1;
 376                 mpll->max_post_div = 1;
 377                 mpll->min_ref_div = 2;
 378                 mpll->max_ref_div = 0xff;
 379                 mpll->min_feedback_div = 4;
 380                 mpll->max_feedback_div = 0xff;
 381                 mpll->best_vco = 0;
 382
 383                 ret = 0;
 384         }
 385
 386         return ret;
 387 }
 388
 389 union gfx_info {
 390         struct  atom_gfx_info_v2_4 v24;
 391 };
 392
 393 int amdgpu_atomfirmware_get_gfx_info(struct amdgpu_device *adev)
 394 {
 395         struct amdgpu_mode_info *mode_info = &adev->mode_info;
 396         int index;
 397         uint8_t frev, crev;
 398         uint16_t data_offset;
 399
 400         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 401                                             gfx_info);
 402         if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
 403                                    &frev, &crev, &data_offset)) {
 404                 union gfx_info *gfx_info = (union gfx_info *)
 405                         (mode_info->atom_context->bios + data_offset);
 406                 switch (crev) {
 407                 case 4:
 408                         adev->gfx.config.max_shader_engines = gfx_info->v24.max_shader_engines;
 409                         adev->gfx.config.max_cu_per_sh = gfx_info->v24.max_cu_per_sh;
 410                         adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se;
 411                         adev->gfx.config.max_backends_per_se = gfx_info->v24.max_backends_per_se;
 412                         adev->gfx.config.max_texture_channel_caches = gfx_info->v24.max_texture_channel_caches;
 413                         adev->gfx.config.max_gprs = le16_to_cpu(gfx_info->v24.gc_num_gprs);
 414                         adev->gfx.config.max_gs_threads = gfx_info->v24.gc_num_max_gs_thds;
 415                         adev->gfx.config.gs_vgt_table_depth = gfx_info->v24.gc_gs_table_depth;
 416                         adev->gfx.config.gs_prim_buffer_depth =
 417                                 le16_to_cpu(gfx_info->v24.gc_gsprim_buff_depth);
 418                         adev->gfx.config.double_offchip_lds_buf =
 419                                 gfx_info->v24.gc_double_offchip_lds_buffer;
 420                         adev->gfx.cu_info.wave_front_size = le16_to_cpu(gfx_info->v24.gc_wave_size);
 421                         adev->gfx.cu_info.max_waves_per_simd = le16_to_cpu(gfx_info->v24.gc_max_waves_per_simd);
 422                         adev->gfx.cu_info.max_scratch_slots_per_cu = gfx_info->v24.gc_max_scratch_slots_per_cu;
 423                         adev->gfx.cu_info.lds_size = le16_to_cpu(gfx_info->v24.gc_lds_size);
 424                         return 0;
 425                 default:
 426                         return -EINVAL;
 427                 }
 428
 429         }
 430         return -EINVAL;
 431 }