drivers/mmc/host/s3cmci.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  linux/drivers/mmc/s3cmci.h - Samsung S3C MCI driver
   4  *
   5  *  Copyright (C) 2004-2006 maintech GmbH, Thomas Kleffel <[email protected]>
   6  *
   7  * Current driver maintained by Ben Dooks and Simtec Electronics
   8  *  Copyright (C) 2008 Simtec Electronics <[email protected]>
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/dmaengine.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/clk.h>
  15 #include <linux/mmc/host.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/cpufreq.h>
  18 #include <linux/debugfs.h>
  19 #include <linux/seq_file.h>
  20 #include <linux/gpio.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/irq.h>
  23 #include <linux/io.h>
  24 #include <linux/of.h>
  25 #include <linux/of_device.h>
  26 #include <linux/mmc/slot-gpio.h>
  27
  28 #include <plat/gpio-cfg.h>
  29 #include <mach/dma.h>
  30 #include <mach/gpio-samsung.h>
  31
  32 #include <linux/platform_data/mmc-s3cmci.h>
  33
  34 #include "s3cmci.h"
  35
  36 #define DRIVER_NAME "s3c-mci"
  37
  38 #define S3C2410_SDICON                  (0x00)
  39 #define S3C2410_SDIPRE                  (0x04)
  40 #define S3C2410_SDICMDARG               (0x08)
  41 #define S3C2410_SDICMDCON               (0x0C)
  42 #define S3C2410_SDICMDSTAT              (0x10)
  43 #define S3C2410_SDIRSP0                 (0x14)
  44 #define S3C2410_SDIRSP1                 (0x18)
  45 #define S3C2410_SDIRSP2                 (0x1C)
  46 #define S3C2410_SDIRSP3                 (0x20)
  47 #define S3C2410_SDITIMER                (0x24)
  48 #define S3C2410_SDIBSIZE                (0x28)
  49 #define S3C2410_SDIDCON                 (0x2C)
  50 #define S3C2410_SDIDCNT                 (0x30)
  51 #define S3C2410_SDIDSTA                 (0x34)
  52 #define S3C2410_SDIFSTA                 (0x38)
  53
  54 #define S3C2410_SDIDATA                 (0x3C)
  55 #define S3C2410_SDIIMSK                 (0x40)
  56
  57 #define S3C2440_SDIDATA                 (0x40)
  58 #define S3C2440_SDIIMSK                 (0x3C)
  59
  60 #define S3C2440_SDICON_SDRESET          (1 << 8)
  61 #define S3C2410_SDICON_SDIOIRQ          (1 << 3)
  62 #define S3C2410_SDICON_FIFORESET        (1 << 1)
  63 #define S3C2410_SDICON_CLOCKTYPE        (1 << 0)
  64
  65 #define S3C2410_SDICMDCON_LONGRSP       (1 << 10)
  66 #define S3C2410_SDICMDCON_WAITRSP       (1 << 9)
  67 #define S3C2410_SDICMDCON_CMDSTART      (1 << 8)
  68 #define S3C2410_SDICMDCON_SENDERHOST    (1 << 6)
  69 #define S3C2410_SDICMDCON_INDEX         (0x3f)
  70
  71 #define S3C2410_SDICMDSTAT_CRCFAIL      (1 << 12)
  72 #define S3C2410_SDICMDSTAT_CMDSENT      (1 << 11)
  73 #define S3C2410_SDICMDSTAT_CMDTIMEOUT   (1 << 10)
  74 #define S3C2410_SDICMDSTAT_RSPFIN       (1 << 9)
  75
  76 #define S3C2440_SDIDCON_DS_WORD         (2 << 22)
  77 #define S3C2410_SDIDCON_TXAFTERRESP     (1 << 20)
  78 #define S3C2410_SDIDCON_RXAFTERCMD      (1 << 19)
  79 #define S3C2410_SDIDCON_BLOCKMODE       (1 << 17)
  80 #define S3C2410_SDIDCON_WIDEBUS         (1 << 16)
  81 #define S3C2410_SDIDCON_DMAEN           (1 << 15)
  82 #define S3C2410_SDIDCON_STOP            (1 << 14)
  83 #define S3C2440_SDIDCON_DATSTART        (1 << 14)
  84
  85 #define S3C2410_SDIDCON_XFER_RXSTART    (2 << 12)
  86 #define S3C2410_SDIDCON_XFER_TXSTART    (3 << 12)
  87
  88 #define S3C2410_SDIDCON_BLKNUM_MASK     (0xFFF)
  89
  90 #define S3C2410_SDIDSTA_SDIOIRQDETECT   (1 << 9)
  91 #define S3C2410_SDIDSTA_FIFOFAIL        (1 << 8)
  92 #define S3C2410_SDIDSTA_CRCFAIL         (1 << 7)
  93 #define S3C2410_SDIDSTA_RXCRCFAIL       (1 << 6)
  94 #define S3C2410_SDIDSTA_DATATIMEOUT     (1 << 5)
  95 #define S3C2410_SDIDSTA_XFERFINISH      (1 << 4)
  96 #define S3C2410_SDIDSTA_TXDATAON        (1 << 1)
  97 #define S3C2410_SDIDSTA_RXDATAON        (1 << 0)
  98
  99 #define S3C2440_SDIFSTA_FIFORESET       (1 << 16)
 100 #define S3C2440_SDIFSTA_FIFOFAIL        (3 << 14)
 101 #define S3C2410_SDIFSTA_TFDET           (1 << 13)
 102 #define S3C2410_SDIFSTA_RFDET           (1 << 12)
 103 #define S3C2410_SDIFSTA_COUNTMASK       (0x7f)
 104
 105 #define S3C2410_SDIIMSK_RESPONSECRC     (1 << 17)
 106 #define S3C2410_SDIIMSK_CMDSENT         (1 << 16)
 107 #define S3C2410_SDIIMSK_CMDTIMEOUT      (1 << 15)
 108 #define S3C2410_SDIIMSK_RESPONSEND      (1 << 14)
 109 #define S3C2410_SDIIMSK_SDIOIRQ         (1 << 12)
 110 #define S3C2410_SDIIMSK_FIFOFAIL        (1 << 11)
 111 #define S3C2410_SDIIMSK_CRCSTATUS       (1 << 10)
 112 #define S3C2410_SDIIMSK_DATACRC         (1 << 9)
 113 #define S3C2410_SDIIMSK_DATATIMEOUT     (1 << 8)
 114 #define S3C2410_SDIIMSK_DATAFINISH      (1 << 7)
 115 #define S3C2410_SDIIMSK_TXFIFOHALF      (1 << 4)
 116 #define S3C2410_SDIIMSK_RXFIFOLAST      (1 << 2)
 117 #define S3C2410_SDIIMSK_RXFIFOHALF      (1 << 0)
 118
 119 enum dbg_channels {
 120         dbg_err   = (1 << 0),
 121         dbg_debug = (1 << 1),
 122         dbg_info  = (1 << 2),
 123         dbg_irq   = (1 << 3),
 124         dbg_sg    = (1 << 4),
 125         dbg_dma   = (1 << 5),
 126         dbg_pio   = (1 << 6),
 127         dbg_fail  = (1 << 7),
 128         dbg_conf  = (1 << 8),
 129 };
 130
 131 static const int dbgmap_err   = dbg_fail;
 132 static const int dbgmap_info  = dbg_info | dbg_conf;
 133 static const int dbgmap_debug = dbg_err | dbg_debug;
 134
 135 #define dbg(host, channels, args...)              \
 136         do {                                      \
 137         if (dbgmap_err & channels)                \
 138                 dev_err(&host->pdev->dev, args);  \
 139         else if (dbgmap_info & channels)          \
 140                 dev_info(&host->pdev->dev, args); \
 141         else if (dbgmap_debug & channels)         \
 142                 dev_dbg(&host->pdev->dev, args);  \
 143         } while (0)
 144
 145 static void finalize_request(struct s3cmci_host *host);
 146 static void s3cmci_send_request(struct mmc_host *mmc);
 147 static void s3cmci_reset(struct s3cmci_host *host);
 148
 149 #ifdef CONFIG_MMC_DEBUG
 150
 151 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix)
 152 {
 153         u32 con, pre, cmdarg, cmdcon, cmdsta, r0, r1, r2, r3, timer, bsize;
 154         u32 datcon, datcnt, datsta, fsta, imask;
 155
 156         con     = readl(host->base + S3C2410_SDICON);
 157         pre     = readl(host->base + S3C2410_SDIPRE);
 158         cmdarg  = readl(host->base + S3C2410_SDICMDARG);
 159         cmdcon  = readl(host->base + S3C2410_SDICMDCON);
 160         cmdsta  = readl(host->base + S3C2410_SDICMDSTAT);
 161         r0      = readl(host->base + S3C2410_SDIRSP0);
 162         r1      = readl(host->base + S3C2410_SDIRSP1);
 163         r2      = readl(host->base + S3C2410_SDIRSP2);
 164         r3      = readl(host->base + S3C2410_SDIRSP3);
 165         timer   = readl(host->base + S3C2410_SDITIMER);
 166         bsize   = readl(host->base + S3C2410_SDIBSIZE);
 167         datcon  = readl(host->base + S3C2410_SDIDCON);
 168         datcnt  = readl(host->base + S3C2410_SDIDCNT);
 169         datsta  = readl(host->base + S3C2410_SDIDSTA);
 170         fsta    = readl(host->base + S3C2410_SDIFSTA);
 171         imask   = readl(host->base + host->sdiimsk);
 172
 173         dbg(host, dbg_debug, "%s  CON:[%08x]  PRE:[%08x]  TMR:[%08x]\n",
 174                                 prefix, con, pre, timer);
 175
 176         dbg(host, dbg_debug, "%s CCON:[%08x] CARG:[%08x] CSTA:[%08x]\n",
 177                                 prefix, cmdcon, cmdarg, cmdsta);
 178
 179         dbg(host, dbg_debug, "%s DCON:[%08x] FSTA:[%08x]"
 180                                " DSTA:[%08x] DCNT:[%08x]\n",
 181                                 prefix, datcon, fsta, datsta, datcnt);
 182
 183         dbg(host, dbg_debug, "%s   R0:[%08x]   R1:[%08x]"
 184                                "   R2:[%08x]   R3:[%08x]\n",
 185                                 prefix, r0, r1, r2, r3);
 186 }
 187
 188 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
 189                            int stop)
 190 {
 191         snprintf(host->dbgmsg_cmd, 300,
 192                  "#%u%s op:%i arg:0x%08x flags:0x08%x retries:%u",
 193                  host->ccnt, (stop ? " (STOP)" : ""),
 194                  cmd->opcode, cmd->arg, cmd->flags, cmd->retries);
 195
 196         if (cmd->data) {
 197                 snprintf(host->dbgmsg_dat, 300,
 198                          "#%u bsize:%u blocks:%u bytes:%u",
 199                          host->dcnt, cmd->data->blksz,
 200                          cmd->data->blocks,
 201                          cmd->data->blocks * cmd->data->blksz);
 202         } else {
 203                 host->dbgmsg_dat[0] = '\0';
 204         }
 205 }
 206
 207 static void dbg_dumpcmd(struct s3cmci_host *host, struct mmc_command *cmd,
 208                         int fail)
 209 {
 210         unsigned int dbglvl = fail ? dbg_fail : dbg_debug;
 211
 212         if (!cmd)
 213                 return;
 214
 215         if (cmd->error == 0) {
 216                 dbg(host, dbglvl, "CMD[OK] %s R0:0x%08x\n",
 217                         host->dbgmsg_cmd, cmd->resp[0]);
 218         } else {
 219                 dbg(host, dbglvl, "CMD[ERR %i] %s Status:%s\n",
 220                         cmd->error, host->dbgmsg_cmd, host->status);
 221         }
 222
 223         if (!cmd->data)
 224                 return;
 225
 226         if (cmd->data->error == 0) {
 227                 dbg(host, dbglvl, "DAT[OK] %s\n", host->dbgmsg_dat);
 228         } else {
 229                 dbg(host, dbglvl, "DAT[ERR %i] %s DCNT:0x%08x\n",
 230                         cmd->data->error, host->dbgmsg_dat,
 231                         readl(host->base + S3C2410_SDIDCNT));
 232         }
 233 }
 234 #else
 235 static void dbg_dumpcmd(struct s3cmci_host *host,
 236                         struct mmc_command *cmd, int fail) { }
 237
 238 static void prepare_dbgmsg(struct s3cmci_host *host, struct mmc_command *cmd,
 239                            int stop) { }
 240
 241 static void dbg_dumpregs(struct s3cmci_host *host, char *prefix) { }
 242
 243 #endif /* CONFIG_MMC_DEBUG */
 244
 245 /**
 246  * s3cmci_host_usedma - return whether the host is using dma or pio
 247  * @host: The host state
 248  *
 249  * Return true if the host is using DMA to transfer data, else false
 250  * to use PIO mode. Will return static data depending on the driver
 251  * configuration.
 252  */
 253 static inline bool s3cmci_host_usedma(struct s3cmci_host *host)
 254 {
 255 #ifdef CONFIG_MMC_S3C_PIO
 256         return false;
 257 #else /* CONFIG_MMC_S3C_DMA */
 258         return true;
 259 #endif
 260 }
 261
 262 static inline u32 enable_imask(struct s3cmci_host *host, u32 imask)
 263 {
 264         u32 newmask;
 265
 266         newmask = readl(host->base + host->sdiimsk);
 267         newmask |= imask;
 268
 269         writel(newmask, host->base + host->sdiimsk);
 270
 271         return newmask;
 272 }
 273
 274 static inline u32 disable_imask(struct s3cmci_host *host, u32 imask)
 275 {
 276         u32 newmask;
 277
 278         newmask = readl(host->base + host->sdiimsk);
 279         newmask &= ~imask;
 280
 281         writel(newmask, host->base + host->sdiimsk);
 282
 283         return newmask;
 284 }
 285
 286 static inline void clear_imask(struct s3cmci_host *host)
 287 {
 288         u32 mask = readl(host->base + host->sdiimsk);
 289
 290         /* preserve the SDIO IRQ mask state */
 291         mask &= S3C2410_SDIIMSK_SDIOIRQ;
 292         writel(mask, host->base + host->sdiimsk);
 293 }
 294
 295 /**
 296  * s3cmci_check_sdio_irq - test whether the SDIO IRQ is being signalled
 297  * @host: The host to check.
 298  *
 299  * Test to see if the SDIO interrupt is being signalled in case the
 300  * controller has failed to re-detect a card interrupt. Read GPE8 and
 301  * see if it is low and if so, signal a SDIO interrupt.
 302  *
 303  * This is currently called if a request is finished (we assume that the
 304  * bus is now idle) and when the SDIO IRQ is enabled in case the IRQ is
 305  * already being indicated.
 306 */
 307 static void s3cmci_check_sdio_irq(struct s3cmci_host *host)
 308 {
 309         if (host->sdio_irqen) {
 310                 if (gpio_get_value(S3C2410_GPE(8)) == 0) {
 311                         pr_debug("%s: signalling irq\n", __func__);
 312                         mmc_signal_sdio_irq(host->mmc);
 313                 }
 314         }
 315 }
 316
 317 static inline int get_data_buffer(struct s3cmci_host *host,
 318                                   u32 *bytes, u32 **pointer)
 319 {
 320         struct scatterlist *sg;
 321
 322         if (host->pio_active == XFER_NONE)
 323                 return -EINVAL;
 324
 325         if ((!host->mrq) || (!host->mrq->data))
 326                 return -EINVAL;
 327
 328         if (host->pio_sgptr >= host->mrq->data->sg_len) {
 329                 dbg(host, dbg_debug, "no more buffers (%i/%i)\n",
 330                       host->pio_sgptr, host->mrq->data->sg_len);
 331                 return -EBUSY;
 332         }
 333         sg = &host->mrq->data->sg[host->pio_sgptr];
 334
 335         *bytes = sg->length;
 336         *pointer = sg_virt(sg);
 337
 338         host->pio_sgptr++;
 339
 340         dbg(host, dbg_sg, "new buffer (%i/%i)\n",
 341             host->pio_sgptr, host->mrq->data->sg_len);
 342
 343         return 0;
 344 }
 345
 346 static inline u32 fifo_count(struct s3cmci_host *host)
 347 {
 348         u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
 349
 350         fifostat &= S3C2410_SDIFSTA_COUNTMASK;
 351         return fifostat;
 352 }
 353
 354 static inline u32 fifo_free(struct s3cmci_host *host)
 355 {
 356         u32 fifostat = readl(host->base + S3C2410_SDIFSTA);
 357
 358         fifostat &= S3C2410_SDIFSTA_COUNTMASK;
 359         return 63 - fifostat;
 360 }
 361
 362 /**
 363  * s3cmci_enable_irq - enable IRQ, after having disabled it.
 364  * @host: The device state.
 365  * @more: True if more IRQs are expected from transfer.
 366  *
 367  * Enable the main IRQ if needed after it has been disabled.
 368  *
 369  * The IRQ can be one of the following states:
 370  *      - disabled during IDLE
 371  *      - disabled whilst processing data
 372  *      - enabled during transfer
 373  *      - enabled whilst awaiting SDIO interrupt detection
 374  */
 375 static void s3cmci_enable_irq(struct s3cmci_host *host, bool more)
 376 {
 377         unsigned long flags;
 378         bool enable = false;
 379
 380         local_irq_save(flags);
 381
 382         host->irq_enabled = more;
 383         host->irq_disabled = false;
 384
 385         enable = more | host->sdio_irqen;
 386
 387         if (host->irq_state != enable) {
 388                 host->irq_state = enable;
 389
 390                 if (enable)
 391                         enable_irq(host->irq);
 392                 else
 393                         disable_irq(host->irq);
 394         }
 395
 396         local_irq_restore(flags);
 397 }
 398
 399 /**
 400  *
 401  */
 402 static void s3cmci_disable_irq(struct s3cmci_host *host, bool transfer)
 403 {
 404         unsigned long flags;
 405
 406         local_irq_save(flags);
 407
 408         /* pr_debug("%s: transfer %d\n", __func__, transfer); */
 409
 410         host->irq_disabled = transfer;
 411
 412         if (transfer && host->irq_state) {
 413                 host->irq_state = false;
 414                 disable_irq(host->irq);
 415         }
 416
 417         local_irq_restore(flags);
 418 }
 419
 420 static void do_pio_read(struct s3cmci_host *host)
 421 {
 422         int res;
 423         u32 fifo;
 424         u32 *ptr;
 425         u32 fifo_words;
 426         void __iomem *from_ptr;
 427
 428         /* write real prescaler to host, it might be set slow to fix */
 429         writel(host->prescaler, host->base + S3C2410_SDIPRE);
 430
 431         from_ptr = host->base + host->sdidata;
 432
 433         while ((fifo = fifo_count(host))) {
 434                 if (!host->pio_bytes) {
 435                         res = get_data_buffer(host, &host->pio_bytes,
 436                                               &host->pio_ptr);
 437                         if (res) {
 438                                 host->pio_active = XFER_NONE;
 439                                 host->complete_what = COMPLETION_FINALIZE;
 440
 441                                 dbg(host, dbg_pio, "pio_read(): "
 442                                     "complete (no more data).\n");
 443                                 return;
 444                         }
 445
 446                         dbg(host, dbg_pio,
 447                             "pio_read(): new target: [%i]@[%p]\n",
 448                             host->pio_bytes, host->pio_ptr);
 449                 }
 450
 451                 dbg(host, dbg_pio,
 452                     "pio_read(): fifo:[%02i] buffer:[%03i] dcnt:[%08X]\n",
 453                     fifo, host->pio_bytes,
 454                     readl(host->base + S3C2410_SDIDCNT));
 455
 456                 /* If we have reached the end of the block, we can
 457                  * read a word and get 1 to 3 bytes.  If we in the
 458                  * middle of the block, we have to read full words,
 459                  * otherwise we will write garbage, so round down to
 460                  * an even multiple of 4. */
 461                 if (fifo >= host->pio_bytes)
 462                         fifo = host->pio_bytes;
 463                 else
 464                         fifo -= fifo & 3;
 465
 466                 host->pio_bytes -= fifo;
 467                 host->pio_count += fifo;
 468
 469                 fifo_words = fifo >> 2;
 470                 ptr = host->pio_ptr;
 471                 while (fifo_words--)
 472                         *ptr++ = readl(from_ptr);
 473                 host->pio_ptr = ptr;
 474
 475                 if (fifo & 3) {
 476                         u32 n = fifo & 3;
 477                         u32 data = readl(from_ptr);
 478                         u8 *p = (u8 *)host->pio_ptr;
 479
 480                         while (n--) {
 481                                 *p++ = data;
 482                                 data >>= 8;
 483                         }
 484                 }
 485         }
 486
 487         if (!host->pio_bytes) {
 488                 res = get_data_buffer(host, &host->pio_bytes, &host->pio_ptr);
 489                 if (res) {
 490                         dbg(host, dbg_pio,
 491                             "pio_read(): complete (no more buffers).\n");
 492                         host->pio_active = XFER_NONE;
 493                         host->complete_what = COMPLETION_FINALIZE;
 494
 495                         return;
 496                 }
 497         }
 498
 499         enable_imask(host,
 500                      S3C2410_SDIIMSK_RXFIFOHALF | S3C2410_SDIIMSK_RXFIFOLAST);
 501 }
 502
 503 static void do_pio_write(struct s3cmci_host *host)
 504 {
 505         void __iomem *to_ptr;
 506         int res;
 507         u32 fifo;
 508         u32 *ptr;
 509
 510         to_ptr = host->base + host->sdidata;
 511
 512         while ((fifo = fifo_free(host)) > 3) {
 513                 if (!host->pio_bytes) {
 514                         res = get_data_buffer(host, &host->pio_bytes,
 515                                                         &host->pio_ptr);
 516                         if (res) {
 517                                 dbg(host, dbg_pio,
 518                                     "pio_write(): complete (no more data).\n");
 519                                 host->pio_active = XFER_NONE;
 520
 521                                 return;
 522                         }
 523
 524                         dbg(host, dbg_pio,
 525                             "pio_write(): new source: [%i]@[%p]\n",
 526                             host->pio_bytes, host->pio_ptr);
 527
 528                 }
 529
 530                 /* If we have reached the end of the block, we have to
 531                  * write exactly the remaining number of bytes.  If we
 532                  * in the middle of the block, we have to write full
 533                  * words, so round down to an even multiple of 4. */
 534                 if (fifo >= host->pio_bytes)
 535                         fifo = host->pio_bytes;
 536                 else
 537                         fifo -= fifo & 3;
 538
 539                 host->pio_bytes -= fifo;
 540                 host->pio_count += fifo;
 541
 542                 fifo = (fifo + 3) >> 2;
 543                 ptr = host->pio_ptr;
 544                 while (fifo--)
 545                         writel(*ptr++, to_ptr);
 546                 host->pio_ptr = ptr;
 547         }
 548
 549         enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
 550 }
 551
 552 static void pio_tasklet(unsigned long data)
 553 {
 554         struct s3cmci_host *host = (struct s3cmci_host *) data;
 555
 556         s3cmci_disable_irq(host, true);
 557
 558         if (host->pio_active == XFER_WRITE)
 559                 do_pio_write(host);
 560
 561         if (host->pio_active == XFER_READ)
 562                 do_pio_read(host);
 563
 564         if (host->complete_what == COMPLETION_FINALIZE) {
 565                 clear_imask(host);
 566                 if (host->pio_active != XFER_NONE) {
 567                         dbg(host, dbg_err, "unfinished %s "
 568                             "- pio_count:[%u] pio_bytes:[%u]\n",
 569                             (host->pio_active == XFER_READ) ? "read" : "write",
 570                             host->pio_count, host->pio_bytes);
 571
 572                         if (host->mrq->data)
 573                                 host->mrq->data->error = -EINVAL;
 574                 }
 575
 576                 s3cmci_enable_irq(host, false);
 577                 finalize_request(host);
 578         } else
 579                 s3cmci_enable_irq(host, true);
 580 }
 581
 582 /*
 583  * ISR for SDI Interface IRQ
 584  * Communication between driver and ISR works as follows:
 585  *   host->mrq                  points to current request
 586  *   host->complete_what        Indicates when the request is considered done
 587  *     COMPLETION_CMDSENT         when the command was sent
 588  *     COMPLETION_RSPFIN          when a response was received
 589  *     COMPLETION_XFERFINISH      when the data transfer is finished
 590  *     COMPLETION_XFERFINISH_RSPFIN both of the above.
 591  *   host->complete_request     is the completion-object the driver waits for
 592  *
 593  * 1) Driver sets up host->mrq and host->complete_what
 594  * 2) Driver prepares the transfer
 595  * 3) Driver enables interrupts
 596  * 4) Driver starts transfer
 597  * 5) Driver waits for host->complete_rquest
 598  * 6) ISR checks for request status (errors and success)
 599  * 6) ISR sets host->mrq->cmd->error and host->mrq->data->error
 600  * 7) ISR completes host->complete_request
 601  * 8) ISR disables interrupts
 602  * 9) Driver wakes up and takes care of the request
 603  *
 604  * Note: "->error"-fields are expected to be set to 0 before the request
 605  *       was issued by mmc.c - therefore they are only set, when an error
 606  *       contition comes up
 607  */
 608
 609 static irqreturn_t s3cmci_irq(int irq, void *dev_id)
 610 {
 611         struct s3cmci_host *host = dev_id;
 612         struct mmc_command *cmd;
 613         u32 mci_csta, mci_dsta, mci_fsta, mci_dcnt, mci_imsk;
 614         u32 mci_cclear = 0, mci_dclear;
 615         unsigned long iflags;
 616
 617         mci_dsta = readl(host->base + S3C2410_SDIDSTA);
 618         mci_imsk = readl(host->base + host->sdiimsk);
 619
 620         if (mci_dsta & S3C2410_SDIDSTA_SDIOIRQDETECT) {
 621                 if (mci_imsk & S3C2410_SDIIMSK_SDIOIRQ) {
 622                         mci_dclear = S3C2410_SDIDSTA_SDIOIRQDETECT;
 623                         writel(mci_dclear, host->base + S3C2410_SDIDSTA);
 624
 625                         mmc_signal_sdio_irq(host->mmc);
 626                         return IRQ_HANDLED;
 627                 }
 628         }
 629
 630         spin_lock_irqsave(&host->complete_lock, iflags);
 631
 632         mci_csta = readl(host->base + S3C2410_SDICMDSTAT);
 633         mci_dcnt = readl(host->base + S3C2410_SDIDCNT);
 634         mci_fsta = readl(host->base + S3C2410_SDIFSTA);
 635         mci_dclear = 0;
 636
 637         if ((host->complete_what == COMPLETION_NONE) ||
 638             (host->complete_what == COMPLETION_FINALIZE)) {
 639                 host->status = "nothing to complete";
 640                 clear_imask(host);
 641                 goto irq_out;
 642         }
 643
 644         if (!host->mrq) {
 645                 host->status = "no active mrq";
 646                 clear_imask(host);
 647                 goto irq_out;
 648         }
 649
 650         cmd = host->cmd_is_stop ? host->mrq->stop : host->mrq->cmd;
 651
 652         if (!cmd) {
 653                 host->status = "no active cmd";
 654                 clear_imask(host);
 655                 goto irq_out;
 656         }
 657
 658         if (!s3cmci_host_usedma(host)) {
 659                 if ((host->pio_active == XFER_WRITE) &&
 660                     (mci_fsta & S3C2410_SDIFSTA_TFDET)) {
 661
 662                         disable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
 663                         tasklet_schedule(&host->pio_tasklet);
 664                         host->status = "pio tx";
 665                 }
 666
 667                 if ((host->pio_active == XFER_READ) &&
 668                     (mci_fsta & S3C2410_SDIFSTA_RFDET)) {
 669
 670                         disable_imask(host,
 671                                       S3C2410_SDIIMSK_RXFIFOHALF |
 672                                       S3C2410_SDIIMSK_RXFIFOLAST);
 673
 674                         tasklet_schedule(&host->pio_tasklet);
 675                         host->status = "pio rx";
 676                 }
 677         }
 678
 679         if (mci_csta & S3C2410_SDICMDSTAT_CMDTIMEOUT) {
 680                 dbg(host, dbg_err, "CMDSTAT: error CMDTIMEOUT\n");
 681                 cmd->error = -ETIMEDOUT;
 682                 host->status = "error: command timeout";
 683                 goto fail_transfer;
 684         }
 685
 686         if (mci_csta & S3C2410_SDICMDSTAT_CMDSENT) {
 687                 if (host->complete_what == COMPLETION_CMDSENT) {
 688                         host->status = "ok: command sent";
 689                         goto close_transfer;
 690                 }
 691
 692                 mci_cclear |= S3C2410_SDICMDSTAT_CMDSENT;
 693         }
 694
 695         if (mci_csta & S3C2410_SDICMDSTAT_CRCFAIL) {
 696                 if (cmd->flags & MMC_RSP_CRC) {
 697                         if (host->mrq->cmd->flags & MMC_RSP_136) {
 698                                 dbg(host, dbg_irq,
 699                                     "fixup: ignore CRC fail with long rsp\n");
 700                         } else {
 701                                 /* note, we used to fail the transfer
 702                                  * here, but it seems that this is just
 703                                  * the hardware getting it wrong.
 704                                  *
 705                                  * cmd->error = -EILSEQ;
 706                                  * host->status = "error: bad command crc";
 707                                  * goto fail_transfer;
 708                                 */
 709                         }
 710                 }
 711
 712                 mci_cclear |= S3C2410_SDICMDSTAT_CRCFAIL;
 713         }
 714
 715         if (mci_csta & S3C2410_SDICMDSTAT_RSPFIN) {
 716                 if (host->complete_what == COMPLETION_RSPFIN) {
 717                         host->status = "ok: command response received";
 718                         goto close_transfer;
 719                 }
 720
 721                 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
 722                         host->complete_what = COMPLETION_XFERFINISH;
 723
 724                 mci_cclear |= S3C2410_SDICMDSTAT_RSPFIN;
 725         }
 726
 727         /* errors handled after this point are only relevant
 728            when a data transfer is in progress */
 729
 730         if (!cmd->data)
 731                 goto clear_status_bits;
 732
 733         /* Check for FIFO failure */
 734         if (host->is2440) {
 735                 if (mci_fsta & S3C2440_SDIFSTA_FIFOFAIL) {
 736                         dbg(host, dbg_err, "FIFO failure\n");
 737                         host->mrq->data->error = -EILSEQ;
 738                         host->status = "error: 2440 fifo failure";
 739                         goto fail_transfer;
 740                 }
 741         } else {
 742                 if (mci_dsta & S3C2410_SDIDSTA_FIFOFAIL) {
 743                         dbg(host, dbg_err, "FIFO failure\n");
 744                         cmd->data->error = -EILSEQ;
 745                         host->status = "error:  fifo failure";
 746                         goto fail_transfer;
 747                 }
 748         }
 749
 750         if (mci_dsta & S3C2410_SDIDSTA_RXCRCFAIL) {
 751                 dbg(host, dbg_err, "bad data crc (outgoing)\n");
 752                 cmd->data->error = -EILSEQ;
 753                 host->status = "error: bad data crc (outgoing)";
 754                 goto fail_transfer;
 755         }
 756
 757         if (mci_dsta & S3C2410_SDIDSTA_CRCFAIL) {
 758                 dbg(host, dbg_err, "bad data crc (incoming)\n");
 759                 cmd->data->error = -EILSEQ;
 760                 host->status = "error: bad data crc (incoming)";
 761                 goto fail_transfer;
 762         }
 763
 764         if (mci_dsta & S3C2410_SDIDSTA_DATATIMEOUT) {
 765                 dbg(host, dbg_err, "data timeout\n");
 766                 cmd->data->error = -ETIMEDOUT;
 767                 host->status = "error: data timeout";
 768                 goto fail_transfer;
 769         }
 770
 771         if (mci_dsta & S3C2410_SDIDSTA_XFERFINISH) {
 772                 if (host->complete_what == COMPLETION_XFERFINISH) {
 773                         host->status = "ok: data transfer completed";
 774                         goto close_transfer;
 775                 }
 776
 777                 if (host->complete_what == COMPLETION_XFERFINISH_RSPFIN)
 778                         host->complete_what = COMPLETION_RSPFIN;
 779
 780                 mci_dclear |= S3C2410_SDIDSTA_XFERFINISH;
 781         }
 782
 783 clear_status_bits:
 784         writel(mci_cclear, host->base + S3C2410_SDICMDSTAT);
 785         writel(mci_dclear, host->base + S3C2410_SDIDSTA);
 786
 787         goto irq_out;
 788
 789 fail_transfer:
 790         host->pio_active = XFER_NONE;
 791
 792 close_transfer:
 793         host->complete_what = COMPLETION_FINALIZE;
 794
 795         clear_imask(host);
 796         tasklet_schedule(&host->pio_tasklet);
 797
 798         goto irq_out;
 799
 800 irq_out:
 801         dbg(host, dbg_irq,
 802             "csta:0x%08x dsta:0x%08x fsta:0x%08x dcnt:0x%08x status:%s.\n",
 803             mci_csta, mci_dsta, mci_fsta, mci_dcnt, host->status);
 804
 805         spin_unlock_irqrestore(&host->complete_lock, iflags);
 806         return IRQ_HANDLED;
 807
 808 }
 809
 810 static void s3cmci_dma_done_callback(void *arg)
 811 {
 812         struct s3cmci_host *host = arg;
 813         unsigned long iflags;
 814
 815         BUG_ON(!host->mrq);
 816         BUG_ON(!host->mrq->data);
 817
 818         spin_lock_irqsave(&host->complete_lock, iflags);
 819
 820         dbg(host, dbg_dma, "DMA FINISHED\n");
 821
 822         host->dma_complete = 1;
 823         host->complete_what = COMPLETION_FINALIZE;
 824
 825         tasklet_schedule(&host->pio_tasklet);
 826         spin_unlock_irqrestore(&host->complete_lock, iflags);
 827
 828 }
 829
 830 static void finalize_request(struct s3cmci_host *host)
 831 {
 832         struct mmc_request *mrq = host->mrq;
 833         struct mmc_command *cmd;
 834         int debug_as_failure = 0;
 835
 836         if (host->complete_what != COMPLETION_FINALIZE)
 837                 return;
 838
 839         if (!mrq)
 840                 return;
 841         cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
 842
 843         if (cmd->data && (cmd->error == 0) &&
 844             (cmd->data->error == 0)) {
 845                 if (s3cmci_host_usedma(host) && (!host->dma_complete)) {
 846                         dbg(host, dbg_dma, "DMA Missing (%d)!\n",
 847                             host->dma_complete);
 848                         return;
 849                 }
 850         }
 851
 852         /* Read response from controller. */
 853         cmd->resp[0] = readl(host->base + S3C2410_SDIRSP0);
 854         cmd->resp[1] = readl(host->base + S3C2410_SDIRSP1);
 855         cmd->resp[2] = readl(host->base + S3C2410_SDIRSP2);
 856         cmd->resp[3] = readl(host->base + S3C2410_SDIRSP3);
 857
 858         writel(host->prescaler, host->base + S3C2410_SDIPRE);
 859
 860         if (cmd->error)
 861                 debug_as_failure = 1;
 862
 863         if (cmd->data && cmd->data->error)
 864                 debug_as_failure = 1;
 865
 866         dbg_dumpcmd(host, cmd, debug_as_failure);
 867
 868         /* Cleanup controller */
 869         writel(0, host->base + S3C2410_SDICMDARG);
 870         writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
 871         writel(0, host->base + S3C2410_SDICMDCON);
 872         clear_imask(host);
 873
 874         if (cmd->data && cmd->error)
 875                 cmd->data->error = cmd->error;
 876
 877         if (cmd->data && cmd->data->stop && (!host->cmd_is_stop)) {
 878                 host->cmd_is_stop = 1;
 879                 s3cmci_send_request(host->mmc);
 880                 return;
 881         }
 882
 883         /* If we have no data transfer we are finished here */
 884         if (!mrq->data)
 885                 goto request_done;
 886
 887         /* Calculate the amout of bytes transfer if there was no error */
 888         if (mrq->data->error == 0) {
 889                 mrq->data->bytes_xfered =
 890                         (mrq->data->blocks * mrq->data->blksz);
 891         } else {
 892                 mrq->data->bytes_xfered = 0;
 893         }
 894
 895         /* If we had an error while transferring data we flush the
 896          * DMA channel and the fifo to clear out any garbage. */
 897         if (mrq->data->error != 0) {
 898                 if (s3cmci_host_usedma(host))
 899                         dmaengine_terminate_all(host->dma);
 900
 901                 if (host->is2440) {
 902                         /* Clear failure register and reset fifo. */
 903                         writel(S3C2440_SDIFSTA_FIFORESET |
 904                                S3C2440_SDIFSTA_FIFOFAIL,
 905                                host->base + S3C2410_SDIFSTA);
 906                 } else {
 907                         u32 mci_con;
 908
 909                         /* reset fifo */
 910                         mci_con = readl(host->base + S3C2410_SDICON);
 911                         mci_con |= S3C2410_SDICON_FIFORESET;
 912
 913                         writel(mci_con, host->base + S3C2410_SDICON);
 914                 }
 915         }
 916
 917 request_done:
 918         host->complete_what = COMPLETION_NONE;
 919         host->mrq = NULL;
 920
 921         s3cmci_check_sdio_irq(host);
 922         mmc_request_done(host->mmc, mrq);
 923 }
 924
 925 static void s3cmci_send_command(struct s3cmci_host *host,
 926                                         struct mmc_command *cmd)
 927 {
 928         u32 ccon, imsk;
 929
 930         imsk  = S3C2410_SDIIMSK_CRCSTATUS | S3C2410_SDIIMSK_CMDTIMEOUT |
 931                 S3C2410_SDIIMSK_RESPONSEND | S3C2410_SDIIMSK_CMDSENT |
 932                 S3C2410_SDIIMSK_RESPONSECRC;
 933
 934         enable_imask(host, imsk);
 935
 936         if (cmd->data)
 937                 host->complete_what = COMPLETION_XFERFINISH_RSPFIN;
 938         else if (cmd->flags & MMC_RSP_PRESENT)
 939                 host->complete_what = COMPLETION_RSPFIN;
 940         else
 941                 host->complete_what = COMPLETION_CMDSENT;
 942
 943         writel(cmd->arg, host->base + S3C2410_SDICMDARG);
 944
 945         ccon  = cmd->opcode & S3C2410_SDICMDCON_INDEX;
 946         ccon |= S3C2410_SDICMDCON_SENDERHOST | S3C2410_SDICMDCON_CMDSTART;
 947
 948         if (cmd->flags & MMC_RSP_PRESENT)
 949                 ccon |= S3C2410_SDICMDCON_WAITRSP;
 950
 951         if (cmd->flags & MMC_RSP_136)
 952                 ccon |= S3C2410_SDICMDCON_LONGRSP;
 953
 954         writel(ccon, host->base + S3C2410_SDICMDCON);
 955 }
 956
 957 static int s3cmci_setup_data(struct s3cmci_host *host, struct mmc_data *data)
 958 {
 959         u32 dcon, imsk, stoptries = 3;
 960
 961         if ((data->blksz & 3) != 0) {
 962                 /* We cannot deal with unaligned blocks with more than
 963                  * one block being transferred. */
 964
 965                 if (data->blocks > 1) {
 966                         pr_warn("%s: can't do non-word sized block transfers (blksz %d)\n",
 967                                 __func__, data->blksz);
 968                         return -EINVAL;
 969                 }
 970         }
 971
 972         while (readl(host->base + S3C2410_SDIDSTA) &
 973                (S3C2410_SDIDSTA_TXDATAON | S3C2410_SDIDSTA_RXDATAON)) {
 974
 975                 dbg(host, dbg_err,
 976                     "mci_setup_data() transfer stillin progress.\n");
 977
 978                 writel(S3C2410_SDIDCON_STOP, host->base + S3C2410_SDIDCON);
 979                 s3cmci_reset(host);
 980
 981                 if ((stoptries--) == 0) {
 982                         dbg_dumpregs(host, "DRF");
 983                         return -EINVAL;
 984                 }
 985         }
 986
 987         dcon  = data->blocks & S3C2410_SDIDCON_BLKNUM_MASK;
 988
 989         if (s3cmci_host_usedma(host))
 990                 dcon |= S3C2410_SDIDCON_DMAEN;
 991
 992         if (host->bus_width == MMC_BUS_WIDTH_4)
 993                 dcon |= S3C2410_SDIDCON_WIDEBUS;
 994
 995         dcon |= S3C2410_SDIDCON_BLOCKMODE;
 996
 997         if (data->flags & MMC_DATA_WRITE) {
 998                 dcon |= S3C2410_SDIDCON_TXAFTERRESP;
 999                 dcon |= S3C2410_SDIDCON_XFER_TXSTART;
1000         }
1001
1002         if (data->flags & MMC_DATA_READ) {
1003                 dcon |= S3C2410_SDIDCON_RXAFTERCMD;
1004                 dcon |= S3C2410_SDIDCON_XFER_RXSTART;
1005         }
1006
1007         if (host->is2440) {
1008                 dcon |= S3C2440_SDIDCON_DS_WORD;
1009                 dcon |= S3C2440_SDIDCON_DATSTART;
1010         }
1011
1012         writel(dcon, host->base + S3C2410_SDIDCON);
1013
1014         /* write BSIZE register */
1015
1016         writel(data->blksz, host->base + S3C2410_SDIBSIZE);
1017
1018         /* add to IMASK register */
1019         imsk = S3C2410_SDIIMSK_FIFOFAIL | S3C2410_SDIIMSK_DATACRC |
1020                S3C2410_SDIIMSK_DATATIMEOUT | S3C2410_SDIIMSK_DATAFINISH;
1021
1022         enable_imask(host, imsk);
1023
1024         /* write TIMER register */
1025
1026         if (host->is2440) {
1027                 writel(0x007FFFFF, host->base + S3C2410_SDITIMER);
1028         } else {
1029                 writel(0x0000FFFF, host->base + S3C2410_SDITIMER);
1030
1031                 /* FIX: set slow clock to prevent timeouts on read */
1032                 if (data->flags & MMC_DATA_READ)
1033                         writel(0xFF, host->base + S3C2410_SDIPRE);
1034         }
1035
1036         return 0;
1037 }
1038
1039 #define BOTH_DIR (MMC_DATA_WRITE | MMC_DATA_READ)
1040
1041 static int s3cmci_prepare_pio(struct s3cmci_host *host, struct mmc_data *data)
1042 {
1043         int rw = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
1044
1045         BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1046
1047         host->pio_sgptr = 0;
1048         host->pio_bytes = 0;
1049         host->pio_count = 0;
1050         host->pio_active = rw ? XFER_WRITE : XFER_READ;
1051
1052         if (rw) {
1053                 do_pio_write(host);
1054                 enable_imask(host, S3C2410_SDIIMSK_TXFIFOHALF);
1055         } else {
1056                 enable_imask(host, S3C2410_SDIIMSK_RXFIFOHALF
1057                              | S3C2410_SDIIMSK_RXFIFOLAST);
1058         }
1059
1060         return 0;
1061 }
1062
1063 static int s3cmci_prepare_dma(struct s3cmci_host *host, struct mmc_data *data)
1064 {
1065         int rw = data->flags & MMC_DATA_WRITE;
1066         struct dma_async_tx_descriptor *desc;
1067         struct dma_slave_config conf = {
1068                 .src_addr = host->mem->start + host->sdidata,
1069                 .dst_addr = host->mem->start + host->sdidata,
1070                 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1071                 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1072         };
1073
1074         BUG_ON((data->flags & BOTH_DIR) == BOTH_DIR);
1075
1076         /* Restore prescaler value */
1077         writel(host->prescaler, host->base + S3C2410_SDIPRE);
1078
1079         if (!rw)
1080                 conf.direction = DMA_DEV_TO_MEM;
1081         else
1082                 conf.direction = DMA_MEM_TO_DEV;
1083
1084         dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1085                    mmc_get_dma_dir(data));
1086
1087         dmaengine_slave_config(host->dma, &conf);
1088         desc = dmaengine_prep_slave_sg(host->dma, data->sg, data->sg_len,
1089                 conf.direction,
1090                 DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
1091         if (!desc)
1092                 goto unmap_exit;
1093         desc->callback = s3cmci_dma_done_callback;
1094         desc->callback_param = host;
1095         dmaengine_submit(desc);
1096         dma_async_issue_pending(host->dma);
1097
1098         return 0;
1099
1100 unmap_exit:
1101         dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1102                      mmc_get_dma_dir(data));
1103         return -ENOMEM;
1104 }
1105
1106 static void s3cmci_send_request(struct mmc_host *mmc)
1107 {
1108         struct s3cmci_host *host = mmc_priv(mmc);
1109         struct mmc_request *mrq = host->mrq;
1110         struct mmc_command *cmd = host->cmd_is_stop ? mrq->stop : mrq->cmd;
1111
1112         host->ccnt++;
1113         prepare_dbgmsg(host, cmd, host->cmd_is_stop);
1114
1115         /* Clear command, data and fifo status registers
1116            Fifo clear only necessary on 2440, but doesn't hurt on 2410
1117         */
1118         writel(0xFFFFFFFF, host->base + S3C2410_SDICMDSTAT);
1119         writel(0xFFFFFFFF, host->base + S3C2410_SDIDSTA);
1120         writel(0xFFFFFFFF, host->base + S3C2410_SDIFSTA);
1121
1122         if (cmd->data) {
1123                 int res = s3cmci_setup_data(host, cmd->data);
1124
1125                 host->dcnt++;
1126
1127                 if (res) {
1128                         dbg(host, dbg_err, "setup data error %d\n", res);
1129                         cmd->error = res;
1130                         cmd->data->error = res;
1131
1132                         mmc_request_done(mmc, mrq);
1133                         return;
1134                 }
1135
1136                 if (s3cmci_host_usedma(host))
1137                         res = s3cmci_prepare_dma(host, cmd->data);
1138                 else
1139                         res = s3cmci_prepare_pio(host, cmd->data);
1140
1141                 if (res) {
1142                         dbg(host, dbg_err, "data prepare error %d\n", res);
1143                         cmd->error = res;
1144                         cmd->data->error = res;
1145
1146                         mmc_request_done(mmc, mrq);
1147                         return;
1148                 }
1149         }
1150
1151         /* Send command */
1152         s3cmci_send_command(host, cmd);
1153
1154         /* Enable Interrupt */
1155         s3cmci_enable_irq(host, true);
1156 }
1157
1158 static void s3cmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1159 {
1160         struct s3cmci_host *host = mmc_priv(mmc);
1161
1162         host->status = "mmc request";
1163         host->cmd_is_stop = 0;
1164         host->mrq = mrq;
1165
1166         if (mmc_gpio_get_cd(mmc) == 0) {
1167                 dbg(host, dbg_err, "%s: no medium present\n", __func__);
1168                 host->mrq->cmd->error = -ENOMEDIUM;
1169                 mmc_request_done(mmc, mrq);
1170         } else
1171                 s3cmci_send_request(mmc);
1172 }
1173
1174 static void s3cmci_set_clk(struct s3cmci_host *host, struct mmc_ios *ios)
1175 {
1176         u32 mci_psc;
1177
1178         /* Set clock */
1179         for (mci_psc = 0; mci_psc < 255; mci_psc++) {
1180                 host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1));
1181
1182                 if (host->real_rate <= ios->clock)
1183                         break;
1184         }
1185
1186         if (mci_psc > 255)
1187                 mci_psc = 255;
1188
1189         host->prescaler = mci_psc;
1190         writel(host->prescaler, host->base + S3C2410_SDIPRE);
1191
1192         /* If requested clock is 0, real_rate will be 0, too */
1193         if (ios->clock == 0)
1194                 host->real_rate = 0;
1195 }
1196
1197 static void s3cmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1198 {
1199         struct s3cmci_host *host = mmc_priv(mmc);
1200         u32 mci_con;
1201
1202         /* Set the power state */
1203
1204         mci_con = readl(host->base + S3C2410_SDICON);
1205
1206         switch (ios->power_mode) {
1207         case MMC_POWER_ON:
1208         case MMC_POWER_UP:
1209                 /* Configure GPE5...GPE10 pins in SD mode */
1210                 if (!host->pdev->dev.of_node)
1211                         s3c_gpio_cfgall_range(S3C2410_GPE(5), 6, S3C_GPIO_SFN(2),
1212                                               S3C_GPIO_PULL_NONE);
1213
1214                 if (host->pdata->set_power)
1215                         host->pdata->set_power(ios->power_mode, ios->vdd);
1216
1217                 if (!host->is2440)
1218                         mci_con |= S3C2410_SDICON_FIFORESET;
1219
1220                 break;
1221
1222         case MMC_POWER_OFF:
1223         default:
1224                 if (!host->pdev->dev.of_node)
1225                         gpio_direction_output(S3C2410_GPE(5), 0);
1226
1227                 if (host->is2440)
1228                         mci_con |= S3C2440_SDICON_SDRESET;
1229
1230                 if (host->pdata->set_power)
1231                         host->pdata->set_power(ios->power_mode, ios->vdd);
1232
1233                 break;
1234         }
1235
1236         s3cmci_set_clk(host, ios);
1237
1238         /* Set CLOCK_ENABLE */
1239         if (ios->clock)
1240                 mci_con |= S3C2410_SDICON_CLOCKTYPE;
1241         else
1242                 mci_con &= ~S3C2410_SDICON_CLOCKTYPE;
1243
1244         writel(mci_con, host->base + S3C2410_SDICON);
1245
1246         if ((ios->power_mode == MMC_POWER_ON) ||
1247             (ios->power_mode == MMC_POWER_UP)) {
1248                 dbg(host, dbg_conf, "running at %lukHz (requested: %ukHz).\n",
1249                         host->real_rate/1000, ios->clock/1000);
1250         } else {
1251                 dbg(host, dbg_conf, "powered down.\n");
1252         }
1253
1254         host->bus_width = ios->bus_width;
1255 }
1256
1257 static void s3cmci_reset(struct s3cmci_host *host)
1258 {
1259         u32 con = readl(host->base + S3C2410_SDICON);
1260
1261         con |= S3C2440_SDICON_SDRESET;
1262         writel(con, host->base + S3C2410_SDICON);
1263 }
1264
1265 static void s3cmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1266 {
1267         struct s3cmci_host *host = mmc_priv(mmc);
1268         unsigned long flags;
1269         u32 con;
1270
1271         local_irq_save(flags);
1272
1273         con = readl(host->base + S3C2410_SDICON);
1274         host->sdio_irqen = enable;
1275
1276         if (enable == host->sdio_irqen)
1277                 goto same_state;
1278
1279         if (enable) {
1280                 con |= S3C2410_SDICON_SDIOIRQ;
1281                 enable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1282
1283                 if (!host->irq_state && !host->irq_disabled) {
1284                         host->irq_state = true;
1285                         enable_irq(host->irq);
1286                 }
1287         } else {
1288                 disable_imask(host, S3C2410_SDIIMSK_SDIOIRQ);
1289                 con &= ~S3C2410_SDICON_SDIOIRQ;
1290
1291                 if (!host->irq_enabled && host->irq_state) {
1292                         disable_irq_nosync(host->irq);
1293                         host->irq_state = false;
1294                 }
1295         }
1296
1297         writel(con, host->base + S3C2410_SDICON);
1298
1299  same_state:
1300         local_irq_restore(flags);
1301
1302         s3cmci_check_sdio_irq(host);
1303 }
1304
1305 static const struct mmc_host_ops s3cmci_ops = {
1306         .request        = s3cmci_request,
1307         .set_ios        = s3cmci_set_ios,
1308         .get_ro         = mmc_gpio_get_ro,
1309         .get_cd         = mmc_gpio_get_cd,
1310         .enable_sdio_irq = s3cmci_enable_sdio_irq,
1311 };
1312
1313 static struct s3c24xx_mci_pdata s3cmci_def_pdata = {
1314         /* This is currently here to avoid a number of if (host->pdata)
1315          * checks. Any zero fields to ensure reasonable defaults are picked. */
1316          .no_wprotect = 1,
1317          .no_detect = 1,
1318 };
1319
1320 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1321
1322 static int s3cmci_cpufreq_transition(struct notifier_block *nb,
1323                                      unsigned long val, void *data)
1324 {
1325         struct s3cmci_host *host;
1326         struct mmc_host *mmc;
1327         unsigned long newclk;
1328         unsigned long flags;
1329
1330         host = container_of(nb, struct s3cmci_host, freq_transition);
1331         newclk = clk_get_rate(host->clk);
1332         mmc = host->mmc;
1333
1334         if ((val == CPUFREQ_PRECHANGE && newclk > host->clk_rate) ||
1335             (val == CPUFREQ_POSTCHANGE && newclk < host->clk_rate)) {
1336                 spin_lock_irqsave(&mmc->lock, flags);
1337
1338                 host->clk_rate = newclk;
1339
1340                 if (mmc->ios.power_mode != MMC_POWER_OFF &&
1341                     mmc->ios.clock != 0)
1342                         s3cmci_set_clk(host, &mmc->ios);
1343
1344                 spin_unlock_irqrestore(&mmc->lock, flags);
1345         }
1346
1347         return 0;
1348 }
1349
1350 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1351 {
1352         host->freq_transition.notifier_call = s3cmci_cpufreq_transition;
1353
1354         return cpufreq_register_notifier(&host->freq_transition,
1355                                          CPUFREQ_TRANSITION_NOTIFIER);
1356 }
1357
1358 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1359 {
1360         cpufreq_unregister_notifier(&host->freq_transition,
1361                                     CPUFREQ_TRANSITION_NOTIFIER);
1362 }
1363
1364 #else
1365 static inline int s3cmci_cpufreq_register(struct s3cmci_host *host)
1366 {
1367         return 0;
1368 }
1369
1370 static inline void s3cmci_cpufreq_deregister(struct s3cmci_host *host)
1371 {
1372 }
1373 #endif
1374
1375
1376 #ifdef CONFIG_DEBUG_FS
1377
1378 static int s3cmci_state_show(struct seq_file *seq, void *v)
1379 {
1380         struct s3cmci_host *host = seq->private;
1381
1382         seq_printf(seq, "Register base = 0x%08x\n", (u32)host->base);
1383         seq_printf(seq, "Clock rate = %ld\n", host->clk_rate);
1384         seq_printf(seq, "Prescale = %d\n", host->prescaler);
1385         seq_printf(seq, "is2440 = %d\n", host->is2440);
1386         seq_printf(seq, "IRQ = %d\n", host->irq);
1387         seq_printf(seq, "IRQ enabled = %d\n", host->irq_enabled);
1388         seq_printf(seq, "IRQ disabled = %d\n", host->irq_disabled);
1389         seq_printf(seq, "IRQ state = %d\n", host->irq_state);
1390         seq_printf(seq, "CD IRQ = %d\n", host->irq_cd);
1391         seq_printf(seq, "Do DMA = %d\n", s3cmci_host_usedma(host));
1392         seq_printf(seq, "SDIIMSK at %d\n", host->sdiimsk);
1393         seq_printf(seq, "SDIDATA at %d\n", host->sdidata);
1394
1395         return 0;
1396 }
1397
1398 DEFINE_SHOW_ATTRIBUTE(s3cmci_state);
1399
1400 #define DBG_REG(_r) { .addr = S3C2410_SDI##_r, .name = #_r }
1401
1402 struct s3cmci_reg {
1403         unsigned short  addr;
1404         unsigned char   *name;
1405 };
1406
1407 static const struct s3cmci_reg debug_regs[] = {
1408         DBG_REG(CON),
1409         DBG_REG(PRE),
1410         DBG_REG(CMDARG),
1411         DBG_REG(CMDCON),
1412         DBG_REG(CMDSTAT),
1413         DBG_REG(RSP0),
1414         DBG_REG(RSP1),
1415         DBG_REG(RSP2),
1416         DBG_REG(RSP3),
1417         DBG_REG(TIMER),
1418         DBG_REG(BSIZE),
1419         DBG_REG(DCON),
1420         DBG_REG(DCNT),
1421         DBG_REG(DSTA),
1422         DBG_REG(FSTA),
1423         {}
1424 };
1425
1426 static int s3cmci_regs_show(struct seq_file *seq, void *v)
1427 {
1428         struct s3cmci_host *host = seq->private;
1429         const struct s3cmci_reg *rptr = debug_regs;
1430
1431         for (; rptr->name; rptr++)
1432                 seq_printf(seq, "SDI%s\t=0x%08x\n", rptr->name,
1433                            readl(host->base + rptr->addr));
1434
1435         seq_printf(seq, "SDIIMSK\t=0x%08x\n", readl(host->base + host->sdiimsk));
1436
1437         return 0;
1438 }
1439
1440 DEFINE_SHOW_ATTRIBUTE(s3cmci_regs);
1441
1442 static void s3cmci_debugfs_attach(struct s3cmci_host *host)
1443 {
1444         struct device *dev = &host->pdev->dev;
1445         struct dentry *root;
1446
1447         root = debugfs_create_dir(dev_name(dev), NULL);
1448         host->debug_root = root;
1449
1450         debugfs_create_file("state", 0444, root, host, &s3cmci_state_fops);
1451         debugfs_create_file("regs", 0444, root, host, &s3cmci_regs_fops);
1452 }
1453
1454 static void s3cmci_debugfs_remove(struct s3cmci_host *host)
1455 {
1456         debugfs_remove_recursive(host->debug_root);
1457 }
1458
1459 #else
1460 static inline void s3cmci_debugfs_attach(struct s3cmci_host *host) { }
1461 static inline void s3cmci_debugfs_remove(struct s3cmci_host *host) { }
1462
1463 #endif /* CONFIG_DEBUG_FS */
1464
1465 static int s3cmci_probe_pdata(struct s3cmci_host *host)
1466 {
1467         struct platform_device *pdev = host->pdev;
1468         struct mmc_host *mmc = host->mmc;
1469         struct s3c24xx_mci_pdata *pdata;
1470         int i, ret;
1471
1472         host->is2440 = platform_get_device_id(pdev)->driver_data;
1473
1474         for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++) {
1475                 ret = gpio_request(i, dev_name(&pdev->dev));
1476                 if (ret) {
1477                         dev_err(&pdev->dev, "failed to get gpio %d\n", i);
1478
1479                         for (i--; i >= S3C2410_GPE(5); i--)
1480                                 gpio_free(i);
1481
1482                         return ret;
1483                 }
1484         }
1485
1486         if (!pdev->dev.platform_data)
1487                 pdev->dev.platform_data = &s3cmci_def_pdata;
1488
1489         pdata = pdev->dev.platform_data;
1490
1491         if (pdata->no_wprotect)
1492                 mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
1493
1494         if (pdata->no_detect)
1495                 mmc->caps |= MMC_CAP_NEEDS_POLL;
1496
1497         if (pdata->wprotect_invert)
1498                 mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1499
1500         /* If we get -ENOENT we have no card detect GPIO line */
1501         ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0);
1502         if (ret != -ENOENT) {
1503                 dev_err(&pdev->dev, "error requesting GPIO for CD %d\n",
1504                         ret);
1505                 return ret;
1506         }
1507
1508         ret = mmc_gpiod_request_ro(host->mmc, "wp", 0, 0);
1509         if (ret != -ENOENT) {
1510                 dev_err(&pdev->dev, "error requesting GPIO for WP %d\n",
1511                         ret);
1512                 return ret;
1513         }
1514
1515         return 0;
1516 }
1517
1518 static int s3cmci_probe_dt(struct s3cmci_host *host)
1519 {
1520         struct platform_device *pdev = host->pdev;
1521         struct s3c24xx_mci_pdata *pdata;
1522         struct mmc_host *mmc = host->mmc;
1523         int ret;
1524
1525         host->is2440 = (int) of_device_get_match_data(&pdev->dev);
1526
1527         ret = mmc_of_parse(mmc);
1528         if (ret)
1529                 return ret;
1530
1531         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1532         if (!pdata)
1533                 return -ENOMEM;
1534
1535         pdev->dev.platform_data = pdata;
1536
1537         return 0;
1538 }
1539
1540 static int s3cmci_probe(struct platform_device *pdev)
1541 {
1542         struct s3cmci_host *host;
1543         struct mmc_host *mmc;
1544         int ret;
1545         int i;
1546
1547         mmc = mmc_alloc_host(sizeof(struct s3cmci_host), &pdev->dev);
1548         if (!mmc) {
1549                 ret = -ENOMEM;
1550                 goto probe_out;
1551         }
1552
1553         host = mmc_priv(mmc);
1554         host->mmc       = mmc;
1555         host->pdev      = pdev;
1556
1557         if (pdev->dev.of_node)
1558                 ret = s3cmci_probe_dt(host);
1559         else
1560                 ret = s3cmci_probe_pdata(host);
1561
1562         if (ret)
1563                 goto probe_free_host;
1564
1565         host->pdata = pdev->dev.platform_data;
1566
1567         spin_lock_init(&host->complete_lock);
1568         tasklet_init(&host->pio_tasklet, pio_tasklet, (unsigned long) host);
1569
1570         if (host->is2440) {
1571                 host->sdiimsk   = S3C2440_SDIIMSK;
1572                 host->sdidata   = S3C2440_SDIDATA;
1573                 host->clk_div   = 1;
1574         } else {
1575                 host->sdiimsk   = S3C2410_SDIIMSK;
1576                 host->sdidata   = S3C2410_SDIDATA;
1577                 host->clk_div   = 2;
1578         }
1579
1580         host->complete_what     = COMPLETION_NONE;
1581         host->pio_active        = XFER_NONE;
1582
1583         host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1584         if (!host->mem) {
1585                 dev_err(&pdev->dev,
1586                         "failed to get io memory region resource.\n");
1587
1588                 ret = -ENOENT;
1589                 goto probe_free_gpio;
1590         }
1591
1592         host->mem = request_mem_region(host->mem->start,
1593                                        resource_size(host->mem), pdev->name);
1594
1595         if (!host->mem) {
1596                 dev_err(&pdev->dev, "failed to request io memory region.\n");
1597                 ret = -ENOENT;
1598                 goto probe_free_gpio;
1599         }
1600
1601         host->base = ioremap(host->mem->start, resource_size(host->mem));
1602         if (!host->base) {
1603                 dev_err(&pdev->dev, "failed to ioremap() io memory region.\n");
1604                 ret = -EINVAL;
1605                 goto probe_free_mem_region;
1606         }
1607
1608         host->irq = platform_get_irq(pdev, 0);
1609         if (host->irq <= 0) {
1610                 ret = -EINVAL;
1611                 goto probe_iounmap;
1612         }
1613
1614         if (request_irq(host->irq, s3cmci_irq, 0, DRIVER_NAME, host)) {
1615                 dev_err(&pdev->dev, "failed to request mci interrupt.\n");
1616                 ret = -ENOENT;
1617                 goto probe_iounmap;
1618         }
1619
1620         /* We get spurious interrupts even when we have set the IMSK
1621          * register to ignore everything, so use disable_irq() to make
1622          * ensure we don't lock the system with un-serviceable requests. */
1623
1624         disable_irq(host->irq);
1625         host->irq_state = false;
1626
1627         /* Depending on the dma state, get a DMA channel to use. */
1628
1629         if (s3cmci_host_usedma(host)) {
1630                 host->dma = dma_request_chan(&pdev->dev, "rx-tx");
1631                 ret = PTR_ERR_OR_ZERO(host->dma);
1632                 if (ret) {
1633                         dev_err(&pdev->dev, "cannot get DMA channel.\n");
1634                         goto probe_free_irq;
1635                 }
1636         }
1637
1638         host->clk = clk_get(&pdev->dev, "sdi");
1639         if (IS_ERR(host->clk)) {
1640                 dev_err(&pdev->dev, "failed to find clock source.\n");
1641                 ret = PTR_ERR(host->clk);
1642                 host->clk = NULL;
1643                 goto probe_free_dma;
1644         }
1645
1646         ret = clk_prepare_enable(host->clk);
1647         if (ret) {
1648                 dev_err(&pdev->dev, "failed to enable clock source.\n");
1649                 goto clk_free;
1650         }
1651
1652         host->clk_rate = clk_get_rate(host->clk);
1653
1654         mmc->ops        = &s3cmci_ops;
1655         mmc->ocr_avail  = MMC_VDD_32_33 | MMC_VDD_33_34;
1656 #ifdef CONFIG_MMC_S3C_HW_SDIO_IRQ
1657         mmc->caps       = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1658 #else
1659         mmc->caps       = MMC_CAP_4_BIT_DATA;
1660 #endif
1661         mmc->f_min      = host->clk_rate / (host->clk_div * 256);
1662         mmc->f_max      = host->clk_rate / host->clk_div;
1663
1664         if (host->pdata->ocr_avail)
1665                 mmc->ocr_avail = host->pdata->ocr_avail;
1666
1667         mmc->max_blk_count      = 4095;
1668         mmc->max_blk_size       = 4095;
1669         mmc->max_req_size       = 4095 * 512;
1670         mmc->max_seg_size       = mmc->max_req_size;
1671
1672         mmc->max_segs           = 128;
1673
1674         dbg(host, dbg_debug,
1675             "probe: mode:%s mapped mci_base:%p irq:%u irq_cd:%u dma:%p.\n",
1676             (host->is2440?"2440":""),
1677             host->base, host->irq, host->irq_cd, host->dma);
1678
1679         ret = s3cmci_cpufreq_register(host);
1680         if (ret) {
1681                 dev_err(&pdev->dev, "failed to register cpufreq\n");
1682                 goto free_dmabuf;
1683         }
1684
1685         ret = mmc_add_host(mmc);
1686         if (ret) {
1687                 dev_err(&pdev->dev, "failed to add mmc host.\n");
1688                 goto free_cpufreq;
1689         }
1690
1691         s3cmci_debugfs_attach(host);
1692
1693         platform_set_drvdata(pdev, mmc);
1694         dev_info(&pdev->dev, "%s - using %s, %s SDIO IRQ\n", mmc_hostname(mmc),
1695                  s3cmci_host_usedma(host) ? "dma" : "pio",
1696                  mmc->caps & MMC_CAP_SDIO_IRQ ? "hw" : "sw");
1697
1698         return 0;
1699
1700  free_cpufreq:
1701         s3cmci_cpufreq_deregister(host);
1702
1703  free_dmabuf:
1704         clk_disable_unprepare(host->clk);
1705
1706  clk_free:
1707         clk_put(host->clk);
1708
1709  probe_free_dma:
1710         if (s3cmci_host_usedma(host))
1711                 dma_release_channel(host->dma);
1712
1713  probe_free_irq:
1714         free_irq(host->irq, host);
1715
1716  probe_iounmap:
1717         iounmap(host->base);
1718
1719  probe_free_mem_region:
1720         release_mem_region(host->mem->start, resource_size(host->mem));
1721
1722  probe_free_gpio:
1723         if (!pdev->dev.of_node)
1724                 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1725                         gpio_free(i);
1726
1727  probe_free_host:
1728         mmc_free_host(mmc);
1729
1730  probe_out:
1731         return ret;
1732 }
1733
1734 static void s3cmci_shutdown(struct platform_device *pdev)
1735 {
1736         struct mmc_host *mmc = platform_get_drvdata(pdev);
1737         struct s3cmci_host *host = mmc_priv(mmc);
1738
1739         if (host->irq_cd >= 0)
1740                 free_irq(host->irq_cd, host);
1741
1742         s3cmci_debugfs_remove(host);
1743         s3cmci_cpufreq_deregister(host);
1744         mmc_remove_host(mmc);
1745         clk_disable_unprepare(host->clk);
1746 }
1747
1748 static int s3cmci_remove(struct platform_device *pdev)
1749 {
1750         struct mmc_host         *mmc  = platform_get_drvdata(pdev);
1751         struct s3cmci_host      *host = mmc_priv(mmc);
1752         int i;
1753
1754         s3cmci_shutdown(pdev);
1755
1756         clk_put(host->clk);
1757
1758         tasklet_disable(&host->pio_tasklet);
1759
1760         if (s3cmci_host_usedma(host))
1761                 dma_release_channel(host->dma);
1762
1763         free_irq(host->irq, host);
1764
1765         if (!pdev->dev.of_node)
1766                 for (i = S3C2410_GPE(5); i <= S3C2410_GPE(10); i++)
1767                         gpio_free(i);
1768
1769         iounmap(host->base);
1770         release_mem_region(host->mem->start, resource_size(host->mem));
1771
1772         mmc_free_host(mmc);
1773         return 0;
1774 }
1775
1776 static const struct of_device_id s3cmci_dt_match[] = {
1777         {
1778                 .compatible = "samsung,s3c2410-sdi",
1779                 .data = (void *)0,
1780         },
1781         {
1782                 .compatible = "samsung,s3c2412-sdi",
1783                 .data = (void *)1,
1784         },
1785         {
1786                 .compatible = "samsung,s3c2440-sdi",
1787                 .data = (void *)1,
1788         },
1789         { /* sentinel */ },
1790 };
1791 MODULE_DEVICE_TABLE(of, s3cmci_dt_match);
1792
1793 static const struct platform_device_id s3cmci_driver_ids[] = {
1794         {
1795                 .name   = "s3c2410-sdi",
1796                 .driver_data    = 0,
1797         }, {
1798                 .name   = "s3c2412-sdi",
1799                 .driver_data    = 1,
1800         }, {
1801                 .name   = "s3c2440-sdi",
1802                 .driver_data    = 1,
1803         },
1804         { }
1805 };
1806
1807 MODULE_DEVICE_TABLE(platform, s3cmci_driver_ids);
1808
1809 static struct platform_driver s3cmci_driver = {
1810         .driver = {
1811                 .name   = "s3c-sdi",
1812                 .of_match_table = s3cmci_dt_match,
1813         },
1814         .id_table       = s3cmci_driver_ids,
1815         .probe          = s3cmci_probe,
1816         .remove         = s3cmci_remove,
1817         .shutdown       = s3cmci_shutdown,
1818 };
1819
1820 module_platform_driver(s3cmci_driver);
1821
1822 MODULE_DESCRIPTION("Samsung S3C MMC/SD Card Interface driver");
1823 MODULE_LICENSE("GPL v2");
1824 MODULE_AUTHOR("Thomas Kleffel <[email protected]>, Ben Dooks <[email protected]>");