drivers/perf/arm-ccn.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *
   4  * Copyright (C) 2014 ARM Limited
   5  */
   6
   7 #include <linux/ctype.h>
   8 #include <linux/hrtimer.h>
   9 #include <linux/idr.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/io.h>
  12 #include <linux/module.h>
  13 #include <linux/mod_devicetable.h>
  14 #include <linux/perf_event.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/slab.h>
  17
  18 #define CCN_NUM_XP_PORTS 2
  19 #define CCN_NUM_VCS 4
  20 #define CCN_NUM_REGIONS 256
  21 #define CCN_REGION_SIZE 0x10000
  22
  23 #define CCN_ALL_OLY_ID                  0xff00
  24 #define CCN_ALL_OLY_ID__OLY_ID__SHIFT                   0
  25 #define CCN_ALL_OLY_ID__OLY_ID__MASK                    0x1f
  26 #define CCN_ALL_OLY_ID__NODE_ID__SHIFT                  8
  27 #define CCN_ALL_OLY_ID__NODE_ID__MASK                   0x3f
  28
  29 #define CCN_MN_ERRINT_STATUS            0x0008
  30 #define CCN_MN_ERRINT_STATUS__INTREQ__DESSERT           0x11
  31 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__ENABLE        0x02
  32 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLED      0x20
  33 #define CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE       0x22
  34 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_ENABLE   0x04
  35 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLED 0x40
  36 #define CCN_MN_ERRINT_STATUS__CORRECTED_ERRORS_DISABLE  0x44
  37 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE        0x08
  38 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED      0x80
  39 #define CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE       0x88
  40 #define CCN_MN_OLY_COMP_LIST_63_0       0x01e0
  41 #define CCN_MN_ERR_SIG_VAL_63_0         0x0300
  42 #define CCN_MN_ERR_SIG_VAL_63_0__DT                     (1 << 1)
  43
  44 #define CCN_DT_ACTIVE_DSM               0x0000
  45 #define CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(n)             ((n) * 8)
  46 #define CCN_DT_ACTIVE_DSM__DSM_ID__MASK                 0xff
  47 #define CCN_DT_CTL                      0x0028
  48 #define CCN_DT_CTL__DT_EN                               (1 << 0)
  49 #define CCN_DT_PMEVCNT(n)               (0x0100 + (n) * 0x8)
  50 #define CCN_DT_PMCCNTR                  0x0140
  51 #define CCN_DT_PMCCNTRSR                0x0190
  52 #define CCN_DT_PMOVSR                   0x0198
  53 #define CCN_DT_PMOVSR_CLR               0x01a0
  54 #define CCN_DT_PMOVSR_CLR__MASK                         0x1f
  55 #define CCN_DT_PMCR                     0x01a8
  56 #define CCN_DT_PMCR__OVFL_INTR_EN                       (1 << 6)
  57 #define CCN_DT_PMCR__PMU_EN                             (1 << 0)
  58 #define CCN_DT_PMSR                     0x01b0
  59 #define CCN_DT_PMSR_REQ                 0x01b8
  60 #define CCN_DT_PMSR_CLR                 0x01c0
  61
  62 #define CCN_HNF_PMU_EVENT_SEL           0x0600
  63 #define CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(n)             ((n) * 4)
  64 #define CCN_HNF_PMU_EVENT_SEL__ID__MASK                 0xf
  65
  66 #define CCN_XP_DT_CONFIG                0x0300
  67 #define CCN_XP_DT_CONFIG__DT_CFG__SHIFT(n)              ((n) * 4)
  68 #define CCN_XP_DT_CONFIG__DT_CFG__MASK                  0xf
  69 #define CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH          0x0
  70 #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT_0_OR_1     0x1
  71 #define CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(n)         (0x2 + (n))
  72 #define CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(n)       (0x4 + (n))
  73 #define CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(d, n) (0x8 + (d) * 4 + (n))
  74 #define CCN_XP_DT_INTERFACE_SEL         0x0308
  75 #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(n)    (0 + (n) * 8)
  76 #define CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK        0x1
  77 #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(n)   (1 + (n) * 8)
  78 #define CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK       0x1
  79 #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(n)    (2 + (n) * 8)
  80 #define CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK        0x3
  81 #define CCN_XP_DT_CMP_VAL_L(n)          (0x0310 + (n) * 0x40)
  82 #define CCN_XP_DT_CMP_VAL_H(n)          (0x0318 + (n) * 0x40)
  83 #define CCN_XP_DT_CMP_MASK_L(n)         (0x0320 + (n) * 0x40)
  84 #define CCN_XP_DT_CMP_MASK_H(n)         (0x0328 + (n) * 0x40)
  85 #define CCN_XP_DT_CONTROL               0x0370
  86 #define CCN_XP_DT_CONTROL__DT_ENABLE                    (1 << 0)
  87 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(n)         (12 + (n) * 4)
  88 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__MASK             0xf
  89 #define CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS           0xf
  90 #define CCN_XP_PMU_EVENT_SEL            0x0600
  91 #define CCN_XP_PMU_EVENT_SEL__ID__SHIFT(n)              ((n) * 7)
  92 #define CCN_XP_PMU_EVENT_SEL__ID__MASK                  0x3f
  93
  94 #define CCN_SBAS_PMU_EVENT_SEL          0x0600
  95 #define CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(n)            ((n) * 4)
  96 #define CCN_SBAS_PMU_EVENT_SEL__ID__MASK                0xf
  97
  98 #define CCN_RNI_PMU_EVENT_SEL           0x0600
  99 #define CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(n)             ((n) * 4)
 100 #define CCN_RNI_PMU_EVENT_SEL__ID__MASK                 0xf
 101
 102 #define CCN_TYPE_MN     0x01
 103 #define CCN_TYPE_DT     0x02
 104 #define CCN_TYPE_HNF    0x04
 105 #define CCN_TYPE_HNI    0x05
 106 #define CCN_TYPE_XP     0x08
 107 #define CCN_TYPE_SBSX   0x0c
 108 #define CCN_TYPE_SBAS   0x10
 109 #define CCN_TYPE_RNI_1P 0x14
 110 #define CCN_TYPE_RNI_2P 0x15
 111 #define CCN_TYPE_RNI_3P 0x16
 112 #define CCN_TYPE_RND_1P 0x18 /* RN-D = RN-I + DVM */
 113 #define CCN_TYPE_RND_2P 0x19
 114 #define CCN_TYPE_RND_3P 0x1a
 115 #define CCN_TYPE_CYCLES 0xff /* Pseudotype */
 116
 117 #define CCN_EVENT_WATCHPOINT 0xfe /* Pseudoevent */
 118
 119 #define CCN_NUM_PMU_EVENTS              4
 120 #define CCN_NUM_XP_WATCHPOINTS          2 /* See DT.dbg_id.num_watchpoints */
 121 #define CCN_NUM_PMU_EVENT_COUNTERS      8 /* See DT.dbg_id.num_pmucntr */
 122 #define CCN_IDX_PMU_CYCLE_COUNTER       CCN_NUM_PMU_EVENT_COUNTERS
 123
 124 #define CCN_NUM_PREDEFINED_MASKS        4
 125 #define CCN_IDX_MASK_ANY                (CCN_NUM_PMU_EVENT_COUNTERS + 0)
 126 #define CCN_IDX_MASK_EXACT              (CCN_NUM_PMU_EVENT_COUNTERS + 1)
 127 #define CCN_IDX_MASK_ORDER              (CCN_NUM_PMU_EVENT_COUNTERS + 2)
 128 #define CCN_IDX_MASK_OPCODE             (CCN_NUM_PMU_EVENT_COUNTERS + 3)
 129
 130 struct arm_ccn_component {
 131         void __iomem *base;
 132         u32 type;
 133
 134         DECLARE_BITMAP(pmu_events_mask, CCN_NUM_PMU_EVENTS);
 135         union {
 136                 struct {
 137                         DECLARE_BITMAP(dt_cmp_mask, CCN_NUM_XP_WATCHPOINTS);
 138                 } xp;
 139         };
 140 };
 141
 142 #define pmu_to_arm_ccn(_pmu) container_of(container_of(_pmu, \
 143         struct arm_ccn_dt, pmu), struct arm_ccn, dt)
 144
 145 struct arm_ccn_dt {
 146         int id;
 147         void __iomem *base;
 148
 149         spinlock_t config_lock;
 150
 151         DECLARE_BITMAP(pmu_counters_mask, CCN_NUM_PMU_EVENT_COUNTERS + 1);
 152         struct {
 153                 struct arm_ccn_component *source;
 154                 struct perf_event *event;
 155         } pmu_counters[CCN_NUM_PMU_EVENT_COUNTERS + 1];
 156
 157         struct {
 158                u64 l, h;
 159         } cmp_mask[CCN_NUM_PMU_EVENT_COUNTERS + CCN_NUM_PREDEFINED_MASKS];
 160
 161         struct hrtimer hrtimer;
 162
 163         unsigned int cpu;
 164         struct hlist_node node;
 165
 166         struct pmu pmu;
 167 };
 168
 169 struct arm_ccn {
 170         struct device *dev;
 171         void __iomem *base;
 172         unsigned int irq;
 173
 174         unsigned sbas_present:1;
 175         unsigned sbsx_present:1;
 176
 177         int num_nodes;
 178         struct arm_ccn_component *node;
 179
 180         int num_xps;
 181         struct arm_ccn_component *xp;
 182
 183         struct arm_ccn_dt dt;
 184         int mn_id;
 185 };
 186
 187 static int arm_ccn_node_to_xp(int node)
 188 {
 189         return node / CCN_NUM_XP_PORTS;
 190 }
 191
 192 static int arm_ccn_node_to_xp_port(int node)
 193 {
 194         return node % CCN_NUM_XP_PORTS;
 195 }
 196
 197
 198 /*
 199  * Bit shifts and masks in these defines must be kept in sync with
 200  * arm_ccn_pmu_config_set() and CCN_FORMAT_ATTRs below!
 201  */
 202 #define CCN_CONFIG_NODE(_config)        (((_config) >> 0) & 0xff)
 203 #define CCN_CONFIG_XP(_config)          (((_config) >> 0) & 0xff)
 204 #define CCN_CONFIG_TYPE(_config)        (((_config) >> 8) & 0xff)
 205 #define CCN_CONFIG_EVENT(_config)       (((_config) >> 16) & 0xff)
 206 #define CCN_CONFIG_PORT(_config)        (((_config) >> 24) & 0x3)
 207 #define CCN_CONFIG_BUS(_config)         (((_config) >> 24) & 0x3)
 208 #define CCN_CONFIG_VC(_config)          (((_config) >> 26) & 0x7)
 209 #define CCN_CONFIG_DIR(_config)         (((_config) >> 29) & 0x1)
 210 #define CCN_CONFIG_MASK(_config)        (((_config) >> 30) & 0xf)
 211
 212 static void arm_ccn_pmu_config_set(u64 *config, u32 node_xp, u32 type, u32 port)
 213 {
 214         *config &= ~((0xff << 0) | (0xff << 8) | (0x3 << 24));
 215         *config |= (node_xp << 0) | (type << 8) | (port << 24);
 216 }
 217
 218 #define CCN_FORMAT_ATTR(_name, _config) \
 219         struct dev_ext_attribute arm_ccn_pmu_format_attr_##_name = \
 220                         { __ATTR(_name, S_IRUGO, device_show_string, \
 221                         NULL), _config }
 222
 223 static CCN_FORMAT_ATTR(node, "config:0-7");
 224 static CCN_FORMAT_ATTR(xp, "config:0-7");
 225 static CCN_FORMAT_ATTR(type, "config:8-15");
 226 static CCN_FORMAT_ATTR(event, "config:16-23");
 227 static CCN_FORMAT_ATTR(port, "config:24-25");
 228 static CCN_FORMAT_ATTR(bus, "config:24-25");
 229 static CCN_FORMAT_ATTR(vc, "config:26-28");
 230 static CCN_FORMAT_ATTR(dir, "config:29-29");
 231 static CCN_FORMAT_ATTR(mask, "config:30-33");
 232 static CCN_FORMAT_ATTR(cmp_l, "config1:0-62");
 233 static CCN_FORMAT_ATTR(cmp_h, "config2:0-59");
 234
 235 static struct attribute *arm_ccn_pmu_format_attrs[] = {
 236         &arm_ccn_pmu_format_attr_node.attr.attr,
 237         &arm_ccn_pmu_format_attr_xp.attr.attr,
 238         &arm_ccn_pmu_format_attr_type.attr.attr,
 239         &arm_ccn_pmu_format_attr_event.attr.attr,
 240         &arm_ccn_pmu_format_attr_port.attr.attr,
 241         &arm_ccn_pmu_format_attr_bus.attr.attr,
 242         &arm_ccn_pmu_format_attr_vc.attr.attr,
 243         &arm_ccn_pmu_format_attr_dir.attr.attr,
 244         &arm_ccn_pmu_format_attr_mask.attr.attr,
 245         &arm_ccn_pmu_format_attr_cmp_l.attr.attr,
 246         &arm_ccn_pmu_format_attr_cmp_h.attr.attr,
 247         NULL
 248 };
 249
 250 static const struct attribute_group arm_ccn_pmu_format_attr_group = {
 251         .name = "format",
 252         .attrs = arm_ccn_pmu_format_attrs,
 253 };
 254
 255
 256 struct arm_ccn_pmu_event {
 257         struct device_attribute attr;
 258         u32 type;
 259         u32 event;
 260         int num_ports;
 261         int num_vcs;
 262         const char *def;
 263         int mask;
 264 };
 265
 266 #define CCN_EVENT_ATTR(_name) \
 267         __ATTR(_name, S_IRUGO, arm_ccn_pmu_event_show, NULL)
 268
 269 /*
 270  * Events defined in TRM for MN, HN-I and SBSX are actually watchpoints set on
 271  * their ports in XP they are connected to. For the sake of usability they are
 272  * explicitly defined here (and translated into a relevant watchpoint in
 273  * arm_ccn_pmu_event_init()) so the user can easily request them without deep
 274  * knowledge of the flit format.
 275  */
 276
 277 #define CCN_EVENT_MN(_name, _def, _mask) { .attr = CCN_EVENT_ATTR(mn_##_name), \
 278                 .type = CCN_TYPE_MN, .event = CCN_EVENT_WATCHPOINT, \
 279                 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, \
 280                 .def = _def, .mask = _mask, }
 281
 282 #define CCN_EVENT_HNI(_name, _def, _mask) { \
 283                 .attr = CCN_EVENT_ATTR(hni_##_name), .type = CCN_TYPE_HNI, \
 284                 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
 285                 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
 286
 287 #define CCN_EVENT_SBSX(_name, _def, _mask) { \
 288                 .attr = CCN_EVENT_ATTR(sbsx_##_name), .type = CCN_TYPE_SBSX, \
 289                 .event = CCN_EVENT_WATCHPOINT, .num_ports = CCN_NUM_XP_PORTS, \
 290                 .num_vcs = CCN_NUM_VCS, .def = _def, .mask = _mask, }
 291
 292 #define CCN_EVENT_HNF(_name, _event) { .attr = CCN_EVENT_ATTR(hnf_##_name), \
 293                 .type = CCN_TYPE_HNF, .event = _event, }
 294
 295 #define CCN_EVENT_XP(_name, _event) { .attr = CCN_EVENT_ATTR(xp_##_name), \
 296                 .type = CCN_TYPE_XP, .event = _event, \
 297                 .num_ports = CCN_NUM_XP_PORTS, .num_vcs = CCN_NUM_VCS, }
 298
 299 /*
 300  * RN-I & RN-D (RN-D = RN-I + DVM) nodes have different type ID depending
 301  * on configuration. One of them is picked to represent the whole group,
 302  * as they all share the same event types.
 303  */
 304 #define CCN_EVENT_RNI(_name, _event) { .attr = CCN_EVENT_ATTR(rni_##_name), \
 305                 .type = CCN_TYPE_RNI_3P, .event = _event, }
 306
 307 #define CCN_EVENT_SBAS(_name, _event) { .attr = CCN_EVENT_ATTR(sbas_##_name), \
 308                 .type = CCN_TYPE_SBAS, .event = _event, }
 309
 310 #define CCN_EVENT_CYCLES(_name) { .attr = CCN_EVENT_ATTR(_name), \
 311                 .type = CCN_TYPE_CYCLES }
 312
 313
 314 static ssize_t arm_ccn_pmu_event_show(struct device *dev,
 315                 struct device_attribute *attr, char *buf)
 316 {
 317         struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
 318         struct arm_ccn_pmu_event *event = container_of(attr,
 319                         struct arm_ccn_pmu_event, attr);
 320         int res;
 321
 322         res = sysfs_emit(buf, "type=0x%x", event->type);
 323         if (event->event)
 324                 res += sysfs_emit_at(buf, res, ",event=0x%x", event->event);
 325         if (event->def)
 326                 res += sysfs_emit_at(buf, res, ",%s", event->def);
 327         if (event->mask)
 328                 res += sysfs_emit_at(buf, res, ",mask=0x%x", event->mask);
 329
 330         /* Arguments required by an event */
 331         switch (event->type) {
 332         case CCN_TYPE_CYCLES:
 333                 break;
 334         case CCN_TYPE_XP:
 335                 res += sysfs_emit_at(buf, res, ",xp=?,vc=?");
 336                 if (event->event == CCN_EVENT_WATCHPOINT)
 337                         res += sysfs_emit_at(buf, res,
 338                                         ",port=?,dir=?,cmp_l=?,cmp_h=?,mask=?");
 339                 else
 340                         res += sysfs_emit_at(buf, res, ",bus=?");
 341
 342                 break;
 343         case CCN_TYPE_MN:
 344                 res += sysfs_emit_at(buf, res, ",node=%d", ccn->mn_id);
 345                 break;
 346         default:
 347                 res += sysfs_emit_at(buf, res, ",node=?");
 348                 break;
 349         }
 350
 351         res += sysfs_emit_at(buf, res, "\n");
 352
 353         return res;
 354 }
 355
 356 static umode_t arm_ccn_pmu_events_is_visible(struct kobject *kobj,
 357                                      struct attribute *attr, int index)
 358 {
 359         struct device *dev = kobj_to_dev(kobj);
 360         struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
 361         struct device_attribute *dev_attr = container_of(attr,
 362                         struct device_attribute, attr);
 363         struct arm_ccn_pmu_event *event = container_of(dev_attr,
 364                         struct arm_ccn_pmu_event, attr);
 365
 366         if (event->type == CCN_TYPE_SBAS && !ccn->sbas_present)
 367                 return 0;
 368         if (event->type == CCN_TYPE_SBSX && !ccn->sbsx_present)
 369                 return 0;
 370
 371         return attr->mode;
 372 }
 373
 374 static struct arm_ccn_pmu_event arm_ccn_pmu_events[] = {
 375         CCN_EVENT_MN(eobarrier, "dir=1,vc=0,cmp_h=0x1c00", CCN_IDX_MASK_OPCODE),
 376         CCN_EVENT_MN(ecbarrier, "dir=1,vc=0,cmp_h=0x1e00", CCN_IDX_MASK_OPCODE),
 377         CCN_EVENT_MN(dvmop, "dir=1,vc=0,cmp_h=0x2800", CCN_IDX_MASK_OPCODE),
 378         CCN_EVENT_HNI(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
 379         CCN_EVENT_HNI(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
 380         CCN_EVENT_HNI(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
 381         CCN_EVENT_HNI(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY),
 382         CCN_EVENT_HNI(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000",
 383                         CCN_IDX_MASK_ORDER),
 384         CCN_EVENT_SBSX(txdatflits, "dir=1,vc=3", CCN_IDX_MASK_ANY),
 385         CCN_EVENT_SBSX(rxdatflits, "dir=0,vc=3", CCN_IDX_MASK_ANY),
 386         CCN_EVENT_SBSX(txreqflits, "dir=1,vc=0", CCN_IDX_MASK_ANY),
 387         CCN_EVENT_SBSX(rxreqflits, "dir=0,vc=0", CCN_IDX_MASK_ANY),
 388         CCN_EVENT_SBSX(rxreqflits_order, "dir=0,vc=0,cmp_h=0x8000",
 389                         CCN_IDX_MASK_ORDER),
 390         CCN_EVENT_HNF(cache_miss, 0x1),
 391         CCN_EVENT_HNF(l3_sf_cache_access, 0x02),
 392         CCN_EVENT_HNF(cache_fill, 0x3),
 393         CCN_EVENT_HNF(pocq_retry, 0x4),
 394         CCN_EVENT_HNF(pocq_reqs_recvd, 0x5),
 395         CCN_EVENT_HNF(sf_hit, 0x6),
 396         CCN_EVENT_HNF(sf_evictions, 0x7),
 397         CCN_EVENT_HNF(snoops_sent, 0x8),
 398         CCN_EVENT_HNF(snoops_broadcast, 0x9),
 399         CCN_EVENT_HNF(l3_eviction, 0xa),
 400         CCN_EVENT_HNF(l3_fill_invalid_way, 0xb),
 401         CCN_EVENT_HNF(mc_retries, 0xc),
 402         CCN_EVENT_HNF(mc_reqs, 0xd),
 403         CCN_EVENT_HNF(qos_hh_retry, 0xe),
 404         CCN_EVENT_RNI(rdata_beats_p0, 0x1),
 405         CCN_EVENT_RNI(rdata_beats_p1, 0x2),
 406         CCN_EVENT_RNI(rdata_beats_p2, 0x3),
 407         CCN_EVENT_RNI(rxdat_flits, 0x4),
 408         CCN_EVENT_RNI(txdat_flits, 0x5),
 409         CCN_EVENT_RNI(txreq_flits, 0x6),
 410         CCN_EVENT_RNI(txreq_flits_retried, 0x7),
 411         CCN_EVENT_RNI(rrt_full, 0x8),
 412         CCN_EVENT_RNI(wrt_full, 0x9),
 413         CCN_EVENT_RNI(txreq_flits_replayed, 0xa),
 414         CCN_EVENT_XP(upload_starvation, 0x1),
 415         CCN_EVENT_XP(download_starvation, 0x2),
 416         CCN_EVENT_XP(respin, 0x3),
 417         CCN_EVENT_XP(valid_flit, 0x4),
 418         CCN_EVENT_XP(watchpoint, CCN_EVENT_WATCHPOINT),
 419         CCN_EVENT_SBAS(rdata_beats_p0, 0x1),
 420         CCN_EVENT_SBAS(rxdat_flits, 0x4),
 421         CCN_EVENT_SBAS(txdat_flits, 0x5),
 422         CCN_EVENT_SBAS(txreq_flits, 0x6),
 423         CCN_EVENT_SBAS(txreq_flits_retried, 0x7),
 424         CCN_EVENT_SBAS(rrt_full, 0x8),
 425         CCN_EVENT_SBAS(wrt_full, 0x9),
 426         CCN_EVENT_SBAS(txreq_flits_replayed, 0xa),
 427         CCN_EVENT_CYCLES(cycles),
 428 };
 429
 430 /* Populated in arm_ccn_init() */
 431 static struct attribute
 432                 *arm_ccn_pmu_events_attrs[ARRAY_SIZE(arm_ccn_pmu_events) + 1];
 433
 434 static const struct attribute_group arm_ccn_pmu_events_attr_group = {
 435         .name = "events",
 436         .is_visible = arm_ccn_pmu_events_is_visible,
 437         .attrs = arm_ccn_pmu_events_attrs,
 438 };
 439
 440
 441 static u64 *arm_ccn_pmu_get_cmp_mask(struct arm_ccn *ccn, const char *name)
 442 {
 443         unsigned long i;
 444
 445         if (WARN_ON(!name || !name[0] || !isxdigit(name[0]) || !name[1]))
 446                 return NULL;
 447         i = isdigit(name[0]) ? name[0] - '0' : 0xa + tolower(name[0]) - 'a';
 448
 449         switch (name[1]) {
 450         case 'l':
 451                 return &ccn->dt.cmp_mask[i].l;
 452         case 'h':
 453                 return &ccn->dt.cmp_mask[i].h;
 454         default:
 455                 return NULL;
 456         }
 457 }
 458
 459 static ssize_t arm_ccn_pmu_cmp_mask_show(struct device *dev,
 460                 struct device_attribute *attr, char *buf)
 461 {
 462         struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
 463         u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name);
 464
 465         return mask ? sysfs_emit(buf, "0x%016llx\n", *mask) : -EINVAL;
 466 }
 467
 468 static ssize_t arm_ccn_pmu_cmp_mask_store(struct device *dev,
 469                 struct device_attribute *attr, const char *buf, size_t count)
 470 {
 471         struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
 472         u64 *mask = arm_ccn_pmu_get_cmp_mask(ccn, attr->attr.name);
 473         int err = -EINVAL;
 474
 475         if (mask)
 476                 err = kstrtoull(buf, 0, mask);
 477
 478         return err ? err : count;
 479 }
 480
 481 #define CCN_CMP_MASK_ATTR(_name) \
 482         struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
 483                         __ATTR(_name, S_IRUGO | S_IWUSR, \
 484                         arm_ccn_pmu_cmp_mask_show, arm_ccn_pmu_cmp_mask_store)
 485
 486 #define CCN_CMP_MASK_ATTR_RO(_name) \
 487         struct device_attribute arm_ccn_pmu_cmp_mask_attr_##_name = \
 488                         __ATTR(_name, S_IRUGO, arm_ccn_pmu_cmp_mask_show, NULL)
 489
 490 static CCN_CMP_MASK_ATTR(0l);
 491 static CCN_CMP_MASK_ATTR(0h);
 492 static CCN_CMP_MASK_ATTR(1l);
 493 static CCN_CMP_MASK_ATTR(1h);
 494 static CCN_CMP_MASK_ATTR(2l);
 495 static CCN_CMP_MASK_ATTR(2h);
 496 static CCN_CMP_MASK_ATTR(3l);
 497 static CCN_CMP_MASK_ATTR(3h);
 498 static CCN_CMP_MASK_ATTR(4l);
 499 static CCN_CMP_MASK_ATTR(4h);
 500 static CCN_CMP_MASK_ATTR(5l);
 501 static CCN_CMP_MASK_ATTR(5h);
 502 static CCN_CMP_MASK_ATTR(6l);
 503 static CCN_CMP_MASK_ATTR(6h);
 504 static CCN_CMP_MASK_ATTR(7l);
 505 static CCN_CMP_MASK_ATTR(7h);
 506 static CCN_CMP_MASK_ATTR_RO(8l);
 507 static CCN_CMP_MASK_ATTR_RO(8h);
 508 static CCN_CMP_MASK_ATTR_RO(9l);
 509 static CCN_CMP_MASK_ATTR_RO(9h);
 510 static CCN_CMP_MASK_ATTR_RO(al);
 511 static CCN_CMP_MASK_ATTR_RO(ah);
 512 static CCN_CMP_MASK_ATTR_RO(bl);
 513 static CCN_CMP_MASK_ATTR_RO(bh);
 514
 515 static struct attribute *arm_ccn_pmu_cmp_mask_attrs[] = {
 516         &arm_ccn_pmu_cmp_mask_attr_0l.attr, &arm_ccn_pmu_cmp_mask_attr_0h.attr,
 517         &arm_ccn_pmu_cmp_mask_attr_1l.attr, &arm_ccn_pmu_cmp_mask_attr_1h.attr,
 518         &arm_ccn_pmu_cmp_mask_attr_2l.attr, &arm_ccn_pmu_cmp_mask_attr_2h.attr,
 519         &arm_ccn_pmu_cmp_mask_attr_3l.attr, &arm_ccn_pmu_cmp_mask_attr_3h.attr,
 520         &arm_ccn_pmu_cmp_mask_attr_4l.attr, &arm_ccn_pmu_cmp_mask_attr_4h.attr,
 521         &arm_ccn_pmu_cmp_mask_attr_5l.attr, &arm_ccn_pmu_cmp_mask_attr_5h.attr,
 522         &arm_ccn_pmu_cmp_mask_attr_6l.attr, &arm_ccn_pmu_cmp_mask_attr_6h.attr,
 523         &arm_ccn_pmu_cmp_mask_attr_7l.attr, &arm_ccn_pmu_cmp_mask_attr_7h.attr,
 524         &arm_ccn_pmu_cmp_mask_attr_8l.attr, &arm_ccn_pmu_cmp_mask_attr_8h.attr,
 525         &arm_ccn_pmu_cmp_mask_attr_9l.attr, &arm_ccn_pmu_cmp_mask_attr_9h.attr,
 526         &arm_ccn_pmu_cmp_mask_attr_al.attr, &arm_ccn_pmu_cmp_mask_attr_ah.attr,
 527         &arm_ccn_pmu_cmp_mask_attr_bl.attr, &arm_ccn_pmu_cmp_mask_attr_bh.attr,
 528         NULL
 529 };
 530
 531 static const struct attribute_group arm_ccn_pmu_cmp_mask_attr_group = {
 532         .name = "cmp_mask",
 533         .attrs = arm_ccn_pmu_cmp_mask_attrs,
 534 };
 535
 536 static ssize_t arm_ccn_pmu_cpumask_show(struct device *dev,
 537                                      struct device_attribute *attr, char *buf)
 538 {
 539         struct arm_ccn *ccn = pmu_to_arm_ccn(dev_get_drvdata(dev));
 540
 541         return cpumap_print_to_pagebuf(true, buf, cpumask_of(ccn->dt.cpu));
 542 }
 543
 544 static struct device_attribute arm_ccn_pmu_cpumask_attr =
 545                 __ATTR(cpumask, S_IRUGO, arm_ccn_pmu_cpumask_show, NULL);
 546
 547 static struct attribute *arm_ccn_pmu_cpumask_attrs[] = {
 548         &arm_ccn_pmu_cpumask_attr.attr,
 549         NULL,
 550 };
 551
 552 static const struct attribute_group arm_ccn_pmu_cpumask_attr_group = {
 553         .attrs = arm_ccn_pmu_cpumask_attrs,
 554 };
 555
 556 /*
 557  * Default poll period is 10ms, which is way over the top anyway,
 558  * as in the worst case scenario (an event every cycle), with 1GHz
 559  * clocked bus, the smallest, 32 bit counter will overflow in
 560  * more than 4s.
 561  */
 562 static unsigned int arm_ccn_pmu_poll_period_us = 10000;
 563 module_param_named(pmu_poll_period_us, arm_ccn_pmu_poll_period_us, uint,
 564                 S_IRUGO | S_IWUSR);
 565
 566 static ktime_t arm_ccn_pmu_timer_period(void)
 567 {
 568         return ns_to_ktime((u64)arm_ccn_pmu_poll_period_us * 1000);
 569 }
 570
 571
 572 static const struct attribute_group *arm_ccn_pmu_attr_groups[] = {
 573         &arm_ccn_pmu_events_attr_group,
 574         &arm_ccn_pmu_format_attr_group,
 575         &arm_ccn_pmu_cmp_mask_attr_group,
 576         &arm_ccn_pmu_cpumask_attr_group,
 577         NULL
 578 };
 579
 580
 581 static int arm_ccn_pmu_alloc_bit(unsigned long *bitmap, unsigned long size)
 582 {
 583         int bit;
 584
 585         do {
 586                 bit = find_first_zero_bit(bitmap, size);
 587                 if (bit >= size)
 588                         return -EAGAIN;
 589         } while (test_and_set_bit(bit, bitmap));
 590
 591         return bit;
 592 }
 593
 594 /* All RN-I and RN-D nodes have identical PMUs */
 595 static int arm_ccn_pmu_type_eq(u32 a, u32 b)
 596 {
 597         if (a == b)
 598                 return 1;
 599
 600         switch (a) {
 601         case CCN_TYPE_RNI_1P:
 602         case CCN_TYPE_RNI_2P:
 603         case CCN_TYPE_RNI_3P:
 604         case CCN_TYPE_RND_1P:
 605         case CCN_TYPE_RND_2P:
 606         case CCN_TYPE_RND_3P:
 607                 switch (b) {
 608                 case CCN_TYPE_RNI_1P:
 609                 case CCN_TYPE_RNI_2P:
 610                 case CCN_TYPE_RNI_3P:
 611                 case CCN_TYPE_RND_1P:
 612                 case CCN_TYPE_RND_2P:
 613                 case CCN_TYPE_RND_3P:
 614                         return 1;
 615                 }
 616                 break;
 617         }
 618
 619         return 0;
 620 }
 621
 622 static int arm_ccn_pmu_event_alloc(struct perf_event *event)
 623 {
 624         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
 625         struct hw_perf_event *hw = &event->hw;
 626         u32 node_xp, type, event_id;
 627         struct arm_ccn_component *source;
 628         int bit;
 629
 630         node_xp = CCN_CONFIG_NODE(event->attr.config);
 631         type = CCN_CONFIG_TYPE(event->attr.config);
 632         event_id = CCN_CONFIG_EVENT(event->attr.config);
 633
 634         /* Allocate the cycle counter */
 635         if (type == CCN_TYPE_CYCLES) {
 636                 if (test_and_set_bit(CCN_IDX_PMU_CYCLE_COUNTER,
 637                                 ccn->dt.pmu_counters_mask))
 638                         return -EAGAIN;
 639
 640                 hw->idx = CCN_IDX_PMU_CYCLE_COUNTER;
 641                 ccn->dt.pmu_counters[CCN_IDX_PMU_CYCLE_COUNTER].event = event;
 642
 643                 return 0;
 644         }
 645
 646         /* Allocate an event counter */
 647         hw->idx = arm_ccn_pmu_alloc_bit(ccn->dt.pmu_counters_mask,
 648                         CCN_NUM_PMU_EVENT_COUNTERS);
 649         if (hw->idx < 0) {
 650                 dev_dbg(ccn->dev, "No more counters available!\n");
 651                 return -EAGAIN;
 652         }
 653
 654         if (type == CCN_TYPE_XP)
 655                 source = &ccn->xp[node_xp];
 656         else
 657                 source = &ccn->node[node_xp];
 658         ccn->dt.pmu_counters[hw->idx].source = source;
 659
 660         /* Allocate an event source or a watchpoint */
 661         if (type == CCN_TYPE_XP && event_id == CCN_EVENT_WATCHPOINT)
 662                 bit = arm_ccn_pmu_alloc_bit(source->xp.dt_cmp_mask,
 663                                 CCN_NUM_XP_WATCHPOINTS);
 664         else
 665                 bit = arm_ccn_pmu_alloc_bit(source->pmu_events_mask,
 666                                 CCN_NUM_PMU_EVENTS);
 667         if (bit < 0) {
 668                 dev_dbg(ccn->dev, "No more event sources/watchpoints on node/XP %d!\n",
 669                                 node_xp);
 670                 clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
 671                 return -EAGAIN;
 672         }
 673         hw->config_base = bit;
 674
 675         ccn->dt.pmu_counters[hw->idx].event = event;
 676
 677         return 0;
 678 }
 679
 680 static void arm_ccn_pmu_event_release(struct perf_event *event)
 681 {
 682         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
 683         struct hw_perf_event *hw = &event->hw;
 684
 685         if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER) {
 686                 clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask);
 687         } else {
 688                 struct arm_ccn_component *source =
 689                                 ccn->dt.pmu_counters[hw->idx].source;
 690
 691                 if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP &&
 692                                 CCN_CONFIG_EVENT(event->attr.config) ==
 693                                 CCN_EVENT_WATCHPOINT)
 694                         clear_bit(hw->config_base, source->xp.dt_cmp_mask);
 695                 else
 696                         clear_bit(hw->config_base, source->pmu_events_mask);
 697                 clear_bit(hw->idx, ccn->dt.pmu_counters_mask);
 698         }
 699
 700         ccn->dt.pmu_counters[hw->idx].source = NULL;
 701         ccn->dt.pmu_counters[hw->idx].event = NULL;
 702 }
 703
 704 static int arm_ccn_pmu_event_init(struct perf_event *event)
 705 {
 706         struct arm_ccn *ccn;
 707         struct hw_perf_event *hw = &event->hw;
 708         u32 node_xp, type, event_id;
 709         int valid;
 710         int i;
 711         struct perf_event *sibling;
 712
 713         if (event->attr.type != event->pmu->type)
 714                 return -ENOENT;
 715
 716         ccn = pmu_to_arm_ccn(event->pmu);
 717
 718         if (hw->sample_period) {
 719                 dev_dbg(ccn->dev, "Sampling not supported!\n");
 720                 return -EOPNOTSUPP;
 721         }
 722
 723         if (has_branch_stack(event)) {
 724                 dev_dbg(ccn->dev, "Can't exclude execution levels!\n");
 725                 return -EINVAL;
 726         }
 727
 728         if (event->cpu < 0) {
 729                 dev_dbg(ccn->dev, "Can't provide per-task data!\n");
 730                 return -EOPNOTSUPP;
 731         }
 732         /*
 733          * Many perf core operations (eg. events rotation) operate on a
 734          * single CPU context. This is obvious for CPU PMUs, where one
 735          * expects the same sets of events being observed on all CPUs,
 736          * but can lead to issues for off-core PMUs, like CCN, where each
 737          * event could be theoretically assigned to a different CPU. To
 738          * mitigate this, we enforce CPU assignment to one, selected
 739          * processor (the one described in the "cpumask" attribute).
 740          */
 741         event->cpu = ccn->dt.cpu;
 742
 743         node_xp = CCN_CONFIG_NODE(event->attr.config);
 744         type = CCN_CONFIG_TYPE(event->attr.config);
 745         event_id = CCN_CONFIG_EVENT(event->attr.config);
 746
 747         /* Validate node/xp vs topology */
 748         switch (type) {
 749         case CCN_TYPE_MN:
 750                 if (node_xp != ccn->mn_id) {
 751                         dev_dbg(ccn->dev, "Invalid MN ID %d!\n", node_xp);
 752                         return -EINVAL;
 753                 }
 754                 break;
 755         case CCN_TYPE_XP:
 756                 if (node_xp >= ccn->num_xps) {
 757                         dev_dbg(ccn->dev, "Invalid XP ID %d!\n", node_xp);
 758                         return -EINVAL;
 759                 }
 760                 break;
 761         case CCN_TYPE_CYCLES:
 762                 break;
 763         default:
 764                 if (node_xp >= ccn->num_nodes) {
 765                         dev_dbg(ccn->dev, "Invalid node ID %d!\n", node_xp);
 766                         return -EINVAL;
 767                 }
 768                 if (!arm_ccn_pmu_type_eq(type, ccn->node[node_xp].type)) {
 769                         dev_dbg(ccn->dev, "Invalid type 0x%x for node %d!\n",
 770                                         type, node_xp);
 771                         return -EINVAL;
 772                 }
 773                 break;
 774         }
 775
 776         /* Validate event ID vs available for the type */
 777         for (i = 0, valid = 0; i < ARRAY_SIZE(arm_ccn_pmu_events) && !valid;
 778                         i++) {
 779                 struct arm_ccn_pmu_event *e = &arm_ccn_pmu_events[i];
 780                 u32 port = CCN_CONFIG_PORT(event->attr.config);
 781                 u32 vc = CCN_CONFIG_VC(event->attr.config);
 782
 783                 if (!arm_ccn_pmu_type_eq(type, e->type))
 784                         continue;
 785                 if (event_id != e->event)
 786                         continue;
 787                 if (e->num_ports && port >= e->num_ports) {
 788                         dev_dbg(ccn->dev, "Invalid port %d for node/XP %d!\n",
 789                                         port, node_xp);
 790                         return -EINVAL;
 791                 }
 792                 if (e->num_vcs && vc >= e->num_vcs) {
 793                         dev_dbg(ccn->dev, "Invalid vc %d for node/XP %d!\n",
 794                                         vc, node_xp);
 795                         return -EINVAL;
 796                 }
 797                 valid = 1;
 798         }
 799         if (!valid) {
 800                 dev_dbg(ccn->dev, "Invalid event 0x%x for node/XP %d!\n",
 801                                 event_id, node_xp);
 802                 return -EINVAL;
 803         }
 804
 805         /* Watchpoint-based event for a node is actually set on XP */
 806         if (event_id == CCN_EVENT_WATCHPOINT && type != CCN_TYPE_XP) {
 807                 u32 port;
 808
 809                 type = CCN_TYPE_XP;
 810                 port = arm_ccn_node_to_xp_port(node_xp);
 811                 node_xp = arm_ccn_node_to_xp(node_xp);
 812
 813                 arm_ccn_pmu_config_set(&event->attr.config,
 814                                 node_xp, type, port);
 815         }
 816
 817         /*
 818          * We must NOT create groups containing mixed PMUs, although software
 819          * events are acceptable (for example to create a CCN group
 820          * periodically read when a hrtimer aka cpu-clock leader triggers).
 821          */
 822         if (event->group_leader->pmu != event->pmu &&
 823                         !is_software_event(event->group_leader))
 824                 return -EINVAL;
 825
 826         for_each_sibling_event(sibling, event->group_leader) {
 827                 if (sibling->pmu != event->pmu &&
 828                                 !is_software_event(sibling))
 829                         return -EINVAL;
 830         }
 831
 832         return 0;
 833 }
 834
 835 static u64 arm_ccn_pmu_read_counter(struct arm_ccn *ccn, int idx)
 836 {
 837         u64 res;
 838
 839         if (idx == CCN_IDX_PMU_CYCLE_COUNTER) {
 840 #ifdef readq
 841                 res = readq(ccn->dt.base + CCN_DT_PMCCNTR);
 842 #else
 843                 /* 40 bit counter, can do snapshot and read in two parts */
 844                 writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ);
 845                 while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1))
 846                         ;
 847                 writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
 848                 res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff;
 849                 res <<= 32;
 850                 res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR);
 851 #endif
 852         } else {
 853                 res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx));
 854         }
 855
 856         return res;
 857 }
 858
 859 static void arm_ccn_pmu_event_update(struct perf_event *event)
 860 {
 861         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
 862         struct hw_perf_event *hw = &event->hw;
 863         u64 prev_count, new_count, mask;
 864
 865         do {
 866                 prev_count = local64_read(&hw->prev_count);
 867                 new_count = arm_ccn_pmu_read_counter(ccn, hw->idx);
 868         } while (local64_xchg(&hw->prev_count, new_count) != prev_count);
 869
 870         mask = (1LLU << (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER ? 40 : 32)) - 1;
 871
 872         local64_add((new_count - prev_count) & mask, &event->count);
 873 }
 874
 875 static void arm_ccn_pmu_xp_dt_config(struct perf_event *event, int enable)
 876 {
 877         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
 878         struct hw_perf_event *hw = &event->hw;
 879         struct arm_ccn_component *xp;
 880         u32 val, dt_cfg;
 881
 882         /* Nothing to do for cycle counter */
 883         if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER)
 884                 return;
 885
 886         if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
 887                 xp = &ccn->xp[CCN_CONFIG_XP(event->attr.config)];
 888         else
 889                 xp = &ccn->xp[arm_ccn_node_to_xp(
 890                                 CCN_CONFIG_NODE(event->attr.config))];
 891
 892         if (enable)
 893                 dt_cfg = hw->event_base;
 894         else
 895                 dt_cfg = CCN_XP_DT_CONFIG__DT_CFG__PASS_THROUGH;
 896
 897         spin_lock(&ccn->dt.config_lock);
 898
 899         val = readl(xp->base + CCN_XP_DT_CONFIG);
 900         val &= ~(CCN_XP_DT_CONFIG__DT_CFG__MASK <<
 901                         CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx));
 902         val |= dt_cfg << CCN_XP_DT_CONFIG__DT_CFG__SHIFT(hw->idx);
 903         writel(val, xp->base + CCN_XP_DT_CONFIG);
 904
 905         spin_unlock(&ccn->dt.config_lock);
 906 }
 907
 908 static void arm_ccn_pmu_event_start(struct perf_event *event, int flags)
 909 {
 910         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
 911         struct hw_perf_event *hw = &event->hw;
 912
 913         local64_set(&event->hw.prev_count,
 914                         arm_ccn_pmu_read_counter(ccn, hw->idx));
 915         hw->state = 0;
 916
 917         /* Set the DT bus input, engaging the counter */
 918         arm_ccn_pmu_xp_dt_config(event, 1);
 919 }
 920
 921 static void arm_ccn_pmu_event_stop(struct perf_event *event, int flags)
 922 {
 923         struct hw_perf_event *hw = &event->hw;
 924
 925         /* Disable counting, setting the DT bus to pass-through mode */
 926         arm_ccn_pmu_xp_dt_config(event, 0);
 927
 928         if (flags & PERF_EF_UPDATE)
 929                 arm_ccn_pmu_event_update(event);
 930
 931         hw->state |= PERF_HES_STOPPED;
 932 }
 933
 934 static void arm_ccn_pmu_xp_watchpoint_config(struct perf_event *event)
 935 {
 936         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
 937         struct hw_perf_event *hw = &event->hw;
 938         struct arm_ccn_component *source =
 939                         ccn->dt.pmu_counters[hw->idx].source;
 940         unsigned long wp = hw->config_base;
 941         u32 val;
 942         u64 cmp_l = event->attr.config1;
 943         u64 cmp_h = event->attr.config2;
 944         u64 mask_l = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].l;
 945         u64 mask_h = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].h;
 946
 947         hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__WATCHPOINT(wp);
 948
 949         /* Direction (RX/TX), device (port) & virtual channel */
 950         val = readl(source->base + CCN_XP_DT_INTERFACE_SEL);
 951         val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__MASK <<
 952                         CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp));
 953         val |= CCN_CONFIG_DIR(event->attr.config) <<
 954                         CCN_XP_DT_INTERFACE_SEL__DT_IO_SEL__SHIFT(wp);
 955         val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__MASK <<
 956                         CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp));
 957         val |= CCN_CONFIG_PORT(event->attr.config) <<
 958                         CCN_XP_DT_INTERFACE_SEL__DT_DEV_SEL__SHIFT(wp);
 959         val &= ~(CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__MASK <<
 960                         CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp));
 961         val |= CCN_CONFIG_VC(event->attr.config) <<
 962                         CCN_XP_DT_INTERFACE_SEL__DT_VC_SEL__SHIFT(wp);
 963         writel(val, source->base + CCN_XP_DT_INTERFACE_SEL);
 964
 965         /* Comparison values */
 966         writel(cmp_l & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_L(wp));
 967         writel((cmp_l >> 32) & 0x7fffffff,
 968                         source->base + CCN_XP_DT_CMP_VAL_L(wp) + 4);
 969         writel(cmp_h & 0xffffffff, source->base + CCN_XP_DT_CMP_VAL_H(wp));
 970         writel((cmp_h >> 32) & 0x0fffffff,
 971                         source->base + CCN_XP_DT_CMP_VAL_H(wp) + 4);
 972
 973         /* Mask */
 974         writel(mask_l & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_L(wp));
 975         writel((mask_l >> 32) & 0x7fffffff,
 976                         source->base + CCN_XP_DT_CMP_MASK_L(wp) + 4);
 977         writel(mask_h & 0xffffffff, source->base + CCN_XP_DT_CMP_MASK_H(wp));
 978         writel((mask_h >> 32) & 0x0fffffff,
 979                         source->base + CCN_XP_DT_CMP_MASK_H(wp) + 4);
 980 }
 981
 982 static void arm_ccn_pmu_xp_event_config(struct perf_event *event)
 983 {
 984         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
 985         struct hw_perf_event *hw = &event->hw;
 986         struct arm_ccn_component *source =
 987                         ccn->dt.pmu_counters[hw->idx].source;
 988         u32 val, id;
 989
 990         hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__XP_PMU_EVENT(hw->config_base);
 991
 992         id = (CCN_CONFIG_VC(event->attr.config) << 4) |
 993                         (CCN_CONFIG_BUS(event->attr.config) << 3) |
 994                         (CCN_CONFIG_EVENT(event->attr.config) << 0);
 995
 996         val = readl(source->base + CCN_XP_PMU_EVENT_SEL);
 997         val &= ~(CCN_XP_PMU_EVENT_SEL__ID__MASK <<
 998                         CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
 999         val |= id << CCN_XP_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
1000         writel(val, source->base + CCN_XP_PMU_EVENT_SEL);
1001 }
1002
1003 static void arm_ccn_pmu_node_event_config(struct perf_event *event)
1004 {
1005         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1006         struct hw_perf_event *hw = &event->hw;
1007         struct arm_ccn_component *source =
1008                         ccn->dt.pmu_counters[hw->idx].source;
1009         u32 type = CCN_CONFIG_TYPE(event->attr.config);
1010         u32 val, port;
1011
1012         port = arm_ccn_node_to_xp_port(CCN_CONFIG_NODE(event->attr.config));
1013         hw->event_base = CCN_XP_DT_CONFIG__DT_CFG__DEVICE_PMU_EVENT(port,
1014                         hw->config_base);
1015
1016         /* These *_event_sel regs should be identical, but let's make sure... */
1017         BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL != CCN_SBAS_PMU_EVENT_SEL);
1018         BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL != CCN_RNI_PMU_EVENT_SEL);
1019         BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(1) !=
1020                         CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1));
1021         BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__SHIFT(1) !=
1022                         CCN_RNI_PMU_EVENT_SEL__ID__SHIFT(1));
1023         BUILD_BUG_ON(CCN_HNF_PMU_EVENT_SEL__ID__MASK !=
1024                         CCN_SBAS_PMU_EVENT_SEL__ID__MASK);
1025         BUILD_BUG_ON(CCN_SBAS_PMU_EVENT_SEL__ID__MASK !=
1026                         CCN_RNI_PMU_EVENT_SEL__ID__MASK);
1027         if (WARN_ON(type != CCN_TYPE_HNF && type != CCN_TYPE_SBAS &&
1028                         !arm_ccn_pmu_type_eq(type, CCN_TYPE_RNI_3P)))
1029                 return;
1030
1031         /* Set the event id for the pre-allocated counter */
1032         val = readl(source->base + CCN_HNF_PMU_EVENT_SEL);
1033         val &= ~(CCN_HNF_PMU_EVENT_SEL__ID__MASK <<
1034                 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base));
1035         val |= CCN_CONFIG_EVENT(event->attr.config) <<
1036                 CCN_HNF_PMU_EVENT_SEL__ID__SHIFT(hw->config_base);
1037         writel(val, source->base + CCN_HNF_PMU_EVENT_SEL);
1038 }
1039
1040 static void arm_ccn_pmu_event_config(struct perf_event *event)
1041 {
1042         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1043         struct hw_perf_event *hw = &event->hw;
1044         u32 xp, offset, val;
1045
1046         /* Cycle counter requires no setup */
1047         if (hw->idx == CCN_IDX_PMU_CYCLE_COUNTER)
1048                 return;
1049
1050         if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP)
1051                 xp = CCN_CONFIG_XP(event->attr.config);
1052         else
1053                 xp = arm_ccn_node_to_xp(CCN_CONFIG_NODE(event->attr.config));
1054
1055         spin_lock(&ccn->dt.config_lock);
1056
1057         /* Set the DT bus "distance" register */
1058         offset = (hw->idx / 4) * 4;
1059         val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1060         val &= ~(CCN_DT_ACTIVE_DSM__DSM_ID__MASK <<
1061                         CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4));
1062         val |= xp << CCN_DT_ACTIVE_DSM__DSM_ID__SHIFT(hw->idx % 4);
1063         writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);
1064
1065         if (CCN_CONFIG_TYPE(event->attr.config) == CCN_TYPE_XP) {
1066                 if (CCN_CONFIG_EVENT(event->attr.config) ==
1067                                 CCN_EVENT_WATCHPOINT)
1068                         arm_ccn_pmu_xp_watchpoint_config(event);
1069                 else
1070                         arm_ccn_pmu_xp_event_config(event);
1071         } else {
1072                 arm_ccn_pmu_node_event_config(event);
1073         }
1074
1075         spin_unlock(&ccn->dt.config_lock);
1076 }
1077
1078 static int arm_ccn_pmu_active_counters(struct arm_ccn *ccn)
1079 {
1080         return bitmap_weight(ccn->dt.pmu_counters_mask,
1081                              CCN_NUM_PMU_EVENT_COUNTERS + 1);
1082 }
1083
1084 static int arm_ccn_pmu_event_add(struct perf_event *event, int flags)
1085 {
1086         int err;
1087         struct hw_perf_event *hw = &event->hw;
1088         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1089
1090         err = arm_ccn_pmu_event_alloc(event);
1091         if (err)
1092                 return err;
1093
1094         /*
1095          * Pin the timer, so that the overflows are handled by the chosen
1096          * event->cpu (this is the same one as presented in "cpumask"
1097          * attribute).
1098          */
1099         if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 1)
1100                 hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(),
1101                               HRTIMER_MODE_REL_PINNED);
1102
1103         arm_ccn_pmu_event_config(event);
1104
1105         hw->state = PERF_HES_STOPPED;
1106
1107         if (flags & PERF_EF_START)
1108                 arm_ccn_pmu_event_start(event, PERF_EF_UPDATE);
1109
1110         return 0;
1111 }
1112
1113 static void arm_ccn_pmu_event_del(struct perf_event *event, int flags)
1114 {
1115         struct arm_ccn *ccn = pmu_to_arm_ccn(event->pmu);
1116
1117         arm_ccn_pmu_event_stop(event, PERF_EF_UPDATE);
1118
1119         arm_ccn_pmu_event_release(event);
1120
1121         if (!ccn->irq && arm_ccn_pmu_active_counters(ccn) == 0)
1122                 hrtimer_cancel(&ccn->dt.hrtimer);
1123 }
1124
1125 static void arm_ccn_pmu_event_read(struct perf_event *event)
1126 {
1127         arm_ccn_pmu_event_update(event);
1128 }
1129
1130 static void arm_ccn_pmu_enable(struct pmu *pmu)
1131 {
1132         struct arm_ccn *ccn = pmu_to_arm_ccn(pmu);
1133
1134         u32 val = readl(ccn->dt.base + CCN_DT_PMCR);
1135         val |= CCN_DT_PMCR__PMU_EN;
1136         writel(val, ccn->dt.base + CCN_DT_PMCR);
1137 }
1138
1139 static void arm_ccn_pmu_disable(struct pmu *pmu)
1140 {
1141         struct arm_ccn *ccn = pmu_to_arm_ccn(pmu);
1142
1143         u32 val = readl(ccn->dt.base + CCN_DT_PMCR);
1144         val &= ~CCN_DT_PMCR__PMU_EN;
1145         writel(val, ccn->dt.base + CCN_DT_PMCR);
1146 }
1147
1148 static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt)
1149 {
1150         u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR);
1151         int idx;
1152
1153         if (!pmovsr)
1154                 return IRQ_NONE;
1155
1156         writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR);
1157
1158         BUILD_BUG_ON(CCN_IDX_PMU_CYCLE_COUNTER != CCN_NUM_PMU_EVENT_COUNTERS);
1159
1160         for (idx = 0; idx < CCN_NUM_PMU_EVENT_COUNTERS + 1; idx++) {
1161                 struct perf_event *event = dt->pmu_counters[idx].event;
1162                 int overflowed = pmovsr & BIT(idx);
1163
1164                 WARN_ON_ONCE(overflowed && !event &&
1165                                 idx != CCN_IDX_PMU_CYCLE_COUNTER);
1166
1167                 if (!event || !overflowed)
1168                         continue;
1169
1170                 arm_ccn_pmu_event_update(event);
1171         }
1172
1173         return IRQ_HANDLED;
1174 }
1175
1176 static enum hrtimer_restart arm_ccn_pmu_timer_handler(struct hrtimer *hrtimer)
1177 {
1178         struct arm_ccn_dt *dt = container_of(hrtimer, struct arm_ccn_dt,
1179                         hrtimer);
1180         unsigned long flags;
1181
1182         local_irq_save(flags);
1183         arm_ccn_pmu_overflow_handler(dt);
1184         local_irq_restore(flags);
1185
1186         hrtimer_forward_now(hrtimer, arm_ccn_pmu_timer_period());
1187         return HRTIMER_RESTART;
1188 }
1189
1190
1191 static int arm_ccn_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
1192 {
1193         struct arm_ccn_dt *dt = hlist_entry_safe(node, struct arm_ccn_dt, node);
1194         struct arm_ccn *ccn = container_of(dt, struct arm_ccn, dt);
1195         unsigned int target;
1196
1197         if (cpu != dt->cpu)
1198                 return 0;
1199         target = cpumask_any_but(cpu_online_mask, cpu);
1200         if (target >= nr_cpu_ids)
1201                 return 0;
1202         perf_pmu_migrate_context(&dt->pmu, cpu, target);
1203         dt->cpu = target;
1204         if (ccn->irq)
1205                 WARN_ON(irq_set_affinity(ccn->irq, cpumask_of(dt->cpu)));
1206         return 0;
1207 }
1208
1209 static DEFINE_IDA(arm_ccn_pmu_ida);
1210
1211 static int arm_ccn_pmu_init(struct arm_ccn *ccn)
1212 {
1213         int i;
1214         char *name;
1215         int err;
1216
1217         /* Initialize DT subsystem */
1218         ccn->dt.base = ccn->base + CCN_REGION_SIZE;
1219         spin_lock_init(&ccn->dt.config_lock);
1220         writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR);
1221         writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL);
1222         writel(CCN_DT_PMCR__OVFL_INTR_EN | CCN_DT_PMCR__PMU_EN,
1223                         ccn->dt.base + CCN_DT_PMCR);
1224         writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);
1225         for (i = 0; i < ccn->num_xps; i++) {
1226                 writel(0, ccn->xp[i].base + CCN_XP_DT_CONFIG);
1227                 writel((CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS <<
1228                                 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(0)) |
1229                                 (CCN_XP_DT_CONTROL__WP_ARM_SEL__ALWAYS <<
1230                                 CCN_XP_DT_CONTROL__WP_ARM_SEL__SHIFT(1)) |
1231                                 CCN_XP_DT_CONTROL__DT_ENABLE,
1232                                 ccn->xp[i].base + CCN_XP_DT_CONTROL);
1233         }
1234         ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].l = ~0;
1235         ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].h = ~0;
1236         ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].l = 0;
1237         ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].h = 0;
1238         ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].l = ~0;
1239         ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].h = ~(0x1 << 15);
1240         ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].l = ~0;
1241         ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].h = ~(0x1f << 9);
1242
1243         /* Get a convenient /sys/event_source/devices/ name */
1244         ccn->dt.id = ida_alloc(&arm_ccn_pmu_ida, GFP_KERNEL);
1245         if (ccn->dt.id == 0) {
1246                 name = "ccn";
1247         } else {
1248                 name = devm_kasprintf(ccn->dev, GFP_KERNEL, "ccn_%d",
1249                                       ccn->dt.id);
1250                 if (!name) {
1251                         err = -ENOMEM;
1252                         goto error_choose_name;
1253                 }
1254         }
1255
1256         /* Perf driver registration */
1257         ccn->dt.pmu = (struct pmu) {
1258                 .module = THIS_MODULE,
1259                 .parent = ccn->dev,
1260                 .attr_groups = arm_ccn_pmu_attr_groups,
1261                 .task_ctx_nr = perf_invalid_context,
1262                 .event_init = arm_ccn_pmu_event_init,
1263                 .add = arm_ccn_pmu_event_add,
1264                 .del = arm_ccn_pmu_event_del,
1265                 .start = arm_ccn_pmu_event_start,
1266                 .stop = arm_ccn_pmu_event_stop,
1267                 .read = arm_ccn_pmu_event_read,
1268                 .pmu_enable = arm_ccn_pmu_enable,
1269                 .pmu_disable = arm_ccn_pmu_disable,
1270                 .capabilities = PERF_PMU_CAP_NO_EXCLUDE,
1271         };
1272
1273         /* No overflow interrupt? Have to use a timer instead. */
1274         if (!ccn->irq) {
1275                 dev_info(ccn->dev, "No access to interrupts, using timer.\n");
1276                 hrtimer_init(&ccn->dt.hrtimer, CLOCK_MONOTONIC,
1277                                 HRTIMER_MODE_REL);
1278                 ccn->dt.hrtimer.function = arm_ccn_pmu_timer_handler;
1279         }
1280
1281         /* Pick one CPU which we will use to collect data from CCN... */
1282         ccn->dt.cpu = raw_smp_processor_id();
1283
1284         /* Also make sure that the overflow interrupt is handled by this CPU */
1285         if (ccn->irq) {
1286                 err = irq_set_affinity(ccn->irq, cpumask_of(ccn->dt.cpu));
1287                 if (err) {
1288                         dev_err(ccn->dev, "Failed to set interrupt affinity!\n");
1289                         goto error_set_affinity;
1290                 }
1291         }
1292
1293         cpuhp_state_add_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE,
1294                                          &ccn->dt.node);
1295
1296         err = perf_pmu_register(&ccn->dt.pmu, name, -1);
1297         if (err)
1298                 goto error_pmu_register;
1299
1300         return 0;
1301
1302 error_pmu_register:
1303         cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE,
1304                                             &ccn->dt.node);
1305 error_set_affinity:
1306 error_choose_name:
1307         ida_free(&arm_ccn_pmu_ida, ccn->dt.id);
1308         for (i = 0; i < ccn->num_xps; i++)
1309                 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
1310         writel(0, ccn->dt.base + CCN_DT_PMCR);
1311         return err;
1312 }
1313
1314 static void arm_ccn_pmu_cleanup(struct arm_ccn *ccn)
1315 {
1316         int i;
1317
1318         cpuhp_state_remove_instance_nocalls(CPUHP_AP_PERF_ARM_CCN_ONLINE,
1319                                             &ccn->dt.node);
1320         for (i = 0; i < ccn->num_xps; i++)
1321                 writel(0, ccn->xp[i].base + CCN_XP_DT_CONTROL);
1322         writel(0, ccn->dt.base + CCN_DT_PMCR);
1323         perf_pmu_unregister(&ccn->dt.pmu);
1324         ida_free(&arm_ccn_pmu_ida, ccn->dt.id);
1325 }
1326
1327 static int arm_ccn_for_each_valid_region(struct arm_ccn *ccn,
1328                 int (*callback)(struct arm_ccn *ccn, int region,
1329                 void __iomem *base, u32 type, u32 id))
1330 {
1331         int region;
1332
1333         for (region = 0; region < CCN_NUM_REGIONS; region++) {
1334                 u32 val, type, id;
1335                 void __iomem *base;
1336                 int err;
1337
1338                 val = readl(ccn->base + CCN_MN_OLY_COMP_LIST_63_0 +
1339                                 4 * (region / 32));
1340                 if (!(val & (1 << (region % 32))))
1341                         continue;
1342
1343                 base = ccn->base + region * CCN_REGION_SIZE;
1344                 val = readl(base + CCN_ALL_OLY_ID);
1345                 type = (val >> CCN_ALL_OLY_ID__OLY_ID__SHIFT) &
1346                                 CCN_ALL_OLY_ID__OLY_ID__MASK;
1347                 id = (val >> CCN_ALL_OLY_ID__NODE_ID__SHIFT) &
1348                                 CCN_ALL_OLY_ID__NODE_ID__MASK;
1349
1350                 err = callback(ccn, region, base, type, id);
1351                 if (err)
1352                         return err;
1353         }
1354
1355         return 0;
1356 }
1357
1358 static int arm_ccn_get_nodes_num(struct arm_ccn *ccn, int region,
1359                 void __iomem *base, u32 type, u32 id)
1360 {
1361
1362         if (type == CCN_TYPE_XP && id >= ccn->num_xps)
1363                 ccn->num_xps = id + 1;
1364         else if (id >= ccn->num_nodes)
1365                 ccn->num_nodes = id + 1;
1366
1367         return 0;
1368 }
1369
1370 static int arm_ccn_init_nodes(struct arm_ccn *ccn, int region,
1371                 void __iomem *base, u32 type, u32 id)
1372 {
1373         struct arm_ccn_component *component;
1374
1375         dev_dbg(ccn->dev, "Region %d: id=%u, type=0x%02x\n", region, id, type);
1376
1377         switch (type) {
1378         case CCN_TYPE_MN:
1379                 ccn->mn_id = id;
1380                 return 0;
1381         case CCN_TYPE_DT:
1382                 return 0;
1383         case CCN_TYPE_XP:
1384                 component = &ccn->xp[id];
1385                 break;
1386         case CCN_TYPE_SBSX:
1387                 ccn->sbsx_present = 1;
1388                 component = &ccn->node[id];
1389                 break;
1390         case CCN_TYPE_SBAS:
1391                 ccn->sbas_present = 1;
1392                 fallthrough;
1393         default:
1394                 component = &ccn->node[id];
1395                 break;
1396         }
1397
1398         component->base = base;
1399         component->type = type;
1400
1401         return 0;
1402 }
1403
1404
1405 static irqreturn_t arm_ccn_error_handler(struct arm_ccn *ccn,
1406                 const u32 *err_sig_val)
1407 {
1408         /* This should be really handled by firmware... */
1409         dev_err(ccn->dev, "Error reported in %08x%08x%08x%08x%08x%08x.\n",
1410                         err_sig_val[5], err_sig_val[4], err_sig_val[3],
1411                         err_sig_val[2], err_sig_val[1], err_sig_val[0]);
1412         dev_err(ccn->dev, "Disabling interrupt generation for all errors.\n");
1413         writel(CCN_MN_ERRINT_STATUS__ALL_ERRORS__DISABLE,
1414                         ccn->base + CCN_MN_ERRINT_STATUS);
1415
1416         return IRQ_HANDLED;
1417 }
1418
1419
1420 static irqreturn_t arm_ccn_irq_handler(int irq, void *dev_id)
1421 {
1422         irqreturn_t res = IRQ_NONE;
1423         struct arm_ccn *ccn = dev_id;
1424         u32 err_sig_val[6];
1425         u32 err_or;
1426         int i;
1427
1428         /* PMU overflow is a special case */
1429         err_or = err_sig_val[0] = readl(ccn->base + CCN_MN_ERR_SIG_VAL_63_0);
1430         if (err_or & CCN_MN_ERR_SIG_VAL_63_0__DT) {
1431                 err_or &= ~CCN_MN_ERR_SIG_VAL_63_0__DT;
1432                 res = arm_ccn_pmu_overflow_handler(&ccn->dt);
1433         }
1434
1435         /* Have to read all err_sig_vals to clear them */
1436         for (i = 1; i < ARRAY_SIZE(err_sig_val); i++) {
1437                 err_sig_val[i] = readl(ccn->base +
1438                                 CCN_MN_ERR_SIG_VAL_63_0 + i * 4);
1439                 err_or |= err_sig_val[i];
1440         }
1441         if (err_or)
1442                 res |= arm_ccn_error_handler(ccn, err_sig_val);
1443
1444         if (res != IRQ_NONE)
1445                 writel(CCN_MN_ERRINT_STATUS__INTREQ__DESSERT,
1446                                 ccn->base + CCN_MN_ERRINT_STATUS);
1447
1448         return res;
1449 }
1450
1451
1452 static int arm_ccn_probe(struct platform_device *pdev)
1453 {
1454         struct arm_ccn *ccn;
1455         int irq;
1456         int err;
1457
1458         ccn = devm_kzalloc(&pdev->dev, sizeof(*ccn), GFP_KERNEL);
1459         if (!ccn)
1460                 return -ENOMEM;
1461         ccn->dev = &pdev->dev;
1462         platform_set_drvdata(pdev, ccn);
1463
1464         ccn->base = devm_platform_ioremap_resource(pdev, 0);
1465         if (IS_ERR(ccn->base))
1466                 return PTR_ERR(ccn->base);
1467
1468         irq = platform_get_irq(pdev, 0);
1469         if (irq < 0)
1470                 return irq;
1471
1472         /* Check if we can use the interrupt */
1473         writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLE,
1474                         ccn->base + CCN_MN_ERRINT_STATUS);
1475         if (readl(ccn->base + CCN_MN_ERRINT_STATUS) &
1476                         CCN_MN_ERRINT_STATUS__PMU_EVENTS__DISABLED) {
1477                 /* Can set 'disable' bits, so can acknowledge interrupts */
1478                 writel(CCN_MN_ERRINT_STATUS__PMU_EVENTS__ENABLE,
1479                                 ccn->base + CCN_MN_ERRINT_STATUS);
1480                 err = devm_request_irq(ccn->dev, irq, arm_ccn_irq_handler,
1481                                        IRQF_NOBALANCING | IRQF_NO_THREAD,
1482                                        dev_name(ccn->dev), ccn);
1483                 if (err)
1484                         return err;
1485
1486                 ccn->irq = irq;
1487         }
1488
1489
1490         /* Build topology */
1491
1492         err = arm_ccn_for_each_valid_region(ccn, arm_ccn_get_nodes_num);
1493         if (err)
1494                 return err;
1495
1496         ccn->node = devm_kcalloc(ccn->dev, ccn->num_nodes, sizeof(*ccn->node),
1497                                  GFP_KERNEL);
1498         ccn->xp = devm_kcalloc(ccn->dev, ccn->num_xps, sizeof(*ccn->node),
1499                                GFP_KERNEL);
1500         if (!ccn->node || !ccn->xp)
1501                 return -ENOMEM;
1502
1503         err = arm_ccn_for_each_valid_region(ccn, arm_ccn_init_nodes);
1504         if (err)
1505                 return err;
1506
1507         return arm_ccn_pmu_init(ccn);
1508 }
1509
1510 static void arm_ccn_remove(struct platform_device *pdev)
1511 {
1512         struct arm_ccn *ccn = platform_get_drvdata(pdev);
1513
1514         arm_ccn_pmu_cleanup(ccn);
1515 }
1516
1517 static const struct of_device_id arm_ccn_match[] = {
1518         { .compatible = "arm,ccn-502", },
1519         { .compatible = "arm,ccn-504", },
1520         { .compatible = "arm,ccn-512", },
1521         {},
1522 };
1523 MODULE_DEVICE_TABLE(of, arm_ccn_match);
1524
1525 static struct platform_driver arm_ccn_driver = {
1526         .driver = {
1527                 .name = "arm-ccn",
1528                 .of_match_table = arm_ccn_match,
1529                 .suppress_bind_attrs = true,
1530         },
1531         .probe = arm_ccn_probe,
1532         .remove_new = arm_ccn_remove,
1533 };
1534
1535 static int __init arm_ccn_init(void)
1536 {
1537         int i, ret;
1538
1539         ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_ARM_CCN_ONLINE,
1540                                       "perf/arm/ccn:online", NULL,
1541                                       arm_ccn_pmu_offline_cpu);
1542         if (ret)
1543                 return ret;
1544
1545         for (i = 0; i < ARRAY_SIZE(arm_ccn_pmu_events); i++)
1546                 arm_ccn_pmu_events_attrs[i] = &arm_ccn_pmu_events[i].attr.attr;
1547
1548         ret = platform_driver_register(&arm_ccn_driver);
1549         if (ret)
1550                 cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CCN_ONLINE);
1551         return ret;
1552 }
1553
1554 static void __exit arm_ccn_exit(void)
1555 {
1556         platform_driver_unregister(&arm_ccn_driver);
1557         cpuhp_remove_multi_state(CPUHP_AP_PERF_ARM_CCN_ONLINE);
1558 }
1559
1560 module_init(arm_ccn_init);
1561 module_exit(arm_ccn_exit);
1562
1563 MODULE_AUTHOR("Pawel Moll <[email protected]>");
1564 MODULE_LICENSE("GPL v2");