1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2019, Intel Corporation. */
7 struct ice_orom_civd_info {
8 u8 signature[4]; /* Must match ASCII '$CIV' characters */
9 u8 checksum; /* Simple modulo 256 sum of all structure bytes must equal 0 */
10 __le32 combo_ver; /* Combo Image Version number */
11 u8 combo_name_len; /* Length of the unicode combo image version string, max of 32 */
12 __le16 combo_name[32]; /* Unicode string representing the Combo Image version */
16 ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access);
17 void ice_release_nvm(struct ice_hw *hw);
19 ice_read_flat_nvm(struct ice_hw *hw, u32 offset, u32 *length, u8 *data,
20 bool read_shadow_ram);
22 ice_get_pfa_module_tlv(struct ice_hw *hw, u16 *module_tlv, u16 *module_tlv_len,
25 ice_get_inactive_orom_ver(struct ice_hw *hw, struct ice_orom_info *orom);
27 ice_get_inactive_nvm_ver(struct ice_hw *hw, struct ice_nvm_info *nvm);
29 ice_get_inactive_netlist_ver(struct ice_hw *hw, struct ice_netlist_info *netlist);
31 ice_read_pba_string(struct ice_hw *hw, u8 *pba_num, u32 pba_num_size);
32 enum ice_status ice_init_nvm(struct ice_hw *hw);
33 enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data);
35 ice_aq_update_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset,
36 u16 length, void *data, bool last_command, u8 command_flags,
37 struct ice_sq_cd *cd);
39 ice_aq_erase_nvm(struct ice_hw *hw, u16 module_typeid, struct ice_sq_cd *cd);
40 enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw);
41 enum ice_status ice_nvm_write_activate(struct ice_hw *hw, u8 cmd_flags);
42 enum ice_status ice_aq_nvm_update_empr(struct ice_hw *hw);
44 ice_nvm_set_pkg_data(struct ice_hw *hw, bool del_pkg_data_flag, u8 *data,
45 u16 length, struct ice_sq_cd *cd);
47 ice_nvm_pass_component_tbl(struct ice_hw *hw, u8 *data, u16 length,
48 u8 transfer_flag, u8 *comp_response,
49 u8 *comp_response_code, struct ice_sq_cd *cd);
50 #endif /* _ICE_NVM_H_ */