drivers/iommu/intel/debugfs.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright © 2018 Intel Corporation.
   4  *
   5  * Authors: Gayatri Kammela <[email protected]>
   6  *          Sohil Mehta <[email protected]>
   7  *          Jacob Pan <[email protected]>
   8  *          Lu Baolu <[email protected]>
   9  */
  10
  11 #include <linux/debugfs.h>
  12 #include <linux/dmar.h>
  13 #include <linux/pci.h>
  14
  15 #include <asm/irq_remapping.h>
  16
  17 #include "iommu.h"
  18 #include "pasid.h"
  19 #include "perf.h"
  20
  21 struct tbl_walk {
  22         u16 bus;
  23         u16 devfn;
  24         u32 pasid;
  25         struct root_entry *rt_entry;
  26         struct context_entry *ctx_entry;
  27         struct pasid_entry *pasid_tbl_entry;
  28 };
  29
  30 struct iommu_regset {
  31         int offset;
  32         const char *regs;
  33 };
  34
  35 #define DEBUG_BUFFER_SIZE       1024
  36 static char debug_buf[DEBUG_BUFFER_SIZE];
  37
  38 #define IOMMU_REGSET_ENTRY(_reg_)                                       \
  39         { DMAR_##_reg_##_REG, __stringify(_reg_) }
  40
  41 static const struct iommu_regset iommu_regs_32[] = {
  42         IOMMU_REGSET_ENTRY(VER),
  43         IOMMU_REGSET_ENTRY(GCMD),
  44         IOMMU_REGSET_ENTRY(GSTS),
  45         IOMMU_REGSET_ENTRY(FSTS),
  46         IOMMU_REGSET_ENTRY(FECTL),
  47         IOMMU_REGSET_ENTRY(FEDATA),
  48         IOMMU_REGSET_ENTRY(FEADDR),
  49         IOMMU_REGSET_ENTRY(FEUADDR),
  50         IOMMU_REGSET_ENTRY(PMEN),
  51         IOMMU_REGSET_ENTRY(PLMBASE),
  52         IOMMU_REGSET_ENTRY(PLMLIMIT),
  53         IOMMU_REGSET_ENTRY(ICS),
  54         IOMMU_REGSET_ENTRY(PRS),
  55         IOMMU_REGSET_ENTRY(PECTL),
  56         IOMMU_REGSET_ENTRY(PEDATA),
  57         IOMMU_REGSET_ENTRY(PEADDR),
  58         IOMMU_REGSET_ENTRY(PEUADDR),
  59 };
  60
  61 static const struct iommu_regset iommu_regs_64[] = {
  62         IOMMU_REGSET_ENTRY(CAP),
  63         IOMMU_REGSET_ENTRY(ECAP),
  64         IOMMU_REGSET_ENTRY(RTADDR),
  65         IOMMU_REGSET_ENTRY(CCMD),
  66         IOMMU_REGSET_ENTRY(AFLOG),
  67         IOMMU_REGSET_ENTRY(PHMBASE),
  68         IOMMU_REGSET_ENTRY(PHMLIMIT),
  69         IOMMU_REGSET_ENTRY(IQH),
  70         IOMMU_REGSET_ENTRY(IQT),
  71         IOMMU_REGSET_ENTRY(IQA),
  72         IOMMU_REGSET_ENTRY(IRTA),
  73         IOMMU_REGSET_ENTRY(PQH),
  74         IOMMU_REGSET_ENTRY(PQT),
  75         IOMMU_REGSET_ENTRY(PQA),
  76         IOMMU_REGSET_ENTRY(MTRRCAP),
  77         IOMMU_REGSET_ENTRY(MTRRDEF),
  78         IOMMU_REGSET_ENTRY(MTRR_FIX64K_00000),
  79         IOMMU_REGSET_ENTRY(MTRR_FIX16K_80000),
  80         IOMMU_REGSET_ENTRY(MTRR_FIX16K_A0000),
  81         IOMMU_REGSET_ENTRY(MTRR_FIX4K_C0000),
  82         IOMMU_REGSET_ENTRY(MTRR_FIX4K_C8000),
  83         IOMMU_REGSET_ENTRY(MTRR_FIX4K_D0000),
  84         IOMMU_REGSET_ENTRY(MTRR_FIX4K_D8000),
  85         IOMMU_REGSET_ENTRY(MTRR_FIX4K_E0000),
  86         IOMMU_REGSET_ENTRY(MTRR_FIX4K_E8000),
  87         IOMMU_REGSET_ENTRY(MTRR_FIX4K_F0000),
  88         IOMMU_REGSET_ENTRY(MTRR_FIX4K_F8000),
  89         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE0),
  90         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK0),
  91         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE1),
  92         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK1),
  93         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE2),
  94         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK2),
  95         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE3),
  96         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK3),
  97         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE4),
  98         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK4),
  99         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE5),
 100         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK5),
 101         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE6),
 102         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK6),
 103         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE7),
 104         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK7),
 105         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE8),
 106         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK8),
 107         IOMMU_REGSET_ENTRY(MTRR_PHYSBASE9),
 108         IOMMU_REGSET_ENTRY(MTRR_PHYSMASK9),
 109         IOMMU_REGSET_ENTRY(VCCAP),
 110         IOMMU_REGSET_ENTRY(VCMD),
 111         IOMMU_REGSET_ENTRY(VCRSP),
 112 };
 113
 114 static struct dentry *intel_iommu_debug;
 115
 116 static int iommu_regset_show(struct seq_file *m, void *unused)
 117 {
 118         struct dmar_drhd_unit *drhd;
 119         struct intel_iommu *iommu;
 120         unsigned long flag;
 121         int i, ret = 0;
 122         u64 value;
 123
 124         rcu_read_lock();
 125         for_each_active_iommu(iommu, drhd) {
 126                 if (!drhd->reg_base_addr) {
 127                         seq_puts(m, "IOMMU: Invalid base address\n");
 128                         ret = -EINVAL;
 129                         goto out;
 130                 }
 131
 132                 seq_printf(m, "IOMMU: %s Register Base Address: %llx\n",
 133                            iommu->name, drhd->reg_base_addr);
 134                 seq_puts(m, "Name\t\t\tOffset\t\tContents\n");
 135                 /*
 136                  * Publish the contents of the 64-bit hardware registers
 137                  * by adding the offset to the pointer (virtual address).
 138                  */
 139                 raw_spin_lock_irqsave(&iommu->register_lock, flag);
 140                 for (i = 0 ; i < ARRAY_SIZE(iommu_regs_32); i++) {
 141                         value = dmar_readl(iommu->reg + iommu_regs_32[i].offset);
 142                         seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n",
 143                                    iommu_regs_32[i].regs, iommu_regs_32[i].offset,
 144                                    value);
 145                 }
 146                 for (i = 0 ; i < ARRAY_SIZE(iommu_regs_64); i++) {
 147                         value = dmar_readq(iommu->reg + iommu_regs_64[i].offset);
 148                         seq_printf(m, "%-16s\t0x%02x\t\t0x%016llx\n",
 149                                    iommu_regs_64[i].regs, iommu_regs_64[i].offset,
 150                                    value);
 151                 }
 152                 raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
 153                 seq_putc(m, '\n');
 154         }
 155 out:
 156         rcu_read_unlock();
 157
 158         return ret;
 159 }
 160 DEFINE_SHOW_ATTRIBUTE(iommu_regset);
 161
 162 static inline void print_tbl_walk(struct seq_file *m)
 163 {
 164         struct tbl_walk *tbl_wlk = m->private;
 165
 166         seq_printf(m, "%02x:%02x.%x\t0x%016llx:0x%016llx\t0x%016llx:0x%016llx\t",
 167                    tbl_wlk->bus, PCI_SLOT(tbl_wlk->devfn),
 168                    PCI_FUNC(tbl_wlk->devfn), tbl_wlk->rt_entry->hi,
 169                    tbl_wlk->rt_entry->lo, tbl_wlk->ctx_entry->hi,
 170                    tbl_wlk->ctx_entry->lo);
 171
 172         /*
 173          * A legacy mode DMAR doesn't support PASID, hence default it to -1
 174          * indicating that it's invalid. Also, default all PASID related fields
 175          * to 0.
 176          */
 177         if (!tbl_wlk->pasid_tbl_entry)
 178                 seq_printf(m, "%-6d\t0x%016llx:0x%016llx:0x%016llx\n", -1,
 179                            (u64)0, (u64)0, (u64)0);
 180         else
 181                 seq_printf(m, "%-6d\t0x%016llx:0x%016llx:0x%016llx\n",
 182                            tbl_wlk->pasid, tbl_wlk->pasid_tbl_entry->val[2],
 183                            tbl_wlk->pasid_tbl_entry->val[1],
 184                            tbl_wlk->pasid_tbl_entry->val[0]);
 185 }
 186
 187 static void pasid_tbl_walk(struct seq_file *m, struct pasid_entry *tbl_entry,
 188                            u16 dir_idx)
 189 {
 190         struct tbl_walk *tbl_wlk = m->private;
 191         u8 tbl_idx;
 192
 193         for (tbl_idx = 0; tbl_idx < PASID_TBL_ENTRIES; tbl_idx++) {
 194                 if (pasid_pte_is_present(tbl_entry)) {
 195                         tbl_wlk->pasid_tbl_entry = tbl_entry;
 196                         tbl_wlk->pasid = (dir_idx << PASID_PDE_SHIFT) + tbl_idx;
 197                         print_tbl_walk(m);
 198                 }
 199
 200                 tbl_entry++;
 201         }
 202 }
 203
 204 static void pasid_dir_walk(struct seq_file *m, u64 pasid_dir_ptr,
 205                            u16 pasid_dir_size)
 206 {
 207         struct pasid_dir_entry *dir_entry = phys_to_virt(pasid_dir_ptr);
 208         struct pasid_entry *pasid_tbl;
 209         u16 dir_idx;
 210
 211         for (dir_idx = 0; dir_idx < pasid_dir_size; dir_idx++) {
 212                 pasid_tbl = get_pasid_table_from_pde(dir_entry);
 213                 if (pasid_tbl)
 214                         pasid_tbl_walk(m, pasid_tbl, dir_idx);
 215
 216                 dir_entry++;
 217         }
 218 }
 219
 220 static void ctx_tbl_walk(struct seq_file *m, struct intel_iommu *iommu, u16 bus)
 221 {
 222         struct context_entry *context;
 223         u16 devfn, pasid_dir_size;
 224         u64 pasid_dir_ptr;
 225
 226         for (devfn = 0; devfn < 256; devfn++) {
 227                 struct tbl_walk tbl_wlk = {0};
 228
 229                 /*
 230                  * Scalable mode root entry points to upper scalable mode
 231                  * context table and lower scalable mode context table. Each
 232                  * scalable mode context table has 128 context entries where as
 233                  * legacy mode context table has 256 context entries. So in
 234                  * scalable mode, the context entries for former 128 devices are
 235                  * in the lower scalable mode context table, while the latter
 236                  * 128 devices are in the upper scalable mode context table.
 237                  * In scalable mode, when devfn > 127, iommu_context_addr()
 238                  * automatically refers to upper scalable mode context table and
 239                  * hence the caller doesn't have to worry about differences
 240                  * between scalable mode and non scalable mode.
 241                  */
 242                 context = iommu_context_addr(iommu, bus, devfn, 0);
 243                 if (!context)
 244                         return;
 245
 246                 if (!context_present(context))
 247                         continue;
 248
 249                 tbl_wlk.bus = bus;
 250                 tbl_wlk.devfn = devfn;
 251                 tbl_wlk.rt_entry = &iommu->root_entry[bus];
 252                 tbl_wlk.ctx_entry = context;
 253                 m->private = &tbl_wlk;
 254
 255                 if (dmar_readq(iommu->reg + DMAR_RTADDR_REG) & DMA_RTADDR_SMT) {
 256                         pasid_dir_ptr = context->lo & VTD_PAGE_MASK;
 257                         pasid_dir_size = get_pasid_dir_size(context);
 258                         pasid_dir_walk(m, pasid_dir_ptr, pasid_dir_size);
 259                         continue;
 260                 }
 261
 262                 print_tbl_walk(m);
 263         }
 264 }
 265
 266 static void root_tbl_walk(struct seq_file *m, struct intel_iommu *iommu)
 267 {
 268         u16 bus;
 269
 270         spin_lock(&iommu->lock);
 271         seq_printf(m, "IOMMU %s: Root Table Address: 0x%llx\n", iommu->name,
 272                    (u64)virt_to_phys(iommu->root_entry));
 273         seq_puts(m, "B.D.F\tRoot_entry\t\t\t\tContext_entry\t\t\t\tPASID\tPASID_table_entry\n");
 274
 275         /*
 276          * No need to check if the root entry is present or not because
 277          * iommu_context_addr() performs the same check before returning
 278          * context entry.
 279          */
 280         for (bus = 0; bus < 256; bus++)
 281                 ctx_tbl_walk(m, iommu, bus);
 282         spin_unlock(&iommu->lock);
 283 }
 284
 285 static int dmar_translation_struct_show(struct seq_file *m, void *unused)
 286 {
 287         struct dmar_drhd_unit *drhd;
 288         struct intel_iommu *iommu;
 289         u32 sts;
 290
 291         rcu_read_lock();
 292         for_each_active_iommu(iommu, drhd) {
 293                 sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);
 294                 if (!(sts & DMA_GSTS_TES)) {
 295                         seq_printf(m, "DMA Remapping is not enabled on %s\n",
 296                                    iommu->name);
 297                         continue;
 298                 }
 299                 root_tbl_walk(m, iommu);
 300                 seq_putc(m, '\n');
 301         }
 302         rcu_read_unlock();
 303
 304         return 0;
 305 }
 306 DEFINE_SHOW_ATTRIBUTE(dmar_translation_struct);
 307
 308 static inline unsigned long level_to_directory_size(int level)
 309 {
 310         return BIT_ULL(VTD_PAGE_SHIFT + VTD_STRIDE_SHIFT * (level - 1));
 311 }
 312
 313 static inline void
 314 dump_page_info(struct seq_file *m, unsigned long iova, u64 *path)
 315 {
 316         seq_printf(m, "0x%013lx |\t0x%016llx\t0x%016llx\t0x%016llx",
 317                    iova >> VTD_PAGE_SHIFT, path[5], path[4], path[3]);
 318         if (path[2]) {
 319                 seq_printf(m, "\t0x%016llx", path[2]);
 320                 if (path[1])
 321                         seq_printf(m, "\t0x%016llx", path[1]);
 322         }
 323         seq_putc(m, '\n');
 324 }
 325
 326 static void pgtable_walk_level(struct seq_file *m, struct dma_pte *pde,
 327                                int level, unsigned long start,
 328                                u64 *path)
 329 {
 330         int i;
 331
 332         if (level > 5 || level < 1)
 333                 return;
 334
 335         for (i = 0; i < BIT_ULL(VTD_STRIDE_SHIFT);
 336                         i++, pde++, start += level_to_directory_size(level)) {
 337                 if (!dma_pte_present(pde))
 338                         continue;
 339
 340                 path[level] = pde->val;
 341                 if (dma_pte_superpage(pde) || level == 1)
 342                         dump_page_info(m, start, path);
 343                 else
 344                         pgtable_walk_level(m, phys_to_virt(dma_pte_addr(pde)),
 345                                            level - 1, start, path);
 346                 path[level] = 0;
 347         }
 348 }
 349
 350 static int __show_device_domain_translation(struct device *dev, void *data)
 351 {
 352         struct dmar_domain *domain;
 353         struct seq_file *m = data;
 354         u64 path[6] = { 0 };
 355
 356         domain = to_dmar_domain(iommu_get_domain_for_dev(dev));
 357         if (!domain)
 358                 return 0;
 359
 360         seq_printf(m, "Device %s @0x%llx\n", dev_name(dev),
 361                    (u64)virt_to_phys(domain->pgd));
 362         seq_puts(m, "IOVA_PFN\t\tPML5E\t\t\tPML4E\t\t\tPDPE\t\t\tPDE\t\t\tPTE\n");
 363
 364         pgtable_walk_level(m, domain->pgd, domain->agaw + 2, 0, path);
 365         seq_putc(m, '\n');
 366
 367         /* Don't iterate */
 368         return 1;
 369 }
 370
 371 static int show_device_domain_translation(struct device *dev, void *data)
 372 {
 373         struct iommu_group *group;
 374
 375         group = iommu_group_get(dev);
 376         if (group) {
 377                 /*
 378                  * The group->mutex is held across the callback, which will
 379                  * block calls to iommu_attach/detach_group/device. Hence,
 380                  * the domain of the device will not change during traversal.
 381                  *
 382                  * All devices in an iommu group share a single domain, hence
 383                  * we only dump the domain of the first device. Even though,
 384                  * this code still possibly races with the iommu_unmap()
 385                  * interface. This could be solved by RCU-freeing the page
 386                  * table pages in the iommu_unmap() path.
 387                  */
 388                 iommu_group_for_each_dev(group, data,
 389                                          __show_device_domain_translation);
 390                 iommu_group_put(group);
 391         }
 392
 393         return 0;
 394 }
 395
 396 static int domain_translation_struct_show(struct seq_file *m, void *unused)
 397 {
 398         return bus_for_each_dev(&pci_bus_type, NULL, m,
 399                                 show_device_domain_translation);
 400 }
 401 DEFINE_SHOW_ATTRIBUTE(domain_translation_struct);
 402
 403 static void invalidation_queue_entry_show(struct seq_file *m,
 404                                           struct intel_iommu *iommu)
 405 {
 406         int index, shift = qi_shift(iommu);
 407         struct qi_desc *desc;
 408         int offset;
 409
 410         if (ecap_smts(iommu->ecap))
 411                 seq_puts(m, "Index\t\tqw0\t\t\tqw1\t\t\tqw2\t\t\tqw3\t\t\tstatus\n");
 412         else
 413                 seq_puts(m, "Index\t\tqw0\t\t\tqw1\t\t\tstatus\n");
 414
 415         for (index = 0; index < QI_LENGTH; index++) {
 416                 offset = index << shift;
 417                 desc = iommu->qi->desc + offset;
 418                 if (ecap_smts(iommu->ecap))
 419                         seq_printf(m, "%5d\t%016llx\t%016llx\t%016llx\t%016llx\t%016x\n",
 420                                    index, desc->qw0, desc->qw1,
 421                                    desc->qw2, desc->qw3,
 422                                    iommu->qi->desc_status[index]);
 423                 else
 424                         seq_printf(m, "%5d\t%016llx\t%016llx\t%016x\n",
 425                                    index, desc->qw0, desc->qw1,
 426                                    iommu->qi->desc_status[index]);
 427         }
 428 }
 429
 430 static int invalidation_queue_show(struct seq_file *m, void *unused)
 431 {
 432         struct dmar_drhd_unit *drhd;
 433         struct intel_iommu *iommu;
 434         unsigned long flags;
 435         struct q_inval *qi;
 436         int shift;
 437
 438         rcu_read_lock();
 439         for_each_active_iommu(iommu, drhd) {
 440                 qi = iommu->qi;
 441                 shift = qi_shift(iommu);
 442
 443                 if (!qi || !ecap_qis(iommu->ecap))
 444                         continue;
 445
 446                 seq_printf(m, "Invalidation queue on IOMMU: %s\n", iommu->name);
 447
 448                 raw_spin_lock_irqsave(&qi->q_lock, flags);
 449                 seq_printf(m, " Base: 0x%llx\tHead: %lld\tTail: %lld\n",
 450                            (u64)virt_to_phys(qi->desc),
 451                            dmar_readq(iommu->reg + DMAR_IQH_REG) >> shift,
 452                            dmar_readq(iommu->reg + DMAR_IQT_REG) >> shift);
 453                 invalidation_queue_entry_show(m, iommu);
 454                 raw_spin_unlock_irqrestore(&qi->q_lock, flags);
 455                 seq_putc(m, '\n');
 456         }
 457         rcu_read_unlock();
 458
 459         return 0;
 460 }
 461 DEFINE_SHOW_ATTRIBUTE(invalidation_queue);
 462
 463 #ifdef CONFIG_IRQ_REMAP
 464 static void ir_tbl_remap_entry_show(struct seq_file *m,
 465                                     struct intel_iommu *iommu)
 466 {
 467         struct irte *ri_entry;
 468         unsigned long flags;
 469         int idx;
 470
 471         seq_puts(m, " Entry SrcID   DstID    Vct IRTE_high\t\tIRTE_low\n");
 472
 473         raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
 474         for (idx = 0; idx < INTR_REMAP_TABLE_ENTRIES; idx++) {
 475                 ri_entry = &iommu->ir_table->base[idx];
 476                 if (!ri_entry->present || ri_entry->p_pst)
 477                         continue;
 478
 479                 seq_printf(m, " %-5d %02x:%02x.%01x %08x %02x  %016llx\t%016llx\n",
 480                            idx, PCI_BUS_NUM(ri_entry->sid),
 481                            PCI_SLOT(ri_entry->sid), PCI_FUNC(ri_entry->sid),
 482                            ri_entry->dest_id, ri_entry->vector,
 483                            ri_entry->high, ri_entry->low);
 484         }
 485         raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 486 }
 487
 488 static void ir_tbl_posted_entry_show(struct seq_file *m,
 489                                      struct intel_iommu *iommu)
 490 {
 491         struct irte *pi_entry;
 492         unsigned long flags;
 493         int idx;
 494
 495         seq_puts(m, " Entry SrcID   PDA_high PDA_low  Vct IRTE_high\t\tIRTE_low\n");
 496
 497         raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
 498         for (idx = 0; idx < INTR_REMAP_TABLE_ENTRIES; idx++) {
 499                 pi_entry = &iommu->ir_table->base[idx];
 500                 if (!pi_entry->present || !pi_entry->p_pst)
 501                         continue;
 502
 503                 seq_printf(m, " %-5d %02x:%02x.%01x %08x %08x %02x  %016llx\t%016llx\n",
 504                            idx, PCI_BUS_NUM(pi_entry->sid),
 505                            PCI_SLOT(pi_entry->sid), PCI_FUNC(pi_entry->sid),
 506                            pi_entry->pda_h, pi_entry->pda_l << 6,
 507                            pi_entry->vector, pi_entry->high,
 508                            pi_entry->low);
 509         }
 510         raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 511 }
 512
 513 /*
 514  * For active IOMMUs go through the Interrupt remapping
 515  * table and print valid entries in a table format for
 516  * Remapped and Posted Interrupts.
 517  */
 518 static int ir_translation_struct_show(struct seq_file *m, void *unused)
 519 {
 520         struct dmar_drhd_unit *drhd;
 521         struct intel_iommu *iommu;
 522         u64 irta;
 523         u32 sts;
 524
 525         rcu_read_lock();
 526         for_each_active_iommu(iommu, drhd) {
 527                 if (!ecap_ir_support(iommu->ecap))
 528                         continue;
 529
 530                 seq_printf(m, "Remapped Interrupt supported on IOMMU: %s\n",
 531                            iommu->name);
 532
 533                 sts = dmar_readl(iommu->reg + DMAR_GSTS_REG);
 534                 if (iommu->ir_table && (sts & DMA_GSTS_IRES)) {
 535                         irta = virt_to_phys(iommu->ir_table->base);
 536                         seq_printf(m, " IR table address:%llx\n", irta);
 537                         ir_tbl_remap_entry_show(m, iommu);
 538                 } else {
 539                         seq_puts(m, "Interrupt Remapping is not enabled\n");
 540                 }
 541                 seq_putc(m, '\n');
 542         }
 543
 544         seq_puts(m, "****\n\n");
 545
 546         for_each_active_iommu(iommu, drhd) {
 547                 if (!cap_pi_support(iommu->cap))
 548                         continue;
 549
 550                 seq_printf(m, "Posted Interrupt supported on IOMMU: %s\n",
 551                            iommu->name);
 552
 553                 if (iommu->ir_table) {
 554                         irta = virt_to_phys(iommu->ir_table->base);
 555                         seq_printf(m, " IR table address:%llx\n", irta);
 556                         ir_tbl_posted_entry_show(m, iommu);
 557                 } else {
 558                         seq_puts(m, "Interrupt Remapping is not enabled\n");
 559                 }
 560                 seq_putc(m, '\n');
 561         }
 562         rcu_read_unlock();
 563
 564         return 0;
 565 }
 566 DEFINE_SHOW_ATTRIBUTE(ir_translation_struct);
 567 #endif
 568
 569 static void latency_show_one(struct seq_file *m, struct intel_iommu *iommu,
 570                              struct dmar_drhd_unit *drhd)
 571 {
 572         int ret;
 573
 574         seq_printf(m, "IOMMU: %s Register Base Address: %llx\n",
 575                    iommu->name, drhd->reg_base_addr);
 576
 577         ret = dmar_latency_snapshot(iommu, debug_buf, DEBUG_BUFFER_SIZE);
 578         if (ret < 0)
 579                 seq_puts(m, "Failed to get latency snapshot");
 580         else
 581                 seq_puts(m, debug_buf);
 582         seq_puts(m, "\n");
 583 }
 584
 585 static int latency_show(struct seq_file *m, void *v)
 586 {
 587         struct dmar_drhd_unit *drhd;
 588         struct intel_iommu *iommu;
 589
 590         rcu_read_lock();
 591         for_each_active_iommu(iommu, drhd)
 592                 latency_show_one(m, iommu, drhd);
 593         rcu_read_unlock();
 594
 595         return 0;
 596 }
 597
 598 static int dmar_perf_latency_open(struct inode *inode, struct file *filp)
 599 {
 600         return single_open(filp, latency_show, NULL);
 601 }
 602
 603 static ssize_t dmar_perf_latency_write(struct file *filp,
 604                                        const char __user *ubuf,
 605                                        size_t cnt, loff_t *ppos)
 606 {
 607         struct dmar_drhd_unit *drhd;
 608         struct intel_iommu *iommu;
 609         int counting;
 610         char buf[64];
 611
 612         if (cnt > 63)
 613                 cnt = 63;
 614
 615         if (copy_from_user(&buf, ubuf, cnt))
 616                 return -EFAULT;
 617
 618         buf[cnt] = 0;
 619
 620         if (kstrtoint(buf, 0, &counting))
 621                 return -EINVAL;
 622
 623         switch (counting) {
 624         case 0:
 625                 rcu_read_lock();
 626                 for_each_active_iommu(iommu, drhd) {
 627                         dmar_latency_disable(iommu, DMAR_LATENCY_INV_IOTLB);
 628                         dmar_latency_disable(iommu, DMAR_LATENCY_INV_DEVTLB);
 629                         dmar_latency_disable(iommu, DMAR_LATENCY_INV_IEC);
 630                         dmar_latency_disable(iommu, DMAR_LATENCY_PRQ);
 631                 }
 632                 rcu_read_unlock();
 633                 break;
 634         case 1:
 635                 rcu_read_lock();
 636                 for_each_active_iommu(iommu, drhd)
 637                         dmar_latency_enable(iommu, DMAR_LATENCY_INV_IOTLB);
 638                 rcu_read_unlock();
 639                 break;
 640         case 2:
 641                 rcu_read_lock();
 642                 for_each_active_iommu(iommu, drhd)
 643                         dmar_latency_enable(iommu, DMAR_LATENCY_INV_DEVTLB);
 644                 rcu_read_unlock();
 645                 break;
 646         case 3:
 647                 rcu_read_lock();
 648                 for_each_active_iommu(iommu, drhd)
 649                         dmar_latency_enable(iommu, DMAR_LATENCY_INV_IEC);
 650                 rcu_read_unlock();
 651                 break;
 652         case 4:
 653                 rcu_read_lock();
 654                 for_each_active_iommu(iommu, drhd)
 655                         dmar_latency_enable(iommu, DMAR_LATENCY_PRQ);
 656                 rcu_read_unlock();
 657                 break;
 658         default:
 659                 return -EINVAL;
 660         }
 661
 662         *ppos += cnt;
 663         return cnt;
 664 }
 665
 666 static const struct file_operations dmar_perf_latency_fops = {
 667         .open           = dmar_perf_latency_open,
 668         .write          = dmar_perf_latency_write,
 669         .read           = seq_read,
 670         .llseek         = seq_lseek,
 671         .release        = single_release,
 672 };
 673
 674 void __init intel_iommu_debugfs_init(void)
 675 {
 676         intel_iommu_debug = debugfs_create_dir("intel", iommu_debugfs_dir);
 677
 678         debugfs_create_file("iommu_regset", 0444, intel_iommu_debug, NULL,
 679                             &iommu_regset_fops);
 680         debugfs_create_file("dmar_translation_struct", 0444, intel_iommu_debug,
 681                             NULL, &dmar_translation_struct_fops);
 682         debugfs_create_file("invalidation_queue", 0444, intel_iommu_debug,
 683                             NULL, &invalidation_queue_fops);
 684 #ifdef CONFIG_IRQ_REMAP
 685         debugfs_create_file("ir_translation_struct", 0444, intel_iommu_debug,
 686                             NULL, &ir_translation_struct_fops);
 687 #endif
 688         debugfs_create_file("dmar_perf_latency", 0644, intel_iommu_debug,
 689                             NULL, &dmar_perf_latency_fops);
 690 }
 691
 692 /*
 693  * Create a debugfs directory for each device, and then create a
 694  * debugfs file in this directory for users to dump the page table
 695  * of the default domain. e.g.
 696  * /sys/kernel/debug/iommu/intel/0000:00:01.0/domain_translation_struct
 697  */
 698 void intel_iommu_debugfs_create_dev(struct device_domain_info *info)
 699 {
 700         info->debugfs_dentry = debugfs_create_dir(dev_name(info->dev), intel_iommu_debug);
 701
 702         debugfs_create_file("domain_translation_struct", 0444, info->debugfs_dentry,
 703                             NULL, &domain_translation_struct_fops);
 704 }
 705
 706 /* Remove the device debugfs directory. */
 707 void intel_iommu_debugfs_remove_dev(struct device_domain_info *info)
 708 {
 709         debugfs_remove_recursive(info->debugfs_dentry);
 710 }
 711
 712 /*
 713  * Create a debugfs directory per pair of {device, pasid}, then create the
 714  * corresponding debugfs file in this directory for users to dump its page
 715  * table. e.g.
 716  * /sys/kernel/debug/iommu/intel/0000:00:01.0/1/domain_translation_struct
 717  *
 718  * The debugfs only dumps the page tables whose mappings are created and
 719  * destroyed by the iommu_map/unmap() interfaces. Check the mapping type
 720  * of the domain before creating debugfs directory.
 721  */
 722 void intel_iommu_debugfs_create_dev_pasid(struct dev_pasid_info *dev_pasid)
 723 {
 724         struct device_domain_info *info = dev_iommu_priv_get(dev_pasid->dev);
 725         char dir_name[10];
 726
 727         sprintf(dir_name, "%x", dev_pasid->pasid);
 728         dev_pasid->debugfs_dentry = debugfs_create_dir(dir_name, info->debugfs_dentry);
 729 }
 730
 731 /* Remove the device pasid debugfs directory. */
 732 void intel_iommu_debugfs_remove_dev_pasid(struct dev_pasid_info *dev_pasid)
 733 {
 734         debugfs_remove_recursive(dev_pasid->debugfs_dentry);
 735 }