drivers/gpu/drm/amd/include/kgd_pp_interface.h

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __KGD_PP_INTERFACE_H__
  25 #define __KGD_PP_INTERFACE_H__
  26
  27 extern const struct amdgpu_ip_block_version pp_smu_ip_block;
  28 extern const struct amdgpu_ip_block_version smu_v11_0_ip_block;
  29 extern const struct amdgpu_ip_block_version smu_v12_0_ip_block;
  30 extern const struct amdgpu_ip_block_version smu_v13_0_ip_block;
  31 extern const struct amdgpu_ip_block_version smu_v14_0_ip_block;
  32
  33 enum smu_event_type {
  34         SMU_EVENT_RESET_COMPLETE = 0,
  35 };
  36
  37 struct amd_vce_state {
  38         /* vce clocks */
  39         u32 evclk;
  40         u32 ecclk;
  41         /* gpu clocks */
  42         u32 sclk;
  43         u32 mclk;
  44         u8 clk_idx;
  45         u8 pstate;
  46 };
  47
  48
  49 enum amd_dpm_forced_level {
  50         AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
  51         AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
  52         AMD_DPM_FORCED_LEVEL_LOW = 0x4,
  53         AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
  54         AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
  55         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
  56         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
  57         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
  58         AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
  59         AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM = 0x200,
  60 };
  61
  62 enum amd_pm_state_type {
  63         /* not used for dpm */
  64         POWER_STATE_TYPE_DEFAULT,
  65         POWER_STATE_TYPE_POWERSAVE,
  66         /* user selectable states */
  67         POWER_STATE_TYPE_BATTERY,
  68         POWER_STATE_TYPE_BALANCED,
  69         POWER_STATE_TYPE_PERFORMANCE,
  70         /* internal states */
  71         POWER_STATE_TYPE_INTERNAL_UVD,
  72         POWER_STATE_TYPE_INTERNAL_UVD_SD,
  73         POWER_STATE_TYPE_INTERNAL_UVD_HD,
  74         POWER_STATE_TYPE_INTERNAL_UVD_HD2,
  75         POWER_STATE_TYPE_INTERNAL_UVD_MVC,
  76         POWER_STATE_TYPE_INTERNAL_BOOT,
  77         POWER_STATE_TYPE_INTERNAL_THERMAL,
  78         POWER_STATE_TYPE_INTERNAL_ACPI,
  79         POWER_STATE_TYPE_INTERNAL_ULV,
  80         POWER_STATE_TYPE_INTERNAL_3DPERF,
  81 };
  82
  83 #define AMD_MAX_VCE_LEVELS 6
  84
  85 enum amd_vce_level {
  86         AMD_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
  87         AMD_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
  88         AMD_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
  89         AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
  90         AMD_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
  91         AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
  92 };
  93
  94 enum amd_fan_ctrl_mode {
  95         AMD_FAN_CTRL_NONE = 0,
  96         AMD_FAN_CTRL_MANUAL = 1,
  97         AMD_FAN_CTRL_AUTO = 2,
  98 };
  99
 100 enum pp_clock_type {
 101         PP_SCLK,
 102         PP_MCLK,
 103         PP_PCIE,
 104         PP_SOCCLK,
 105         PP_FCLK,
 106         PP_DCEFCLK,
 107         PP_VCLK,
 108         PP_VCLK1,
 109         PP_DCLK,
 110         PP_DCLK1,
 111         OD_SCLK,
 112         OD_MCLK,
 113         OD_VDDC_CURVE,
 114         OD_RANGE,
 115         OD_VDDGFX_OFFSET,
 116         OD_CCLK,
 117         OD_FAN_CURVE,
 118         OD_ACOUSTIC_LIMIT,
 119         OD_ACOUSTIC_TARGET,
 120         OD_FAN_TARGET_TEMPERATURE,
 121         OD_FAN_MINIMUM_PWM,
 122         OD_FAN_ZERO_RPM_ENABLE,
 123         OD_FAN_ZERO_RPM_STOP_TEMP,
 124 };
 125
 126 enum amd_pp_sensors {
 127         AMDGPU_PP_SENSOR_GFX_SCLK = 0,
 128         AMDGPU_PP_SENSOR_CPU_CLK,
 129         AMDGPU_PP_SENSOR_VDDNB,
 130         AMDGPU_PP_SENSOR_VDDGFX,
 131         AMDGPU_PP_SENSOR_UVD_VCLK,
 132         AMDGPU_PP_SENSOR_UVD_DCLK,
 133         AMDGPU_PP_SENSOR_VCE_ECCLK,
 134         AMDGPU_PP_SENSOR_GPU_LOAD,
 135         AMDGPU_PP_SENSOR_MEM_LOAD,
 136         AMDGPU_PP_SENSOR_GFX_MCLK,
 137         AMDGPU_PP_SENSOR_GPU_TEMP,
 138         AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP,
 139         AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
 140         AMDGPU_PP_SENSOR_MEM_TEMP,
 141         AMDGPU_PP_SENSOR_VCE_POWER,
 142         AMDGPU_PP_SENSOR_UVD_POWER,
 143         AMDGPU_PP_SENSOR_GPU_AVG_POWER,
 144         AMDGPU_PP_SENSOR_GPU_INPUT_POWER,
 145         AMDGPU_PP_SENSOR_SS_APU_SHARE,
 146         AMDGPU_PP_SENSOR_SS_DGPU_SHARE,
 147         AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
 148         AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
 149         AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
 150         AMDGPU_PP_SENSOR_MIN_FAN_RPM,
 151         AMDGPU_PP_SENSOR_MAX_FAN_RPM,
 152         AMDGPU_PP_SENSOR_VCN_POWER_STATE,
 153         AMDGPU_PP_SENSOR_PEAK_PSTATE_SCLK,
 154         AMDGPU_PP_SENSOR_PEAK_PSTATE_MCLK,
 155         AMDGPU_PP_SENSOR_VCN_LOAD,
 156 };
 157
 158 enum amd_pp_task {
 159         AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
 160         AMD_PP_TASK_ENABLE_USER_STATE,
 161         AMD_PP_TASK_READJUST_POWER_STATE,
 162         AMD_PP_TASK_COMPLETE_INIT,
 163         AMD_PP_TASK_MAX
 164 };
 165
 166 enum PP_SMC_POWER_PROFILE {
 167         PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0,
 168         PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1,
 169         PP_SMC_POWER_PROFILE_POWERSAVING  = 0x2,
 170         PP_SMC_POWER_PROFILE_VIDEO        = 0x3,
 171         PP_SMC_POWER_PROFILE_VR           = 0x4,
 172         PP_SMC_POWER_PROFILE_COMPUTE      = 0x5,
 173         PP_SMC_POWER_PROFILE_CUSTOM       = 0x6,
 174         PP_SMC_POWER_PROFILE_WINDOW3D     = 0x7,
 175         PP_SMC_POWER_PROFILE_CAPPED       = 0x8,
 176         PP_SMC_POWER_PROFILE_UNCAPPED     = 0x9,
 177         PP_SMC_POWER_PROFILE_COUNT,
 178 };
 179
 180 extern const char * const amdgpu_pp_profile_name[PP_SMC_POWER_PROFILE_COUNT];
 181
 182
 183
 184 enum {
 185         PP_GROUP_UNKNOWN = 0,
 186         PP_GROUP_GFX = 1,
 187         PP_GROUP_SYS,
 188         PP_GROUP_MAX
 189 };
 190
 191 enum PP_OD_DPM_TABLE_COMMAND {
 192         PP_OD_EDIT_SCLK_VDDC_TABLE,
 193         PP_OD_EDIT_MCLK_VDDC_TABLE,
 194         PP_OD_EDIT_CCLK_VDDC_TABLE,
 195         PP_OD_EDIT_VDDC_CURVE,
 196         PP_OD_RESTORE_DEFAULT_TABLE,
 197         PP_OD_COMMIT_DPM_TABLE,
 198         PP_OD_EDIT_VDDGFX_OFFSET,
 199         PP_OD_EDIT_FAN_CURVE,
 200         PP_OD_EDIT_ACOUSTIC_LIMIT,
 201         PP_OD_EDIT_ACOUSTIC_TARGET,
 202         PP_OD_EDIT_FAN_TARGET_TEMPERATURE,
 203         PP_OD_EDIT_FAN_MINIMUM_PWM,
 204         PP_OD_EDIT_FAN_ZERO_RPM_ENABLE,
 205         PP_OD_EDIT_FAN_ZERO_RPM_STOP_TEMP,
 206 };
 207
 208 struct pp_states_info {
 209         uint32_t nums;
 210         uint32_t states[16];
 211 };
 212
 213 enum PP_HWMON_TEMP {
 214         PP_TEMP_EDGE = 0,
 215         PP_TEMP_JUNCTION,
 216         PP_TEMP_MEM,
 217         PP_TEMP_MAX
 218 };
 219
 220 enum pp_mp1_state {
 221         PP_MP1_STATE_NONE,
 222         PP_MP1_STATE_SHUTDOWN,
 223         PP_MP1_STATE_UNLOAD,
 224         PP_MP1_STATE_RESET,
 225         PP_MP1_STATE_FLR,
 226 };
 227
 228 enum pp_df_cstate {
 229         DF_CSTATE_DISALLOW = 0,
 230         DF_CSTATE_ALLOW,
 231 };
 232
 233 /**
 234  * DOC: amdgpu_pp_power
 235  *
 236  * APU power is managed to system-level requirements through the PPT
 237  * (package power tracking) feature. PPT is intended to limit power to the
 238  * requirements of the power source and could be dynamically updated to
 239  * maximize APU performance within the system power budget.
 240  *
 241  * Two types of power measurement can be requested, where supported, with
 242  * :c:type:`enum pp_power_type <pp_power_type>`.
 243  */
 244
 245 /**
 246  * enum pp_power_limit_level - Used to query the power limits
 247  *
 248  * @PP_PWR_LIMIT_MIN: Minimum Power Limit
 249  * @PP_PWR_LIMIT_CURRENT: Current Power Limit
 250  * @PP_PWR_LIMIT_DEFAULT: Default Power Limit
 251  * @PP_PWR_LIMIT_MAX: Maximum Power Limit
 252  */
 253 enum pp_power_limit_level {
 254         PP_PWR_LIMIT_MIN = -1,
 255         PP_PWR_LIMIT_CURRENT,
 256         PP_PWR_LIMIT_DEFAULT,
 257         PP_PWR_LIMIT_MAX,
 258 };
 259
 260 /**
 261  * enum pp_power_type - Used to specify the type of the requested power
 262  *
 263  * @PP_PWR_TYPE_SUSTAINED: manages the configurable, thermally significant
 264  * moving average of APU power (default ~5000 ms).
 265  * @PP_PWR_TYPE_FAST: manages the ~10 ms moving average of APU power,
 266  * where supported.
 267  */
 268 enum pp_power_type {
 269         PP_PWR_TYPE_SUSTAINED,
 270         PP_PWR_TYPE_FAST,
 271 };
 272
 273 enum pp_xgmi_plpd_mode {
 274         XGMI_PLPD_NONE = -1,
 275         XGMI_PLPD_DISALLOW,
 276         XGMI_PLPD_DEFAULT,
 277         XGMI_PLPD_OPTIMIZED,
 278         XGMI_PLPD_COUNT,
 279 };
 280
 281 enum pp_pm_policy {
 282         PP_PM_POLICY_NONE = -1,
 283         PP_PM_POLICY_SOC_PSTATE = 0,
 284         PP_PM_POLICY_XGMI_PLPD,
 285         PP_PM_POLICY_NUM,
 286 };
 287
 288 enum pp_policy_soc_pstate {
 289         SOC_PSTATE_DEFAULT = 0,
 290         SOC_PSTATE_0,
 291         SOC_PSTATE_1,
 292         SOC_PSTATE_2,
 293         SOC_PSTAT_COUNT,
 294 };
 295
 296 #define PP_POLICY_MAX_LEVELS 5
 297
 298 #define PP_GROUP_MASK        0xF0000000
 299 #define PP_GROUP_SHIFT       28
 300
 301 #define PP_BLOCK_MASK        0x0FFFFF00
 302 #define PP_BLOCK_SHIFT       8
 303
 304 #define PP_BLOCK_GFX_CG         0x01
 305 #define PP_BLOCK_GFX_MG         0x02
 306 #define PP_BLOCK_GFX_3D         0x04
 307 #define PP_BLOCK_GFX_RLC        0x08
 308 #define PP_BLOCK_GFX_CP         0x10
 309 #define PP_BLOCK_SYS_BIF        0x01
 310 #define PP_BLOCK_SYS_MC         0x02
 311 #define PP_BLOCK_SYS_ROM        0x04
 312 #define PP_BLOCK_SYS_DRM        0x08
 313 #define PP_BLOCK_SYS_HDP        0x10
 314 #define PP_BLOCK_SYS_SDMA       0x20
 315
 316 #define PP_STATE_MASK           0x0000000F
 317 #define PP_STATE_SHIFT          0
 318 #define PP_STATE_SUPPORT_MASK   0x000000F0
 319 #define PP_STATE_SUPPORT_SHIFT  0
 320
 321 #define PP_STATE_CG             0x01
 322 #define PP_STATE_LS             0x02
 323 #define PP_STATE_DS             0x04
 324 #define PP_STATE_SD             0x08
 325 #define PP_STATE_SUPPORT_CG     0x10
 326 #define PP_STATE_SUPPORT_LS     0x20
 327 #define PP_STATE_SUPPORT_DS     0x40
 328 #define PP_STATE_SUPPORT_SD     0x80
 329
 330 #define PP_CG_MSG_ID(group, block, support, state) \
 331                 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
 332                 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
 333
 334 #define XGMI_MODE_PSTATE_D3 0
 335 #define XGMI_MODE_PSTATE_D0 1
 336
 337 #define NUM_HBM_INSTANCES 4
 338 #define NUM_XGMI_LINKS 8
 339 #define MAX_GFX_CLKS 8
 340 #define MAX_CLKS 4
 341 #define NUM_VCN 4
 342 #define NUM_JPEG_ENG 32
 343 #define MAX_XCC 8
 344 #define NUM_XCP 8
 345 struct seq_file;
 346 enum amd_pp_clock_type;
 347 struct amd_pp_simple_clock_info;
 348 struct amd_pp_display_configuration;
 349 struct amd_pp_clock_info;
 350 struct pp_display_clock_request;
 351 struct pp_clock_levels_with_voltage;
 352 struct pp_clock_levels_with_latency;
 353 struct amd_pp_clocks;
 354 struct pp_smu_wm_range_sets;
 355 struct pp_smu_nv_clock_table;
 356 struct dpm_clocks;
 357
 358 struct amdgpu_xcp_metrics {
 359         /* Utilization Instantaneous (%) */
 360         u32 gfx_busy_inst[MAX_XCC];
 361         u16 jpeg_busy[NUM_JPEG_ENG];
 362         u16 vcn_busy[NUM_VCN];
 363         /* Utilization Accumulated (%) */
 364         u64 gfx_busy_acc[MAX_XCC];
 365 };
 366
 367 struct amd_pm_funcs {
 368 /* export for dpm on ci and si */
 369         int (*pre_set_power_state)(void *handle);
 370         int (*set_power_state)(void *handle);
 371         void (*post_set_power_state)(void *handle);
 372         void (*display_configuration_changed)(void *handle);
 373         void (*print_power_state)(void *handle, void *ps);
 374         bool (*vblank_too_short)(void *handle);
 375         void (*enable_bapm)(void *handle, bool enable);
 376         int (*check_state_equal)(void *handle,
 377                                 void  *cps,
 378                                 void  *rps,
 379                                 bool  *equal);
 380 /* export for sysfs */
 381         int (*set_fan_control_mode)(void *handle, u32 mode);
 382         int (*get_fan_control_mode)(void *handle, u32 *fan_mode);
 383         int (*set_fan_speed_pwm)(void *handle, u32 speed);
 384         int (*get_fan_speed_pwm)(void *handle, u32 *speed);
 385         int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
 386         int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
 387         int (*emit_clock_levels)(void *handle, enum pp_clock_type type, char *buf, int *offset);
 388         int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
 389         int (*get_sclk_od)(void *handle);
 390         int (*set_sclk_od)(void *handle, uint32_t value);
 391         int (*get_mclk_od)(void *handle);
 392         int (*set_mclk_od)(void *handle, uint32_t value);
 393         int (*read_sensor)(void *handle, int idx, void *value, int *size);
 394         int (*get_apu_thermal_limit)(void *handle, uint32_t *limit);
 395         int (*set_apu_thermal_limit)(void *handle, uint32_t limit);
 396         enum amd_dpm_forced_level (*get_performance_level)(void *handle);
 397         enum amd_pm_state_type (*get_current_power_state)(void *handle);
 398         int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
 399         int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);
 400         int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
 401         int (*get_pp_table)(void *handle, char **table);
 402         int (*set_pp_table)(void *handle, const char *buf, size_t size);
 403         void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
 404         int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
 405 /* export to amdgpu */
 406         struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
 407         int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
 408                         enum amd_pm_state_type *user_state);
 409         int (*load_firmware)(void *handle);
 410         int (*wait_for_fw_loading_complete)(void *handle);
 411         int (*set_powergating_by_smu)(void *handle,
 412                                 uint32_t block_type, bool gate);
 413         int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
 414         int (*set_power_limit)(void *handle, uint32_t n);
 415         int (*get_power_limit)(void *handle, uint32_t *limit,
 416                         enum pp_power_limit_level pp_limit_level,
 417                         enum pp_power_type power_type);
 418         int (*get_power_profile_mode)(void *handle, char *buf);
 419         int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
 420         int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size);
 421         int (*odn_edit_dpm_table)(void *handle, enum PP_OD_DPM_TABLE_COMMAND type,
 422                                   long *input, uint32_t size);
 423         int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
 424         int (*smu_i2c_bus_access)(void *handle, bool acquire);
 425         int (*gfx_state_change_set)(void *handle, uint32_t state);
 426 /* export to DC */
 427         u32 (*get_sclk)(void *handle, bool low);
 428         u32 (*get_mclk)(void *handle, bool low);
 429         int (*display_configuration_change)(void *handle,
 430                 const struct amd_pp_display_configuration *input);
 431         int (*get_display_power_level)(void *handle,
 432                 struct amd_pp_simple_clock_info *output);
 433         int (*get_current_clocks)(void *handle,
 434                 struct amd_pp_clock_info *clocks);
 435         int (*get_clock_by_type)(void *handle,
 436                 enum amd_pp_clock_type type,
 437                 struct amd_pp_clocks *clocks);
 438         int (*get_clock_by_type_with_latency)(void *handle,
 439                 enum amd_pp_clock_type type,
 440                 struct pp_clock_levels_with_latency *clocks);
 441         int (*get_clock_by_type_with_voltage)(void *handle,
 442                 enum amd_pp_clock_type type,
 443                 struct pp_clock_levels_with_voltage *clocks);
 444         int (*set_watermarks_for_clocks_ranges)(void *handle,
 445                                                 void *clock_ranges);
 446         int (*display_clock_voltage_request)(void *handle,
 447                                 struct pp_display_clock_request *clock);
 448         int (*get_display_mode_validation_clocks)(void *handle,
 449                 struct amd_pp_simple_clock_info *clocks);
 450         int (*notify_smu_enable_pwe)(void *handle);
 451         int (*enable_mgpu_fan_boost)(void *handle);
 452         int (*set_active_display_count)(void *handle, uint32_t count);
 453         int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
 454         int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
 455         int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
 456         int (*get_asic_baco_capability)(void *handle);
 457         int (*get_asic_baco_state)(void *handle, int *state);
 458         int (*set_asic_baco_state)(void *handle, int state);
 459         int (*get_ppfeature_status)(void *handle, char *buf);
 460         int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
 461         int (*asic_reset_mode_2)(void *handle);
 462         int (*asic_reset_enable_gfx_features)(void *handle);
 463         int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
 464         int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
 465         ssize_t (*get_gpu_metrics)(void *handle, void **table);
 466         ssize_t (*get_pm_metrics)(void *handle, void *pmmetrics, size_t size);
 467         int (*set_watermarks_for_clock_ranges)(void *handle,
 468                                                struct pp_smu_wm_range_sets *ranges);
 469         int (*display_disable_memory_clock_switch)(void *handle,
 470                                                    bool disable_memory_clock_switch);
 471         int (*get_max_sustainable_clocks_by_dc)(void *handle,
 472                                                 struct pp_smu_nv_clock_table *max_clocks);
 473         int (*get_uclk_dpm_states)(void *handle,
 474                                    unsigned int *clock_values_in_khz,
 475                                    unsigned int *num_states);
 476         int (*get_dpm_clock_table)(void *handle,
 477                                    struct dpm_clocks *clock_table);
 478         int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size);
 479         void (*pm_compute_clocks)(void *handle);
 480         int (*notify_rlc_state)(void *handle, bool en);
 481 };
 482
 483 struct metrics_table_header {
 484         uint16_t                        structure_size;
 485         uint8_t                         format_revision;
 486         uint8_t                         content_revision;
 487 };
 488
 489 /*
 490  * gpu_metrics_v1_0 is not recommended as it's not naturally aligned.
 491  * Use gpu_metrics_v1_1 or later instead.
 492  */
 493 struct gpu_metrics_v1_0 {
 494         struct metrics_table_header     common_header;
 495
 496         /* Driver attached timestamp (in ns) */
 497         uint64_t                        system_clock_counter;
 498
 499         /* Temperature */
 500         uint16_t                        temperature_edge;
 501         uint16_t                        temperature_hotspot;
 502         uint16_t                        temperature_mem;
 503         uint16_t                        temperature_vrgfx;
 504         uint16_t                        temperature_vrsoc;
 505         uint16_t                        temperature_vrmem;
 506
 507         /* Utilization */
 508         uint16_t                        average_gfx_activity;
 509         uint16_t                        average_umc_activity; // memory controller
 510         uint16_t                        average_mm_activity; // UVD or VCN
 511
 512         /* Power/Energy */
 513         uint16_t                        average_socket_power;
 514         uint32_t                        energy_accumulator;
 515
 516         /* Average clocks */
 517         uint16_t                        average_gfxclk_frequency;
 518         uint16_t                        average_socclk_frequency;
 519         uint16_t                        average_uclk_frequency;
 520         uint16_t                        average_vclk0_frequency;
 521         uint16_t                        average_dclk0_frequency;
 522         uint16_t                        average_vclk1_frequency;
 523         uint16_t                        average_dclk1_frequency;
 524
 525         /* Current clocks */
 526         uint16_t                        current_gfxclk;
 527         uint16_t                        current_socclk;
 528         uint16_t                        current_uclk;
 529         uint16_t                        current_vclk0;
 530         uint16_t                        current_dclk0;
 531         uint16_t                        current_vclk1;
 532         uint16_t                        current_dclk1;
 533
 534         /* Throttle status */
 535         uint32_t                        throttle_status;
 536
 537         /* Fans */
 538         uint16_t                        current_fan_speed;
 539
 540         /* Link width/speed */
 541         uint8_t                         pcie_link_width;
 542         uint8_t                         pcie_link_speed; // in 0.1 GT/s
 543 };
 544
 545 struct gpu_metrics_v1_1 {
 546         struct metrics_table_header     common_header;
 547
 548         /* Temperature */
 549         uint16_t                        temperature_edge;
 550         uint16_t                        temperature_hotspot;
 551         uint16_t                        temperature_mem;
 552         uint16_t                        temperature_vrgfx;
 553         uint16_t                        temperature_vrsoc;
 554         uint16_t                        temperature_vrmem;
 555
 556         /* Utilization */
 557         uint16_t                        average_gfx_activity;
 558         uint16_t                        average_umc_activity; // memory controller
 559         uint16_t                        average_mm_activity; // UVD or VCN
 560
 561         /* Power/Energy */
 562         uint16_t                        average_socket_power;
 563         uint64_t                        energy_accumulator;
 564
 565         /* Driver attached timestamp (in ns) */
 566         uint64_t                        system_clock_counter;
 567
 568         /* Average clocks */
 569         uint16_t                        average_gfxclk_frequency;
 570         uint16_t                        average_socclk_frequency;
 571         uint16_t                        average_uclk_frequency;
 572         uint16_t                        average_vclk0_frequency;
 573         uint16_t                        average_dclk0_frequency;
 574         uint16_t                        average_vclk1_frequency;
 575         uint16_t                        average_dclk1_frequency;
 576
 577         /* Current clocks */
 578         uint16_t                        current_gfxclk;
 579         uint16_t                        current_socclk;
 580         uint16_t                        current_uclk;
 581         uint16_t                        current_vclk0;
 582         uint16_t                        current_dclk0;
 583         uint16_t                        current_vclk1;
 584         uint16_t                        current_dclk1;
 585
 586         /* Throttle status */
 587         uint32_t                        throttle_status;
 588
 589         /* Fans */
 590         uint16_t                        current_fan_speed;
 591
 592         /* Link width/speed */
 593         uint16_t                        pcie_link_width;
 594         uint16_t                        pcie_link_speed; // in 0.1 GT/s
 595
 596         uint16_t                        padding;
 597
 598         uint32_t                        gfx_activity_acc;
 599         uint32_t                        mem_activity_acc;
 600
 601         uint16_t                        temperature_hbm[NUM_HBM_INSTANCES];
 602 };
 603
 604 struct gpu_metrics_v1_2 {
 605         struct metrics_table_header     common_header;
 606
 607         /* Temperature */
 608         uint16_t                        temperature_edge;
 609         uint16_t                        temperature_hotspot;
 610         uint16_t                        temperature_mem;
 611         uint16_t                        temperature_vrgfx;
 612         uint16_t                        temperature_vrsoc;
 613         uint16_t                        temperature_vrmem;
 614
 615         /* Utilization */
 616         uint16_t                        average_gfx_activity;
 617         uint16_t                        average_umc_activity; // memory controller
 618         uint16_t                        average_mm_activity; // UVD or VCN
 619
 620         /* Power/Energy */
 621         uint16_t                        average_socket_power;
 622         uint64_t                        energy_accumulator;
 623
 624         /* Driver attached timestamp (in ns) */
 625         uint64_t                        system_clock_counter;
 626
 627         /* Average clocks */
 628         uint16_t                        average_gfxclk_frequency;
 629         uint16_t                        average_socclk_frequency;
 630         uint16_t                        average_uclk_frequency;
 631         uint16_t                        average_vclk0_frequency;
 632         uint16_t                        average_dclk0_frequency;
 633         uint16_t                        average_vclk1_frequency;
 634         uint16_t                        average_dclk1_frequency;
 635
 636         /* Current clocks */
 637         uint16_t                        current_gfxclk;
 638         uint16_t                        current_socclk;
 639         uint16_t                        current_uclk;
 640         uint16_t                        current_vclk0;
 641         uint16_t                        current_dclk0;
 642         uint16_t                        current_vclk1;
 643         uint16_t                        current_dclk1;
 644
 645         /* Throttle status (ASIC dependent) */
 646         uint32_t                        throttle_status;
 647
 648         /* Fans */
 649         uint16_t                        current_fan_speed;
 650
 651         /* Link width/speed */
 652         uint16_t                        pcie_link_width;
 653         uint16_t                        pcie_link_speed; // in 0.1 GT/s
 654
 655         uint16_t                        padding;
 656
 657         uint32_t                        gfx_activity_acc;
 658         uint32_t                        mem_activity_acc;
 659
 660         uint16_t                        temperature_hbm[NUM_HBM_INSTANCES];
 661
 662         /* PMFW attached timestamp (10ns resolution) */
 663         uint64_t                        firmware_timestamp;
 664 };
 665
 666 struct gpu_metrics_v1_3 {
 667         struct metrics_table_header     common_header;
 668
 669         /* Temperature */
 670         uint16_t                        temperature_edge;
 671         uint16_t                        temperature_hotspot;
 672         uint16_t                        temperature_mem;
 673         uint16_t                        temperature_vrgfx;
 674         uint16_t                        temperature_vrsoc;
 675         uint16_t                        temperature_vrmem;
 676
 677         /* Utilization */
 678         uint16_t                        average_gfx_activity;
 679         uint16_t                        average_umc_activity; // memory controller
 680         uint16_t                        average_mm_activity; // UVD or VCN
 681
 682         /* Power/Energy */
 683         uint16_t                        average_socket_power;
 684         uint64_t                        energy_accumulator;
 685
 686         /* Driver attached timestamp (in ns) */
 687         uint64_t                        system_clock_counter;
 688
 689         /* Average clocks */
 690         uint16_t                        average_gfxclk_frequency;
 691         uint16_t                        average_socclk_frequency;
 692         uint16_t                        average_uclk_frequency;
 693         uint16_t                        average_vclk0_frequency;
 694         uint16_t                        average_dclk0_frequency;
 695         uint16_t                        average_vclk1_frequency;
 696         uint16_t                        average_dclk1_frequency;
 697
 698         /* Current clocks */
 699         uint16_t                        current_gfxclk;
 700         uint16_t                        current_socclk;
 701         uint16_t                        current_uclk;
 702         uint16_t                        current_vclk0;
 703         uint16_t                        current_dclk0;
 704         uint16_t                        current_vclk1;
 705         uint16_t                        current_dclk1;
 706
 707         /* Throttle status */
 708         uint32_t                        throttle_status;
 709
 710         /* Fans */
 711         uint16_t                        current_fan_speed;
 712
 713         /* Link width/speed */
 714         uint16_t                        pcie_link_width;
 715         uint16_t                        pcie_link_speed; // in 0.1 GT/s
 716
 717         uint16_t                        padding;
 718
 719         uint32_t                        gfx_activity_acc;
 720         uint32_t                        mem_activity_acc;
 721
 722         uint16_t                        temperature_hbm[NUM_HBM_INSTANCES];
 723
 724         /* PMFW attached timestamp (10ns resolution) */
 725         uint64_t                        firmware_timestamp;
 726
 727         /* Voltage (mV) */
 728         uint16_t                        voltage_soc;
 729         uint16_t                        voltage_gfx;
 730         uint16_t                        voltage_mem;
 731
 732         uint16_t                        padding1;
 733
 734         /* Throttle status (ASIC independent) */
 735         uint64_t                        indep_throttle_status;
 736 };
 737
 738 struct gpu_metrics_v1_4 {
 739         struct metrics_table_header     common_header;
 740
 741         /* Temperature (Celsius) */
 742         uint16_t                        temperature_hotspot;
 743         uint16_t                        temperature_mem;
 744         uint16_t                        temperature_vrsoc;
 745
 746         /* Power (Watts) */
 747         uint16_t                        curr_socket_power;
 748
 749         /* Utilization (%) */
 750         uint16_t                        average_gfx_activity;
 751         uint16_t                        average_umc_activity; // memory controller
 752         uint16_t                        vcn_activity[NUM_VCN];
 753
 754         /* Energy (15.259uJ (2^-16) units) */
 755         uint64_t                        energy_accumulator;
 756
 757         /* Driver attached timestamp (in ns) */
 758         uint64_t                        system_clock_counter;
 759
 760         /* Throttle status */
 761         uint32_t                        throttle_status;
 762
 763         /* Clock Lock Status. Each bit corresponds to clock instance */
 764         uint32_t                        gfxclk_lock_status;
 765
 766         /* Link width (number of lanes) and speed (in 0.1 GT/s) */
 767         uint16_t                        pcie_link_width;
 768         uint16_t                        pcie_link_speed;
 769
 770         /* XGMI bus width and bitrate (in Gbps) */
 771         uint16_t                        xgmi_link_width;
 772         uint16_t                        xgmi_link_speed;
 773
 774         /* Utilization Accumulated (%) */
 775         uint32_t                        gfx_activity_acc;
 776         uint32_t                        mem_activity_acc;
 777
 778         /*PCIE accumulated bandwidth (GB/sec) */
 779         uint64_t                        pcie_bandwidth_acc;
 780
 781         /*PCIE instantaneous bandwidth (GB/sec) */
 782         uint64_t                        pcie_bandwidth_inst;
 783
 784         /* PCIE L0 to recovery state transition accumulated count */
 785         uint64_t                        pcie_l0_to_recov_count_acc;
 786
 787         /* PCIE replay accumulated count */
 788         uint64_t                        pcie_replay_count_acc;
 789
 790         /* PCIE replay rollover accumulated count */
 791         uint64_t                        pcie_replay_rover_count_acc;
 792
 793         /* XGMI accumulated data transfer size(KiloBytes) */
 794         uint64_t                        xgmi_read_data_acc[NUM_XGMI_LINKS];
 795         uint64_t                        xgmi_write_data_acc[NUM_XGMI_LINKS];
 796
 797         /* PMFW attached timestamp (10ns resolution) */
 798         uint64_t                        firmware_timestamp;
 799
 800         /* Current clocks (Mhz) */
 801         uint16_t                        current_gfxclk[MAX_GFX_CLKS];
 802         uint16_t                        current_socclk[MAX_CLKS];
 803         uint16_t                        current_vclk0[MAX_CLKS];
 804         uint16_t                        current_dclk0[MAX_CLKS];
 805         uint16_t                        current_uclk;
 806
 807         uint16_t                        padding;
 808 };
 809
 810 struct gpu_metrics_v1_5 {
 811         struct metrics_table_header     common_header;
 812
 813         /* Temperature (Celsius) */
 814         uint16_t                        temperature_hotspot;
 815         uint16_t                        temperature_mem;
 816         uint16_t                        temperature_vrsoc;
 817
 818         /* Power (Watts) */
 819         uint16_t                        curr_socket_power;
 820
 821         /* Utilization (%) */
 822         uint16_t                        average_gfx_activity;
 823         uint16_t                        average_umc_activity; // memory controller
 824         uint16_t                        vcn_activity[NUM_VCN];
 825         uint16_t                        jpeg_activity[NUM_JPEG_ENG];
 826
 827         /* Energy (15.259uJ (2^-16) units) */
 828         uint64_t                        energy_accumulator;
 829
 830         /* Driver attached timestamp (in ns) */
 831         uint64_t                        system_clock_counter;
 832
 833         /* Throttle status */
 834         uint32_t                        throttle_status;
 835
 836         /* Clock Lock Status. Each bit corresponds to clock instance */
 837         uint32_t                        gfxclk_lock_status;
 838
 839         /* Link width (number of lanes) and speed (in 0.1 GT/s) */
 840         uint16_t                        pcie_link_width;
 841         uint16_t                        pcie_link_speed;
 842
 843         /* XGMI bus width and bitrate (in Gbps) */
 844         uint16_t                        xgmi_link_width;
 845         uint16_t                        xgmi_link_speed;
 846
 847         /* Utilization Accumulated (%) */
 848         uint32_t                        gfx_activity_acc;
 849         uint32_t                        mem_activity_acc;
 850
 851         /*PCIE accumulated bandwidth (GB/sec) */
 852         uint64_t                        pcie_bandwidth_acc;
 853
 854         /*PCIE instantaneous bandwidth (GB/sec) */
 855         uint64_t                        pcie_bandwidth_inst;
 856
 857         /* PCIE L0 to recovery state transition accumulated count */
 858         uint64_t                        pcie_l0_to_recov_count_acc;
 859
 860         /* PCIE replay accumulated count */
 861         uint64_t                        pcie_replay_count_acc;
 862
 863         /* PCIE replay rollover accumulated count */
 864         uint64_t                        pcie_replay_rover_count_acc;
 865
 866         /* PCIE NAK sent  accumulated count */
 867         uint32_t                        pcie_nak_sent_count_acc;
 868
 869         /* PCIE NAK received accumulated count */
 870         uint32_t                        pcie_nak_rcvd_count_acc;
 871
 872         /* XGMI accumulated data transfer size(KiloBytes) */
 873         uint64_t                        xgmi_read_data_acc[NUM_XGMI_LINKS];
 874         uint64_t                        xgmi_write_data_acc[NUM_XGMI_LINKS];
 875
 876         /* PMFW attached timestamp (10ns resolution) */
 877         uint64_t                        firmware_timestamp;
 878
 879         /* Current clocks (Mhz) */
 880         uint16_t                        current_gfxclk[MAX_GFX_CLKS];
 881         uint16_t                        current_socclk[MAX_CLKS];
 882         uint16_t                        current_vclk0[MAX_CLKS];
 883         uint16_t                        current_dclk0[MAX_CLKS];
 884         uint16_t                        current_uclk;
 885
 886         uint16_t                        padding;
 887 };
 888
 889 struct gpu_metrics_v1_6 {
 890         struct metrics_table_header     common_header;
 891
 892         /* Temperature (Celsius) */
 893         uint16_t                        temperature_hotspot;
 894         uint16_t                        temperature_mem;
 895         uint16_t                        temperature_vrsoc;
 896
 897         /* Power (Watts) */
 898         uint16_t                        curr_socket_power;
 899
 900         /* Utilization (%) */
 901         uint16_t                        average_gfx_activity;
 902         uint16_t                        average_umc_activity; // memory controller
 903
 904         /* Energy (15.259uJ (2^-16) units) */
 905         uint64_t                        energy_accumulator;
 906
 907         /* Driver attached timestamp (in ns) */
 908         uint64_t                        system_clock_counter;
 909
 910         /* Accumulation cycle counter */
 911         uint32_t                        accumulation_counter;
 912
 913         /* Accumulated throttler residencies */
 914         uint32_t                        prochot_residency_acc;
 915         uint32_t                        ppt_residency_acc;
 916         uint32_t                        socket_thm_residency_acc;
 917         uint32_t                        vr_thm_residency_acc;
 918         uint32_t                        hbm_thm_residency_acc;
 919
 920         /* Clock Lock Status. Each bit corresponds to clock instance */
 921         uint32_t                        gfxclk_lock_status;
 922
 923         /* Link width (number of lanes) and speed (in 0.1 GT/s) */
 924         uint16_t                        pcie_link_width;
 925         uint16_t                        pcie_link_speed;
 926
 927         /* XGMI bus width and bitrate (in Gbps) */
 928         uint16_t                        xgmi_link_width;
 929         uint16_t                        xgmi_link_speed;
 930
 931         /* Utilization Accumulated (%) */
 932         uint32_t                        gfx_activity_acc;
 933         uint32_t                        mem_activity_acc;
 934
 935         /*PCIE accumulated bandwidth (GB/sec) */
 936         uint64_t                        pcie_bandwidth_acc;
 937
 938         /*PCIE instantaneous bandwidth (GB/sec) */
 939         uint64_t                        pcie_bandwidth_inst;
 940
 941         /* PCIE L0 to recovery state transition accumulated count */
 942         uint64_t                        pcie_l0_to_recov_count_acc;
 943
 944         /* PCIE replay accumulated count */
 945         uint64_t                        pcie_replay_count_acc;
 946
 947         /* PCIE replay rollover accumulated count */
 948         uint64_t                        pcie_replay_rover_count_acc;
 949
 950         /* PCIE NAK sent  accumulated count */
 951         uint32_t                        pcie_nak_sent_count_acc;
 952
 953         /* PCIE NAK received accumulated count */
 954         uint32_t                        pcie_nak_rcvd_count_acc;
 955
 956         /* XGMI accumulated data transfer size(KiloBytes) */
 957         uint64_t                        xgmi_read_data_acc[NUM_XGMI_LINKS];
 958         uint64_t                        xgmi_write_data_acc[NUM_XGMI_LINKS];
 959
 960         /* PMFW attached timestamp (10ns resolution) */
 961         uint64_t                        firmware_timestamp;
 962
 963         /* Current clocks (Mhz) */
 964         uint16_t                        current_gfxclk[MAX_GFX_CLKS];
 965         uint16_t                        current_socclk[MAX_CLKS];
 966         uint16_t                        current_vclk0[MAX_CLKS];
 967         uint16_t                        current_dclk0[MAX_CLKS];
 968         uint16_t                        current_uclk;
 969
 970         /* Number of current partition */
 971         uint16_t                        num_partition;
 972
 973         /* XCP metrics stats */
 974         struct amdgpu_xcp_metrics       xcp_stats[NUM_XCP];
 975
 976         /* PCIE other end recovery counter */
 977         uint32_t                        pcie_lc_perf_other_end_recovery;
 978 };
 979
 980 /*
 981  * gpu_metrics_v2_0 is not recommended as it's not naturally aligned.
 982  * Use gpu_metrics_v2_1 or later instead.
 983  */
 984 struct gpu_metrics_v2_0 {
 985         struct metrics_table_header     common_header;
 986
 987         /* Driver attached timestamp (in ns) */
 988         uint64_t                        system_clock_counter;
 989
 990         /* Temperature */
 991         uint16_t                        temperature_gfx; // gfx temperature on APUs
 992         uint16_t                        temperature_soc; // soc temperature on APUs
 993         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
 994         uint16_t                        temperature_l3[2];
 995
 996         /* Utilization */
 997         uint16_t                        average_gfx_activity;
 998         uint16_t                        average_mm_activity; // UVD or VCN
 999
1000         /* Power/Energy */
1001         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
1002         uint16_t                        average_cpu_power;
1003         uint16_t                        average_soc_power;
1004         uint16_t                        average_gfx_power;
1005         uint16_t                        average_core_power[8]; // CPU core power on APUs
1006
1007         /* Average clocks */
1008         uint16_t                        average_gfxclk_frequency;
1009         uint16_t                        average_socclk_frequency;
1010         uint16_t                        average_uclk_frequency;
1011         uint16_t                        average_fclk_frequency;
1012         uint16_t                        average_vclk_frequency;
1013         uint16_t                        average_dclk_frequency;
1014
1015         /* Current clocks */
1016         uint16_t                        current_gfxclk;
1017         uint16_t                        current_socclk;
1018         uint16_t                        current_uclk;
1019         uint16_t                        current_fclk;
1020         uint16_t                        current_vclk;
1021         uint16_t                        current_dclk;
1022         uint16_t                        current_coreclk[8]; // CPU core clocks
1023         uint16_t                        current_l3clk[2];
1024
1025         /* Throttle status */
1026         uint32_t                        throttle_status;
1027
1028         /* Fans */
1029         uint16_t                        fan_pwm;
1030
1031         uint16_t                        padding;
1032 };
1033
1034 struct gpu_metrics_v2_1 {
1035         struct metrics_table_header     common_header;
1036
1037         /* Temperature */
1038         uint16_t                        temperature_gfx; // gfx temperature on APUs
1039         uint16_t                        temperature_soc; // soc temperature on APUs
1040         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
1041         uint16_t                        temperature_l3[2];
1042
1043         /* Utilization */
1044         uint16_t                        average_gfx_activity;
1045         uint16_t                        average_mm_activity; // UVD or VCN
1046
1047         /* Driver attached timestamp (in ns) */
1048         uint64_t                        system_clock_counter;
1049
1050         /* Power/Energy */
1051         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
1052         uint16_t                        average_cpu_power;
1053         uint16_t                        average_soc_power;
1054         uint16_t                        average_gfx_power;
1055         uint16_t                        average_core_power[8]; // CPU core power on APUs
1056
1057         /* Average clocks */
1058         uint16_t                        average_gfxclk_frequency;
1059         uint16_t                        average_socclk_frequency;
1060         uint16_t                        average_uclk_frequency;
1061         uint16_t                        average_fclk_frequency;
1062         uint16_t                        average_vclk_frequency;
1063         uint16_t                        average_dclk_frequency;
1064
1065         /* Current clocks */
1066         uint16_t                        current_gfxclk;
1067         uint16_t                        current_socclk;
1068         uint16_t                        current_uclk;
1069         uint16_t                        current_fclk;
1070         uint16_t                        current_vclk;
1071         uint16_t                        current_dclk;
1072         uint16_t                        current_coreclk[8]; // CPU core clocks
1073         uint16_t                        current_l3clk[2];
1074
1075         /* Throttle status */
1076         uint32_t                        throttle_status;
1077
1078         /* Fans */
1079         uint16_t                        fan_pwm;
1080
1081         uint16_t                        padding[3];
1082 };
1083
1084 struct gpu_metrics_v2_2 {
1085         struct metrics_table_header     common_header;
1086
1087         /* Temperature */
1088         uint16_t                        temperature_gfx; // gfx temperature on APUs
1089         uint16_t                        temperature_soc; // soc temperature on APUs
1090         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
1091         uint16_t                        temperature_l3[2];
1092
1093         /* Utilization */
1094         uint16_t                        average_gfx_activity;
1095         uint16_t                        average_mm_activity; // UVD or VCN
1096
1097         /* Driver attached timestamp (in ns) */
1098         uint64_t                        system_clock_counter;
1099
1100         /* Power/Energy */
1101         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
1102         uint16_t                        average_cpu_power;
1103         uint16_t                        average_soc_power;
1104         uint16_t                        average_gfx_power;
1105         uint16_t                        average_core_power[8]; // CPU core power on APUs
1106
1107         /* Average clocks */
1108         uint16_t                        average_gfxclk_frequency;
1109         uint16_t                        average_socclk_frequency;
1110         uint16_t                        average_uclk_frequency;
1111         uint16_t                        average_fclk_frequency;
1112         uint16_t                        average_vclk_frequency;
1113         uint16_t                        average_dclk_frequency;
1114
1115         /* Current clocks */
1116         uint16_t                        current_gfxclk;
1117         uint16_t                        current_socclk;
1118         uint16_t                        current_uclk;
1119         uint16_t                        current_fclk;
1120         uint16_t                        current_vclk;
1121         uint16_t                        current_dclk;
1122         uint16_t                        current_coreclk[8]; // CPU core clocks
1123         uint16_t                        current_l3clk[2];
1124
1125         /* Throttle status (ASIC dependent) */
1126         uint32_t                        throttle_status;
1127
1128         /* Fans */
1129         uint16_t                        fan_pwm;
1130
1131         uint16_t                        padding[3];
1132
1133         /* Throttle status (ASIC independent) */
1134         uint64_t                        indep_throttle_status;
1135 };
1136
1137 struct gpu_metrics_v2_3 {
1138         struct metrics_table_header     common_header;
1139
1140         /* Temperature */
1141         uint16_t                        temperature_gfx; // gfx temperature on APUs
1142         uint16_t                        temperature_soc; // soc temperature on APUs
1143         uint16_t                        temperature_core[8]; // CPU core temperature on APUs
1144         uint16_t                        temperature_l3[2];
1145
1146         /* Utilization */
1147         uint16_t                        average_gfx_activity;
1148         uint16_t                        average_mm_activity; // UVD or VCN
1149
1150         /* Driver attached timestamp (in ns) */
1151         uint64_t                        system_clock_counter;
1152
1153         /* Power/Energy */
1154         uint16_t                        average_socket_power; // dGPU + APU power on A + A platform
1155         uint16_t                        average_cpu_power;
1156         uint16_t                        average_soc_power;
1157         uint16_t                        average_gfx_power;
1158         uint16_t                        average_core_power[8]; // CPU core power on APUs
1159
1160         /* Average clocks */
1161         uint16_t                        average_gfxclk_frequency;
1162         uint16_t                        average_socclk_frequency;
1163         uint16_t                        average_uclk_frequency;
1164         uint16_t                        average_fclk_frequency;
1165         uint16_t                        average_vclk_frequency;
1166         uint16_t                        average_dclk_frequency;
1167
1168         /* Current clocks */
1169         uint16_t                        current_gfxclk;
1170         uint16_t                        current_socclk;
1171         uint16_t                        current_uclk;
1172         uint16_t                        current_fclk;
1173         uint16_t                        current_vclk;
1174         uint16_t                        current_dclk;
1175         uint16_t                        current_coreclk[8]; // CPU core clocks
1176         uint16_t                        current_l3clk[2];
1177
1178         /* Throttle status (ASIC dependent) */
1179         uint32_t                        throttle_status;
1180
1181         /* Fans */
1182         uint16_t                        fan_pwm;
1183
1184         uint16_t                        padding[3];
1185
1186         /* Throttle status (ASIC independent) */
1187         uint64_t                        indep_throttle_status;
1188
1189         /* Average Temperature */
1190         uint16_t                        average_temperature_gfx; // average gfx temperature on APUs
1191         uint16_t                        average_temperature_soc; // average soc temperature on APUs
1192         uint16_t                        average_temperature_core[8]; // average CPU core temperature on APUs
1193         uint16_t                        average_temperature_l3[2];
1194 };
1195
1196 struct gpu_metrics_v2_4 {
1197         struct metrics_table_header     common_header;
1198
1199         /* Temperature (unit: centi-Celsius) */
1200         uint16_t                        temperature_gfx;
1201         uint16_t                        temperature_soc;
1202         uint16_t                        temperature_core[8];
1203         uint16_t                        temperature_l3[2];
1204
1205         /* Utilization (unit: centi) */
1206         uint16_t                        average_gfx_activity;
1207         uint16_t                        average_mm_activity;
1208
1209         /* Driver attached timestamp (in ns) */
1210         uint64_t                        system_clock_counter;
1211
1212         /* Power/Energy (unit: mW) */
1213         uint16_t                        average_socket_power;
1214         uint16_t                        average_cpu_power;
1215         uint16_t                        average_soc_power;
1216         uint16_t                        average_gfx_power;
1217         uint16_t                        average_core_power[8];
1218
1219         /* Average clocks (unit: MHz) */
1220         uint16_t                        average_gfxclk_frequency;
1221         uint16_t                        average_socclk_frequency;
1222         uint16_t                        average_uclk_frequency;
1223         uint16_t                        average_fclk_frequency;
1224         uint16_t                        average_vclk_frequency;
1225         uint16_t                        average_dclk_frequency;
1226
1227         /* Current clocks (unit: MHz) */
1228         uint16_t                        current_gfxclk;
1229         uint16_t                        current_socclk;
1230         uint16_t                        current_uclk;
1231         uint16_t                        current_fclk;
1232         uint16_t                        current_vclk;
1233         uint16_t                        current_dclk;
1234         uint16_t                        current_coreclk[8];
1235         uint16_t                        current_l3clk[2];
1236
1237         /* Throttle status (ASIC dependent) */
1238         uint32_t                        throttle_status;
1239
1240         /* Fans */
1241         uint16_t                        fan_pwm;
1242
1243         uint16_t                        padding[3];
1244
1245         /* Throttle status (ASIC independent) */
1246         uint64_t                        indep_throttle_status;
1247
1248         /* Average Temperature (unit: centi-Celsius) */
1249         uint16_t                        average_temperature_gfx;
1250         uint16_t                        average_temperature_soc;
1251         uint16_t                        average_temperature_core[8];
1252         uint16_t                        average_temperature_l3[2];
1253
1254         /* Power/Voltage (unit: mV) */
1255         uint16_t                        average_cpu_voltage;
1256         uint16_t                        average_soc_voltage;
1257         uint16_t                        average_gfx_voltage;
1258
1259         /* Power/Current (unit: mA) */
1260         uint16_t                        average_cpu_current;
1261         uint16_t                        average_soc_current;
1262         uint16_t                        average_gfx_current;
1263 };
1264
1265 struct gpu_metrics_v3_0 {
1266         struct metrics_table_header     common_header;
1267
1268         /* Temperature */
1269         /* gfx temperature on APUs */
1270         uint16_t                        temperature_gfx;
1271         /* soc temperature on APUs */
1272         uint16_t                        temperature_soc;
1273         /* CPU core temperature on APUs */
1274         uint16_t                        temperature_core[16];
1275         /* skin temperature on APUs */
1276         uint16_t                        temperature_skin;
1277
1278         /* Utilization */
1279         /* time filtered GFX busy % [0-100] */
1280         uint16_t                        average_gfx_activity;
1281         /* time filtered VCN busy % [0-100] */
1282         uint16_t                        average_vcn_activity;
1283         /* time filtered IPU per-column busy % [0-100] */
1284         uint16_t                        average_ipu_activity[8];
1285         /* time filtered per-core C0 residency % [0-100]*/
1286         uint16_t                        average_core_c0_activity[16];
1287         /* time filtered DRAM read bandwidth [MB/sec] */
1288         uint16_t                        average_dram_reads;
1289         /* time filtered DRAM write bandwidth [MB/sec] */
1290         uint16_t                        average_dram_writes;
1291         /* time filtered IPU read bandwidth [MB/sec] */
1292         uint16_t                        average_ipu_reads;
1293         /* time filtered IPU write bandwidth [MB/sec] */
1294         uint16_t                        average_ipu_writes;
1295
1296         /* Driver attached timestamp (in ns) */
1297         uint64_t                        system_clock_counter;
1298
1299         /* Power/Energy */
1300         /* time filtered power used for PPT/STAPM [APU+dGPU] [mW] */
1301         uint32_t                        average_socket_power;
1302         /* time filtered IPU power [mW] */
1303         uint16_t                        average_ipu_power;
1304         /* time filtered APU power [mW] */
1305         uint32_t                        average_apu_power;
1306         /* time filtered GFX power [mW] */
1307         uint32_t                        average_gfx_power;
1308         /* time filtered dGPU power [mW] */
1309         uint32_t                        average_dgpu_power;
1310         /* time filtered sum of core power across all cores in the socket [mW] */
1311         uint32_t                        average_all_core_power;
1312         /* calculated core power [mW] */
1313         uint16_t                        average_core_power[16];
1314         /* time filtered total system power [mW] */
1315         uint16_t                        average_sys_power;
1316         /* maximum IRM defined STAPM power limit [mW] */
1317         uint16_t                        stapm_power_limit;
1318         /* time filtered STAPM power limit [mW] */
1319         uint16_t                        current_stapm_power_limit;
1320
1321         /* time filtered clocks [MHz] */
1322         uint16_t                        average_gfxclk_frequency;
1323         uint16_t                        average_socclk_frequency;
1324         uint16_t                        average_vpeclk_frequency;
1325         uint16_t                        average_ipuclk_frequency;
1326         uint16_t                        average_fclk_frequency;
1327         uint16_t                        average_vclk_frequency;
1328         uint16_t                        average_uclk_frequency;
1329         uint16_t                        average_mpipu_frequency;
1330
1331         /* Current clocks */
1332         /* target core frequency [MHz] */
1333         uint16_t                        current_coreclk[16];
1334         /* CCLK frequency limit enforced on classic cores [MHz] */
1335         uint16_t                        current_core_maxfreq;
1336         /* GFXCLK frequency limit enforced on GFX [MHz] */
1337         uint16_t                        current_gfx_maxfreq;
1338
1339         /* Throttle Residency (ASIC dependent) */
1340         uint32_t                        throttle_residency_prochot;
1341         uint32_t                        throttle_residency_spl;
1342         uint32_t                        throttle_residency_fppt;
1343         uint32_t                        throttle_residency_sppt;
1344         uint32_t                        throttle_residency_thm_core;
1345         uint32_t                        throttle_residency_thm_gfx;
1346         uint32_t                        throttle_residency_thm_soc;
1347
1348         /* Metrics table alpha filter time constant [us] */
1349         uint32_t                        time_filter_alphavalue;
1350 };
1351
1352 struct amdgpu_pmmetrics_header {
1353         uint16_t structure_size;
1354         uint16_t pad;
1355         uint32_t mp1_ip_discovery_version;
1356         uint32_t pmfw_version;
1357         uint32_t pmmetrics_version;
1358 };
1359
1360 struct amdgpu_pm_metrics {
1361         struct amdgpu_pmmetrics_header common_header;
1362
1363         uint8_t data[];
1364 };
1365
1366 #endif