drivers/gpu/drm/i915/intel_device_info.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <drm/drm_print.h>
  26 #include <drm/i915_pciids.h>
  27
  28 #include "display/intel_cdclk.h"
  29 #include "display/intel_de.h"
  30 #include "intel_device_info.h"
  31 #include "i915_drv.h"
  32
  33 #define PLATFORM_NAME(x) [INTEL_##x] = #x
  34 static const char * const platform_names[] = {
  35         PLATFORM_NAME(I830),
  36         PLATFORM_NAME(I845G),
  37         PLATFORM_NAME(I85X),
  38         PLATFORM_NAME(I865G),
  39         PLATFORM_NAME(I915G),
  40         PLATFORM_NAME(I915GM),
  41         PLATFORM_NAME(I945G),
  42         PLATFORM_NAME(I945GM),
  43         PLATFORM_NAME(G33),
  44         PLATFORM_NAME(PINEVIEW),
  45         PLATFORM_NAME(I965G),
  46         PLATFORM_NAME(I965GM),
  47         PLATFORM_NAME(G45),
  48         PLATFORM_NAME(GM45),
  49         PLATFORM_NAME(IRONLAKE),
  50         PLATFORM_NAME(SANDYBRIDGE),
  51         PLATFORM_NAME(IVYBRIDGE),
  52         PLATFORM_NAME(VALLEYVIEW),
  53         PLATFORM_NAME(HASWELL),
  54         PLATFORM_NAME(BROADWELL),
  55         PLATFORM_NAME(CHERRYVIEW),
  56         PLATFORM_NAME(SKYLAKE),
  57         PLATFORM_NAME(BROXTON),
  58         PLATFORM_NAME(KABYLAKE),
  59         PLATFORM_NAME(GEMINILAKE),
  60         PLATFORM_NAME(COFFEELAKE),
  61         PLATFORM_NAME(COMETLAKE),
  62         PLATFORM_NAME(CANNONLAKE),
  63         PLATFORM_NAME(ICELAKE),
  64         PLATFORM_NAME(ELKHARTLAKE),
  65         PLATFORM_NAME(JASPERLAKE),
  66         PLATFORM_NAME(TIGERLAKE),
  67         PLATFORM_NAME(ROCKETLAKE),
  68         PLATFORM_NAME(DG1),
  69 };
  70 #undef PLATFORM_NAME
  71
  72 const char *intel_platform_name(enum intel_platform platform)
  73 {
  74         BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);
  75
  76         if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
  77                          platform_names[platform] == NULL))
  78                 return "<unknown>";
  79
  80         return platform_names[platform];
  81 }
  82
  83 static const char *iommu_name(void)
  84 {
  85         const char *msg = "n/a";
  86
  87 #ifdef CONFIG_INTEL_IOMMU
  88         msg = enableddisabled(intel_iommu_gfx_mapped);
  89 #endif
  90
  91         return msg;
  92 }
  93
  94 void intel_device_info_print_static(const struct intel_device_info *info,
  95                                     struct drm_printer *p)
  96 {
  97         drm_printf(p, "gen: %d\n", info->gen);
  98         drm_printf(p, "gt: %d\n", info->gt);
  99         drm_printf(p, "iommu: %s\n", iommu_name());
 100         drm_printf(p, "memory-regions: %x\n", info->memory_regions);
 101         drm_printf(p, "page-sizes: %x\n", info->page_sizes);
 102         drm_printf(p, "platform: %s\n", intel_platform_name(info->platform));
 103         drm_printf(p, "ppgtt-size: %d\n", info->ppgtt_size);
 104         drm_printf(p, "ppgtt-type: %d\n", info->ppgtt_type);
 105         drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size);
 106
 107 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name));
 108         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
 109 #undef PRINT_FLAG
 110
 111 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->display.name));
 112         DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
 113 #undef PRINT_FLAG
 114 }
 115
 116 void intel_device_info_print_runtime(const struct intel_runtime_info *info,
 117                                      struct drm_printer *p)
 118 {
 119         drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq);
 120         drm_printf(p, "CS timestamp frequency: %u Hz\n",
 121                    info->cs_timestamp_frequency_hz);
 122 }
 123
 124 static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv)
 125 {
 126         u32 ts_override = intel_uncore_read(&dev_priv->uncore,
 127                                             GEN9_TIMESTAMP_OVERRIDE);
 128         u32 base_freq, frac_freq;
 129
 130         base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >>
 131                      GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1;
 132         base_freq *= 1000000;
 133
 134         frac_freq = ((ts_override &
 135                       GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >>
 136                      GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT);
 137         frac_freq = 1000000 / (frac_freq + 1);
 138
 139         return base_freq + frac_freq;
 140 }
 141
 142 static u32 gen10_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
 143                                         u32 rpm_config_reg)
 144 {
 145         u32 f19_2_mhz = 19200000;
 146         u32 f24_mhz = 24000000;
 147         u32 crystal_clock = (rpm_config_reg &
 148                              GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
 149                             GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
 150
 151         switch (crystal_clock) {
 152         case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
 153                 return f19_2_mhz;
 154         case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
 155                 return f24_mhz;
 156         default:
 157                 MISSING_CASE(crystal_clock);
 158                 return 0;
 159         }
 160 }
 161
 162 static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
 163                                         u32 rpm_config_reg)
 164 {
 165         u32 f19_2_mhz = 19200000;
 166         u32 f24_mhz = 24000000;
 167         u32 f25_mhz = 25000000;
 168         u32 f38_4_mhz = 38400000;
 169         u32 crystal_clock = (rpm_config_reg &
 170                              GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
 171                             GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
 172
 173         switch (crystal_clock) {
 174         case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
 175                 return f24_mhz;
 176         case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
 177                 return f19_2_mhz;
 178         case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ:
 179                 return f38_4_mhz;
 180         case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ:
 181                 return f25_mhz;
 182         default:
 183                 MISSING_CASE(crystal_clock);
 184                 return 0;
 185         }
 186 }
 187
 188 static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 189 {
 190         struct intel_uncore *uncore = &dev_priv->uncore;
 191         u32 f12_5_mhz = 12500000;
 192         u32 f19_2_mhz = 19200000;
 193         u32 f24_mhz = 24000000;
 194
 195         if (INTEL_GEN(dev_priv) <= 4) {
 196                 /* PRMs say:
 197                  *
 198                  *     "The value in this register increments once every 16
 199                  *      hclks." (through the “Clocking Configuration”
 200                  *      (“CLKCFG”) MCHBAR register)
 201                  */
 202                 return RUNTIME_INFO(dev_priv)->rawclk_freq * 1000 / 16;
 203         } else if (INTEL_GEN(dev_priv) <= 8) {
 204                 /* PRMs say:
 205                  *
 206                  *     "The PCU TSC counts 10ns increments; this timestamp
 207                  *      reflects bits 38:3 of the TSC (i.e. 80ns granularity,
 208                  *      rolling over every 1.5 hours).
 209                  */
 210                 return f12_5_mhz;
 211         } else if (INTEL_GEN(dev_priv) <= 9) {
 212                 u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
 213                 u32 freq = 0;
 214
 215                 if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
 216                         freq = read_reference_ts_freq(dev_priv);
 217                 } else {
 218                         freq = IS_GEN9_LP(dev_priv) ? f19_2_mhz : f24_mhz;
 219
 220                         /* Now figure out how the command stream's timestamp
 221                          * register increments from this frequency (it might
 222                          * increment only every few clock cycle).
 223                          */
 224                         freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
 225                                       CTC_SHIFT_PARAMETER_SHIFT);
 226                 }
 227
 228                 return freq;
 229         } else if (INTEL_GEN(dev_priv) <= 12) {
 230                 u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
 231                 u32 freq = 0;
 232
 233                 /* First figure out the reference frequency. There are 2 ways
 234                  * we can compute the frequency, either through the
 235                  * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
 236                  * tells us which one we should use.
 237                  */
 238                 if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
 239                         freq = read_reference_ts_freq(dev_priv);
 240                 } else {
 241                         u32 rpm_config_reg = intel_uncore_read(uncore, RPM_CONFIG0);
 242
 243                         if (INTEL_GEN(dev_priv) <= 10)
 244                                 freq = gen10_get_crystal_clock_freq(dev_priv,
 245                                                                 rpm_config_reg);
 246                         else
 247                                 freq = gen11_get_crystal_clock_freq(dev_priv,
 248                                                                 rpm_config_reg);
 249
 250                         /* Now figure out how the command stream's timestamp
 251                          * register increments from this frequency (it might
 252                          * increment only every few clock cycle).
 253                          */
 254                         freq >>= 3 - ((rpm_config_reg &
 255                                        GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
 256                                       GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
 257                 }
 258
 259                 return freq;
 260         }
 261
 262         MISSING_CASE("Unknown gen, unable to read command streamer timestamp frequency\n");
 263         return 0;
 264 }
 265
 266 #undef INTEL_VGA_DEVICE
 267 #define INTEL_VGA_DEVICE(id, info) (id)
 268
 269 static const u16 subplatform_ult_ids[] = {
 270         INTEL_HSW_ULT_GT1_IDS(0),
 271         INTEL_HSW_ULT_GT2_IDS(0),
 272         INTEL_HSW_ULT_GT3_IDS(0),
 273         INTEL_BDW_ULT_GT1_IDS(0),
 274         INTEL_BDW_ULT_GT2_IDS(0),
 275         INTEL_BDW_ULT_GT3_IDS(0),
 276         INTEL_BDW_ULT_RSVD_IDS(0),
 277         INTEL_SKL_ULT_GT1_IDS(0),
 278         INTEL_SKL_ULT_GT2_IDS(0),
 279         INTEL_SKL_ULT_GT3_IDS(0),
 280         INTEL_KBL_ULT_GT1_IDS(0),
 281         INTEL_KBL_ULT_GT2_IDS(0),
 282         INTEL_KBL_ULT_GT3_IDS(0),
 283         INTEL_CFL_U_GT2_IDS(0),
 284         INTEL_CFL_U_GT3_IDS(0),
 285         INTEL_WHL_U_GT1_IDS(0),
 286         INTEL_WHL_U_GT2_IDS(0),
 287         INTEL_WHL_U_GT3_IDS(0),
 288         INTEL_CML_U_GT1_IDS(0),
 289         INTEL_CML_U_GT2_IDS(0),
 290 };
 291
 292 static const u16 subplatform_ulx_ids[] = {
 293         INTEL_HSW_ULX_GT1_IDS(0),
 294         INTEL_HSW_ULX_GT2_IDS(0),
 295         INTEL_BDW_ULX_GT1_IDS(0),
 296         INTEL_BDW_ULX_GT2_IDS(0),
 297         INTEL_BDW_ULX_GT3_IDS(0),
 298         INTEL_BDW_ULX_RSVD_IDS(0),
 299         INTEL_SKL_ULX_GT1_IDS(0),
 300         INTEL_SKL_ULX_GT2_IDS(0),
 301         INTEL_KBL_ULX_GT1_IDS(0),
 302         INTEL_KBL_ULX_GT2_IDS(0),
 303         INTEL_AML_KBL_GT2_IDS(0),
 304         INTEL_AML_CFL_GT2_IDS(0),
 305 };
 306
 307 static const u16 subplatform_portf_ids[] = {
 308         INTEL_CNL_PORT_F_IDS(0),
 309         INTEL_ICL_PORT_F_IDS(0),
 310 };
 311
 312 static bool find_devid(u16 id, const u16 *p, unsigned int num)
 313 {
 314         for (; num; num--, p++) {
 315                 if (*p == id)
 316                         return true;
 317         }
 318
 319         return false;
 320 }
 321
 322 void intel_device_info_subplatform_init(struct drm_i915_private *i915)
 323 {
 324         const struct intel_device_info *info = INTEL_INFO(i915);
 325         const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
 326         const unsigned int pi = __platform_mask_index(rinfo, info->platform);
 327         const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
 328         u16 devid = INTEL_DEVID(i915);
 329         u32 mask = 0;
 330
 331         /* Make sure IS_<platform> checks are working. */
 332         RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
 333
 334         /* Find and mark subplatform bits based on the PCI device id. */
 335         if (find_devid(devid, subplatform_ult_ids,
 336                        ARRAY_SIZE(subplatform_ult_ids))) {
 337                 mask = BIT(INTEL_SUBPLATFORM_ULT);
 338         } else if (find_devid(devid, subplatform_ulx_ids,
 339                               ARRAY_SIZE(subplatform_ulx_ids))) {
 340                 mask = BIT(INTEL_SUBPLATFORM_ULX);
 341                 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
 342                         /* ULX machines are also considered ULT. */
 343                         mask |= BIT(INTEL_SUBPLATFORM_ULT);
 344                 }
 345         } else if (find_devid(devid, subplatform_portf_ids,
 346                               ARRAY_SIZE(subplatform_portf_ids))) {
 347                 mask = BIT(INTEL_SUBPLATFORM_PORTF);
 348         }
 349
 350         if (IS_TIGERLAKE(i915)) {
 351                 struct pci_dev *root, *pdev = i915->drm.pdev;
 352
 353                 root = list_first_entry(&pdev->bus->devices, typeof(*root), bus_list);
 354
 355                 drm_WARN_ON(&i915->drm, mask);
 356                 drm_WARN_ON(&i915->drm, (root->device & TGL_ROOT_DEVICE_MASK) !=
 357                             TGL_ROOT_DEVICE_ID);
 358
 359                 switch (root->device & TGL_ROOT_DEVICE_SKU_MASK) {
 360                 case TGL_ROOT_DEVICE_SKU_ULX:
 361                         mask = BIT(INTEL_SUBPLATFORM_ULX);
 362                         break;
 363                 case TGL_ROOT_DEVICE_SKU_ULT:
 364                         mask = BIT(INTEL_SUBPLATFORM_ULT);
 365                         break;
 366                 }
 367         }
 368
 369         GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_BITS);
 370
 371         RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
 372 }
 373
 374 /**
 375  * intel_device_info_runtime_init - initialize runtime info
 376  * @dev_priv: the i915 device
 377  *
 378  * Determine various intel_device_info fields at runtime.
 379  *
 380  * Use it when either:
 381  *   - it's judged too laborious to fill n static structures with the limit
 382  *     when a simple if statement does the job,
 383  *   - run-time checks (eg read fuse/strap registers) are needed.
 384  *
 385  * This function needs to be called:
 386  *   - after the MMIO has been setup as we are reading registers,
 387  *   - after the PCH has been detected,
 388  *   - before the first usage of the fields it can tweak.
 389  */
 390 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 391 {
 392         struct intel_device_info *info = mkwrite_device_info(dev_priv);
 393         struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
 394         enum pipe pipe;
 395
 396         if (INTEL_GEN(dev_priv) >= 10) {
 397                 for_each_pipe(dev_priv, pipe)
 398                         runtime->num_scalers[pipe] = 2;
 399         } else if (IS_GEN(dev_priv, 9)) {
 400                 runtime->num_scalers[PIPE_A] = 2;
 401                 runtime->num_scalers[PIPE_B] = 2;
 402                 runtime->num_scalers[PIPE_C] = 1;
 403         }
 404
 405         BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
 406
 407         if (IS_ROCKETLAKE(dev_priv))
 408                 for_each_pipe(dev_priv, pipe)
 409                         runtime->num_sprites[pipe] = 4;
 410         else if (INTEL_GEN(dev_priv) >= 11)
 411                 for_each_pipe(dev_priv, pipe)
 412                         runtime->num_sprites[pipe] = 6;
 413         else if (IS_GEN(dev_priv, 10) || IS_GEMINILAKE(dev_priv))
 414                 for_each_pipe(dev_priv, pipe)
 415                         runtime->num_sprites[pipe] = 3;
 416         else if (IS_BROXTON(dev_priv)) {
 417                 /*
 418                  * Skylake and Broxton currently don't expose the topmost plane as its
 419                  * use is exclusive with the legacy cursor and we only want to expose
 420                  * one of those, not both. Until we can safely expose the topmost plane
 421                  * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
 422                  * we don't expose the topmost plane at all to prevent ABI breakage
 423                  * down the line.
 424                  */
 425
 426                 runtime->num_sprites[PIPE_A] = 2;
 427                 runtime->num_sprites[PIPE_B] = 2;
 428                 runtime->num_sprites[PIPE_C] = 1;
 429         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 430                 for_each_pipe(dev_priv, pipe)
 431                         runtime->num_sprites[pipe] = 2;
 432         } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) {
 433                 for_each_pipe(dev_priv, pipe)
 434                         runtime->num_sprites[pipe] = 1;
 435         }
 436
 437         if (HAS_DISPLAY(dev_priv) && IS_GEN_RANGE(dev_priv, 7, 8) &&
 438             HAS_PCH_SPLIT(dev_priv)) {
 439                 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
 440                 u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP);
 441
 442                 /*
 443                  * SFUSE_STRAP is supposed to have a bit signalling the display
 444                  * is fused off. Unfortunately it seems that, at least in
 445                  * certain cases, fused off display means that PCH display
 446                  * reads don't land anywhere. In that case, we read 0s.
 447                  *
 448                  * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
 449                  * should be set when taking over after the firmware.
 450                  */
 451                 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
 452                     sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
 453                     (HAS_PCH_CPT(dev_priv) &&
 454                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
 455                         drm_info(&dev_priv->drm,
 456                                  "Display fused off, disabling\n");
 457                         info->pipe_mask = 0;
 458                         info->cpu_transcoder_mask = 0;
 459                 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
 460                         drm_info(&dev_priv->drm, "PipeC fused off\n");
 461                         info->pipe_mask &= ~BIT(PIPE_C);
 462                         info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
 463                 }
 464         } else if (HAS_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 9) {
 465                 u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
 466
 467                 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
 468                         info->pipe_mask &= ~BIT(PIPE_A);
 469                         info->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
 470                 }
 471                 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
 472                         info->pipe_mask &= ~BIT(PIPE_B);
 473                         info->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
 474                 }
 475                 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
 476                         info->pipe_mask &= ~BIT(PIPE_C);
 477                         info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
 478                 }
 479                 if (INTEL_GEN(dev_priv) >= 12 &&
 480                     (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
 481                         info->pipe_mask &= ~BIT(PIPE_D);
 482                         info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
 483                 }
 484
 485                 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
 486                         info->display.has_hdcp = 0;
 487
 488                 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
 489                         info->display.has_fbc = 0;
 490
 491                 if (INTEL_GEN(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
 492                         info->display.has_csr = 0;
 493
 494                 if (INTEL_GEN(dev_priv) >= 10 &&
 495                     (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))
 496                         info->display.has_dsc = 0;
 497         }
 498
 499         if (IS_GEN(dev_priv, 6) && intel_vtd_active()) {
 500                 drm_info(&dev_priv->drm,
 501                          "Disabling ppGTT for VT-d support\n");
 502                 info->ppgtt_type = INTEL_PPGTT_NONE;
 503         }
 504
 505         runtime->rawclk_freq = intel_read_rawclk(dev_priv);
 506         drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
 507
 508         /* Initialize command stream timestamp frequency */
 509         runtime->cs_timestamp_frequency_hz =
 510                 read_timestamp_frequency(dev_priv);
 511         if (runtime->cs_timestamp_frequency_hz) {
 512                 runtime->cs_timestamp_period_ns =
 513                         i915_cs_timestamp_ticks_to_ns(dev_priv, 1);
 514                 drm_dbg(&dev_priv->drm,
 515                         "CS timestamp wraparound in %lldms\n",
 516                         div_u64(mul_u32_u32(runtime->cs_timestamp_period_ns,
 517                                             S32_MAX),
 518                                 USEC_PER_SEC));
 519         }
 520
 521         if (!HAS_DISPLAY(dev_priv)) {
 522                 dev_priv->drm.driver_features &= ~(DRIVER_MODESET |
 523                                                    DRIVER_ATOMIC);
 524                 memset(&info->display, 0, sizeof(info->display));
 525                 memset(runtime->num_sprites, 0, sizeof(runtime->num_sprites));
 526                 memset(runtime->num_scalers, 0, sizeof(runtime->num_scalers));
 527         }
 528 }
 529
 530 void intel_driver_caps_print(const struct intel_driver_caps *caps,
 531                              struct drm_printer *p)
 532 {
 533         drm_printf(p, "Has logical contexts? %s\n",
 534                    yesno(caps->has_logical_contexts));
 535         drm_printf(p, "scheduler: %x\n", caps->scheduler);
 536 }