drivers/gpu/drm/i915/display/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <[email protected]>
  25  *
  26  */
  27
  28 #include <linux/export.h>
  29 #include <linux/i2c.h>
  30 #include <linux/notifier.h>
  31 #include <linux/slab.h>
  32 #include <linux/types.h>
  33
  34 #include <asm/byteorder.h>
  35
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_dp_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include <drm/drm_probe_helper.h>
  41
  42 #include "i915_debugfs.h"
  43 #include "i915_drv.h"
  44 #include "i915_trace.h"
  45 #include "intel_atomic.h"
  46 #include "intel_audio.h"
  47 #include "intel_connector.h"
  48 #include "intel_ddi.h"
  49 #include "intel_display_types.h"
  50 #include "intel_dp.h"
  51 #include "intel_dp_link_training.h"
  52 #include "intel_dp_mst.h"
  53 #include "intel_dpio_phy.h"
  54 #include "intel_fifo_underrun.h"
  55 #include "intel_hdcp.h"
  56 #include "intel_hdmi.h"
  57 #include "intel_hotplug.h"
  58 #include "intel_lspcon.h"
  59 #include "intel_lvds.h"
  60 #include "intel_panel.h"
  61 #include "intel_psr.h"
  62 #include "intel_sideband.h"
  63 #include "intel_tc.h"
  64 #include "intel_vdsc.h"
  65
  66 #define DP_DPRX_ESI_LEN 14
  67
  68 /* DP DSC throughput values used for slice count calculations KPixels/s */
  69 #define DP_DSC_PEAK_PIXEL_RATE                  2720000
  70 #define DP_DSC_MAX_ENC_THROUGHPUT_0             340000
  71 #define DP_DSC_MAX_ENC_THROUGHPUT_1             400000
  72
  73 /* DP DSC FEC Overhead factor = 1/(0.972261) */
  74 #define DP_DSC_FEC_OVERHEAD_FACTOR              972261
  75
  76 /* Compliance test status bits  */
  77 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  78 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  79 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  80 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  81
  82 struct dp_link_dpll {
  83         int clock;
  84         struct dpll dpll;
  85 };
  86
  87 static const struct dp_link_dpll g4x_dpll[] = {
  88         { 162000,
  89                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  90         { 270000,
  91                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  92 };
  93
  94 static const struct dp_link_dpll pch_dpll[] = {
  95         { 162000,
  96                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  97         { 270000,
  98                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  99 };
 100
 101 static const struct dp_link_dpll vlv_dpll[] = {
 102         { 162000,
 103                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
 104         { 270000,
 105                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
 106 };
 107
 108 /*
 109  * CHV supports eDP 1.4 that have  more link rates.
 110  * Below only provides the fixed rate but exclude variable rate.
 111  */
 112 static const struct dp_link_dpll chv_dpll[] = {
 113         /*
 114          * CHV requires to program fractional division for m2.
 115          * m2 is stored in fixed point format using formula below
 116          * (m2_int << 22) | m2_fraction
 117          */
 118         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
 119                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
 120         { 270000,       /* m2_int = 27, m2_fraction = 0 */
 121                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
 122 };
 123
 124 /* Constants for DP DSC configurations */
 125 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};
 126
 127 /* With Single pipe configuration, HW is capable of supporting maximum
 128  * of 4 slices per line.
 129  */
 130 static const u8 valid_dsc_slicecount[] = {1, 2, 4};
 131
 132 /**
 133  * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 134  * @intel_dp: DP struct
 135  *
 136  * If a CPU or PCH DP output is attached to an eDP panel, this function
 137  * will return true, and false otherwise.
 138  */
 139 bool intel_dp_is_edp(struct intel_dp *intel_dp)
 140 {
 141         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 142
 143         return dig_port->base.type == INTEL_OUTPUT_EDP;
 144 }
 145
 146 static void intel_dp_link_down(struct intel_encoder *encoder,
 147                                const struct intel_crtc_state *old_crtc_state);
 148 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 149 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 150 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
 151                                            const struct intel_crtc_state *crtc_state);
 152 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
 153                                       enum pipe pipe);
 154 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 155
 156 /* update sink rates from dpcd */
 157 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 158 {
 159         static const int dp_rates[] = {
 160                 162000, 270000, 540000, 810000
 161         };
 162         int i, max_rate;
 163         int max_lttpr_rate;
 164
 165         if (drm_dp_has_quirk(&intel_dp->desc, 0,
 166                              DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) {
 167                 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */
 168                 static const int quirk_rates[] = { 162000, 270000, 324000 };
 169
 170                 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates));
 171                 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates);
 172
 173                 return;
 174         }
 175
 176         max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 177         max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps);
 178         if (max_lttpr_rate)
 179                 max_rate = min(max_rate, max_lttpr_rate);
 180
 181         for (i = 0; i < ARRAY_SIZE(dp_rates); i++) {
 182                 if (dp_rates[i] > max_rate)
 183                         break;
 184                 intel_dp->sink_rates[i] = dp_rates[i];
 185         }
 186
 187         intel_dp->num_sink_rates = i;
 188 }
 189
 190 /* Get length of rates array potentially limited by max_rate. */
 191 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate)
 192 {
 193         int i;
 194
 195         /* Limit results by potentially reduced max rate */
 196         for (i = 0; i < len; i++) {
 197                 if (rates[len - i - 1] <= max_rate)
 198                         return len - i;
 199         }
 200
 201         return 0;
 202 }
 203
 204 /* Get length of common rates array potentially limited by max_rate. */
 205 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp,
 206                                           int max_rate)
 207 {
 208         return intel_dp_rate_limit_len(intel_dp->common_rates,
 209                                        intel_dp->num_common_rates, max_rate);
 210 }
 211
 212 /* Theoretical max between source and sink */
 213 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 214 {
 215         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 216 }
 217
 218 /* Theoretical max between source and sink */
 219 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 220 {
 221         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 222         int source_max = dig_port->max_lanes;
 223         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 224         int fia_max = intel_tc_port_fia_max_lane_count(dig_port);
 225         int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps);
 226
 227         if (lttpr_max)
 228                 sink_max = min(sink_max, lttpr_max);
 229
 230         return min3(source_max, sink_max, fia_max);
 231 }
 232
 233 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 234 {
 235         return intel_dp->max_link_lane_count;
 236 }
 237
 238 int
 239 intel_dp_link_required(int pixel_clock, int bpp)
 240 {
 241         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 242         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 243 }
 244
 245 int
 246 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 247 {
 248         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 249          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 250          * is transmitted every LS_Clk per lane, there is no need to account for
 251          * the channel encoding that is done in the PHY layer here.
 252          */
 253
 254         return max_link_clock * max_lanes;
 255 }
 256
 257 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp)
 258 {
 259         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 260         struct intel_encoder *encoder = &intel_dig_port->base;
 261         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 262
 263         return INTEL_GEN(dev_priv) >= 12 ||
 264                 (INTEL_GEN(dev_priv) == 11 &&
 265                  encoder->port != PORT_A);
 266 }
 267
 268 static int cnl_max_source_rate(struct intel_dp *intel_dp)
 269 {
 270         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 271         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 272         enum port port = dig_port->base.port;
 273
 274         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 275
 276         /* Low voltage SKUs are limited to max of 5.4G */
 277         if (voltage == VOLTAGE_INFO_0_85V)
 278                 return 540000;
 279
 280         /* For this SKU 8.1G is supported in all ports */
 281         if (IS_CNL_WITH_PORT_F(dev_priv))
 282                 return 810000;
 283
 284         /* For other SKUs, max rate on ports A and D is 5.4G */
 285         if (port == PORT_A || port == PORT_D)
 286                 return 540000;
 287
 288         return 810000;
 289 }
 290
 291 static int icl_max_source_rate(struct intel_dp *intel_dp)
 292 {
 293         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 294         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 295         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
 296
 297         if (intel_phy_is_combo(dev_priv, phy) &&
 298             !intel_dp_is_edp(intel_dp))
 299                 return 540000;
 300
 301         return 810000;
 302 }
 303
 304 static int ehl_max_source_rate(struct intel_dp *intel_dp)
 305 {
 306         if (intel_dp_is_edp(intel_dp))
 307                 return 540000;
 308
 309         return 810000;
 310 }
 311
 312 static void
 313 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 314 {
 315         /* The values must be in increasing order */
 316         static const int cnl_rates[] = {
 317                 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000
 318         };
 319         static const int bxt_rates[] = {
 320                 162000, 216000, 243000, 270000, 324000, 432000, 540000
 321         };
 322         static const int skl_rates[] = {
 323                 162000, 216000, 270000, 324000, 432000, 540000
 324         };
 325         static const int hsw_rates[] = {
 326                 162000, 270000, 540000
 327         };
 328         static const int g4x_rates[] = {
 329                 162000, 270000
 330         };
 331         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 332         struct intel_encoder *encoder = &dig_port->base;
 333         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 334         const int *source_rates;
 335         int size, max_rate = 0, vbt_max_rate;
 336
 337         /* This should only be done once */
 338         drm_WARN_ON(&dev_priv->drm,
 339                     intel_dp->source_rates || intel_dp->num_source_rates);
 340
 341         if (INTEL_GEN(dev_priv) >= 10) {
 342                 source_rates = cnl_rates;
 343                 size = ARRAY_SIZE(cnl_rates);
 344                 if (IS_GEN(dev_priv, 10))
 345                         max_rate = cnl_max_source_rate(intel_dp);
 346                 else if (IS_JSL_EHL(dev_priv))
 347                         max_rate = ehl_max_source_rate(intel_dp);
 348                 else
 349                         max_rate = icl_max_source_rate(intel_dp);
 350         } else if (IS_GEN9_LP(dev_priv)) {
 351                 source_rates = bxt_rates;
 352                 size = ARRAY_SIZE(bxt_rates);
 353         } else if (IS_GEN9_BC(dev_priv)) {
 354                 source_rates = skl_rates;
 355                 size = ARRAY_SIZE(skl_rates);
 356         } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
 357                    IS_BROADWELL(dev_priv)) {
 358                 source_rates = hsw_rates;
 359                 size = ARRAY_SIZE(hsw_rates);
 360         } else {
 361                 source_rates = g4x_rates;
 362                 size = ARRAY_SIZE(g4x_rates);
 363         }
 364
 365         vbt_max_rate = intel_bios_dp_max_link_rate(encoder);
 366         if (max_rate && vbt_max_rate)
 367                 max_rate = min(max_rate, vbt_max_rate);
 368         else if (vbt_max_rate)
 369                 max_rate = vbt_max_rate;
 370
 371         if (max_rate)
 372                 size = intel_dp_rate_limit_len(source_rates, size, max_rate);
 373
 374         intel_dp->source_rates = source_rates;
 375         intel_dp->num_source_rates = size;
 376 }
 377
 378 static int intersect_rates(const int *source_rates, int source_len,
 379                            const int *sink_rates, int sink_len,
 380                            int *common_rates)
 381 {
 382         int i = 0, j = 0, k = 0;
 383
 384         while (i < source_len && j < sink_len) {
 385                 if (source_rates[i] == sink_rates[j]) {
 386                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 387                                 return k;
 388                         common_rates[k] = source_rates[i];
 389                         ++k;
 390                         ++i;
 391                         ++j;
 392                 } else if (source_rates[i] < sink_rates[j]) {
 393                         ++i;
 394                 } else {
 395                         ++j;
 396                 }
 397         }
 398         return k;
 399 }
 400
 401 /* return index of rate in rates array, or -1 if not found */
 402 static int intel_dp_rate_index(const int *rates, int len, int rate)
 403 {
 404         int i;
 405
 406         for (i = 0; i < len; i++)
 407                 if (rate == rates[i])
 408                         return i;
 409
 410         return -1;
 411 }
 412
 413 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 414 {
 415         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 416
 417         drm_WARN_ON(&i915->drm,
 418                     !intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 419
 420         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 421                                                      intel_dp->num_source_rates,
 422                                                      intel_dp->sink_rates,
 423                                                      intel_dp->num_sink_rates,
 424                                                      intel_dp->common_rates);
 425
 426         /* Paranoia, there should always be something in common. */
 427         if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) {
 428                 intel_dp->common_rates[0] = 162000;
 429                 intel_dp->num_common_rates = 1;
 430         }
 431 }
 432
 433 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
 434                                        u8 lane_count)
 435 {
 436         /*
 437          * FIXME: we need to synchronize the current link parameters with
 438          * hardware readout. Currently fast link training doesn't work on
 439          * boot-up.
 440          */
 441         if (link_rate == 0 ||
 442             link_rate > intel_dp->max_link_rate)
 443                 return false;
 444
 445         if (lane_count == 0 ||
 446             lane_count > intel_dp_max_lane_count(intel_dp))
 447                 return false;
 448
 449         return true;
 450 }
 451
 452 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp,
 453                                                      int link_rate,
 454                                                      u8 lane_count)
 455 {
 456         const struct drm_display_mode *fixed_mode =
 457                 intel_dp->attached_connector->panel.fixed_mode;
 458         int mode_rate, max_rate;
 459
 460         mode_rate = intel_dp_link_required(fixed_mode->clock, 18);
 461         max_rate = intel_dp_max_data_rate(link_rate, lane_count);
 462         if (mode_rate > max_rate)
 463                 return false;
 464
 465         return true;
 466 }
 467
 468 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 469                                             int link_rate, u8 lane_count)
 470 {
 471         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 472         int index;
 473
 474         /*
 475          * TODO: Enable fallback on MST links once MST link compute can handle
 476          * the fallback params.
 477          */
 478         if (intel_dp->is_mst) {
 479                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 480                 return -1;
 481         }
 482
 483         index = intel_dp_rate_index(intel_dp->common_rates,
 484                                     intel_dp->num_common_rates,
 485                                     link_rate);
 486         if (index > 0) {
 487                 if (intel_dp_is_edp(intel_dp) &&
 488                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 489                                                               intel_dp->common_rates[index - 1],
 490                                                               lane_count)) {
 491                         drm_dbg_kms(&i915->drm,
 492                                     "Retrying Link training for eDP with same parameters\n");
 493                         return 0;
 494                 }
 495                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 496                 intel_dp->max_link_lane_count = lane_count;
 497         } else if (lane_count > 1) {
 498                 if (intel_dp_is_edp(intel_dp) &&
 499                     !intel_dp_can_link_train_fallback_for_edp(intel_dp,
 500                                                               intel_dp_max_common_rate(intel_dp),
 501                                                               lane_count >> 1)) {
 502                         drm_dbg_kms(&i915->drm,
 503                                     "Retrying Link training for eDP with same parameters\n");
 504                         return 0;
 505                 }
 506                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 507                 intel_dp->max_link_lane_count = lane_count >> 1;
 508         } else {
 509                 drm_err(&i915->drm, "Link Training Unsuccessful\n");
 510                 return -1;
 511         }
 512
 513         return 0;
 514 }
 515
 516 u32 intel_dp_mode_to_fec_clock(u32 mode_clock)
 517 {
 518         return div_u64(mul_u32_u32(mode_clock, 1000000U),
 519                        DP_DSC_FEC_OVERHEAD_FACTOR);
 520 }
 521
 522 static int
 523 small_joiner_ram_size_bits(struct drm_i915_private *i915)
 524 {
 525         if (INTEL_GEN(i915) >= 11)
 526                 return 7680 * 8;
 527         else
 528                 return 6144 * 8;
 529 }
 530
 531 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915,
 532                                        u32 link_clock, u32 lane_count,
 533                                        u32 mode_clock, u32 mode_hdisplay,
 534                                        bool bigjoiner)
 535 {
 536         u32 bits_per_pixel, max_bpp_small_joiner_ram;
 537         int i;
 538
 539         /*
 540          * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)*
 541          * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP)
 542          * for SST -> TimeSlotsPerMTP is 1,
 543          * for MST -> TimeSlotsPerMTP has to be calculated
 544          */
 545         bits_per_pixel = (link_clock * lane_count * 8) /
 546                          intel_dp_mode_to_fec_clock(mode_clock);
 547         drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel);
 548
 549         /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */
 550         max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) /
 551                 mode_hdisplay;
 552
 553         if (bigjoiner)
 554                 max_bpp_small_joiner_ram *= 2;
 555
 556         drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n",
 557                     max_bpp_small_joiner_ram);
 558
 559         /*
 560          * Greatest allowed DSC BPP = MIN (output BPP from available Link BW
 561          * check, output bpp from small joiner RAM check)
 562          */
 563         bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram);
 564
 565         if (bigjoiner) {
 566                 u32 max_bpp_bigjoiner =
 567                         i915->max_cdclk_freq * 48 /
 568                         intel_dp_mode_to_fec_clock(mode_clock);
 569
 570                 DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner);
 571                 bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner);
 572         }
 573
 574         /* Error out if the max bpp is less than smallest allowed valid bpp */
 575         if (bits_per_pixel < valid_dsc_bpp[0]) {
 576                 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n",
 577                             bits_per_pixel, valid_dsc_bpp[0]);
 578                 return 0;
 579         }
 580
 581         /* Find the nearest match in the array of known BPPs from VESA */
 582         for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {
 583                 if (bits_per_pixel < valid_dsc_bpp[i + 1])
 584                         break;
 585         }
 586         bits_per_pixel = valid_dsc_bpp[i];
 587
 588         /*
 589          * Compressed BPP in U6.4 format so multiply by 16, for Gen 11,
 590          * fractional part is 0
 591          */
 592         return bits_per_pixel << 4;
 593 }
 594
 595 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp,
 596                                        int mode_clock, int mode_hdisplay,
 597                                        bool bigjoiner)
 598 {
 599         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
 600         u8 min_slice_count, i;
 601         int max_slice_width;
 602
 603         if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE)
 604                 min_slice_count = DIV_ROUND_UP(mode_clock,
 605                                                DP_DSC_MAX_ENC_THROUGHPUT_0);
 606         else
 607                 min_slice_count = DIV_ROUND_UP(mode_clock,
 608                                                DP_DSC_MAX_ENC_THROUGHPUT_1);
 609
 610         max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd);
 611         if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {
 612                 drm_dbg_kms(&i915->drm,
 613                             "Unsupported slice width %d by DP DSC Sink device\n",
 614                             max_slice_width);
 615                 return 0;
 616         }
 617         /* Also take into account max slice width */
 618         min_slice_count = max_t(u8, min_slice_count,
 619                                 DIV_ROUND_UP(mode_hdisplay,
 620                                              max_slice_width));
 621
 622         /* Find the closest match to the valid slice count values */
 623         for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {
 624                 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner;
 625
 626                 if (test_slice_count >
 627                     drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false))
 628                         break;
 629
 630                 /* big joiner needs small joiner to be enabled */
 631                 if (bigjoiner && test_slice_count < 4)
 632                         continue;
 633
 634                 if (min_slice_count <= test_slice_count)
 635                         return test_slice_count;
 636         }
 637
 638         drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n",
 639                     min_slice_count);
 640         return 0;
 641 }
 642
 643 static enum intel_output_format
 644 intel_dp_output_format(struct drm_connector *connector,
 645                        const struct drm_display_mode *mode)
 646 {
 647         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
 648         const struct drm_display_info *info = &connector->display_info;
 649
 650         if (!connector->ycbcr_420_allowed ||
 651             !drm_mode_is_420_only(info, mode))
 652                 return INTEL_OUTPUT_FORMAT_RGB;
 653
 654         if (intel_dp->dfp.ycbcr_444_to_420)
 655                 return INTEL_OUTPUT_FORMAT_YCBCR444;
 656         else
 657                 return INTEL_OUTPUT_FORMAT_YCBCR420;
 658 }
 659
 660 int intel_dp_min_bpp(enum intel_output_format output_format)
 661 {
 662         if (output_format == INTEL_OUTPUT_FORMAT_RGB)
 663                 return 6 * 3;
 664         else
 665                 return 8 * 3;
 666 }
 667
 668 static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp)
 669 {
 670         /*
 671          * bpp value was assumed to RGB format. And YCbCr 4:2:0 output
 672          * format of the number of bytes per pixel will be half the number
 673          * of bytes of RGB pixel.
 674          */
 675         if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 676                 bpp /= 2;
 677
 678         return bpp;
 679 }
 680
 681 static int
 682 intel_dp_mode_min_output_bpp(struct drm_connector *connector,
 683                              const struct drm_display_mode *mode)
 684 {
 685         enum intel_output_format output_format =
 686                 intel_dp_output_format(connector, mode);
 687
 688         return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));
 689 }
 690
 691 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv,
 692                                   int hdisplay)
 693 {
 694         /*
 695          * Older platforms don't like hdisplay==4096 with DP.
 696          *
 697          * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline
 698          * and frame counter increment), but we don't get vblank interrupts,
 699          * and the pipe underruns immediately. The link also doesn't seem
 700          * to get trained properly.
 701          *
 702          * On CHV the vblank interrupts don't seem to disappear but
 703          * otherwise the symptoms are similar.
 704          *
 705          * TODO: confirm the behaviour on HSW+
 706          */
 707         return hdisplay == 4096 && !HAS_DDI(dev_priv);
 708 }
 709
 710 static enum drm_mode_status
 711 intel_dp_mode_valid_downstream(struct intel_connector *connector,
 712                                const struct drm_display_mode *mode,
 713                                int target_clock)
 714 {
 715         struct intel_dp *intel_dp = intel_attached_dp(connector);
 716         const struct drm_display_info *info = &connector->base.display_info;
 717         int tmds_clock;
 718
 719         if (intel_dp->dfp.max_dotclock &&
 720             target_clock > intel_dp->dfp.max_dotclock)
 721                 return MODE_CLOCK_HIGH;
 722
 723         /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */
 724         tmds_clock = target_clock;
 725         if (drm_mode_is_420_only(info, mode))
 726                 tmds_clock /= 2;
 727
 728         if (intel_dp->dfp.min_tmds_clock &&
 729             tmds_clock < intel_dp->dfp.min_tmds_clock)
 730                 return MODE_CLOCK_LOW;
 731         if (intel_dp->dfp.max_tmds_clock &&
 732             tmds_clock > intel_dp->dfp.max_tmds_clock)
 733                 return MODE_CLOCK_HIGH;
 734
 735         return MODE_OK;
 736 }
 737
 738 static enum drm_mode_status
 739 intel_dp_mode_valid(struct drm_connector *connector,
 740                     struct drm_display_mode *mode)
 741 {
 742         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
 743         struct intel_connector *intel_connector = to_intel_connector(connector);
 744         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 745         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 746         int target_clock = mode->clock;
 747         int max_rate, mode_rate, max_lanes, max_link_clock;
 748         int max_dotclk = dev_priv->max_dotclk_freq;
 749         u16 dsc_max_output_bpp = 0;
 750         u8 dsc_slice_count = 0;
 751         enum drm_mode_status status;
 752         bool dsc = false, bigjoiner = false;
 753
 754         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
 755                 return MODE_NO_DBLESCAN;
 756
 757         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 758                 return MODE_H_ILLEGAL;
 759
 760         if (intel_dp_is_edp(intel_dp) && fixed_mode) {
 761                 if (mode->hdisplay > fixed_mode->hdisplay)
 762                         return MODE_PANEL;
 763
 764                 if (mode->vdisplay > fixed_mode->vdisplay)
 765                         return MODE_PANEL;
 766
 767                 target_clock = fixed_mode->clock;
 768         }
 769
 770         if (mode->clock < 10000)
 771                 return MODE_CLOCK_LOW;
 772
 773         if ((target_clock > max_dotclk || mode->hdisplay > 5120) &&
 774             intel_dp_can_bigjoiner(intel_dp)) {
 775                 bigjoiner = true;
 776                 max_dotclk *= 2;
 777         }
 778         if (target_clock > max_dotclk)
 779                 return MODE_CLOCK_HIGH;
 780
 781         max_link_clock = intel_dp_max_link_rate(intel_dp);
 782         max_lanes = intel_dp_max_lane_count(intel_dp);
 783
 784         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 785         mode_rate = intel_dp_link_required(target_clock,
 786                                            intel_dp_mode_min_output_bpp(connector, mode));
 787
 788         if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay))
 789                 return MODE_H_ILLEGAL;
 790
 791         /*
 792          * Output bpp is stored in 6.4 format so right shift by 4 to get the
 793          * integer value since we support only integer values of bpp.
 794          */
 795         if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) &&
 796             drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
 797                 if (intel_dp_is_edp(intel_dp)) {
 798                         dsc_max_output_bpp =
 799                                 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4;
 800                         dsc_slice_count =
 801                                 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
 802                                                                 true);
 803                 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) {
 804                         dsc_max_output_bpp =
 805                                 intel_dp_dsc_get_output_bpp(dev_priv,
 806                                                             max_link_clock,
 807                                                             max_lanes,
 808                                                             target_clock,
 809                                                             mode->hdisplay,
 810                                                             bigjoiner) >> 4;
 811                         dsc_slice_count =
 812                                 intel_dp_dsc_get_slice_count(intel_dp,
 813                                                              target_clock,
 814                                                              mode->hdisplay,
 815                                                              bigjoiner);
 816                 }
 817
 818                 dsc = dsc_max_output_bpp && dsc_slice_count;
 819         }
 820
 821         /* big joiner configuration needs DSC */
 822         if (bigjoiner && !dsc)
 823                 return MODE_CLOCK_HIGH;
 824
 825         if (mode_rate > max_rate && !dsc)
 826                 return MODE_CLOCK_HIGH;
 827
 828         status = intel_dp_mode_valid_downstream(intel_connector,
 829                                                 mode, target_clock);
 830         if (status != MODE_OK)
 831                 return status;
 832
 833         return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
 834 }
 835
 836 u32 intel_dp_pack_aux(const u8 *src, int src_bytes)
 837 {
 838         int i;
 839         u32 v = 0;
 840
 841         if (src_bytes > 4)
 842                 src_bytes = 4;
 843         for (i = 0; i < src_bytes; i++)
 844                 v |= ((u32)src[i]) << ((3 - i) * 8);
 845         return v;
 846 }
 847
 848 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes)
 849 {
 850         int i;
 851         if (dst_bytes > 4)
 852                 dst_bytes = 4;
 853         for (i = 0; i < dst_bytes; i++)
 854                 dst[i] = src >> ((3-i) * 8);
 855 }
 856
 857 static void
 858 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp);
 859 static void
 860 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
 861                                               bool force_disable_vdd);
 862 static void
 863 intel_dp_pps_init(struct intel_dp *intel_dp);
 864
 865 static intel_wakeref_t
 866 pps_lock(struct intel_dp *intel_dp)
 867 {
 868         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 869         intel_wakeref_t wakeref;
 870
 871         /*
 872          * See intel_power_sequencer_reset() why we need
 873          * a power domain reference here.
 874          */
 875         wakeref = intel_display_power_get(dev_priv,
 876                                           intel_aux_power_domain(dp_to_dig_port(intel_dp)));
 877
 878         mutex_lock(&dev_priv->pps_mutex);
 879
 880         return wakeref;
 881 }
 882
 883 static intel_wakeref_t
 884 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref)
 885 {
 886         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 887
 888         mutex_unlock(&dev_priv->pps_mutex);
 889         intel_display_power_put(dev_priv,
 890                                 intel_aux_power_domain(dp_to_dig_port(intel_dp)),
 891                                 wakeref);
 892         return 0;
 893 }
 894
 895 #define with_pps_lock(dp, wf) \
 896         for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf)))
 897
 898 static void
 899 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 900 {
 901         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
 902         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 903         enum pipe pipe = intel_dp->pps_pipe;
 904         bool pll_enabled, release_cl_override = false;
 905         enum dpio_phy phy = DPIO_PHY(pipe);
 906         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 907         u32 DP;
 908
 909         if (drm_WARN(&dev_priv->drm,
 910                      intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN,
 911                      "skipping pipe %c power sequencer kick due to [ENCODER:%d:%s] being active\n",
 912                      pipe_name(pipe), dig_port->base.base.base.id,
 913                      dig_port->base.base.name))
 914                 return;
 915
 916         drm_dbg_kms(&dev_priv->drm,
 917                     "kicking pipe %c power sequencer for [ENCODER:%d:%s]\n",
 918                     pipe_name(pipe), dig_port->base.base.base.id,
 919                     dig_port->base.base.name);
 920
 921         /* Preserve the BIOS-computed detected bit. This is
 922          * supposed to be read-only.
 923          */
 924         DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
 925         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 926         DP |= DP_PORT_WIDTH(1);
 927         DP |= DP_LINK_TRAIN_PAT_1;
 928
 929         if (IS_CHERRYVIEW(dev_priv))
 930                 DP |= DP_PIPE_SEL_CHV(pipe);
 931         else
 932                 DP |= DP_PIPE_SEL(pipe);
 933
 934         pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE;
 935
 936         /*
 937          * The DPLL for the pipe must be enabled for this to work.
 938          * So enable temporarily it if it's not already enabled.
 939          */
 940         if (!pll_enabled) {
 941                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 942                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 943
 944                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 945                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 946                         drm_err(&dev_priv->drm,
 947                                 "Failed to force on pll for pipe %c!\n",
 948                                 pipe_name(pipe));
 949                         return;
 950                 }
 951         }
 952
 953         /*
 954          * Similar magic as in intel_dp_enable_port().
 955          * We _must_ do this port enable + disable trick
 956          * to make this power sequencer lock onto the port.
 957          * Otherwise even VDD force bit won't work.
 958          */
 959         intel_de_write(dev_priv, intel_dp->output_reg, DP);
 960         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 961
 962         intel_de_write(dev_priv, intel_dp->output_reg, DP | DP_PORT_EN);
 963         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 964
 965         intel_de_write(dev_priv, intel_dp->output_reg, DP & ~DP_PORT_EN);
 966         intel_de_posting_read(dev_priv, intel_dp->output_reg);
 967
 968         if (!pll_enabled) {
 969                 vlv_force_pll_off(dev_priv, pipe);
 970
 971                 if (release_cl_override)
 972                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 973         }
 974 }
 975
 976 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 977 {
 978         struct intel_encoder *encoder;
 979         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 980
 981         /*
 982          * We don't have power sequencer currently.
 983          * Pick one that's not used by other ports.
 984          */
 985         for_each_intel_dp(&dev_priv->drm, encoder) {
 986                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 987
 988                 if (encoder->type == INTEL_OUTPUT_EDP) {
 989                         drm_WARN_ON(&dev_priv->drm,
 990                                     intel_dp->active_pipe != INVALID_PIPE &&
 991                                     intel_dp->active_pipe !=
 992                                     intel_dp->pps_pipe);
 993
 994                         if (intel_dp->pps_pipe != INVALID_PIPE)
 995                                 pipes &= ~(1 << intel_dp->pps_pipe);
 996                 } else {
 997                         drm_WARN_ON(&dev_priv->drm,
 998                                     intel_dp->pps_pipe != INVALID_PIPE);
 999
1000                         if (intel_dp->active_pipe != INVALID_PIPE)
1001                                 pipes &= ~(1 << intel_dp->active_pipe);
1002                 }
1003         }
1004
1005         if (pipes == 0)
1006                 return INVALID_PIPE;
1007
1008         return ffs(pipes) - 1;
1009 }
1010
1011 static enum pipe
1012 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
1013 {
1014         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1015         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1016         enum pipe pipe;
1017
1018         lockdep_assert_held(&dev_priv->pps_mutex);
1019
1020         /* We should never land here with regular DP ports */
1021         drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
1022
1023         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE &&
1024                     intel_dp->active_pipe != intel_dp->pps_pipe);
1025
1026         if (intel_dp->pps_pipe != INVALID_PIPE)
1027                 return intel_dp->pps_pipe;
1028
1029         pipe = vlv_find_free_pps(dev_priv);
1030
1031         /*
1032          * Didn't find one. This should not happen since there
1033          * are two power sequencers and up to two eDP ports.
1034          */
1035         if (drm_WARN_ON(&dev_priv->drm, pipe == INVALID_PIPE))
1036                 pipe = PIPE_A;
1037
1038         vlv_steal_power_sequencer(dev_priv, pipe);
1039         intel_dp->pps_pipe = pipe;
1040
1041         drm_dbg_kms(&dev_priv->drm,
1042                     "picked pipe %c power sequencer for [ENCODER:%d:%s]\n",
1043                     pipe_name(intel_dp->pps_pipe),
1044                     dig_port->base.base.base.id,
1045                     dig_port->base.base.name);
1046
1047         /* init power sequencer on this pipe and port */
1048         intel_dp_init_panel_power_sequencer(intel_dp);
1049         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
1050
1051         /*
1052          * Even vdd force doesn't work until we've made
1053          * the power sequencer lock in on the port.
1054          */
1055         vlv_power_sequencer_kick(intel_dp);
1056
1057         return intel_dp->pps_pipe;
1058 }
1059
1060 static int
1061 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
1062 {
1063         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1064         int backlight_controller = dev_priv->vbt.backlight.controller;
1065
1066         lockdep_assert_held(&dev_priv->pps_mutex);
1067
1068         /* We should never land here with regular DP ports */
1069         drm_WARN_ON(&dev_priv->drm, !intel_dp_is_edp(intel_dp));
1070
1071         if (!intel_dp->pps_reset)
1072                 return backlight_controller;
1073
1074         intel_dp->pps_reset = false;
1075
1076         /*
1077          * Only the HW needs to be reprogrammed, the SW state is fixed and
1078          * has been setup during connector init.
1079          */
1080         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
1081
1082         return backlight_controller;
1083 }
1084
1085 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
1086                                enum pipe pipe);
1087
1088 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
1089                                enum pipe pipe)
1090 {
1091         return intel_de_read(dev_priv, PP_STATUS(pipe)) & PP_ON;
1092 }
1093
1094 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
1095                                 enum pipe pipe)
1096 {
1097         return intel_de_read(dev_priv, PP_CONTROL(pipe)) & EDP_FORCE_VDD;
1098 }
1099
1100 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
1101                          enum pipe pipe)
1102 {
1103         return true;
1104 }
1105
1106 static enum pipe
1107 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
1108                      enum port port,
1109                      vlv_pipe_check pipe_check)
1110 {
1111         enum pipe pipe;
1112
1113         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
1114                 u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) &
1115                         PANEL_PORT_SELECT_MASK;
1116
1117                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
1118                         continue;
1119
1120                 if (!pipe_check(dev_priv, pipe))
1121                         continue;
1122
1123                 return pipe;
1124         }
1125
1126         return INVALID_PIPE;
1127 }
1128
1129 static void
1130 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
1131 {
1132         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1133         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1134         enum port port = dig_port->base.port;
1135
1136         lockdep_assert_held(&dev_priv->pps_mutex);
1137
1138         /* try to find a pipe with this port selected */
1139         /* first pick one where the panel is on */
1140         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1141                                                   vlv_pipe_has_pp_on);
1142         /* didn't find one? pick one where vdd is on */
1143         if (intel_dp->pps_pipe == INVALID_PIPE)
1144                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1145                                                           vlv_pipe_has_vdd_on);
1146         /* didn't find one? pick one with just the correct port */
1147         if (intel_dp->pps_pipe == INVALID_PIPE)
1148                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
1149                                                           vlv_pipe_any);
1150
1151         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
1152         if (intel_dp->pps_pipe == INVALID_PIPE) {
1153                 drm_dbg_kms(&dev_priv->drm,
1154                             "no initial power sequencer for [ENCODER:%d:%s]\n",
1155                             dig_port->base.base.base.id,
1156                             dig_port->base.base.name);
1157                 return;
1158         }
1159
1160         drm_dbg_kms(&dev_priv->drm,
1161                     "initial power sequencer for [ENCODER:%d:%s]: pipe %c\n",
1162                     dig_port->base.base.base.id,
1163                     dig_port->base.base.name,
1164                     pipe_name(intel_dp->pps_pipe));
1165
1166         intel_dp_init_panel_power_sequencer(intel_dp);
1167         intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
1168 }
1169
1170 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
1171 {
1172         struct intel_encoder *encoder;
1173
1174         if (drm_WARN_ON(&dev_priv->drm,
1175                         !(IS_VALLEYVIEW(dev_priv) ||
1176                           IS_CHERRYVIEW(dev_priv) ||
1177                           IS_GEN9_LP(dev_priv))))
1178                 return;
1179
1180         /*
1181          * We can't grab pps_mutex here due to deadlock with power_domain
1182          * mutex when power_domain functions are called while holding pps_mutex.
1183          * That also means that in order to use pps_pipe the code needs to
1184          * hold both a power domain reference and pps_mutex, and the power domain
1185          * reference get/put must be done while _not_ holding pps_mutex.
1186          * pps_{lock,unlock}() do these steps in the correct order, so one
1187          * should use them always.
1188          */
1189
1190         for_each_intel_dp(&dev_priv->drm, encoder) {
1191                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1192
1193                 drm_WARN_ON(&dev_priv->drm,
1194                             intel_dp->active_pipe != INVALID_PIPE);
1195
1196                 if (encoder->type != INTEL_OUTPUT_EDP)
1197                         continue;
1198
1199                 if (IS_GEN9_LP(dev_priv))
1200                         intel_dp->pps_reset = true;
1201                 else
1202                         intel_dp->pps_pipe = INVALID_PIPE;
1203         }
1204 }
1205
1206 struct pps_registers {
1207         i915_reg_t pp_ctrl;
1208         i915_reg_t pp_stat;
1209         i915_reg_t pp_on;
1210         i915_reg_t pp_off;
1211         i915_reg_t pp_div;
1212 };
1213
1214 static void intel_pps_get_registers(struct intel_dp *intel_dp,
1215                                     struct pps_registers *regs)
1216 {
1217         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1218         int pps_idx = 0;
1219
1220         memset(regs, 0, sizeof(*regs));
1221
1222         if (IS_GEN9_LP(dev_priv))
1223                 pps_idx = bxt_power_sequencer_idx(intel_dp);
1224         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1225                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
1226
1227         regs->pp_ctrl = PP_CONTROL(pps_idx);
1228         regs->pp_stat = PP_STATUS(pps_idx);
1229         regs->pp_on = PP_ON_DELAYS(pps_idx);
1230         regs->pp_off = PP_OFF_DELAYS(pps_idx);
1231
1232         /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */
1233         if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
1234                 regs->pp_div = INVALID_MMIO_REG;
1235         else
1236                 regs->pp_div = PP_DIVISOR(pps_idx);
1237 }
1238
1239 static i915_reg_t
1240 _pp_ctrl_reg(struct intel_dp *intel_dp)
1241 {
1242         struct pps_registers regs;
1243
1244         intel_pps_get_registers(intel_dp, &regs);
1245
1246         return regs.pp_ctrl;
1247 }
1248
1249 static i915_reg_t
1250 _pp_stat_reg(struct intel_dp *intel_dp)
1251 {
1252         struct pps_registers regs;
1253
1254         intel_pps_get_registers(intel_dp, &regs);
1255
1256         return regs.pp_stat;
1257 }
1258
1259 static bool edp_have_panel_power(struct intel_dp *intel_dp)
1260 {
1261         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1262
1263         lockdep_assert_held(&dev_priv->pps_mutex);
1264
1265         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1266             intel_dp->pps_pipe == INVALID_PIPE)
1267                 return false;
1268
1269         return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0;
1270 }
1271
1272 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
1273 {
1274         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1275
1276         lockdep_assert_held(&dev_priv->pps_mutex);
1277
1278         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
1279             intel_dp->pps_pipe == INVALID_PIPE)
1280                 return false;
1281
1282         return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
1283 }
1284
1285 static void
1286 intel_dp_check_edp(struct intel_dp *intel_dp)
1287 {
1288         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1289
1290         if (!intel_dp_is_edp(intel_dp))
1291                 return;
1292
1293         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
1294                 drm_WARN(&dev_priv->drm, 1,
1295                          "eDP powered off while attempting aux channel communication.\n");
1296                 drm_dbg_kms(&dev_priv->drm, "Status 0x%08x Control 0x%08x\n",
1297                             intel_de_read(dev_priv, _pp_stat_reg(intel_dp)),
1298                             intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)));
1299         }
1300 }
1301
1302 static u32
1303 intel_dp_aux_wait_done(struct intel_dp *intel_dp)
1304 {
1305         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1306         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1307         const unsigned int timeout_ms = 10;
1308         u32 status;
1309         bool done;
1310
1311 #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1312         done = wait_event_timeout(i915->gmbus_wait_queue, C,
1313                                   msecs_to_jiffies_timeout(timeout_ms));
1314
1315         /* just trace the final value */
1316         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1317
1318         if (!done)
1319                 drm_err(&i915->drm,
1320                         "%s: did not complete or timeout within %ums (status 0x%08x)\n",
1321                         intel_dp->aux.name, timeout_ms, status);
1322 #undef C
1323
1324         return status;
1325 }
1326
1327 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1328 {
1329         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1330
1331         if (index)
1332                 return 0;
1333
1334         /*
1335          * The clock divider is based off the hrawclk, and would like to run at
1336          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
1337          */
1338         return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000);
1339 }
1340
1341 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1342 {
1343         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1344         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1345         u32 freq;
1346
1347         if (index)
1348                 return 0;
1349
1350         /*
1351          * The clock divider is based off the cdclk or PCH rawclk, and would
1352          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
1353          * divide by 2000 and use that
1354          */
1355         if (dig_port->aux_ch == AUX_CH_A)
1356                 freq = dev_priv->cdclk.hw.cdclk;
1357         else
1358                 freq = RUNTIME_INFO(dev_priv)->rawclk_freq;
1359         return DIV_ROUND_CLOSEST(freq, 2000);
1360 }
1361
1362 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1363 {
1364         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1365         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1366
1367         if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) {
1368                 /* Workaround for non-ULT HSW */
1369                 switch (index) {
1370                 case 0: return 63;
1371                 case 1: return 72;
1372                 default: return 0;
1373                 }
1374         }
1375
1376         return ilk_get_aux_clock_divider(intel_dp, index);
1377 }
1378
1379 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
1380 {
1381         /*
1382          * SKL doesn't need us to program the AUX clock divider (Hardware will
1383          * derive the clock from CDCLK automatically). We still implement the
1384          * get_aux_clock_divider vfunc to plug-in into the existing code.
1385          */
1386         return index ? 0 : 1;
1387 }
1388
1389 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
1390                                 int send_bytes,
1391                                 u32 aux_clock_divider)
1392 {
1393         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1394         struct drm_i915_private *dev_priv =
1395                         to_i915(dig_port->base.base.dev);
1396         u32 precharge, timeout;
1397
1398         if (IS_GEN(dev_priv, 6))
1399                 precharge = 3;
1400         else
1401                 precharge = 5;
1402
1403         if (IS_BROADWELL(dev_priv))
1404                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1405         else
1406                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1407
1408         return DP_AUX_CH_CTL_SEND_BUSY |
1409                DP_AUX_CH_CTL_DONE |
1410                DP_AUX_CH_CTL_INTERRUPT |
1411                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1412                timeout |
1413                DP_AUX_CH_CTL_RECEIVE_ERROR |
1414                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1415                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1416                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1417 }
1418
1419 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1420                                 int send_bytes,
1421                                 u32 unused)
1422 {
1423         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1424         struct drm_i915_private *i915 =
1425                         to_i915(dig_port->base.base.dev);
1426         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
1427         u32 ret;
1428
1429         ret = DP_AUX_CH_CTL_SEND_BUSY |
1430               DP_AUX_CH_CTL_DONE |
1431               DP_AUX_CH_CTL_INTERRUPT |
1432               DP_AUX_CH_CTL_TIME_OUT_ERROR |
1433               DP_AUX_CH_CTL_TIME_OUT_MAX |
1434               DP_AUX_CH_CTL_RECEIVE_ERROR |
1435               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1436               DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1437               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1438
1439         if (intel_phy_is_tc(i915, phy) &&
1440             dig_port->tc_mode == TC_PORT_TBT_ALT)
1441                 ret |= DP_AUX_CH_CTL_TBT_IO;
1442
1443         return ret;
1444 }
1445
1446 static int
1447 intel_dp_aux_xfer(struct intel_dp *intel_dp,
1448                   const u8 *send, int send_bytes,
1449                   u8 *recv, int recv_size,
1450                   u32 aux_send_ctl_flags)
1451 {
1452         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1453         struct drm_i915_private *i915 =
1454                         to_i915(dig_port->base.base.dev);
1455         struct intel_uncore *uncore = &i915->uncore;
1456         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
1457         bool is_tc_port = intel_phy_is_tc(i915, phy);
1458         i915_reg_t ch_ctl, ch_data[5];
1459         u32 aux_clock_divider;
1460         enum intel_display_power_domain aux_domain;
1461         intel_wakeref_t aux_wakeref;
1462         intel_wakeref_t pps_wakeref;
1463         int i, ret, recv_bytes;
1464         int try, clock = 0;
1465         u32 status;
1466         bool vdd;
1467
1468         ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp);
1469         for (i = 0; i < ARRAY_SIZE(ch_data); i++)
1470                 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i);
1471
1472         if (is_tc_port)
1473                 intel_tc_port_lock(dig_port);
1474
1475         aux_domain = intel_aux_power_domain(dig_port);
1476
1477         aux_wakeref = intel_display_power_get(i915, aux_domain);
1478         pps_wakeref = pps_lock(intel_dp);
1479
1480         /*
1481          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1482          * In such cases we want to leave VDD enabled and it's up to upper layers
1483          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1484          * ourselves.
1485          */
1486         vdd = edp_panel_vdd_on(intel_dp);
1487
1488         /* dp aux is extremely sensitive to irq latency, hence request the
1489          * lowest possible wakeup latency and so prevent the cpu from going into
1490          * deep sleep states.
1491          */
1492         cpu_latency_qos_update_request(&i915->pm_qos, 0);
1493
1494         intel_dp_check_edp(intel_dp);
1495
1496         /* Try to wait for any previous AUX channel activity */
1497         for (try = 0; try < 3; try++) {
1498                 status = intel_uncore_read_notrace(uncore, ch_ctl);
1499                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1500                         break;
1501                 msleep(1);
1502         }
1503         /* just trace the final value */
1504         trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true);
1505
1506         if (try == 3) {
1507                 const u32 status = intel_uncore_read(uncore, ch_ctl);
1508
1509                 if (status != intel_dp->aux_busy_last_status) {
1510                         drm_WARN(&i915->drm, 1,
1511                                  "%s: not started (status 0x%08x)\n",
1512                                  intel_dp->aux.name, status);
1513                         intel_dp->aux_busy_last_status = status;
1514                 }
1515
1516                 ret = -EBUSY;
1517                 goto out;
1518         }
1519
1520         /* Only 5 data registers! */
1521         if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) {
1522                 ret = -E2BIG;
1523                 goto out;
1524         }
1525
1526         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1527                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1528                                                           send_bytes,
1529                                                           aux_clock_divider);
1530
1531                 send_ctl |= aux_send_ctl_flags;
1532
1533                 /* Must try at least 3 times according to DP spec */
1534                 for (try = 0; try < 5; try++) {
1535                         /* Load the send data into the aux channel data registers */
1536                         for (i = 0; i < send_bytes; i += 4)
1537                                 intel_uncore_write(uncore,
1538                                                    ch_data[i >> 2],
1539                                                    intel_dp_pack_aux(send + i,
1540                                                                      send_bytes - i));
1541
1542                         /* Send the command and wait for it to complete */
1543                         intel_uncore_write(uncore, ch_ctl, send_ctl);
1544
1545                         status = intel_dp_aux_wait_done(intel_dp);
1546
1547                         /* Clear done status and any errors */
1548                         intel_uncore_write(uncore,
1549                                            ch_ctl,
1550                                            status |
1551                                            DP_AUX_CH_CTL_DONE |
1552                                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
1553                                            DP_AUX_CH_CTL_RECEIVE_ERROR);
1554
1555                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1556                          *   400us delay required for errors and timeouts
1557                          *   Timeout errors from the HW already meet this
1558                          *   requirement so skip to next iteration
1559                          */
1560                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1561                                 continue;
1562
1563                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1564                                 usleep_range(400, 500);
1565                                 continue;
1566                         }
1567                         if (status & DP_AUX_CH_CTL_DONE)
1568                                 goto done;
1569                 }
1570         }
1571
1572         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1573                 drm_err(&i915->drm, "%s: not done (status 0x%08x)\n",
1574                         intel_dp->aux.name, status);
1575                 ret = -EBUSY;
1576                 goto out;
1577         }
1578
1579 done:
1580         /* Check for timeout or receive error.
1581          * Timeouts occur when the sink is not connected
1582          */
1583         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1584                 drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n",
1585                         intel_dp->aux.name, status);
1586                 ret = -EIO;
1587                 goto out;
1588         }
1589
1590         /* Timeouts occur when the device isn't connected, so they're
1591          * "normal" -- don't fill the kernel log with these */
1592         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1593                 drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n",
1594                             intel_dp->aux.name, status);
1595                 ret = -ETIMEDOUT;
1596                 goto out;
1597         }
1598
1599         /* Unload any bytes sent back from the other side */
1600         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1601                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1602
1603         /*
1604          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1605          * We have no idea of what happened so we return -EBUSY so
1606          * drm layer takes care for the necessary retries.
1607          */
1608         if (recv_bytes == 0 || recv_bytes > 20) {
1609                 drm_dbg_kms(&i915->drm,
1610                             "%s: Forbidden recv_bytes = %d on aux transaction\n",
1611                             intel_dp->aux.name, recv_bytes);
1612                 ret = -EBUSY;
1613                 goto out;
1614         }
1615
1616         if (recv_bytes > recv_size)
1617                 recv_bytes = recv_size;
1618
1619         for (i = 0; i < recv_bytes; i += 4)
1620                 intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]),
1621                                     recv + i, recv_bytes - i);
1622
1623         ret = recv_bytes;
1624 out:
1625         cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);
1626
1627         if (vdd)
1628                 edp_panel_vdd_off(intel_dp, false);
1629
1630         pps_unlock(intel_dp, pps_wakeref);
1631         intel_display_power_put_async(i915, aux_domain, aux_wakeref);
1632
1633         if (is_tc_port)
1634                 intel_tc_port_unlock(dig_port);
1635
1636         return ret;
1637 }
1638
1639 #define BARE_ADDRESS_SIZE       3
1640 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1641
1642 static void
1643 intel_dp_aux_header(u8 txbuf[HEADER_SIZE],
1644                     const struct drm_dp_aux_msg *msg)
1645 {
1646         txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf);
1647         txbuf[1] = (msg->address >> 8) & 0xff;
1648         txbuf[2] = msg->address & 0xff;
1649         txbuf[3] = msg->size - 1;
1650 }
1651
1652 static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg)
1653 {
1654         /*
1655          * If we're trying to send the HDCP Aksv, we need to set a the Aksv
1656          * select bit to inform the hardware to send the Aksv after our header
1657          * since we can't access that data from software.
1658          */
1659         if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE &&
1660             msg->address == DP_AUX_HDCP_AKSV)
1661                 return DP_AUX_CH_CTL_AUX_AKSV_SELECT;
1662
1663         return 0;
1664 }
1665
1666 static ssize_t
1667 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1668 {
1669         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1670         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1671         u8 txbuf[20], rxbuf[20];
1672         size_t txsize, rxsize;
1673         u32 flags = intel_dp_aux_xfer_flags(msg);
1674         int ret;
1675
1676         intel_dp_aux_header(txbuf, msg);
1677
1678         switch (msg->request & ~DP_AUX_I2C_MOT) {
1679         case DP_AUX_NATIVE_WRITE:
1680         case DP_AUX_I2C_WRITE:
1681         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1682                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1683                 rxsize = 2; /* 0 or 1 data bytes */
1684
1685                 if (drm_WARN_ON(&i915->drm, txsize > 20))
1686                         return -E2BIG;
1687
1688                 drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size);
1689
1690                 if (msg->buffer)
1691                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1692
1693                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1694                                         rxbuf, rxsize, flags);
1695                 if (ret > 0) {
1696                         msg->reply = rxbuf[0] >> 4;
1697
1698                         if (ret > 1) {
1699                                 /* Number of bytes written in a short write. */
1700                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1701                         } else {
1702                                 /* Return payload size. */
1703                                 ret = msg->size;
1704                         }
1705                 }
1706                 break;
1707
1708         case DP_AUX_NATIVE_READ:
1709         case DP_AUX_I2C_READ:
1710                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1711                 rxsize = msg->size + 1;
1712
1713                 if (drm_WARN_ON(&i915->drm, rxsize > 20))
1714                         return -E2BIG;
1715
1716                 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize,
1717                                         rxbuf, rxsize, flags);
1718                 if (ret > 0) {
1719                         msg->reply = rxbuf[0] >> 4;
1720                         /*
1721                          * Assume happy day, and copy the data. The caller is
1722                          * expected to check msg->reply before touching it.
1723                          *
1724                          * Return payload size.
1725                          */
1726                         ret--;
1727                         memcpy(msg->buffer, rxbuf + 1, ret);
1728                 }
1729                 break;
1730
1731         default:
1732                 ret = -EINVAL;
1733                 break;
1734         }
1735
1736         return ret;
1737 }
1738
1739
1740 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp)
1741 {
1742         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1743         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1744         enum aux_ch aux_ch = dig_port->aux_ch;
1745
1746         switch (aux_ch) {
1747         case AUX_CH_B:
1748         case AUX_CH_C:
1749         case AUX_CH_D:
1750                 return DP_AUX_CH_CTL(aux_ch);
1751         default:
1752                 MISSING_CASE(aux_ch);
1753                 return DP_AUX_CH_CTL(AUX_CH_B);
1754         }
1755 }
1756
1757 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index)
1758 {
1759         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1760         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1761         enum aux_ch aux_ch = dig_port->aux_ch;
1762
1763         switch (aux_ch) {
1764         case AUX_CH_B:
1765         case AUX_CH_C:
1766         case AUX_CH_D:
1767                 return DP_AUX_CH_DATA(aux_ch, index);
1768         default:
1769                 MISSING_CASE(aux_ch);
1770                 return DP_AUX_CH_DATA(AUX_CH_B, index);
1771         }
1772 }
1773
1774 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp)
1775 {
1776         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1777         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1778         enum aux_ch aux_ch = dig_port->aux_ch;
1779
1780         switch (aux_ch) {
1781         case AUX_CH_A:
1782                 return DP_AUX_CH_CTL(aux_ch);
1783         case AUX_CH_B:
1784         case AUX_CH_C:
1785         case AUX_CH_D:
1786                 return PCH_DP_AUX_CH_CTL(aux_ch);
1787         default:
1788                 MISSING_CASE(aux_ch);
1789                 return DP_AUX_CH_CTL(AUX_CH_A);
1790         }
1791 }
1792
1793 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index)
1794 {
1795         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1796         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1797         enum aux_ch aux_ch = dig_port->aux_ch;
1798
1799         switch (aux_ch) {
1800         case AUX_CH_A:
1801                 return DP_AUX_CH_DATA(aux_ch, index);
1802         case AUX_CH_B:
1803         case AUX_CH_C:
1804         case AUX_CH_D:
1805                 return PCH_DP_AUX_CH_DATA(aux_ch, index);
1806         default:
1807                 MISSING_CASE(aux_ch);
1808                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1809         }
1810 }
1811
1812 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp)
1813 {
1814         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1815         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1816         enum aux_ch aux_ch = dig_port->aux_ch;
1817
1818         switch (aux_ch) {
1819         case AUX_CH_A:
1820         case AUX_CH_B:
1821         case AUX_CH_C:
1822         case AUX_CH_D:
1823         case AUX_CH_E:
1824         case AUX_CH_F:
1825                 return DP_AUX_CH_CTL(aux_ch);
1826         default:
1827                 MISSING_CASE(aux_ch);
1828                 return DP_AUX_CH_CTL(AUX_CH_A);
1829         }
1830 }
1831
1832 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index)
1833 {
1834         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1835         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1836         enum aux_ch aux_ch = dig_port->aux_ch;
1837
1838         switch (aux_ch) {
1839         case AUX_CH_A:
1840         case AUX_CH_B:
1841         case AUX_CH_C:
1842         case AUX_CH_D:
1843         case AUX_CH_E:
1844         case AUX_CH_F:
1845                 return DP_AUX_CH_DATA(aux_ch, index);
1846         default:
1847                 MISSING_CASE(aux_ch);
1848                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1849         }
1850 }
1851
1852 static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
1853 {
1854         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1855         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1856         enum aux_ch aux_ch = dig_port->aux_ch;
1857
1858         switch (aux_ch) {
1859         case AUX_CH_A:
1860         case AUX_CH_B:
1861         case AUX_CH_C:
1862         case AUX_CH_USBC1:
1863         case AUX_CH_USBC2:
1864         case AUX_CH_USBC3:
1865         case AUX_CH_USBC4:
1866         case AUX_CH_USBC5:
1867         case AUX_CH_USBC6:
1868                 return DP_AUX_CH_CTL(aux_ch);
1869         default:
1870                 MISSING_CASE(aux_ch);
1871                 return DP_AUX_CH_CTL(AUX_CH_A);
1872         }
1873 }
1874
1875 static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
1876 {
1877         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1878         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1879         enum aux_ch aux_ch = dig_port->aux_ch;
1880
1881         switch (aux_ch) {
1882         case AUX_CH_A:
1883         case AUX_CH_B:
1884         case AUX_CH_C:
1885         case AUX_CH_USBC1:
1886         case AUX_CH_USBC2:
1887         case AUX_CH_USBC3:
1888         case AUX_CH_USBC4:
1889         case AUX_CH_USBC5:
1890         case AUX_CH_USBC6:
1891                 return DP_AUX_CH_DATA(aux_ch, index);
1892         default:
1893                 MISSING_CASE(aux_ch);
1894                 return DP_AUX_CH_DATA(AUX_CH_A, index);
1895         }
1896 }
1897
1898 static void
1899 intel_dp_aux_fini(struct intel_dp *intel_dp)
1900 {
1901         kfree(intel_dp->aux.name);
1902 }
1903
1904 static void
1905 intel_dp_aux_init(struct intel_dp *intel_dp)
1906 {
1907         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
1908         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1909         struct intel_encoder *encoder = &dig_port->base;
1910         enum aux_ch aux_ch = dig_port->aux_ch;
1911
1912         if (INTEL_GEN(dev_priv) >= 12) {
1913                 intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg;
1914                 intel_dp->aux_ch_data_reg = tgl_aux_data_reg;
1915         } else if (INTEL_GEN(dev_priv) >= 9) {
1916                 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg;
1917                 intel_dp->aux_ch_data_reg = skl_aux_data_reg;
1918         } else if (HAS_PCH_SPLIT(dev_priv)) {
1919                 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg;
1920                 intel_dp->aux_ch_data_reg = ilk_aux_data_reg;
1921         } else {
1922                 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg;
1923                 intel_dp->aux_ch_data_reg = g4x_aux_data_reg;
1924         }
1925
1926         if (INTEL_GEN(dev_priv) >= 9)
1927                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
1928         else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
1929                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
1930         else if (HAS_PCH_SPLIT(dev_priv))
1931                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
1932         else
1933                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
1934
1935         if (INTEL_GEN(dev_priv) >= 9)
1936                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
1937         else
1938                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
1939
1940         drm_dp_aux_init(&intel_dp->aux);
1941
1942         /* Failure to allocate our preferred name is not critical */
1943         if (INTEL_GEN(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
1944                 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s",
1945                                                aux_ch - AUX_CH_USBC1 + '1',
1946                                                encoder->base.name);
1947         else
1948                 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
1949                                                aux_ch_name(aux_ch),
1950                                                encoder->base.name);
1951
1952         intel_dp->aux.transfer = intel_dp_aux_transfer;
1953 }
1954
1955 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1956 {
1957         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1958
1959         return max_rate >= 540000;
1960 }
1961
1962 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp)
1963 {
1964         int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1];
1965
1966         return max_rate >= 810000;
1967 }
1968
1969 static void
1970 intel_dp_set_clock(struct intel_encoder *encoder,
1971                    struct intel_crtc_state *pipe_config)
1972 {
1973         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1974         const struct dp_link_dpll *divisor = NULL;
1975         int i, count = 0;
1976
1977         if (IS_G4X(dev_priv)) {
1978                 divisor = g4x_dpll;
1979                 count = ARRAY_SIZE(g4x_dpll);
1980         } else if (HAS_PCH_SPLIT(dev_priv)) {
1981                 divisor = pch_dpll;
1982                 count = ARRAY_SIZE(pch_dpll);
1983         } else if (IS_CHERRYVIEW(dev_priv)) {
1984                 divisor = chv_dpll;
1985                 count = ARRAY_SIZE(chv_dpll);
1986         } else if (IS_VALLEYVIEW(dev_priv)) {
1987                 divisor = vlv_dpll;
1988                 count = ARRAY_SIZE(vlv_dpll);
1989         }
1990
1991         if (divisor && count) {
1992                 for (i = 0; i < count; i++) {
1993                         if (pipe_config->port_clock == divisor[i].clock) {
1994                                 pipe_config->dpll = divisor[i].dpll;
1995                                 pipe_config->clock_set = true;
1996                                 break;
1997                         }
1998                 }
1999         }
2000 }
2001
2002 static void snprintf_int_array(char *str, size_t len,
2003                                const int *array, int nelem)
2004 {
2005         int i;
2006
2007         str[0] = '\0';
2008
2009         for (i = 0; i < nelem; i++) {
2010                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
2011                 if (r >= len)
2012                         return;
2013                 str += r;
2014                 len -= r;
2015         }
2016 }
2017
2018 static void intel_dp_print_rates(struct intel_dp *intel_dp)
2019 {
2020         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2021         char str[128]; /* FIXME: too big for stack? */
2022
2023         if (!drm_debug_enabled(DRM_UT_KMS))
2024                 return;
2025
2026         snprintf_int_array(str, sizeof(str),
2027                            intel_dp->source_rates, intel_dp->num_source_rates);
2028         drm_dbg_kms(&i915->drm, "source rates: %s\n", str);
2029
2030         snprintf_int_array(str, sizeof(str),
2031                            intel_dp->sink_rates, intel_dp->num_sink_rates);
2032         drm_dbg_kms(&i915->drm, "sink rates: %s\n", str);
2033
2034         snprintf_int_array(str, sizeof(str),
2035                            intel_dp->common_rates, intel_dp->num_common_rates);
2036         drm_dbg_kms(&i915->drm, "common rates: %s\n", str);
2037 }
2038
2039 int
2040 intel_dp_max_link_rate(struct intel_dp *intel_dp)
2041 {
2042         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2043         int len;
2044
2045         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
2046         if (drm_WARN_ON(&i915->drm, len <= 0))
2047                 return 162000;
2048
2049         return intel_dp->common_rates[len - 1];
2050 }
2051
2052 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
2053 {
2054         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2055         int i = intel_dp_rate_index(intel_dp->sink_rates,
2056                                     intel_dp->num_sink_rates, rate);
2057
2058         if (drm_WARN_ON(&i915->drm, i < 0))
2059                 i = 0;
2060
2061         return i;
2062 }
2063
2064 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
2065                            u8 *link_bw, u8 *rate_select)
2066 {
2067         /* eDP 1.4 rate select method. */
2068         if (intel_dp->use_rate_select) {
2069                 *link_bw = 0;
2070                 *rate_select =
2071                         intel_dp_rate_select(intel_dp, port_clock);
2072         } else {
2073                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
2074                 *rate_select = 0;
2075         }
2076 }
2077
2078 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
2079                                          const struct intel_crtc_state *pipe_config)
2080 {
2081         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2082
2083         /* On TGL, FEC is supported on all Pipes */
2084         if (INTEL_GEN(dev_priv) >= 12)
2085                 return true;
2086
2087         if (IS_GEN(dev_priv, 11) && pipe_config->cpu_transcoder != TRANSCODER_A)
2088                 return true;
2089
2090         return false;
2091 }
2092
2093 static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
2094                                   const struct intel_crtc_state *pipe_config)
2095 {
2096         return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
2097                 drm_dp_sink_supports_fec(intel_dp->fec_capable);
2098 }
2099
2100 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp,
2101                                   const struct intel_crtc_state *crtc_state)
2102 {
2103         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable)
2104                 return false;
2105
2106         return intel_dsc_source_support(crtc_state) &&
2107                 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd);
2108 }
2109
2110 static bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp,
2111                                    const struct intel_crtc_state *crtc_state)
2112 {
2113         return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
2114                 (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 &&
2115                  intel_dp->dfp.ycbcr_444_to_420);
2116 }
2117
2118 static int intel_dp_hdmi_tmds_clock(struct intel_dp *intel_dp,
2119                                     const struct intel_crtc_state *crtc_state, int bpc)
2120 {
2121         int clock = crtc_state->hw.adjusted_mode.crtc_clock * bpc / 8;
2122
2123         if (intel_dp_hdmi_ycbcr420(intel_dp, crtc_state))
2124                 clock /= 2;
2125
2126         return clock;
2127 }
2128
2129 static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp,
2130                                            const struct intel_crtc_state *crtc_state, int bpc)
2131 {
2132         int tmds_clock = intel_dp_hdmi_tmds_clock(intel_dp, crtc_state, bpc);
2133
2134         if (intel_dp->dfp.min_tmds_clock &&
2135             tmds_clock < intel_dp->dfp.min_tmds_clock)
2136                 return false;
2137
2138         if (intel_dp->dfp.max_tmds_clock &&
2139             tmds_clock > intel_dp->dfp.max_tmds_clock)
2140                 return false;
2141
2142         return true;
2143 }
2144
2145 static bool intel_dp_hdmi_deep_color_possible(struct intel_dp *intel_dp,
2146                                               const struct intel_crtc_state *crtc_state,
2147                                               int bpc)
2148 {
2149
2150         return intel_hdmi_deep_color_possible(crtc_state, bpc,
2151                                               intel_dp->has_hdmi_sink,
2152                                               intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) &&
2153                 intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc);
2154 }
2155
2156 static int intel_dp_max_bpp(struct intel_dp *intel_dp,
2157                             const struct intel_crtc_state *crtc_state)
2158 {
2159         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2160         struct intel_connector *intel_connector = intel_dp->attached_connector;
2161         int bpp, bpc;
2162
2163         bpc = crtc_state->pipe_bpp / 3;
2164
2165         if (intel_dp->dfp.max_bpc)
2166                 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc);
2167
2168         if (intel_dp->dfp.min_tmds_clock) {
2169                 for (; bpc >= 10; bpc -= 2) {
2170                         if (intel_dp_hdmi_deep_color_possible(intel_dp, crtc_state, bpc))
2171                                 break;
2172                 }
2173         }
2174
2175         bpp = bpc * 3;
2176         if (intel_dp_is_edp(intel_dp)) {
2177                 /* Get bpp from vbt only for panels that dont have bpp in edid */
2178                 if (intel_connector->base.display_info.bpc == 0 &&
2179                     dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) {
2180                         drm_dbg_kms(&dev_priv->drm,
2181                                     "clamping bpp for eDP panel to BIOS-provided %i\n",
2182                                     dev_priv->vbt.edp.bpp);
2183                         bpp = dev_priv->vbt.edp.bpp;
2184                 }
2185         }
2186
2187         return bpp;
2188 }
2189
2190 /* Adjust link config limits based on compliance test requests. */
2191 void
2192 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
2193                                   struct intel_crtc_state *pipe_config,
2194                                   struct link_config_limits *limits)
2195 {
2196         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2197
2198         /* For DP Compliance we override the computed bpp for the pipe */
2199         if (intel_dp->compliance.test_data.bpc != 0) {
2200                 int bpp = 3 * intel_dp->compliance.test_data.bpc;
2201
2202                 limits->min_bpp = limits->max_bpp = bpp;
2203                 pipe_config->dither_force_disable = bpp == 6 * 3;
2204
2205                 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
2206         }
2207
2208         /* Use values requested by Compliance Test Request */
2209         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
2210                 int index;
2211
2212                 /* Validate the compliance test data since max values
2213                  * might have changed due to link train fallback.
2214                  */
2215                 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate,
2216                                                intel_dp->compliance.test_lane_count)) {
2217                         index = intel_dp_rate_index(intel_dp->common_rates,
2218                                                     intel_dp->num_common_rates,
2219                                                     intel_dp->compliance.test_link_rate);
2220                         if (index >= 0)
2221                                 limits->min_clock = limits->max_clock = index;
2222                         limits->min_lane_count = limits->max_lane_count =
2223                                 intel_dp->compliance.test_lane_count;
2224                 }
2225         }
2226 }
2227
2228 /* Optimize link config in order: max bpp, min clock, min lanes */
2229 static int
2230 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
2231                                   struct intel_crtc_state *pipe_config,
2232                                   const struct link_config_limits *limits)
2233 {
2234         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2235         int bpp, clock, lane_count;
2236         int mode_rate, link_clock, link_avail;
2237
2238         for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
2239                 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
2240
2241                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
2242                                                    output_bpp);
2243
2244                 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) {
2245                         for (lane_count = limits->min_lane_count;
2246                              lane_count <= limits->max_lane_count;
2247                              lane_count <<= 1) {
2248                                 link_clock = intel_dp->common_rates[clock];
2249                                 link_avail = intel_dp_max_data_rate(link_clock,
2250                                                                     lane_count);
2251
2252                                 if (mode_rate <= link_avail) {
2253                                         pipe_config->lane_count = lane_count;
2254                                         pipe_config->pipe_bpp = bpp;
2255                                         pipe_config->port_clock = link_clock;
2256
2257                                         return 0;
2258                                 }
2259                         }
2260                 }
2261         }
2262
2263         return -EINVAL;
2264 }
2265
2266 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
2267 {
2268         int i, num_bpc;
2269         u8 dsc_bpc[3] = {0};
2270
2271         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
2272                                                        dsc_bpc);
2273         for (i = 0; i < num_bpc; i++) {
2274                 if (dsc_max_bpc >= dsc_bpc[i])
2275                         return dsc_bpc[i] * 3;
2276         }
2277
2278         return 0;
2279 }
2280
2281 #define DSC_SUPPORTED_VERSION_MIN               1
2282
2283 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
2284                                        struct intel_crtc_state *crtc_state)
2285 {
2286         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2287         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2288         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
2289         u8 line_buf_depth;
2290         int ret;
2291
2292         ret = intel_dsc_compute_params(encoder, crtc_state);
2293         if (ret)
2294                 return ret;
2295
2296         /*
2297          * Slice Height of 8 works for all currently available panels. So start
2298          * with that if pic_height is an integral multiple of 8. Eventually add
2299          * logic to try multiple slice heights.
2300          */
2301         if (vdsc_cfg->pic_height % 8 == 0)
2302                 vdsc_cfg->slice_height = 8;
2303         else if (vdsc_cfg->pic_height % 4 == 0)
2304                 vdsc_cfg->slice_height = 4;
2305         else
2306                 vdsc_cfg->slice_height = 2;
2307
2308         vdsc_cfg->dsc_version_major =
2309                 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2310                  DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
2311         vdsc_cfg->dsc_version_minor =
2312                 min(DSC_SUPPORTED_VERSION_MIN,
2313                     (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
2314                      DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
2315
2316         vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
2317                 DP_DSC_RGB;
2318
2319         line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
2320         if (!line_buf_depth) {
2321                 drm_dbg_kms(&i915->drm,
2322                             "DSC Sink Line Buffer Depth invalid\n");
2323                 return -EINVAL;
2324         }
2325
2326         if (vdsc_cfg->dsc_version_minor == 2)
2327                 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
2328                         DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
2329         else
2330                 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
2331                         DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
2332
2333         vdsc_cfg->block_pred_enable =
2334                 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
2335                 DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
2336
2337         return drm_dsc_compute_rc_parameters(vdsc_cfg);
2338 }
2339
2340 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
2341                                        struct intel_crtc_state *pipe_config,
2342                                        struct drm_connector_state *conn_state,
2343                                        struct link_config_limits *limits)
2344 {
2345         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2346         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2347         const struct drm_display_mode *adjusted_mode =
2348                 &pipe_config->hw.adjusted_mode;
2349         u8 dsc_max_bpc;
2350         int pipe_bpp;
2351         int ret;
2352
2353         pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
2354                 intel_dp_supports_fec(intel_dp, pipe_config);
2355
2356         if (!intel_dp_supports_dsc(intel_dp, pipe_config))
2357                 return -EINVAL;
2358
2359         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
2360         if (INTEL_GEN(dev_priv) >= 12)
2361                 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
2362         else
2363                 dsc_max_bpc = min_t(u8, 10,
2364                                     conn_state->max_requested_bpc);
2365
2366         pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc);
2367
2368         /* Min Input BPC for ICL+ is 8 */
2369         if (pipe_bpp < 8 * 3) {
2370                 drm_dbg_kms(&dev_priv->drm,
2371                             "No DSC support for less than 8bpc\n");
2372                 return -EINVAL;
2373         }
2374
2375         /*
2376          * For now enable DSC for max bpp, max link rate, max lane count.
2377          * Optimize this later for the minimum possible link rate/lane count
2378          * with DSC enabled for the requested mode.
2379          */
2380         pipe_config->pipe_bpp = pipe_bpp;
2381         pipe_config->port_clock = intel_dp->common_rates[limits->max_clock];
2382         pipe_config->lane_count = limits->max_lane_count;
2383
2384         if (intel_dp_is_edp(intel_dp)) {
2385                 pipe_config->dsc.compressed_bpp =
2386                         min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4,
2387                               pipe_config->pipe_bpp);
2388                 pipe_config->dsc.slice_count =
2389                         drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd,
2390                                                         true);
2391         } else {
2392                 u16 dsc_max_output_bpp;
2393                 u8 dsc_dp_slice_count;
2394
2395                 dsc_max_output_bpp =
2396                         intel_dp_dsc_get_output_bpp(dev_priv,
2397                                                     pipe_config->port_clock,
2398                                                     pipe_config->lane_count,
2399                                                     adjusted_mode->crtc_clock,
2400                                                     adjusted_mode->crtc_hdisplay,
2401                                                     pipe_config->bigjoiner);
2402                 dsc_dp_slice_count =
2403                         intel_dp_dsc_get_slice_count(intel_dp,
2404                                                      adjusted_mode->crtc_clock,
2405                                                      adjusted_mode->crtc_hdisplay,
2406                                                      pipe_config->bigjoiner);
2407                 if (!dsc_max_output_bpp || !dsc_dp_slice_count) {
2408                         drm_dbg_kms(&dev_priv->drm,
2409                                     "Compressed BPP/Slice Count not supported\n");
2410                         return -EINVAL;
2411                 }
2412                 pipe_config->dsc.compressed_bpp = min_t(u16,
2413                                                                dsc_max_output_bpp >> 4,
2414                                                                pipe_config->pipe_bpp);
2415                 pipe_config->dsc.slice_count = dsc_dp_slice_count;
2416         }
2417         /*
2418          * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate
2419          * is greater than the maximum Cdclock and if slice count is even
2420          * then we need to use 2 VDSC instances.
2421          */
2422         if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq ||
2423             pipe_config->bigjoiner) {
2424                 if (pipe_config->dsc.slice_count < 2) {
2425                         drm_dbg_kms(&dev_priv->drm,
2426                                     "Cannot split stream to use 2 VDSC instances\n");
2427                         return -EINVAL;
2428                 }
2429
2430                 pipe_config->dsc.dsc_split = true;
2431         }
2432
2433         ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
2434         if (ret < 0) {
2435                 drm_dbg_kms(&dev_priv->drm,
2436                             "Cannot compute valid DSC parameters for Input Bpp = %d "
2437                             "Compressed BPP = %d\n",
2438                             pipe_config->pipe_bpp,
2439                             pipe_config->dsc.compressed_bpp);
2440                 return ret;
2441         }
2442
2443         pipe_config->dsc.compression_enable = true;
2444         drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d "
2445                     "Compressed Bpp = %d Slice Count = %d\n",
2446                     pipe_config->pipe_bpp,
2447                     pipe_config->dsc.compressed_bpp,
2448                     pipe_config->dsc.slice_count);
2449
2450         return 0;
2451 }
2452
2453 static int
2454 intel_dp_compute_link_config(struct intel_encoder *encoder,
2455                              struct intel_crtc_state *pipe_config,
2456                              struct drm_connector_state *conn_state)
2457 {
2458         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2459         const struct drm_display_mode *adjusted_mode =
2460                 &pipe_config->hw.adjusted_mode;
2461         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2462         struct link_config_limits limits;
2463         int common_len;
2464         int ret;
2465
2466         common_len = intel_dp_common_len_rate_limit(intel_dp,
2467                                                     intel_dp->max_link_rate);
2468
2469         /* No common link rates between source and sink */
2470         drm_WARN_ON(encoder->base.dev, common_len <= 0);
2471
2472         limits.min_clock = 0;
2473         limits.max_clock = common_len - 1;
2474
2475         limits.min_lane_count = 1;
2476         limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
2477
2478         limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
2479         limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config);
2480
2481         if (intel_dp_is_edp(intel_dp)) {
2482                 /*
2483                  * Use the maximum clock and number of lanes the eDP panel
2484                  * advertizes being capable of. The panels are generally
2485                  * designed to support only a single clock and lane
2486                  * configuration, and typically these values correspond to the
2487                  * native resolution of the panel.
2488                  */
2489                 limits.min_lane_count = limits.max_lane_count;
2490                 limits.min_clock = limits.max_clock;
2491         }
2492
2493         intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
2494
2495         drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
2496                     "max rate %d max bpp %d pixel clock %iKHz\n",
2497                     limits.max_lane_count,
2498                     intel_dp->common_rates[limits.max_clock],
2499                     limits.max_bpp, adjusted_mode->crtc_clock);
2500
2501         if ((adjusted_mode->crtc_clock > i915->max_dotclk_freq ||
2502              adjusted_mode->crtc_hdisplay > 5120) &&
2503             intel_dp_can_bigjoiner(intel_dp))
2504                 pipe_config->bigjoiner = true;
2505
2506         /*
2507          * Optimize for slow and wide. This is the place to add alternative
2508          * optimization policy.
2509          */
2510         ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits);
2511
2512         /* enable compression if the mode doesn't fit available BW */
2513         drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
2514         if (ret || intel_dp->force_dsc_en || pipe_config->bigjoiner) {
2515                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
2516                                                   conn_state, &limits);
2517                 if (ret < 0)
2518                         return ret;
2519         }
2520
2521         if (pipe_config->dsc.compression_enable) {
2522                 drm_dbg_kms(&i915->drm,
2523                             "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n",
2524                             pipe_config->lane_count, pipe_config->port_clock,
2525                             pipe_config->pipe_bpp,
2526                             pipe_config->dsc.compressed_bpp);
2527
2528                 drm_dbg_kms(&i915->drm,
2529                             "DP link rate required %i available %i\n",
2530                             intel_dp_link_required(adjusted_mode->crtc_clock,
2531                                                    pipe_config->dsc.compressed_bpp),
2532                             intel_dp_max_data_rate(pipe_config->port_clock,
2533                                                    pipe_config->lane_count));
2534         } else {
2535                 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n",
2536                             pipe_config->lane_count, pipe_config->port_clock,
2537                             pipe_config->pipe_bpp);
2538
2539                 drm_dbg_kms(&i915->drm,
2540                             "DP link rate required %i available %i\n",
2541                             intel_dp_link_required(adjusted_mode->crtc_clock,
2542                                                    pipe_config->pipe_bpp),
2543                             intel_dp_max_data_rate(pipe_config->port_clock,
2544                                                    pipe_config->lane_count));
2545         }
2546         return 0;
2547 }
2548
2549 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
2550                                   const struct drm_connector_state *conn_state)
2551 {
2552         const struct intel_digital_connector_state *intel_conn_state =
2553                 to_intel_digital_connector_state(conn_state);
2554         const struct drm_display_mode *adjusted_mode =
2555                 &crtc_state->hw.adjusted_mode;
2556
2557         /*
2558          * Our YCbCr output is always limited range.
2559          * crtc_state->limited_color_range only applies to RGB,
2560          * and it must never be set for YCbCr or we risk setting
2561          * some conflicting bits in PIPECONF which will mess up
2562          * the colors on the monitor.
2563          */
2564         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2565                 return false;
2566
2567         if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2568                 /*
2569                  * See:
2570                  * CEA-861-E - 5.1 Default Encoding Parameters
2571                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
2572                  */
2573                 return crtc_state->pipe_bpp != 18 &&
2574                         drm_default_rgb_quant_range(adjusted_mode) ==
2575                         HDMI_QUANTIZATION_RANGE_LIMITED;
2576         } else {
2577                 return intel_conn_state->broadcast_rgb ==
2578                         INTEL_BROADCAST_RGB_LIMITED;
2579         }
2580 }
2581
2582 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv,
2583                                     enum port port)
2584 {
2585         if (IS_G4X(dev_priv))
2586                 return false;
2587         if (INTEL_GEN(dev_priv) < 12 && port == PORT_A)
2588                 return false;
2589
2590         return true;
2591 }
2592
2593 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
2594                                              const struct drm_connector_state *conn_state,
2595                                              struct drm_dp_vsc_sdp *vsc)
2596 {
2597         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2598         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2599
2600         /*
2601          * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2602          * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/
2603          * Colorimetry Format indication.
2604          */
2605         vsc->revision = 0x5;
2606         vsc->length = 0x13;
2607
2608         /* DP 1.4a spec, Table 2-120 */
2609         switch (crtc_state->output_format) {
2610         case INTEL_OUTPUT_FORMAT_YCBCR444:
2611                 vsc->pixelformat = DP_PIXELFORMAT_YUV444;
2612                 break;
2613         case INTEL_OUTPUT_FORMAT_YCBCR420:
2614                 vsc->pixelformat = DP_PIXELFORMAT_YUV420;
2615                 break;
2616         case INTEL_OUTPUT_FORMAT_RGB:
2617         default:
2618                 vsc->pixelformat = DP_PIXELFORMAT_RGB;
2619         }
2620
2621         switch (conn_state->colorspace) {
2622         case DRM_MODE_COLORIMETRY_BT709_YCC:
2623                 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2624                 break;
2625         case DRM_MODE_COLORIMETRY_XVYCC_601:
2626                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601;
2627                 break;
2628         case DRM_MODE_COLORIMETRY_XVYCC_709:
2629                 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709;
2630                 break;
2631         case DRM_MODE_COLORIMETRY_SYCC_601:
2632                 vsc->colorimetry = DP_COLORIMETRY_SYCC_601;
2633                 break;
2634         case DRM_MODE_COLORIMETRY_OPYCC_601:
2635                 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601;
2636                 break;
2637         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
2638                 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC;
2639                 break;
2640         case DRM_MODE_COLORIMETRY_BT2020_RGB:
2641                 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB;
2642                 break;
2643         case DRM_MODE_COLORIMETRY_BT2020_YCC:
2644                 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC;
2645                 break;
2646         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65:
2647         case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER:
2648                 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB;
2649                 break;
2650         default:
2651                 /*
2652                  * RGB->YCBCR color conversion uses the BT.709
2653                  * color space.
2654                  */
2655                 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
2656                         vsc->colorimetry = DP_COLORIMETRY_BT709_YCC;
2657                 else
2658                         vsc->colorimetry = DP_COLORIMETRY_DEFAULT;
2659                 break;
2660         }
2661
2662         vsc->bpc = crtc_state->pipe_bpp / 3;
2663
2664         /* only RGB pixelformat supports 6 bpc */
2665         drm_WARN_ON(&dev_priv->drm,
2666                     vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);
2667
2668         /* all YCbCr are always limited range */
2669         vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA;
2670         vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED;
2671 }
2672
2673 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
2674                                      struct intel_crtc_state *crtc_state,
2675                                      const struct drm_connector_state *conn_state)
2676 {
2677         struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc;
2678
2679         /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */
2680         if (crtc_state->has_psr)
2681                 return;
2682
2683         if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
2684                 return;
2685
2686         crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
2687         vsc->sdp_type = DP_SDP_VSC;
2688         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2689                                          &crtc_state->infoframes.vsc);
2690 }
2691
2692 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp,
2693                                   const struct intel_crtc_state *crtc_state,
2694                                   const struct drm_connector_state *conn_state,
2695                                   struct drm_dp_vsc_sdp *vsc)
2696 {
2697         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2698
2699         vsc->sdp_type = DP_SDP_VSC;
2700
2701         if (dev_priv->psr.psr2_enabled) {
2702                 if (dev_priv->psr.colorimetry_support &&
2703                     intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
2704                         /* [PSR2, +Colorimetry] */
2705                         intel_dp_compute_vsc_colorimetry(crtc_state, conn_state,
2706                                                          vsc);
2707                 } else {
2708                         /*
2709                          * [PSR2, -Colorimetry]
2710                          * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11
2711                          * 3D stereo + PSR/PSR2 + Y-coordinate.
2712                          */
2713                         vsc->revision = 0x4;
2714                         vsc->length = 0xe;
2715                 }
2716         } else {
2717                 /*
2718                  * [PSR1]
2719                  * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118
2720                  * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or
2721                  * higher).
2722                  */
2723                 vsc->revision = 0x2;
2724                 vsc->length = 0x8;
2725         }
2726 }
2727
2728 static void
2729 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
2730                                             struct intel_crtc_state *crtc_state,
2731                                             const struct drm_connector_state *conn_state)
2732 {
2733         int ret;
2734         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2735         struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;
2736
2737         if (!conn_state->hdr_output_metadata)
2738                 return;
2739
2740         ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);
2741
2742         if (ret) {
2743                 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n");
2744                 return;
2745         }
2746
2747         crtc_state->infoframes.enable |=
2748                 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA);
2749 }
2750
2751 static void
2752 intel_dp_drrs_compute_config(struct intel_dp *intel_dp,
2753                              struct intel_crtc_state *pipe_config,
2754                              int output_bpp, bool constant_n)
2755 {
2756         struct intel_connector *intel_connector = intel_dp->attached_connector;
2757         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2758
2759         /*
2760          * DRRS and PSR can't be enable together, so giving preference to PSR
2761          * as it allows more power-savings by complete shutting down display,
2762          * so to guarantee this, intel_dp_drrs_compute_config() must be called
2763          * after intel_psr_compute_config().
2764          */
2765         if (pipe_config->has_psr)
2766                 return;
2767
2768         if (!intel_connector->panel.downclock_mode ||
2769             dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
2770                 return;
2771
2772         pipe_config->has_drrs = true;
2773         intel_link_compute_m_n(output_bpp, pipe_config->lane_count,
2774                                intel_connector->panel.downclock_mode->clock,
2775                                pipe_config->port_clock, &pipe_config->dp_m2_n2,
2776                                constant_n, pipe_config->fec_enable);
2777 }
2778
2779 int
2780 intel_dp_compute_config(struct intel_encoder *encoder,
2781                         struct intel_crtc_state *pipe_config,
2782                         struct drm_connector_state *conn_state)
2783 {
2784         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2785         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2786         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2787         enum port port = encoder->port;
2788         struct intel_connector *intel_connector = intel_dp->attached_connector;
2789         struct intel_digital_connector_state *intel_conn_state =
2790                 to_intel_digital_connector_state(conn_state);
2791         bool constant_n = drm_dp_has_quirk(&intel_dp->desc, 0,
2792                                            DP_DPCD_QUIRK_CONSTANT_N);
2793         int ret = 0, output_bpp;
2794
2795         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
2796                 pipe_config->has_pch_encoder = true;
2797
2798         pipe_config->output_format = intel_dp_output_format(&intel_connector->base,
2799                                                             adjusted_mode);
2800
2801         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
2802                 ret = intel_pch_panel_fitting(pipe_config, conn_state);
2803                 if (ret)
2804                         return ret;
2805         }
2806
2807         if (!intel_dp_port_has_audio(dev_priv, port))
2808                 pipe_config->has_audio = false;
2809         else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2810                 pipe_config->has_audio = intel_dp->has_audio;
2811         else
2812                 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON;
2813
2814         if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2815                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
2816                                        adjusted_mode);
2817
2818                 if (HAS_GMCH(dev_priv))
2819                         ret = intel_gmch_panel_fitting(pipe_config, conn_state);
2820                 else
2821                         ret = intel_pch_panel_fitting(pipe_config, conn_state);
2822                 if (ret)
2823                         return ret;
2824         }
2825
2826         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2827                 return -EINVAL;
2828
2829         if (HAS_GMCH(dev_priv) &&
2830             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2831                 return -EINVAL;
2832
2833         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2834                 return -EINVAL;
2835
2836         if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay))
2837                 return -EINVAL;
2838
2839         ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state);
2840         if (ret < 0)
2841                 return ret;
2842
2843         pipe_config->limited_color_range =
2844                 intel_dp_limited_color_range(pipe_config, conn_state);
2845
2846         if (pipe_config->dsc.compression_enable)
2847                 output_bpp = pipe_config->dsc.compressed_bpp;
2848         else
2849                 output_bpp = intel_dp_output_bpp(pipe_config->output_format,
2850                                                  pipe_config->pipe_bpp);
2851
2852         intel_link_compute_m_n(output_bpp,
2853                                pipe_config->lane_count,
2854                                adjusted_mode->crtc_clock,
2855                                pipe_config->port_clock,
2856                                &pipe_config->dp_m_n,
2857                                constant_n, pipe_config->fec_enable);
2858
2859         if (!HAS_DDI(dev_priv))
2860                 intel_dp_set_clock(encoder, pipe_config);
2861
2862         intel_psr_compute_config(intel_dp, pipe_config);
2863         intel_dp_drrs_compute_config(intel_dp, pipe_config, output_bpp,
2864                                      constant_n);
2865         intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
2866         intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
2867
2868         return 0;
2869 }
2870
2871 void intel_dp_set_link_params(struct intel_dp *intel_dp,
2872                               int link_rate, int lane_count)
2873 {
2874         intel_dp->link_trained = false;
2875         intel_dp->link_rate = link_rate;
2876         intel_dp->lane_count = lane_count;
2877 }
2878
2879 static void intel_dp_prepare(struct intel_encoder *encoder,
2880                              const struct intel_crtc_state *pipe_config)
2881 {
2882         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2883         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2884         enum port port = encoder->port;
2885         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2886         const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2887
2888         intel_dp_set_link_params(intel_dp,
2889                                  pipe_config->port_clock,
2890                                  pipe_config->lane_count);
2891
2892         /*
2893          * There are four kinds of DP registers:
2894          *
2895          *      IBX PCH
2896          *      SNB CPU
2897          *      IVB CPU
2898          *      CPT PCH
2899          *
2900          * IBX PCH and CPU are the same for almost everything,
2901          * except that the CPU DP PLL is configured in this
2902          * register
2903          *
2904          * CPT PCH is quite different, having many bits moved
2905          * to the TRANS_DP_CTL register instead. That
2906          * configuration happens (oddly) in ilk_pch_enable
2907          */
2908
2909         /* Preserve the BIOS-computed detected bit. This is
2910          * supposed to be read-only.
2911          */
2912         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
2913
2914         /* Handle DP bits in common between all three register formats */
2915         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
2916         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
2917
2918         /* Split out the IBX/CPU vs CPT settings */
2919
2920         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
2921                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2922                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2923                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2924                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2925                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2926
2927                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2928                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2929
2930                 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
2931         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2932                 u32 trans_dp;
2933
2934                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
2935
2936                 trans_dp = intel_de_read(dev_priv, TRANS_DP_CTL(crtc->pipe));
2937                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2938                         trans_dp |= TRANS_DP_ENH_FRAMING;
2939                 else
2940                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
2941                 intel_de_write(dev_priv, TRANS_DP_CTL(crtc->pipe), trans_dp);
2942         } else {
2943                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
2944                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
2945
2946                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
2947                         intel_dp->DP |= DP_SYNC_HS_HIGH;
2948                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
2949                         intel_dp->DP |= DP_SYNC_VS_HIGH;
2950                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
2951
2952                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2953                         intel_dp->DP |= DP_ENHANCED_FRAMING;
2954
2955                 if (IS_CHERRYVIEW(dev_priv))
2956                         intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
2957                 else
2958                         intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
2959         }
2960 }
2961
2962 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
2963 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
2964
2965 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
2966 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
2967
2968 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
2969 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
2970
2971 static void intel_pps_verify_state(struct intel_dp *intel_dp);
2972
2973 static void wait_panel_status(struct intel_dp *intel_dp,
2974                                        u32 mask,
2975                                        u32 value)
2976 {
2977         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
2978         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2979
2980         lockdep_assert_held(&dev_priv->pps_mutex);
2981
2982         intel_pps_verify_state(intel_dp);
2983
2984         pp_stat_reg = _pp_stat_reg(intel_dp);
2985         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2986
2987         drm_dbg_kms(&dev_priv->drm,
2988                     "mask %08x value %08x status %08x control %08x\n",
2989                     mask, value,
2990                     intel_de_read(dev_priv, pp_stat_reg),
2991                     intel_de_read(dev_priv, pp_ctrl_reg));
2992
2993         if (intel_de_wait_for_register(dev_priv, pp_stat_reg,
2994                                        mask, value, 5000))
2995                 drm_err(&dev_priv->drm,
2996                         "Panel status timeout: status %08x control %08x\n",
2997                         intel_de_read(dev_priv, pp_stat_reg),
2998                         intel_de_read(dev_priv, pp_ctrl_reg));
2999
3000         drm_dbg_kms(&dev_priv->drm, "Wait complete\n");
3001 }
3002
3003 static void wait_panel_on(struct intel_dp *intel_dp)
3004 {
3005         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3006
3007         drm_dbg_kms(&i915->drm, "Wait for panel power on\n");
3008         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
3009 }
3010
3011 static void wait_panel_off(struct intel_dp *intel_dp)
3012 {
3013         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3014
3015         drm_dbg_kms(&i915->drm, "Wait for panel power off time\n");
3016         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
3017 }
3018
3019 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
3020 {
3021         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3022         ktime_t panel_power_on_time;
3023         s64 panel_power_off_duration;
3024
3025         drm_dbg_kms(&i915->drm, "Wait for panel power cycle\n");
3026
3027         /* take the difference of currrent time and panel power off time
3028          * and then make panel wait for t11_t12 if needed. */
3029         panel_power_on_time = ktime_get_boottime();
3030         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
3031
3032         /* When we disable the VDD override bit last we have to do the manual
3033          * wait. */
3034         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
3035                 wait_remaining_ms_from_jiffies(jiffies,
3036                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
3037
3038         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
3039 }
3040
3041 static void wait_backlight_on(struct intel_dp *intel_dp)
3042 {
3043         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
3044                                        intel_dp->backlight_on_delay);
3045 }
3046
3047 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
3048 {
3049         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
3050                                        intel_dp->backlight_off_delay);
3051 }
3052
3053 /* Read the current pp_control value, unlocking the register if it
3054  * is locked
3055  */
3056
3057 static  u32 ilk_get_pp_control(struct intel_dp *intel_dp)
3058 {
3059         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3060         u32 control;
3061
3062         lockdep_assert_held(&dev_priv->pps_mutex);
3063
3064         control = intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp));
3065         if (drm_WARN_ON(&dev_priv->drm, !HAS_DDI(dev_priv) &&
3066                         (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
3067                 control &= ~PANEL_UNLOCK_MASK;
3068                 control |= PANEL_UNLOCK_REGS;
3069         }
3070         return control;
3071 }
3072
3073 /*
3074  * Must be paired with edp_panel_vdd_off().
3075  * Must hold pps_mutex around the whole on/off sequence.
3076  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
3077  */
3078 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
3079 {
3080         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3081         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3082         u32 pp;
3083         i915_reg_t pp_stat_reg, pp_ctrl_reg;
3084         bool need_to_disable = !intel_dp->want_panel_vdd;
3085
3086         lockdep_assert_held(&dev_priv->pps_mutex);
3087
3088         if (!intel_dp_is_edp(intel_dp))
3089                 return false;
3090
3091         cancel_delayed_work(&intel_dp->panel_vdd_work);
3092         intel_dp->want_panel_vdd = true;
3093
3094         if (edp_have_panel_vdd(intel_dp))
3095                 return need_to_disable;
3096
3097         intel_display_power_get(dev_priv,
3098                                 intel_aux_power_domain(dig_port));
3099
3100         drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD on\n",
3101                     dig_port->base.base.base.id,
3102                     dig_port->base.base.name);
3103
3104         if (!edp_have_panel_power(intel_dp))
3105                 wait_panel_power_cycle(intel_dp);
3106
3107         pp = ilk_get_pp_control(intel_dp);
3108         pp |= EDP_FORCE_VDD;
3109
3110         pp_stat_reg = _pp_stat_reg(intel_dp);
3111         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3112
3113         intel_de_write(dev_priv, pp_ctrl_reg, pp);
3114         intel_de_posting_read(dev_priv, pp_ctrl_reg);
3115         drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
3116                     intel_de_read(dev_priv, pp_stat_reg),
3117                     intel_de_read(dev_priv, pp_ctrl_reg));
3118         /*
3119          * If the panel wasn't on, delay before accessing aux channel
3120          */
3121         if (!edp_have_panel_power(intel_dp)) {
3122                 drm_dbg_kms(&dev_priv->drm,
3123                             "[ENCODER:%d:%s] panel power wasn't enabled\n",
3124                             dig_port->base.base.base.id,
3125                             dig_port->base.base.name);
3126                 msleep(intel_dp->panel_power_up_delay);
3127         }
3128
3129         return need_to_disable;
3130 }
3131
3132 /*
3133  * Must be paired with intel_edp_panel_vdd_off() or
3134  * intel_edp_panel_off().
3135  * Nested calls to these functions are not allowed since
3136  * we drop the lock. Caller must use some higher level
3137  * locking to prevent nested calls from other threads.
3138  */
3139 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
3140 {
3141         intel_wakeref_t wakeref;
3142         bool vdd;
3143
3144         if (!intel_dp_is_edp(intel_dp))
3145                 return;
3146
3147         vdd = false;
3148         with_pps_lock(intel_dp, wakeref)
3149                 vdd = edp_panel_vdd_on(intel_dp);
3150         I915_STATE_WARN(!vdd, "[ENCODER:%d:%s] VDD already requested on\n",
3151                         dp_to_dig_port(intel_dp)->base.base.base.id,
3152                         dp_to_dig_port(intel_dp)->base.base.name);
3153 }
3154
3155 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
3156 {
3157         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3158         struct intel_digital_port *dig_port =
3159                 dp_to_dig_port(intel_dp);
3160         u32 pp;
3161         i915_reg_t pp_stat_reg, pp_ctrl_reg;
3162
3163         lockdep_assert_held(&dev_priv->pps_mutex);
3164
3165         drm_WARN_ON(&dev_priv->drm, intel_dp->want_panel_vdd);
3166
3167         if (!edp_have_panel_vdd(intel_dp))
3168                 return;
3169
3170         drm_dbg_kms(&dev_priv->drm, "Turning [ENCODER:%d:%s] VDD off\n",
3171                     dig_port->base.base.base.id,
3172                     dig_port->base.base.name);
3173
3174         pp = ilk_get_pp_control(intel_dp);
3175         pp &= ~EDP_FORCE_VDD;
3176
3177         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3178         pp_stat_reg = _pp_stat_reg(intel_dp);
3179
3180         intel_de_write(dev_priv, pp_ctrl_reg, pp);
3181         intel_de_posting_read(dev_priv, pp_ctrl_reg);
3182
3183         /* Make sure sequencer is idle before allowing subsequent activity */
3184         drm_dbg_kms(&dev_priv->drm, "PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
3185                     intel_de_read(dev_priv, pp_stat_reg),
3186                     intel_de_read(dev_priv, pp_ctrl_reg));
3187
3188         if ((pp & PANEL_POWER_ON) == 0)
3189                 intel_dp->panel_power_off_time = ktime_get_boottime();
3190
3191         intel_display_power_put_unchecked(dev_priv,
3192                                           intel_aux_power_domain(dig_port));
3193 }
3194
3195 static void edp_panel_vdd_work(struct work_struct *__work)
3196 {
3197         struct intel_dp *intel_dp =
3198                 container_of(to_delayed_work(__work),
3199                              struct intel_dp, panel_vdd_work);
3200         intel_wakeref_t wakeref;
3201
3202         with_pps_lock(intel_dp, wakeref) {
3203                 if (!intel_dp->want_panel_vdd)
3204                         edp_panel_vdd_off_sync(intel_dp);
3205         }
3206 }
3207
3208 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
3209 {
3210         unsigned long delay;
3211
3212         /*
3213          * Queue the timer to fire a long time from now (relative to the power
3214          * down delay) to keep the panel power up across a sequence of
3215          * operations.
3216          */
3217         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
3218         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
3219 }
3220
3221 /*
3222  * Must be paired with edp_panel_vdd_on().
3223  * Must hold pps_mutex around the whole on/off sequence.
3224  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
3225  */
3226 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
3227 {
3228         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3229
3230         lockdep_assert_held(&dev_priv->pps_mutex);
3231
3232         if (!intel_dp_is_edp(intel_dp))
3233                 return;
3234
3235         I915_STATE_WARN(!intel_dp->want_panel_vdd, "[ENCODER:%d:%s] VDD not forced on",
3236                         dp_to_dig_port(intel_dp)->base.base.base.id,
3237                         dp_to_dig_port(intel_dp)->base.base.name);
3238
3239         intel_dp->want_panel_vdd = false;
3240
3241         if (sync)
3242                 edp_panel_vdd_off_sync(intel_dp);
3243         else
3244                 edp_panel_vdd_schedule_off(intel_dp);
3245 }
3246
3247 static void edp_panel_on(struct intel_dp *intel_dp)
3248 {
3249         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3250         u32 pp;
3251         i915_reg_t pp_ctrl_reg;
3252
3253         lockdep_assert_held(&dev_priv->pps_mutex);
3254
3255         if (!intel_dp_is_edp(intel_dp))
3256                 return;
3257
3258         drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power on\n",
3259                     dp_to_dig_port(intel_dp)->base.base.base.id,
3260                     dp_to_dig_port(intel_dp)->base.base.name);
3261
3262         if (drm_WARN(&dev_priv->drm, edp_have_panel_power(intel_dp),
3263                      "[ENCODER:%d:%s] panel power already on\n",
3264                      dp_to_dig_port(intel_dp)->base.base.base.id,
3265                      dp_to_dig_port(intel_dp)->base.base.name))
3266                 return;
3267
3268         wait_panel_power_cycle(intel_dp);
3269
3270         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3271         pp = ilk_get_pp_control(intel_dp);
3272         if (IS_GEN(dev_priv, 5)) {
3273                 /* ILK workaround: disable reset around power sequence */
3274                 pp &= ~PANEL_POWER_RESET;
3275                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3276                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3277         }
3278
3279         pp |= PANEL_POWER_ON;
3280         if (!IS_GEN(dev_priv, 5))
3281                 pp |= PANEL_POWER_RESET;
3282
3283         intel_de_write(dev_priv, pp_ctrl_reg, pp);
3284         intel_de_posting_read(dev_priv, pp_ctrl_reg);
3285
3286         wait_panel_on(intel_dp);
3287         intel_dp->last_power_on = jiffies;
3288
3289         if (IS_GEN(dev_priv, 5)) {
3290                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
3291                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3292                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3293         }
3294 }
3295
3296 void intel_edp_panel_on(struct intel_dp *intel_dp)
3297 {
3298         intel_wakeref_t wakeref;
3299
3300         if (!intel_dp_is_edp(intel_dp))
3301                 return;
3302
3303         with_pps_lock(intel_dp, wakeref)
3304                 edp_panel_on(intel_dp);
3305 }
3306
3307
3308 static void edp_panel_off(struct intel_dp *intel_dp)
3309 {
3310         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3311         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3312         u32 pp;
3313         i915_reg_t pp_ctrl_reg;
3314
3315         lockdep_assert_held(&dev_priv->pps_mutex);
3316
3317         if (!intel_dp_is_edp(intel_dp))
3318                 return;
3319
3320         drm_dbg_kms(&dev_priv->drm, "Turn [ENCODER:%d:%s] panel power off\n",
3321                     dig_port->base.base.base.id, dig_port->base.base.name);
3322
3323         drm_WARN(&dev_priv->drm, !intel_dp->want_panel_vdd,
3324                  "Need [ENCODER:%d:%s] VDD to turn off panel\n",
3325                  dig_port->base.base.base.id, dig_port->base.base.name);
3326
3327         pp = ilk_get_pp_control(intel_dp);
3328         /* We need to switch off panel power _and_ force vdd, for otherwise some
3329          * panels get very unhappy and cease to work. */
3330         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
3331                 EDP_BLC_ENABLE);
3332
3333         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3334
3335         intel_dp->want_panel_vdd = false;
3336
3337         intel_de_write(dev_priv, pp_ctrl_reg, pp);
3338         intel_de_posting_read(dev_priv, pp_ctrl_reg);
3339
3340         wait_panel_off(intel_dp);
3341         intel_dp->panel_power_off_time = ktime_get_boottime();
3342
3343         /* We got a reference when we enabled the VDD. */
3344         intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port));
3345 }
3346
3347 void intel_edp_panel_off(struct intel_dp *intel_dp)
3348 {
3349         intel_wakeref_t wakeref;
3350
3351         if (!intel_dp_is_edp(intel_dp))
3352                 return;
3353
3354         with_pps_lock(intel_dp, wakeref)
3355                 edp_panel_off(intel_dp);
3356 }
3357
3358 /* Enable backlight in the panel power control. */
3359 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
3360 {
3361         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3362         intel_wakeref_t wakeref;
3363
3364         /*
3365          * If we enable the backlight right away following a panel power
3366          * on, we may see slight flicker as the panel syncs with the eDP
3367          * link.  So delay a bit to make sure the image is solid before
3368          * allowing it to appear.
3369          */
3370         wait_backlight_on(intel_dp);
3371
3372         with_pps_lock(intel_dp, wakeref) {
3373                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3374                 u32 pp;
3375
3376                 pp = ilk_get_pp_control(intel_dp);
3377                 pp |= EDP_BLC_ENABLE;
3378
3379                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3380                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3381         }
3382 }
3383
3384 /* Enable backlight PWM and backlight PP control. */
3385 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
3386                             const struct drm_connector_state *conn_state)
3387 {
3388         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));
3389         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3390
3391         if (!intel_dp_is_edp(intel_dp))
3392                 return;
3393
3394         drm_dbg_kms(&i915->drm, "\n");
3395
3396         intel_panel_enable_backlight(crtc_state, conn_state);
3397         _intel_edp_backlight_on(intel_dp);
3398 }
3399
3400 /* Disable backlight in the panel power control. */
3401 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
3402 {
3403         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3404         intel_wakeref_t wakeref;
3405
3406         if (!intel_dp_is_edp(intel_dp))
3407                 return;
3408
3409         with_pps_lock(intel_dp, wakeref) {
3410                 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
3411                 u32 pp;
3412
3413                 pp = ilk_get_pp_control(intel_dp);
3414                 pp &= ~EDP_BLC_ENABLE;
3415
3416                 intel_de_write(dev_priv, pp_ctrl_reg, pp);
3417                 intel_de_posting_read(dev_priv, pp_ctrl_reg);
3418         }
3419
3420         intel_dp->last_backlight_off = jiffies;
3421         edp_wait_backlight_off(intel_dp);
3422 }
3423
3424 /* Disable backlight PP control and backlight PWM. */
3425 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)
3426 {
3427         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));
3428         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3429
3430         if (!intel_dp_is_edp(intel_dp))
3431                 return;
3432
3433         drm_dbg_kms(&i915->drm, "\n");
3434
3435         _intel_edp_backlight_off(intel_dp);
3436         intel_panel_disable_backlight(old_conn_state);
3437 }
3438
3439 /*
3440  * Hook for controlling the panel power control backlight through the bl_power
3441  * sysfs attribute. Take care to handle multiple calls.
3442  */
3443 static void intel_edp_backlight_power(struct intel_connector *connector,
3444                                       bool enable)
3445 {
3446         struct drm_i915_private *i915 = to_i915(connector->base.dev);
3447         struct intel_dp *intel_dp = intel_attached_dp(connector);
3448         intel_wakeref_t wakeref;
3449         bool is_enabled;
3450
3451         is_enabled = false;
3452         with_pps_lock(intel_dp, wakeref)
3453                 is_enabled = ilk_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
3454         if (is_enabled == enable)
3455                 return;
3456
3457         drm_dbg_kms(&i915->drm, "panel power control backlight %s\n",
3458                     enable ? "enable" : "disable");
3459
3460         if (enable)
3461                 _intel_edp_backlight_on(intel_dp);
3462         else
3463                 _intel_edp_backlight_off(intel_dp);
3464 }
3465
3466 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
3467 {
3468         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3469         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3470         bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN;
3471
3472         I915_STATE_WARN(cur_state != state,
3473                         "[ENCODER:%d:%s] state assertion failure (expected %s, current %s)\n",
3474                         dig_port->base.base.base.id, dig_port->base.base.name,
3475                         onoff(state), onoff(cur_state));
3476 }
3477 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
3478
3479 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
3480 {
3481         bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE;
3482
3483         I915_STATE_WARN(cur_state != state,
3484                         "eDP PLL state assertion failure (expected %s, current %s)\n",
3485                         onoff(state), onoff(cur_state));
3486 }
3487 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
3488 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
3489
3490 static void ilk_edp_pll_on(struct intel_dp *intel_dp,
3491                            const struct intel_crtc_state *pipe_config)
3492 {
3493         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3494         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3495
3496         assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder);
3497         assert_dp_port_disabled(intel_dp);
3498         assert_edp_pll_disabled(dev_priv);
3499
3500         drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n",
3501                     pipe_config->port_clock);
3502
3503         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
3504
3505         if (pipe_config->port_clock == 162000)
3506                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
3507         else
3508                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
3509
3510         intel_de_write(dev_priv, DP_A, intel_dp->DP);
3511         intel_de_posting_read(dev_priv, DP_A);
3512         udelay(500);
3513
3514         /*
3515          * [DevILK] Work around required when enabling DP PLL
3516          * while a pipe is enabled going to FDI:
3517          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
3518          * 2. Program DP PLL enable
3519          */
3520         if (IS_GEN(dev_priv, 5))
3521                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
3522
3523         intel_dp->DP |= DP_PLL_ENABLE;
3524
3525         intel_de_write(dev_priv, DP_A, intel_dp->DP);
3526         intel_de_posting_read(dev_priv, DP_A);
3527         udelay(200);
3528 }
3529
3530 static void ilk_edp_pll_off(struct intel_dp *intel_dp,
3531                             const struct intel_crtc_state *old_crtc_state)
3532 {
3533         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
3534         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3535
3536         assert_pipe_disabled(dev_priv, old_crtc_state->cpu_transcoder);
3537         assert_dp_port_disabled(intel_dp);
3538         assert_edp_pll_enabled(dev_priv);
3539
3540         drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n");
3541
3542         intel_dp->DP &= ~DP_PLL_ENABLE;
3543
3544         intel_de_write(dev_priv, DP_A, intel_dp->DP);
3545         intel_de_posting_read(dev_priv, DP_A);
3546         udelay(200);
3547 }
3548
3549 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp)
3550 {
3551         /*
3552          * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus
3553          * be capable of signalling downstream hpd with a long pulse.
3554          * Whether or not that means D3 is safe to use is not clear,
3555          * but let's assume so until proven otherwise.
3556          *
3557          * FIXME should really check all downstream ports...
3558          */
3559         return intel_dp->dpcd[DP_DPCD_REV] == 0x11 &&
3560                 drm_dp_is_branch(intel_dp->dpcd) &&
3561                 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD;
3562 }
3563
3564 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
3565                                            const struct intel_crtc_state *crtc_state,
3566                                            bool enable)
3567 {
3568         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3569         int ret;
3570
3571         if (!crtc_state->dsc.compression_enable)
3572                 return;
3573
3574         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
3575                                  enable ? DP_DECOMPRESSION_EN : 0);
3576         if (ret < 0)
3577                 drm_dbg_kms(&i915->drm,
3578                             "Failed to %s sink decompression state\n",
3579                             enable ? "enable" : "disable");
3580 }
3581
3582 /* If the device supports it, try to set the power state appropriately */
3583 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)
3584 {
3585         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3586         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3587         int ret, i;
3588
3589         /* Should have a valid DPCD by this point */
3590         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
3591                 return;
3592
3593         if (mode != DP_SET_POWER_D0) {
3594                 if (downstream_hpd_needs_d0(intel_dp))
3595                         return;
3596
3597                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3598         } else {
3599                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
3600
3601                 lspcon_resume(dp_to_dig_port(intel_dp));
3602
3603                 /*
3604                  * When turning on, we need to retry for 1ms to give the sink
3605                  * time to wake up.
3606                  */
3607                 for (i = 0; i < 3; i++) {
3608                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);
3609                         if (ret == 1)
3610                                 break;
3611                         msleep(1);
3612                 }
3613
3614                 if (ret == 1 && lspcon->active)
3615                         lspcon_wait_pcon_mode(lspcon);
3616         }
3617
3618         if (ret != 1)
3619                 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n",
3620                             encoder->base.base.id, encoder->base.name,
3621                             mode == DP_SET_POWER_D0 ? "D0" : "D3");
3622 }
3623
3624 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv,
3625                                  enum port port, enum pipe *pipe)
3626 {
3627         enum pipe p;
3628
3629         for_each_pipe(dev_priv, p) {
3630                 u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p));
3631
3632                 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) {
3633                         *pipe = p;
3634                         return true;
3635                 }
3636         }
3637
3638         drm_dbg_kms(&dev_priv->drm, "No pipe for DP port %c found\n",
3639                     port_name(port));
3640
3641         /* must initialize pipe to something for the asserts */
3642         *pipe = PIPE_A;
3643
3644         return false;
3645 }
3646
3647 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
3648                            i915_reg_t dp_reg, enum port port,
3649                            enum pipe *pipe)
3650 {
3651         bool ret;
3652         u32 val;
3653
3654         val = intel_de_read(dev_priv, dp_reg);
3655
3656         ret = val & DP_PORT_EN;
3657
3658         /* asserts want to know the pipe even if the port is disabled */
3659         if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
3660                 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB;
3661         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3662                 ret &= cpt_dp_port_selected(dev_priv, port, pipe);
3663         else if (IS_CHERRYVIEW(dev_priv))
3664                 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV;
3665         else
3666                 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT;
3667
3668         return ret;
3669 }
3670
3671 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
3672                                   enum pipe *pipe)
3673 {
3674         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3675         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3676         intel_wakeref_t wakeref;
3677         bool ret;
3678
3679         wakeref = intel_display_power_get_if_enabled(dev_priv,
3680                                                      encoder->power_domain);
3681         if (!wakeref)
3682                 return false;
3683
3684         ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
3685                                     encoder->port, pipe);
3686
3687         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
3688
3689         return ret;
3690 }
3691
3692 static void intel_dp_get_config(struct intel_encoder *encoder,
3693                                 struct intel_crtc_state *pipe_config)
3694 {
3695         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3696         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3697         u32 tmp, flags = 0;
3698         enum port port = encoder->port;
3699         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3700
3701         if (encoder->type == INTEL_OUTPUT_EDP)
3702                 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3703         else
3704                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3705
3706         tmp = intel_de_read(dev_priv, intel_dp->output_reg);
3707
3708         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
3709
3710         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
3711                 u32 trans_dp = intel_de_read(dev_priv,
3712                                              TRANS_DP_CTL(crtc->pipe));
3713
3714                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
3715                         flags |= DRM_MODE_FLAG_PHSYNC;
3716                 else
3717                         flags |= DRM_MODE_FLAG_NHSYNC;
3718
3719                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
3720                         flags |= DRM_MODE_FLAG_PVSYNC;
3721                 else
3722                         flags |= DRM_MODE_FLAG_NVSYNC;
3723         } else {
3724                 if (tmp & DP_SYNC_HS_HIGH)
3725                         flags |= DRM_MODE_FLAG_PHSYNC;
3726                 else
3727                         flags |= DRM_MODE_FLAG_NHSYNC;
3728
3729                 if (tmp & DP_SYNC_VS_HIGH)
3730                         flags |= DRM_MODE_FLAG_PVSYNC;
3731                 else
3732                         flags |= DRM_MODE_FLAG_NVSYNC;
3733         }
3734
3735         pipe_config->hw.adjusted_mode.flags |= flags;
3736
3737         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
3738                 pipe_config->limited_color_range = true;
3739
3740         pipe_config->lane_count =
3741                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
3742
3743         intel_dp_get_m_n(crtc, pipe_config);
3744
3745         if (port == PORT_A) {
3746                 if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
3747                         pipe_config->port_clock = 162000;
3748                 else
3749                         pipe_config->port_clock = 270000;
3750         }
3751
3752         pipe_config->hw.adjusted_mode.crtc_clock =
3753                 intel_dotclock_calculate(pipe_config->port_clock,
3754                                          &pipe_config->dp_m_n);
3755
3756         if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
3757             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
3758                 /*
3759                  * This is a big fat ugly hack.
3760                  *
3761                  * Some machines in UEFI boot mode provide us a VBT that has 18
3762                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
3763                  * unknown we fail to light up. Yet the same BIOS boots up with
3764                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
3765                  * max, not what it tells us to use.
3766                  *
3767                  * Note: This will still be broken if the eDP panel is not lit
3768                  * up by the BIOS, and thus we can't get the mode at module
3769                  * load.
3770                  */
3771                 drm_dbg_kms(&dev_priv->drm,
3772                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
3773                             pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
3774                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
3775         }
3776 }
3777
3778 static bool
3779 intel_dp_get_dpcd(struct intel_dp *intel_dp);
3780
3781 /**
3782  * intel_dp_sync_state - sync the encoder state during init/resume
3783  * @encoder: intel encoder to sync
3784  * @crtc_state: state for the CRTC connected to the encoder
3785  *
3786  * Sync any state stored in the encoder wrt. HW state during driver init
3787  * and system resume.
3788  */
3789 void intel_dp_sync_state(struct intel_encoder *encoder,
3790                          const struct intel_crtc_state *crtc_state)
3791 {
3792         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3793
3794         /*
3795          * Don't clobber DPCD if it's been already read out during output
3796          * setup (eDP) or detect.
3797          */
3798         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3799                 intel_dp_get_dpcd(intel_dp);
3800
3801         intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
3802         intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
3803 }
3804
3805 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
3806                                     struct intel_crtc_state *crtc_state)
3807 {
3808         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3809         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3810
3811         /*
3812          * If BIOS has set an unsupported or non-standard link rate for some
3813          * reason force an encoder recompute and full modeset.
3814          */
3815         if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,
3816                                 crtc_state->port_clock) < 0) {
3817                 drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n");
3818                 crtc_state->uapi.connectors_changed = true;
3819                 return false;
3820         }
3821
3822         /*
3823          * FIXME hack to force full modeset when DSC is being used.
3824          *
3825          * As long as we do not have full state readout and config comparison
3826          * of crtc_state->dsc, we have no way to ensure reliable fastset.
3827          * Remove once we have readout for DSC.
3828          */
3829         if (crtc_state->dsc.compression_enable) {
3830                 drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n");
3831                 crtc_state->uapi.mode_changed = true;
3832                 return false;
3833         }
3834
3835         if (CAN_PSR(i915) && intel_dp_is_edp(intel_dp)) {
3836                 drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n");
3837                 crtc_state->uapi.mode_changed = true;
3838                 return false;
3839         }
3840
3841         return true;
3842 }
3843
3844 static void intel_disable_dp(struct intel_atomic_state *state,
3845                              struct intel_encoder *encoder,
3846                              const struct intel_crtc_state *old_crtc_state,
3847                              const struct drm_connector_state *old_conn_state)
3848 {
3849         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3850
3851         intel_dp->link_trained = false;
3852
3853         if (old_crtc_state->has_audio)
3854                 intel_audio_codec_disable(encoder,
3855                                           old_crtc_state, old_conn_state);
3856
3857         /* Make sure the panel is off before trying to change the mode. But also
3858          * ensure that we have vdd while we switch off the panel. */
3859         intel_edp_panel_vdd_on(intel_dp);
3860         intel_edp_backlight_off(old_conn_state);
3861         intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
3862         intel_edp_panel_off(intel_dp);
3863 }
3864
3865 static void g4x_disable_dp(struct intel_atomic_state *state,
3866                            struct intel_encoder *encoder,
3867                            const struct intel_crtc_state *old_crtc_state,
3868                            const struct drm_connector_state *old_conn_state)
3869 {
3870         intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
3871 }
3872
3873 static void vlv_disable_dp(struct intel_atomic_state *state,
3874                            struct intel_encoder *encoder,
3875                            const struct intel_crtc_state *old_crtc_state,
3876                            const struct drm_connector_state *old_conn_state)
3877 {
3878         intel_disable_dp(state, encoder, old_crtc_state, old_conn_state);
3879 }
3880
3881 static void g4x_post_disable_dp(struct intel_atomic_state *state,
3882                                 struct intel_encoder *encoder,
3883                                 const struct intel_crtc_state *old_crtc_state,
3884                                 const struct drm_connector_state *old_conn_state)
3885 {
3886         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3887         enum port port = encoder->port;
3888
3889         /*
3890          * Bspec does not list a specific disable sequence for g4x DP.
3891          * Follow the ilk+ sequence (disable pipe before the port) for
3892          * g4x DP as it does not suffer from underruns like the normal
3893          * g4x modeset sequence (disable pipe after the port).
3894          */
3895         intel_dp_link_down(encoder, old_crtc_state);
3896
3897         /* Only ilk+ has port A */
3898         if (port == PORT_A)
3899                 ilk_edp_pll_off(intel_dp, old_crtc_state);
3900 }
3901
3902 static void vlv_post_disable_dp(struct intel_atomic_state *state,
3903                                 struct intel_encoder *encoder,
3904                                 const struct intel_crtc_state *old_crtc_state,
3905                                 const struct drm_connector_state *old_conn_state)
3906 {
3907         intel_dp_link_down(encoder, old_crtc_state);
3908 }
3909
3910 static void chv_post_disable_dp(struct intel_atomic_state *state,
3911                                 struct intel_encoder *encoder,
3912                                 const struct intel_crtc_state *old_crtc_state,
3913                                 const struct drm_connector_state *old_conn_state)
3914 {
3915         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3916
3917         intel_dp_link_down(encoder, old_crtc_state);
3918
3919         vlv_dpio_get(dev_priv);
3920
3921         /* Assert data lane reset */
3922         chv_data_lane_soft_reset(encoder, old_crtc_state, true);
3923
3924         vlv_dpio_put(dev_priv);
3925 }
3926
3927 static void
3928 cpt_set_link_train(struct intel_dp *intel_dp,
3929                    const struct intel_crtc_state *crtc_state,
3930                    u8 dp_train_pat)
3931 {
3932         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3933         u32 *DP = &intel_dp->DP;
3934
3935         *DP &= ~DP_LINK_TRAIN_MASK_CPT;
3936
3937         switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
3938         case DP_TRAINING_PATTERN_DISABLE:
3939                 *DP |= DP_LINK_TRAIN_OFF_CPT;
3940                 break;
3941         case DP_TRAINING_PATTERN_1:
3942                 *DP |= DP_LINK_TRAIN_PAT_1_CPT;
3943                 break;
3944         case DP_TRAINING_PATTERN_2:
3945                 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3946                 break;
3947         case DP_TRAINING_PATTERN_3:
3948                 drm_dbg_kms(&dev_priv->drm,
3949                             "TPS3 not supported, using TPS2 instead\n");
3950                 *DP |= DP_LINK_TRAIN_PAT_2_CPT;
3951                 break;
3952         }
3953
3954         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
3955         intel_de_posting_read(dev_priv, intel_dp->output_reg);
3956 }
3957
3958 static void
3959 g4x_set_link_train(struct intel_dp *intel_dp,
3960                    const struct intel_crtc_state *crtc_state,
3961                    u8 dp_train_pat)
3962 {
3963         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3964         u32 *DP = &intel_dp->DP;
3965
3966         *DP &= ~DP_LINK_TRAIN_MASK;
3967
3968         switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
3969         case DP_TRAINING_PATTERN_DISABLE:
3970                 *DP |= DP_LINK_TRAIN_OFF;
3971                 break;
3972         case DP_TRAINING_PATTERN_1:
3973                 *DP |= DP_LINK_TRAIN_PAT_1;
3974                 break;
3975         case DP_TRAINING_PATTERN_2:
3976                 *DP |= DP_LINK_TRAIN_PAT_2;
3977                 break;
3978         case DP_TRAINING_PATTERN_3:
3979                 drm_dbg_kms(&dev_priv->drm,
3980                             "TPS3 not supported, using TPS2 instead\n");
3981                 *DP |= DP_LINK_TRAIN_PAT_2;
3982                 break;
3983         }
3984
3985         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
3986         intel_de_posting_read(dev_priv, intel_dp->output_reg);
3987 }
3988
3989 static void intel_dp_enable_port(struct intel_dp *intel_dp,
3990                                  const struct intel_crtc_state *crtc_state)
3991 {
3992         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
3993
3994         /* enable with pattern 1 (as per spec) */
3995
3996         intel_dp_program_link_training_pattern(intel_dp, crtc_state,
3997                                                DP_TRAINING_PATTERN_1);
3998
3999         /*
4000          * Magic for VLV/CHV. We _must_ first set up the register
4001          * without actually enabling the port, and then do another
4002          * write to enable the port. Otherwise link training will
4003          * fail when the power sequencer is freshly used for this port.
4004          */
4005         intel_dp->DP |= DP_PORT_EN;
4006         if (crtc_state->has_audio)
4007                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
4008
4009         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4010         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4011 }
4012
4013 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp)
4014 {
4015         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4016         u8 tmp;
4017
4018         if (intel_dp->dpcd[DP_DPCD_REV] < 0x13)
4019                 return;
4020
4021         if (!drm_dp_is_branch(intel_dp->dpcd))
4022                 return;
4023
4024         tmp = intel_dp->has_hdmi_sink ?
4025                 DP_HDMI_DVI_OUTPUT_CONFIG : 0;
4026
4027         if (drm_dp_dpcd_writeb(&intel_dp->aux,
4028                                DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)
4029                 drm_dbg_kms(&i915->drm, "Failed to set protocol converter HDMI mode to %s\n",
4030                             enableddisabled(intel_dp->has_hdmi_sink));
4031
4032         tmp = intel_dp->dfp.ycbcr_444_to_420 ?
4033                 DP_CONVERSION_TO_YCBCR420_ENABLE : 0;
4034
4035         if (drm_dp_dpcd_writeb(&intel_dp->aux,
4036                                DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)
4037                 drm_dbg_kms(&i915->drm,
4038                             "Failed to set protocol converter YCbCr 4:2:0 conversion mode to %s\n",
4039                             enableddisabled(intel_dp->dfp.ycbcr_444_to_420));
4040
4041         tmp = 0;
4042
4043         if (drm_dp_dpcd_writeb(&intel_dp->aux,
4044                                DP_PROTOCOL_CONVERTER_CONTROL_2, tmp) <= 0)
4045                 drm_dbg_kms(&i915->drm,
4046                             "Failed to set protocol converter YCbCr 4:2:2 conversion mode to %s\n",
4047                             enableddisabled(false));
4048 }
4049
4050 static void intel_enable_dp(struct intel_atomic_state *state,
4051                             struct intel_encoder *encoder,
4052                             const struct intel_crtc_state *pipe_config,
4053                             const struct drm_connector_state *conn_state)
4054 {
4055         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4056         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4057         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
4058         u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg);
4059         enum pipe pipe = crtc->pipe;
4060         intel_wakeref_t wakeref;
4061
4062         if (drm_WARN_ON(&dev_priv->drm, dp_reg & DP_PORT_EN))
4063                 return;
4064
4065         with_pps_lock(intel_dp, wakeref) {
4066                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4067                         vlv_init_panel_power_sequencer(encoder, pipe_config);
4068
4069                 intel_dp_enable_port(intel_dp, pipe_config);
4070
4071                 edp_panel_vdd_on(intel_dp);
4072                 edp_panel_on(intel_dp);
4073                 edp_panel_vdd_off(intel_dp, true);
4074         }
4075
4076         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4077                 unsigned int lane_mask = 0x0;
4078
4079                 if (IS_CHERRYVIEW(dev_priv))
4080                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
4081
4082                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
4083                                     lane_mask);
4084         }
4085
4086         intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
4087         intel_dp_configure_protocol_converter(intel_dp);
4088         intel_dp_start_link_train(intel_dp, pipe_config);
4089         intel_dp_stop_link_train(intel_dp, pipe_config);
4090
4091         if (pipe_config->has_audio) {
4092                 drm_dbg(&dev_priv->drm, "Enabling DP audio on pipe %c\n",
4093                         pipe_name(pipe));
4094                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
4095         }
4096 }
4097
4098 static void g4x_enable_dp(struct intel_atomic_state *state,
4099                           struct intel_encoder *encoder,
4100                           const struct intel_crtc_state *pipe_config,
4101                           const struct drm_connector_state *conn_state)
4102 {
4103         intel_enable_dp(state, encoder, pipe_config, conn_state);
4104         intel_edp_backlight_on(pipe_config, conn_state);
4105 }
4106
4107 static void vlv_enable_dp(struct intel_atomic_state *state,
4108                           struct intel_encoder *encoder,
4109                           const struct intel_crtc_state *pipe_config,
4110                           const struct drm_connector_state *conn_state)
4111 {
4112         intel_edp_backlight_on(pipe_config, conn_state);
4113 }
4114
4115 static void g4x_pre_enable_dp(struct intel_atomic_state *state,
4116                               struct intel_encoder *encoder,
4117                               const struct intel_crtc_state *pipe_config,
4118                               const struct drm_connector_state *conn_state)
4119 {
4120         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4121         enum port port = encoder->port;
4122
4123         intel_dp_prepare(encoder, pipe_config);
4124
4125         /* Only ilk+ has port A */
4126         if (port == PORT_A)
4127                 ilk_edp_pll_on(intel_dp, pipe_config);
4128 }
4129
4130 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
4131 {
4132         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4133         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4134         enum pipe pipe = intel_dp->pps_pipe;
4135         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
4136
4137         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
4138
4139         if (drm_WARN_ON(&dev_priv->drm, pipe != PIPE_A && pipe != PIPE_B))
4140                 return;
4141
4142         edp_panel_vdd_off_sync(intel_dp);
4143
4144         /*
4145          * VLV seems to get confused when multiple power sequencers
4146          * have the same port selected (even if only one has power/vdd
4147          * enabled). The failure manifests as vlv_wait_port_ready() failing
4148          * CHV on the other hand doesn't seem to mind having the same port
4149          * selected in multiple power sequencers, but let's clear the
4150          * port select always when logically disconnecting a power sequencer
4151          * from a port.
4152          */
4153         drm_dbg_kms(&dev_priv->drm,
4154                     "detaching pipe %c power sequencer from [ENCODER:%d:%s]\n",
4155                     pipe_name(pipe), dig_port->base.base.base.id,
4156                     dig_port->base.base.name);
4157         intel_de_write(dev_priv, pp_on_reg, 0);
4158         intel_de_posting_read(dev_priv, pp_on_reg);
4159
4160         intel_dp->pps_pipe = INVALID_PIPE;
4161 }
4162
4163 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv,
4164                                       enum pipe pipe)
4165 {
4166         struct intel_encoder *encoder;
4167
4168         lockdep_assert_held(&dev_priv->pps_mutex);
4169
4170         for_each_intel_dp(&dev_priv->drm, encoder) {
4171                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4172
4173                 drm_WARN(&dev_priv->drm, intel_dp->active_pipe == pipe,
4174                          "stealing pipe %c power sequencer from active [ENCODER:%d:%s]\n",
4175                          pipe_name(pipe), encoder->base.base.id,
4176                          encoder->base.name);
4177
4178                 if (intel_dp->pps_pipe != pipe)
4179                         continue;
4180
4181                 drm_dbg_kms(&dev_priv->drm,
4182                             "stealing pipe %c power sequencer from [ENCODER:%d:%s]\n",
4183                             pipe_name(pipe), encoder->base.base.id,
4184                             encoder->base.name);
4185
4186                 /* make sure vdd is off before we steal it */
4187                 vlv_detach_power_sequencer(intel_dp);
4188         }
4189 }
4190
4191 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder,
4192                                            const struct intel_crtc_state *crtc_state)
4193 {
4194         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4195         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4196         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4197
4198         lockdep_assert_held(&dev_priv->pps_mutex);
4199
4200         drm_WARN_ON(&dev_priv->drm, intel_dp->active_pipe != INVALID_PIPE);
4201
4202         if (intel_dp->pps_pipe != INVALID_PIPE &&
4203             intel_dp->pps_pipe != crtc->pipe) {
4204                 /*
4205                  * If another power sequencer was being used on this
4206                  * port previously make sure to turn off vdd there while
4207                  * we still have control of it.
4208                  */
4209                 vlv_detach_power_sequencer(intel_dp);
4210         }
4211
4212         /*
4213          * We may be stealing the power
4214          * sequencer from another port.
4215          */
4216         vlv_steal_power_sequencer(dev_priv, crtc->pipe);
4217
4218         intel_dp->active_pipe = crtc->pipe;
4219
4220         if (!intel_dp_is_edp(intel_dp))
4221                 return;
4222
4223         /* now it's all ours */
4224         intel_dp->pps_pipe = crtc->pipe;
4225
4226         drm_dbg_kms(&dev_priv->drm,
4227                     "initializing pipe %c power sequencer for [ENCODER:%d:%s]\n",
4228                     pipe_name(intel_dp->pps_pipe), encoder->base.base.id,
4229                     encoder->base.name);
4230
4231         /* init power sequencer on this pipe and port */
4232         intel_dp_init_panel_power_sequencer(intel_dp);
4233         intel_dp_init_panel_power_sequencer_registers(intel_dp, true);
4234 }
4235
4236 static void vlv_pre_enable_dp(struct intel_atomic_state *state,
4237                               struct intel_encoder *encoder,
4238                               const struct intel_crtc_state *pipe_config,
4239                               const struct drm_connector_state *conn_state)
4240 {
4241         vlv_phy_pre_encoder_enable(encoder, pipe_config);
4242
4243         intel_enable_dp(state, encoder, pipe_config, conn_state);
4244 }
4245
4246 static void vlv_dp_pre_pll_enable(struct intel_atomic_state *state,
4247                                   struct intel_encoder *encoder,
4248                                   const struct intel_crtc_state *pipe_config,
4249                                   const struct drm_connector_state *conn_state)
4250 {
4251         intel_dp_prepare(encoder, pipe_config);
4252
4253         vlv_phy_pre_pll_enable(encoder, pipe_config);
4254 }
4255
4256 static void chv_pre_enable_dp(struct intel_atomic_state *state,
4257                               struct intel_encoder *encoder,
4258                               const struct intel_crtc_state *pipe_config,
4259                               const struct drm_connector_state *conn_state)
4260 {
4261         chv_phy_pre_encoder_enable(encoder, pipe_config);
4262
4263         intel_enable_dp(state, encoder, pipe_config, conn_state);
4264
4265         /* Second common lane will stay alive on its own now */
4266         chv_phy_release_cl2_override(encoder);
4267 }
4268
4269 static void chv_dp_pre_pll_enable(struct intel_atomic_state *state,
4270                                   struct intel_encoder *encoder,
4271                                   const struct intel_crtc_state *pipe_config,
4272                                   const struct drm_connector_state *conn_state)
4273 {
4274         intel_dp_prepare(encoder, pipe_config);
4275
4276         chv_phy_pre_pll_enable(encoder, pipe_config);
4277 }
4278
4279 static void chv_dp_post_pll_disable(struct intel_atomic_state *state,
4280                                     struct intel_encoder *encoder,
4281                                     const struct intel_crtc_state *old_crtc_state,
4282                                     const struct drm_connector_state *old_conn_state)
4283 {
4284         chv_phy_post_pll_disable(encoder, old_crtc_state);
4285 }
4286
4287 static u8 intel_dp_voltage_max_2(struct intel_dp *intel_dp,
4288                                  const struct intel_crtc_state *crtc_state)
4289 {
4290         return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
4291 }
4292
4293 static u8 intel_dp_voltage_max_3(struct intel_dp *intel_dp,
4294                                  const struct intel_crtc_state *crtc_state)
4295 {
4296         return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
4297 }
4298
4299 static u8 intel_dp_preemph_max_2(struct intel_dp *intel_dp)
4300 {
4301         return DP_TRAIN_PRE_EMPH_LEVEL_2;
4302 }
4303
4304 static u8 intel_dp_preemph_max_3(struct intel_dp *intel_dp)
4305 {
4306         return DP_TRAIN_PRE_EMPH_LEVEL_3;
4307 }
4308
4309 static void vlv_set_signal_levels(struct intel_dp *intel_dp,
4310                                   const struct intel_crtc_state *crtc_state)
4311 {
4312         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4313         unsigned long demph_reg_value, preemph_reg_value,
4314                 uniqtranscale_reg_value;
4315         u8 train_set = intel_dp->train_set[0];
4316
4317         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4318         case DP_TRAIN_PRE_EMPH_LEVEL_0:
4319                 preemph_reg_value = 0x0004000;
4320                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4321                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4322                         demph_reg_value = 0x2B405555;
4323                         uniqtranscale_reg_value = 0x552AB83A;
4324                         break;
4325                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4326                         demph_reg_value = 0x2B404040;
4327                         uniqtranscale_reg_value = 0x5548B83A;
4328                         break;
4329                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4330                         demph_reg_value = 0x2B245555;
4331                         uniqtranscale_reg_value = 0x5560B83A;
4332                         break;
4333                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4334                         demph_reg_value = 0x2B405555;
4335                         uniqtranscale_reg_value = 0x5598DA3A;
4336                         break;
4337                 default:
4338                         return;
4339                 }
4340                 break;
4341         case DP_TRAIN_PRE_EMPH_LEVEL_1:
4342                 preemph_reg_value = 0x0002000;
4343                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4344                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4345                         demph_reg_value = 0x2B404040;
4346                         uniqtranscale_reg_value = 0x5552B83A;
4347                         break;
4348                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4349                         demph_reg_value = 0x2B404848;
4350                         uniqtranscale_reg_value = 0x5580B83A;
4351                         break;
4352                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4353                         demph_reg_value = 0x2B404040;
4354                         uniqtranscale_reg_value = 0x55ADDA3A;
4355                         break;
4356                 default:
4357                         return;
4358                 }
4359                 break;
4360         case DP_TRAIN_PRE_EMPH_LEVEL_2:
4361                 preemph_reg_value = 0x0000000;
4362                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4363                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4364                         demph_reg_value = 0x2B305555;
4365                         uniqtranscale_reg_value = 0x5570B83A;
4366                         break;
4367                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4368                         demph_reg_value = 0x2B2B4040;
4369                         uniqtranscale_reg_value = 0x55ADDA3A;
4370                         break;
4371                 default:
4372                         return;
4373                 }
4374                 break;
4375         case DP_TRAIN_PRE_EMPH_LEVEL_3:
4376                 preemph_reg_value = 0x0006000;
4377                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4378                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4379                         demph_reg_value = 0x1B405555;
4380                         uniqtranscale_reg_value = 0x55ADDA3A;
4381                         break;
4382                 default:
4383                         return;
4384                 }
4385                 break;
4386         default:
4387                 return;
4388         }
4389
4390         vlv_set_phy_signal_level(encoder, crtc_state,
4391                                  demph_reg_value, preemph_reg_value,
4392                                  uniqtranscale_reg_value, 0);
4393 }
4394
4395 static void chv_set_signal_levels(struct intel_dp *intel_dp,
4396                                   const struct intel_crtc_state *crtc_state)
4397 {
4398         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4399         u32 deemph_reg_value, margin_reg_value;
4400         bool uniq_trans_scale = false;
4401         u8 train_set = intel_dp->train_set[0];
4402
4403         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4404         case DP_TRAIN_PRE_EMPH_LEVEL_0:
4405                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4406                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4407                         deemph_reg_value = 128;
4408                         margin_reg_value = 52;
4409                         break;
4410                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4411                         deemph_reg_value = 128;
4412                         margin_reg_value = 77;
4413                         break;
4414                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4415                         deemph_reg_value = 128;
4416                         margin_reg_value = 102;
4417                         break;
4418                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4419                         deemph_reg_value = 128;
4420                         margin_reg_value = 154;
4421                         uniq_trans_scale = true;
4422                         break;
4423                 default:
4424                         return;
4425                 }
4426                 break;
4427         case DP_TRAIN_PRE_EMPH_LEVEL_1:
4428                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4429                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4430                         deemph_reg_value = 85;
4431                         margin_reg_value = 78;
4432                         break;
4433                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4434                         deemph_reg_value = 85;
4435                         margin_reg_value = 116;
4436                         break;
4437                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4438                         deemph_reg_value = 85;
4439                         margin_reg_value = 154;
4440                         break;
4441                 default:
4442                         return;
4443                 }
4444                 break;
4445         case DP_TRAIN_PRE_EMPH_LEVEL_2:
4446                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4447                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4448                         deemph_reg_value = 64;
4449                         margin_reg_value = 104;
4450                         break;
4451                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4452                         deemph_reg_value = 64;
4453                         margin_reg_value = 154;
4454                         break;
4455                 default:
4456                         return;
4457                 }
4458                 break;
4459         case DP_TRAIN_PRE_EMPH_LEVEL_3:
4460                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4461                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4462                         deemph_reg_value = 43;
4463                         margin_reg_value = 154;
4464                         break;
4465                 default:
4466                         return;
4467                 }
4468                 break;
4469         default:
4470                 return;
4471         }
4472
4473         chv_set_phy_signal_level(encoder, crtc_state,
4474                                  deemph_reg_value, margin_reg_value,
4475                                  uniq_trans_scale);
4476 }
4477
4478 static u32 g4x_signal_levels(u8 train_set)
4479 {
4480         u32 signal_levels = 0;
4481
4482         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
4483         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
4484         default:
4485                 signal_levels |= DP_VOLTAGE_0_4;
4486                 break;
4487         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
4488                 signal_levels |= DP_VOLTAGE_0_6;
4489                 break;
4490         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
4491                 signal_levels |= DP_VOLTAGE_0_8;
4492                 break;
4493         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
4494                 signal_levels |= DP_VOLTAGE_1_2;
4495                 break;
4496         }
4497         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
4498         case DP_TRAIN_PRE_EMPH_LEVEL_0:
4499         default:
4500                 signal_levels |= DP_PRE_EMPHASIS_0;
4501                 break;
4502         case DP_TRAIN_PRE_EMPH_LEVEL_1:
4503                 signal_levels |= DP_PRE_EMPHASIS_3_5;
4504                 break;
4505         case DP_TRAIN_PRE_EMPH_LEVEL_2:
4506                 signal_levels |= DP_PRE_EMPHASIS_6;
4507                 break;
4508         case DP_TRAIN_PRE_EMPH_LEVEL_3:
4509                 signal_levels |= DP_PRE_EMPHASIS_9_5;
4510                 break;
4511         }
4512         return signal_levels;
4513 }
4514
4515 static void
4516 g4x_set_signal_levels(struct intel_dp *intel_dp,
4517                       const struct intel_crtc_state *crtc_state)
4518 {
4519         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4520         u8 train_set = intel_dp->train_set[0];
4521         u32 signal_levels;
4522
4523         signal_levels = g4x_signal_levels(train_set);
4524
4525         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4526                     signal_levels);
4527
4528         intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK);
4529         intel_dp->DP |= signal_levels;
4530
4531         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4532         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4533 }
4534
4535 /* SNB CPU eDP voltage swing and pre-emphasis control */
4536 static u32 snb_cpu_edp_signal_levels(u8 train_set)
4537 {
4538         u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4539                                         DP_TRAIN_PRE_EMPHASIS_MASK);
4540
4541         switch (signal_levels) {
4542         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4543         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4544                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4545         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4546                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
4547         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4548         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4549                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
4550         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4551         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4552                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
4553         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4554         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4555                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
4556         default:
4557                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4558                               "0x%x\n", signal_levels);
4559                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
4560         }
4561 }
4562
4563 static void
4564 snb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
4565                               const struct intel_crtc_state *crtc_state)
4566 {
4567         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4568         u8 train_set = intel_dp->train_set[0];
4569         u32 signal_levels;
4570
4571         signal_levels = snb_cpu_edp_signal_levels(train_set);
4572
4573         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4574                     signal_levels);
4575
4576         intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
4577         intel_dp->DP |= signal_levels;
4578
4579         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4580         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4581 }
4582
4583 /* IVB CPU eDP voltage swing and pre-emphasis control */
4584 static u32 ivb_cpu_edp_signal_levels(u8 train_set)
4585 {
4586         u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
4587                                         DP_TRAIN_PRE_EMPHASIS_MASK);
4588
4589         switch (signal_levels) {
4590         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4591                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
4592         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4593                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
4594         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4595         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
4596                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
4597
4598         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4599                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
4600         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4601                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
4602
4603         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
4604                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
4605         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
4606                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
4607
4608         default:
4609                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
4610                               "0x%x\n", signal_levels);
4611                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
4612         }
4613 }
4614
4615 static void
4616 ivb_cpu_edp_set_signal_levels(struct intel_dp *intel_dp,
4617                               const struct intel_crtc_state *crtc_state)
4618 {
4619         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4620         u8 train_set = intel_dp->train_set[0];
4621         u32 signal_levels;
4622
4623         signal_levels = ivb_cpu_edp_signal_levels(train_set);
4624
4625         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
4626                     signal_levels);
4627
4628         intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
4629         intel_dp->DP |= signal_levels;
4630
4631         intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
4632         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4633 }
4634
4635 void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
4636                                 const struct intel_crtc_state *crtc_state)
4637 {
4638         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4639         u8 train_set = intel_dp->train_set[0];
4640
4641         drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s\n",
4642                     train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
4643                     train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "");
4644         drm_dbg_kms(&dev_priv->drm, "Using pre-emphasis level %d%s\n",
4645                     (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
4646                     DP_TRAIN_PRE_EMPHASIS_SHIFT,
4647                     train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
4648                     " (max)" : "");
4649
4650         intel_dp->set_signal_levels(intel_dp, crtc_state);
4651 }
4652
4653 void
4654 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
4655                                        const struct intel_crtc_state *crtc_state,
4656                                        u8 dp_train_pat)
4657 {
4658         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4659
4660         if ((intel_dp_training_pattern_symbol(dp_train_pat)) !=
4661             DP_TRAINING_PATTERN_DISABLE)
4662                 drm_dbg_kms(&dev_priv->drm,
4663                             "Using DP training pattern TPS%d\n",
4664                             intel_dp_training_pattern_symbol(dp_train_pat));
4665
4666         intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
4667 }
4668
4669 static void
4670 intel_dp_link_down(struct intel_encoder *encoder,
4671                    const struct intel_crtc_state *old_crtc_state)
4672 {
4673         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4674         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4675         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
4676         enum port port = encoder->port;
4677         u32 DP = intel_dp->DP;
4678
4679         if (drm_WARN_ON(&dev_priv->drm,
4680                         (intel_de_read(dev_priv, intel_dp->output_reg) &
4681                          DP_PORT_EN) == 0))
4682                 return;
4683
4684         drm_dbg_kms(&dev_priv->drm, "\n");
4685
4686         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
4687             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
4688                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
4689                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
4690         } else {
4691                 DP &= ~DP_LINK_TRAIN_MASK;
4692                 DP |= DP_LINK_TRAIN_PAT_IDLE;
4693         }
4694         intel_de_write(dev_priv, intel_dp->output_reg, DP);
4695         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4696
4697         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
4698         intel_de_write(dev_priv, intel_dp->output_reg, DP);
4699         intel_de_posting_read(dev_priv, intel_dp->output_reg);
4700
4701         /*
4702          * HW workaround for IBX, we need to move the port
4703          * to transcoder A after disabling it to allow the
4704          * matching HDMI port to be enabled on transcoder A.
4705          */
4706         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
4707                 /*
4708                  * We get CPU/PCH FIFO underruns on the other pipe when
4709                  * doing the workaround. Sweep them under the rug.
4710                  */
4711                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4712                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
4713
4714                 /* always enable with pattern 1 (as per spec) */
4715                 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
4716                 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
4717                         DP_LINK_TRAIN_PAT_1;
4718                 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4719                 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4720
4721                 DP &= ~DP_PORT_EN;
4722                 intel_de_write(dev_priv, intel_dp->output_reg, DP);
4723                 intel_de_posting_read(dev_priv, intel_dp->output_reg);
4724
4725                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
4726                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4727                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
4728         }
4729
4730         msleep(intel_dp->panel_power_down_delay);
4731
4732         intel_dp->DP = DP;
4733
4734         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
4735                 intel_wakeref_t wakeref;
4736
4737                 with_pps_lock(intel_dp, wakeref)
4738                         intel_dp->active_pipe = INVALID_PIPE;
4739         }
4740 }
4741
4742 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
4743 {
4744         u8 dprx = 0;
4745
4746         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
4747                               &dprx) != 1)
4748                 return false;
4749         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
4750 }
4751
4752 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp)
4753 {
4754         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4755
4756         /*
4757          * Clear the cached register set to avoid using stale values
4758          * for the sinks that do not support DSC.
4759          */
4760         memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
4761
4762         /* Clear fec_capable to avoid using stale values */
4763         intel_dp->fec_capable = 0;
4764
4765         /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */
4766         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 ||
4767             intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4768                 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT,
4769                                      intel_dp->dsc_dpcd,
4770                                      sizeof(intel_dp->dsc_dpcd)) < 0)
4771                         drm_err(&i915->drm,
4772                                 "Failed to read DPCD register 0x%x\n",
4773                                 DP_DSC_SUPPORT);
4774
4775                 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n",
4776                             (int)sizeof(intel_dp->dsc_dpcd),
4777                             intel_dp->dsc_dpcd);
4778
4779                 /* FEC is supported only on DP 1.4 */
4780                 if (!intel_dp_is_edp(intel_dp) &&
4781                     drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY,
4782                                       &intel_dp->fec_capable) < 0)
4783                         drm_err(&i915->drm,
4784                                 "Failed to read FEC DPCD register\n");
4785
4786                 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n",
4787                             intel_dp->fec_capable);
4788         }
4789 }
4790
4791 static bool
4792 intel_edp_init_dpcd(struct intel_dp *intel_dp)
4793 {
4794         struct drm_i915_private *dev_priv =
4795                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
4796
4797         /* this function is meant to be called only once */
4798         drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
4799
4800         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
4801                 return false;
4802
4803         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4804                          drm_dp_is_branch(intel_dp->dpcd));
4805
4806         /*
4807          * Read the eDP display control registers.
4808          *
4809          * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in
4810          * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it
4811          * set, but require eDP 1.4+ detection (e.g. for supported link rates
4812          * method). The display control registers should read zero if they're
4813          * not supported anyway.
4814          */
4815         if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
4816                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
4817                              sizeof(intel_dp->edp_dpcd))
4818                 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n",
4819                             (int)sizeof(intel_dp->edp_dpcd),
4820                             intel_dp->edp_dpcd);
4821
4822         /*
4823          * This has to be called after intel_dp->edp_dpcd is filled, PSR checks
4824          * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1]
4825          */
4826         intel_psr_init_dpcd(intel_dp);
4827
4828         /* Read the eDP 1.4+ supported link rates. */
4829         if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {
4830                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
4831                 int i;
4832
4833                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
4834                                 sink_rates, sizeof(sink_rates));
4835
4836                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
4837                         int val = le16_to_cpu(sink_rates[i]);
4838
4839                         if (val == 0)
4840                                 break;
4841
4842                         /* Value read multiplied by 200kHz gives the per-lane
4843                          * link rate in kHz. The source rates are, however,
4844                          * stored in terms of LS_Clk kHz. The full conversion
4845                          * back to symbols is
4846                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
4847                          */
4848                         intel_dp->sink_rates[i] = (val * 200) / 10;
4849                 }
4850                 intel_dp->num_sink_rates = i;
4851         }
4852
4853         /*
4854          * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available,
4855          * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise.
4856          */
4857         if (intel_dp->num_sink_rates)
4858                 intel_dp->use_rate_select = true;
4859         else
4860                 intel_dp_set_sink_rates(intel_dp);
4861
4862         intel_dp_set_common_rates(intel_dp);
4863
4864         /* Read the eDP DSC DPCD registers */
4865         if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
4866                 intel_dp_get_dsc_sink_cap(intel_dp);
4867
4868         return true;
4869 }
4870
4871 static bool
4872 intel_dp_has_sink_count(struct intel_dp *intel_dp)
4873 {
4874         if (!intel_dp->attached_connector)
4875                 return false;
4876
4877         return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base,
4878                                           intel_dp->dpcd,
4879                                           &intel_dp->desc);
4880 }
4881
4882 static bool
4883 intel_dp_get_dpcd(struct intel_dp *intel_dp)
4884 {
4885         int ret;
4886
4887         intel_dp_lttpr_init(intel_dp);
4888
4889         if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd))
4890                 return false;
4891
4892         /*
4893          * Don't clobber cached eDP rates. Also skip re-reading
4894          * the OUI/ID since we know it won't change.
4895          */
4896         if (!intel_dp_is_edp(intel_dp)) {
4897                 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4898                                  drm_dp_is_branch(intel_dp->dpcd));
4899
4900                 intel_dp_set_sink_rates(intel_dp);
4901                 intel_dp_set_common_rates(intel_dp);
4902         }
4903
4904         if (intel_dp_has_sink_count(intel_dp)) {
4905                 ret = drm_dp_read_sink_count(&intel_dp->aux);
4906                 if (ret < 0)
4907                         return false;
4908
4909                 /*
4910                  * Sink count can change between short pulse hpd hence
4911                  * a member variable in intel_dp will track any changes
4912                  * between short pulse interrupts.
4913                  */
4914                 intel_dp->sink_count = ret;
4915
4916                 /*
4917                  * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
4918                  * a dongle is present but no display. Unless we require to know
4919                  * if a dongle is present or not, we don't need to update
4920                  * downstream port information. So, an early return here saves
4921                  * time from performing other operations which are not required.
4922                  */
4923                 if (!intel_dp->sink_count)
4924                         return false;
4925         }
4926
4927         return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd,
4928                                            intel_dp->downstream_ports) == 0;
4929 }
4930
4931 static bool
4932 intel_dp_can_mst(struct intel_dp *intel_dp)
4933 {
4934         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4935
4936         return i915->params.enable_dp_mst &&
4937                 intel_dp->can_mst &&
4938                 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
4939 }
4940
4941 static void
4942 intel_dp_configure_mst(struct intel_dp *intel_dp)
4943 {
4944         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4945         struct intel_encoder *encoder =
4946                 &dp_to_dig_port(intel_dp)->base;
4947         bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd);
4948
4949         drm_dbg_kms(&i915->drm,
4950                     "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n",
4951                     encoder->base.base.id, encoder->base.name,
4952                     yesno(intel_dp->can_mst), yesno(sink_can_mst),
4953                     yesno(i915->params.enable_dp_mst));
4954
4955         if (!intel_dp->can_mst)
4956                 return;
4957
4958         intel_dp->is_mst = sink_can_mst &&
4959                 i915->params.enable_dp_mst;
4960
4961         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4962                                         intel_dp->is_mst);
4963 }
4964
4965 static bool
4966 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4967 {
4968         return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI,
4969                                 sink_irq_vector, DP_DPRX_ESI_LEN) ==
4970                 DP_DPRX_ESI_LEN;
4971 }
4972
4973 bool
4974 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
4975                        const struct drm_connector_state *conn_state)
4976 {
4977         /*
4978          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
4979          * of Color Encoding Format and Content Color Gamut], in order to
4980          * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP.
4981          */
4982         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
4983                 return true;
4984
4985         switch (conn_state->colorspace) {
4986         case DRM_MODE_COLORIMETRY_SYCC_601:
4987         case DRM_MODE_COLORIMETRY_OPYCC_601:
4988         case DRM_MODE_COLORIMETRY_BT2020_YCC:
4989         case DRM_MODE_COLORIMETRY_BT2020_RGB:
4990         case DRM_MODE_COLORIMETRY_BT2020_CYCC:
4991                 return true;
4992         default:
4993                 break;
4994         }
4995
4996         return false;
4997 }
4998
4999 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc,
5000                                      struct dp_sdp *sdp, size_t size)
5001 {
5002         size_t length = sizeof(struct dp_sdp);
5003
5004         if (size < length)
5005                 return -ENOSPC;
5006
5007         memset(sdp, 0, size);
5008
5009         /*
5010          * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
5011          * VSC SDP Header Bytes
5012          */
5013         sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
5014         sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */
5015         sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
5016         sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */
5017
5018         /*
5019          * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as
5020          * per DP 1.4a spec.
5021          */
5022         if (vsc->revision != 0x5)
5023                 goto out;
5024
5025         /* VSC SDP Payload for DB16 through DB18 */
5026         /* Pixel Encoding and Colorimetry Formats  */
5027         sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */
5028         sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
5029
5030         switch (vsc->bpc) {
5031         case 6:
5032                 /* 6bpc: 0x0 */
5033                 break;
5034         case 8:
5035                 sdp->db[17] = 0x1; /* DB17[3:0] */
5036                 break;
5037         case 10:
5038                 sdp->db[17] = 0x2;
5039                 break;
5040         case 12:
5041                 sdp->db[17] = 0x3;
5042                 break;
5043         case 16:
5044                 sdp->db[17] = 0x4;
5045                 break;
5046         default:
5047                 MISSING_CASE(vsc->bpc);
5048                 break;
5049         }
5050         /* Dynamic Range and Component Bit Depth */
5051         if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
5052                 sdp->db[17] |= 0x80;  /* DB17[7] */
5053
5054         /* Content Type */
5055         sdp->db[18] = vsc->content_type & 0x7;
5056
5057 out:
5058         return length;
5059 }
5060
5061 static ssize_t
5062 intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe,
5063                                          struct dp_sdp *sdp,
5064                                          size_t size)
5065 {
5066         size_t length = sizeof(struct dp_sdp);
5067         const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE;
5068         unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE];
5069         ssize_t len;
5070
5071         if (size < length)
5072                 return -ENOSPC;
5073
5074         memset(sdp, 0, size);
5075
5076         len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));
5077         if (len < 0) {
5078                 DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n");
5079                 return -ENOSPC;
5080         }
5081
5082         if (len != infoframe_size) {
5083                 DRM_DEBUG_KMS("wrong static hdr metadata size\n");
5084                 return -ENOSPC;
5085         }
5086
5087         /*
5088          * Set up the infoframe sdp packet for HDR static metadata.
5089          * Prepare VSC Header for SU as per DP 1.4a spec,
5090          * Table 2-100 and Table 2-101
5091          */
5092
5093         /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
5094         sdp->sdp_header.HB0 = 0;
5095         /*
5096          * Packet Type 80h + Non-audio INFOFRAME Type value
5097          * HDMI_INFOFRAME_TYPE_DRM: 0x87
5098          * - 80h + Non-audio INFOFRAME Type value
5099          * - InfoFrame Type: 0x07
5100          *    [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame]
5101          */
5102         sdp->sdp_header.HB1 = drm_infoframe->type;
5103         /*
5104          * Least Significant Eight Bits of (Data Byte Count – 1)
5105          * infoframe_size - 1
5106          */
5107         sdp->sdp_header.HB2 = 0x1D;
5108         /* INFOFRAME SDP Version Number */
5109         sdp->sdp_header.HB3 = (0x13 << 2);
5110         /* CTA Header Byte 2 (INFOFRAME Version Number) */
5111         sdp->db[0] = drm_infoframe->version;
5112         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
5113         sdp->db[1] = drm_infoframe->length;
5114         /*
5115          * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
5116          * HDMI_INFOFRAME_HEADER_SIZE
5117          */
5118         BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
5119         memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
5120                HDMI_DRM_INFOFRAME_SIZE);
5121
5122         /*
5123          * Size of DP infoframe sdp packet for HDR static metadata consists of
5124          * - DP SDP Header(struct dp_sdp_header): 4 bytes
5125          * - Two Data Blocks: 2 bytes
5126          *    CTA Header Byte2 (INFOFRAME Version Number)
5127          *    CTA Header Byte3 (Length of INFOFRAME)
5128          * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
5129          *
5130          * Prior to GEN11's GMP register size is identical to DP HDR static metadata
5131          * infoframe size. But GEN11+ has larger than that size, write_infoframe
5132          * will pad rest of the size.
5133          */
5134         return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE;
5135 }
5136
5137 static void intel_write_dp_sdp(struct intel_encoder *encoder,
5138                                const struct intel_crtc_state *crtc_state,
5139                                unsigned int type)
5140 {
5141         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5142         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5143         struct dp_sdp sdp = {};
5144         ssize_t len;
5145
5146         if ((crtc_state->infoframes.enable &
5147              intel_hdmi_infoframe_enable(type)) == 0)
5148                 return;
5149
5150         switch (type) {
5151         case DP_SDP_VSC:
5152                 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp,
5153                                             sizeof(sdp));
5154                 break;
5155         case HDMI_PACKET_TYPE_GAMUT_METADATA:
5156                 len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm,
5157                                                                &sdp, sizeof(sdp));
5158                 break;
5159         default:
5160                 MISSING_CASE(type);
5161                 return;
5162         }
5163
5164         if (drm_WARN_ON(&dev_priv->drm, len < 0))
5165                 return;
5166
5167         dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);
5168 }
5169
5170 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder,
5171                             const struct intel_crtc_state *crtc_state,
5172                             struct drm_dp_vsc_sdp *vsc)
5173 {
5174         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5175         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5176         struct dp_sdp sdp = {};
5177         ssize_t len;
5178
5179         len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp));
5180
5181         if (drm_WARN_ON(&dev_priv->drm, len < 0))
5182                 return;
5183
5184         dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC,
5185                                         &sdp, len);
5186 }
5187
5188 void intel_dp_set_infoframes(struct intel_encoder *encoder,
5189                              bool enable,
5190                              const struct intel_crtc_state *crtc_state,
5191                              const struct drm_connector_state *conn_state)
5192 {
5193         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5194         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5195         i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
5196         u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
5197                          VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |
5198                          VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;
5199         u32 val = intel_de_read(dev_priv, reg);
5200
5201         /* TODO: Add DSC case (DIP_ENABLE_PPS) */
5202         /* When PSR is enabled, this routine doesn't disable VSC DIP */
5203         if (intel_psr_enabled(intel_dp))
5204                 val &= ~dip_enable;
5205         else
5206                 val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
5207
5208         if (!enable) {
5209                 intel_de_write(dev_priv, reg, val);
5210                 intel_de_posting_read(dev_priv, reg);
5211                 return;
5212         }
5213
5214         intel_de_write(dev_priv, reg, val);
5215         intel_de_posting_read(dev_priv, reg);
5216
5217         /* When PSR is enabled, VSC SDP is handled by PSR routine */
5218         if (!intel_psr_enabled(intel_dp))
5219                 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
5220
5221         intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA);
5222 }
5223
5224 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc,
5225                                    const void *buffer, size_t size)
5226 {
5227         const struct dp_sdp *sdp = buffer;
5228
5229         if (size < sizeof(struct dp_sdp))
5230                 return -EINVAL;
5231
5232         memset(vsc, 0, size);
5233
5234         if (sdp->sdp_header.HB0 != 0)
5235                 return -EINVAL;
5236
5237         if (sdp->sdp_header.HB1 != DP_SDP_VSC)
5238                 return -EINVAL;
5239
5240         vsc->sdp_type = sdp->sdp_header.HB1;
5241         vsc->revision = sdp->sdp_header.HB2;
5242         vsc->length = sdp->sdp_header.HB3;
5243
5244         if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) ||
5245             (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) {
5246                 /*
5247                  * - HB2 = 0x2, HB3 = 0x8
5248                  *   VSC SDP supporting 3D stereo + PSR
5249                  * - HB2 = 0x4, HB3 = 0xe
5250                  *   VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of
5251                  *   first scan line of the SU region (applies to eDP v1.4b
5252                  *   and higher).
5253                  */
5254                 return 0;
5255         } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) {
5256                 /*
5257                  * - HB2 = 0x5, HB3 = 0x13
5258                  *   VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry
5259                  *   Format.
5260                  */
5261                 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf;
5262                 vsc->colorimetry = sdp->db[16] & 0xf;
5263                 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1;
5264
5265                 switch (sdp->db[17] & 0x7) {
5266                 case 0x0:
5267                         vsc->bpc = 6;
5268                         break;
5269                 case 0x1:
5270                         vsc->bpc = 8;
5271                         break;
5272                 case 0x2:
5273                         vsc->bpc = 10;
5274                         break;
5275                 case 0x3:
5276                         vsc->bpc = 12;
5277                         break;
5278                 case 0x4:
5279                         vsc->bpc = 16;
5280                         break;
5281                 default:
5282                         MISSING_CASE(sdp->db[17] & 0x7);
5283                         return -EINVAL;
5284                 }
5285
5286                 vsc->content_type = sdp->db[18] & 0x7;
5287         } else {
5288                 return -EINVAL;
5289         }
5290
5291         return 0;
5292 }
5293
5294 static int
5295 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe,
5296                                            const void *buffer, size_t size)
5297 {
5298         int ret;
5299
5300         const struct dp_sdp *sdp = buffer;
5301
5302         if (size < sizeof(struct dp_sdp))
5303                 return -EINVAL;
5304
5305         if (sdp->sdp_header.HB0 != 0)
5306                 return -EINVAL;
5307
5308         if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM)
5309                 return -EINVAL;
5310
5311         /*
5312          * Least Significant Eight Bits of (Data Byte Count – 1)
5313          * 1Dh (i.e., Data Byte Count = 30 bytes).
5314          */
5315         if (sdp->sdp_header.HB2 != 0x1D)
5316                 return -EINVAL;
5317
5318         /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */
5319         if ((sdp->sdp_header.HB3 & 0x3) != 0)
5320                 return -EINVAL;
5321
5322         /* INFOFRAME SDP Version Number */
5323         if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13)
5324                 return -EINVAL;
5325
5326         /* CTA Header Byte 2 (INFOFRAME Version Number) */
5327         if (sdp->db[0] != 1)
5328                 return -EINVAL;
5329
5330         /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */
5331         if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE)
5332                 return -EINVAL;
5333
5334         ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2],
5335                                              HDMI_DRM_INFOFRAME_SIZE);
5336
5337         return ret;
5338 }
5339
5340 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder,
5341                                   struct intel_crtc_state *crtc_state,
5342                                   struct drm_dp_vsc_sdp *vsc)
5343 {
5344         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5345         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5346         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5347         unsigned int type = DP_SDP_VSC;
5348         struct dp_sdp sdp = {};
5349         int ret;
5350
5351         /* When PSR is enabled, VSC SDP is handled by PSR routine */
5352         if (intel_psr_enabled(intel_dp))
5353                 return;
5354
5355         if ((crtc_state->infoframes.enable &
5356              intel_hdmi_infoframe_enable(type)) == 0)
5357                 return;
5358
5359         dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp));
5360
5361         ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));
5362
5363         if (ret)
5364                 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n");
5365 }
5366
5367 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,
5368                                                      struct intel_crtc_state *crtc_state,
5369                                                      struct hdmi_drm_infoframe *drm_infoframe)
5370 {
5371         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
5372         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5373         unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;
5374         struct dp_sdp sdp = {};
5375         int ret;
5376
5377         if ((crtc_state->infoframes.enable &
5378             intel_hdmi_infoframe_enable(type)) == 0)
5379                 return;
5380
5381         dig_port->read_infoframe(encoder, crtc_state, type, &sdp,
5382                                  sizeof(sdp));
5383
5384         ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp,
5385                                                          sizeof(sdp));
5386
5387         if (ret)
5388                 drm_dbg_kms(&dev_priv->drm,
5389                             "Failed to unpack DP HDR Metadata Infoframe SDP\n");
5390 }
5391
5392 void intel_read_dp_sdp(struct intel_encoder *encoder,
5393                        struct intel_crtc_state *crtc_state,
5394                        unsigned int type)
5395 {
5396         if (encoder->type != INTEL_OUTPUT_DDI)
5397                 return;
5398
5399         switch (type) {
5400         case DP_SDP_VSC:
5401                 intel_read_dp_vsc_sdp(encoder, crtc_state,
5402                                       &crtc_state->infoframes.vsc);
5403                 break;
5404         case HDMI_PACKET_TYPE_GAMUT_METADATA:
5405                 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state,
5406                                                          &crtc_state->infoframes.drm.drm);
5407                 break;
5408         default:
5409                 MISSING_CASE(type);
5410                 break;
5411         }
5412 }
5413
5414 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp)
5415 {
5416         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5417         int status = 0;
5418         int test_link_rate;
5419         u8 test_lane_count, test_link_bw;
5420         /* (DP CTS 1.2)
5421          * 4.3.1.11
5422          */
5423         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
5424         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
5425                                    &test_lane_count);
5426
5427         if (status <= 0) {
5428                 drm_dbg_kms(&i915->drm, "Lane count read failed\n");
5429                 return DP_TEST_NAK;
5430         }
5431         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
5432
5433         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
5434                                    &test_link_bw);
5435         if (status <= 0) {
5436                 drm_dbg_kms(&i915->drm, "Link Rate read failed\n");
5437                 return DP_TEST_NAK;
5438         }
5439         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
5440
5441         /* Validate the requested link rate and lane count */
5442         if (!intel_dp_link_params_valid(intel_dp, test_link_rate,
5443                                         test_lane_count))
5444                 return DP_TEST_NAK;
5445
5446         intel_dp->compliance.test_lane_count = test_lane_count;
5447         intel_dp->compliance.test_link_rate = test_link_rate;
5448
5449         return DP_TEST_ACK;
5450 }
5451
5452 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
5453 {
5454         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5455         u8 test_pattern;
5456         u8 test_misc;
5457         __be16 h_width, v_height;
5458         int status = 0;
5459
5460         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
5461         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
5462                                    &test_pattern);
5463         if (status <= 0) {
5464                 drm_dbg_kms(&i915->drm, "Test pattern read failed\n");
5465                 return DP_TEST_NAK;
5466         }
5467         if (test_pattern != DP_COLOR_RAMP)
5468                 return DP_TEST_NAK;
5469
5470         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
5471                                   &h_width, 2);
5472         if (status <= 0) {
5473                 drm_dbg_kms(&i915->drm, "H Width read failed\n");
5474                 return DP_TEST_NAK;
5475         }
5476
5477         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
5478                                   &v_height, 2);
5479         if (status <= 0) {
5480                 drm_dbg_kms(&i915->drm, "V Height read failed\n");
5481                 return DP_TEST_NAK;
5482         }
5483
5484         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
5485                                    &test_misc);
5486         if (status <= 0) {
5487                 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n");
5488                 return DP_TEST_NAK;
5489         }
5490         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
5491                 return DP_TEST_NAK;
5492         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
5493                 return DP_TEST_NAK;
5494         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
5495         case DP_TEST_BIT_DEPTH_6:
5496                 intel_dp->compliance.test_data.bpc = 6;
5497                 break;
5498         case DP_TEST_BIT_DEPTH_8:
5499                 intel_dp->compliance.test_data.bpc = 8;
5500                 break;
5501         default:
5502                 return DP_TEST_NAK;
5503         }
5504
5505         intel_dp->compliance.test_data.video_pattern = test_pattern;
5506         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
5507         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
5508         /* Set test active flag here so userspace doesn't interrupt things */
5509         intel_dp->compliance.test_active = true;
5510
5511         return DP_TEST_ACK;
5512 }
5513
5514 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp)
5515 {
5516         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5517         u8 test_result = DP_TEST_ACK;
5518         struct intel_connector *intel_connector = intel_dp->attached_connector;
5519         struct drm_connector *connector = &intel_connector->base;
5520
5521         if (intel_connector->detect_edid == NULL ||
5522             connector->edid_corrupt ||
5523             intel_dp->aux.i2c_defer_count > 6) {
5524                 /* Check EDID read for NACKs, DEFERs and corruption
5525                  * (DP CTS 1.2 Core r1.1)
5526                  *    4.2.2.4 : Failed EDID read, I2C_NAK
5527                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
5528                  *    4.2.2.6 : EDID corruption detected
5529                  * Use failsafe mode for all cases
5530                  */
5531                 if (intel_dp->aux.i2c_nack_count > 0 ||
5532                         intel_dp->aux.i2c_defer_count > 0)
5533                         drm_dbg_kms(&i915->drm,
5534                                     "EDID read had %d NACKs, %d DEFERs\n",
5535                                     intel_dp->aux.i2c_nack_count,
5536                                     intel_dp->aux.i2c_defer_count);
5537                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
5538         } else {
5539                 struct edid *block = intel_connector->detect_edid;
5540
5541                 /* We have to write the checksum
5542                  * of the last block read
5543                  */
5544                 block += intel_connector->detect_edid->extensions;
5545
5546                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
5547                                        block->checksum) <= 0)
5548                         drm_dbg_kms(&i915->drm,
5549                                     "Failed to write EDID checksum\n");
5550
5551                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
5552                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
5553         }
5554
5555         /* Set test active flag here so userspace doesn't interrupt things */
5556         intel_dp->compliance.test_active = true;
5557
5558         return test_result;
5559 }
5560
5561 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp,
5562                                         const struct intel_crtc_state *crtc_state)
5563 {
5564         struct drm_i915_private *dev_priv =
5565                         to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
5566         struct drm_dp_phy_test_params *data =
5567                         &intel_dp->compliance.test_data.phytest;
5568         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5569         enum pipe pipe = crtc->pipe;
5570         u32 pattern_val;
5571
5572         switch (data->phy_pattern) {
5573         case DP_PHY_TEST_PATTERN_NONE:
5574                 DRM_DEBUG_KMS("Disable Phy Test Pattern\n");
5575                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0);
5576                 break;
5577         case DP_PHY_TEST_PATTERN_D10_2:
5578                 DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n");
5579                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5580                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2);
5581                 break;
5582         case DP_PHY_TEST_PATTERN_ERROR_COUNT:
5583                 DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n");
5584                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5585                                DDI_DP_COMP_CTL_ENABLE |
5586                                DDI_DP_COMP_CTL_SCRAMBLED_0);
5587                 break;
5588         case DP_PHY_TEST_PATTERN_PRBS7:
5589                 DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n");
5590                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5591                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7);
5592                 break;
5593         case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
5594                 /*
5595                  * FIXME: Ideally pattern should come from DPCD 0x250. As
5596                  * current firmware of DPR-100 could not set it, so hardcoding
5597                  * now for complaince test.
5598                  */
5599                 DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n");
5600                 pattern_val = 0x3e0f83e0;
5601                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val);
5602                 pattern_val = 0x0f83e0f8;
5603                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val);
5604                 pattern_val = 0x0000f83e;
5605                 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val);
5606                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5607                                DDI_DP_COMP_CTL_ENABLE |
5608                                DDI_DP_COMP_CTL_CUSTOM80);
5609                 break;
5610         case DP_PHY_TEST_PATTERN_CP2520:
5611                 /*
5612                  * FIXME: Ideally pattern should come from DPCD 0x24A. As
5613                  * current firmware of DPR-100 could not set it, so hardcoding
5614                  * now for complaince test.
5615                  */
5616                 DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n");
5617                 pattern_val = 0xFB;
5618                 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe),
5619                                DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 |
5620                                pattern_val);
5621                 break;
5622         default:
5623                 WARN(1, "Invalid Phy Test Pattern\n");
5624         }
5625 }
5626
5627 static void
5628 intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp,
5629                                   const struct intel_crtc_state *crtc_state)
5630 {
5631         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5632         struct drm_device *dev = dig_port->base.base.dev;
5633         struct drm_i915_private *dev_priv = to_i915(dev);
5634         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
5635         enum pipe pipe = crtc->pipe;
5636         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
5637
5638         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
5639                                                  TRANS_DDI_FUNC_CTL(pipe));
5640         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
5641         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
5642
5643         trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE |
5644                                       TGL_TRANS_DDI_PORT_MASK);
5645         trans_conf_value &= ~PIPECONF_ENABLE;
5646         dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE;
5647
5648         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
5649         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
5650                        trans_ddi_func_ctl_value);
5651         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
5652 }
5653
5654 static void
5655 intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp,
5656                                  const struct intel_crtc_state *crtc_state)
5657 {
5658         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5659         struct drm_device *dev = dig_port->base.base.dev;
5660         struct drm_i915_private *dev_priv = to_i915(dev);
5661         enum port port = dig_port->base.port;
5662         struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
5663         enum pipe pipe = crtc->pipe;
5664         u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value;
5665
5666         trans_ddi_func_ctl_value = intel_de_read(dev_priv,
5667                                                  TRANS_DDI_FUNC_CTL(pipe));
5668         trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe));
5669         dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe));
5670
5671         trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE |
5672                                     TGL_TRANS_DDI_SELECT_PORT(port);
5673         trans_conf_value |= PIPECONF_ENABLE;
5674         dp_tp_ctl_value |= DP_TP_CTL_ENABLE;
5675
5676         intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value);
5677         intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value);
5678         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe),
5679                        trans_ddi_func_ctl_value);
5680 }
5681
5682 static void intel_dp_process_phy_request(struct intel_dp *intel_dp,
5683                                          const struct intel_crtc_state *crtc_state)
5684 {
5685         struct drm_dp_phy_test_params *data =
5686                 &intel_dp->compliance.test_data.phytest;
5687         u8 link_status[DP_LINK_STATUS_SIZE];
5688
5689         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
5690                                              link_status) < 0) {
5691                 DRM_DEBUG_KMS("failed to get link status\n");
5692                 return;
5693         }
5694
5695         /* retrieve vswing & pre-emphasis setting */
5696         intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX,
5697                                   link_status);
5698
5699         intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state);
5700
5701         intel_dp_set_signal_levels(intel_dp, crtc_state);
5702
5703         intel_dp_phy_pattern_update(intel_dp, crtc_state);
5704
5705         intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state);
5706
5707         drm_dp_set_phy_test_pattern(&intel_dp->aux, data,
5708                                     link_status[DP_DPCD_REV]);
5709 }
5710
5711 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
5712 {
5713         struct drm_dp_phy_test_params *data =
5714                 &intel_dp->compliance.test_data.phytest;
5715
5716         if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) {
5717                 DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n");
5718                 return DP_TEST_NAK;
5719         }
5720
5721         /* Set test active flag here so userspace doesn't interrupt things */
5722         intel_dp->compliance.test_active = true;
5723
5724         return DP_TEST_ACK;
5725 }
5726
5727 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
5728 {
5729         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5730         u8 response = DP_TEST_NAK;
5731         u8 request = 0;
5732         int status;
5733
5734         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
5735         if (status <= 0) {
5736                 drm_dbg_kms(&i915->drm,
5737                             "Could not read test request from sink\n");
5738                 goto update_status;
5739         }
5740
5741         switch (request) {
5742         case DP_TEST_LINK_TRAINING:
5743                 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n");
5744                 response = intel_dp_autotest_link_training(intel_dp);
5745                 break;
5746         case DP_TEST_LINK_VIDEO_PATTERN:
5747                 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n");
5748                 response = intel_dp_autotest_video_pattern(intel_dp);
5749                 break;
5750         case DP_TEST_LINK_EDID_READ:
5751                 drm_dbg_kms(&i915->drm, "EDID test requested\n");
5752                 response = intel_dp_autotest_edid(intel_dp);
5753                 break;
5754         case DP_TEST_LINK_PHY_TEST_PATTERN:
5755                 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n");
5756                 response = intel_dp_autotest_phy_pattern(intel_dp);
5757                 break;
5758         default:
5759                 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n",
5760                             request);
5761                 break;
5762         }
5763
5764         if (response & DP_TEST_ACK)
5765                 intel_dp->compliance.test_type = request;
5766
5767 update_status:
5768         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
5769         if (status <= 0)
5770                 drm_dbg_kms(&i915->drm,
5771                             "Could not write test response to sink\n");
5772 }
5773
5774 /**
5775  * intel_dp_check_mst_status - service any pending MST interrupts, check link status
5776  * @intel_dp: Intel DP struct
5777  *
5778  * Read any pending MST interrupts, call MST core to handle these and ack the
5779  * interrupts. Check if the main and AUX link state is ok.
5780  *
5781  * Returns:
5782  * - %true if pending interrupts were serviced (or no interrupts were
5783  *   pending) w/o detecting an error condition.
5784  * - %false if an error condition - like AUX failure or a loss of link - is
5785  *   detected, which needs servicing from the hotplug work.
5786  */
5787 static bool
5788 intel_dp_check_mst_status(struct intel_dp *intel_dp)
5789 {
5790         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5791         bool link_ok = true;
5792
5793         drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0);
5794
5795         for (;;) {
5796                 u8 esi[DP_DPRX_ESI_LEN] = {};
5797                 bool handled;
5798                 int retry;
5799
5800                 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {
5801                         drm_dbg_kms(&i915->drm,
5802                                     "failed to get ESI - device may have failed\n");
5803                         link_ok = false;
5804
5805                         break;
5806                 }
5807
5808                 /* check link status - esi[10] = 0x200c */
5809                 if (intel_dp->active_mst_links > 0 && link_ok &&
5810                     !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
5811                         drm_dbg_kms(&i915->drm,
5812                                     "channel EQ not ok, retraining\n");
5813                         link_ok = false;
5814                 }
5815
5816                 drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi);
5817
5818                 drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
5819                 if (!handled)
5820                         break;
5821
5822                 for (retry = 0; retry < 3; retry++) {
5823                         int wret;
5824
5825                         wret = drm_dp_dpcd_write(&intel_dp->aux,
5826                                                  DP_SINK_COUNT_ESI+1,
5827                                                  &esi[1], 3);
5828                         if (wret == 3)
5829                                 break;
5830                 }
5831         }
5832
5833         return link_ok;
5834 }
5835
5836 static bool
5837 intel_dp_needs_link_retrain(struct intel_dp *intel_dp)
5838 {
5839         u8 link_status[DP_LINK_STATUS_SIZE];
5840
5841         if (!intel_dp->link_trained)
5842                 return false;
5843
5844         /*
5845          * While PSR source HW is enabled, it will control main-link sending
5846          * frames, enabling and disabling it so trying to do a retrain will fail
5847          * as the link would or not be on or it could mix training patterns
5848          * and frame data at the same time causing retrain to fail.
5849          * Also when exiting PSR, HW will retrain the link anyways fixing
5850          * any link status error.
5851          */
5852         if (intel_psr_enabled(intel_dp))
5853                 return false;
5854
5855         if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX,
5856                                              link_status) < 0)
5857                 return false;
5858
5859         /*
5860          * Validate the cached values of intel_dp->link_rate and
5861          * intel_dp->lane_count before attempting to retrain.
5862          *
5863          * FIXME would be nice to user the crtc state here, but since
5864          * we need to call this from the short HPD handler that seems
5865          * a bit hard.
5866          */
5867         if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate,
5868                                         intel_dp->lane_count))
5869                 return false;
5870
5871         /* Retrain if Channel EQ or CR not ok */
5872         return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count);
5873 }
5874
5875 static bool intel_dp_has_connector(struct intel_dp *intel_dp,
5876                                    const struct drm_connector_state *conn_state)
5877 {
5878         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5879         struct intel_encoder *encoder;
5880         enum pipe pipe;
5881
5882         if (!conn_state->best_encoder)
5883                 return false;
5884
5885         /* SST */
5886         encoder = &dp_to_dig_port(intel_dp)->base;
5887         if (conn_state->best_encoder == &encoder->base)
5888                 return true;
5889
5890         /* MST */
5891         for_each_pipe(i915, pipe) {
5892                 encoder = &intel_dp->mst_encoders[pipe]->base;
5893                 if (conn_state->best_encoder == &encoder->base)
5894                         return true;
5895         }
5896
5897         return false;
5898 }
5899
5900 static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp,
5901                                       struct drm_modeset_acquire_ctx *ctx,
5902                                       u32 *crtc_mask)
5903 {
5904         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
5905         struct drm_connector_list_iter conn_iter;
5906         struct intel_connector *connector;
5907         int ret = 0;
5908
5909         *crtc_mask = 0;
5910
5911         if (!intel_dp_needs_link_retrain(intel_dp))
5912                 return 0;
5913
5914         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
5915         for_each_intel_connector_iter(connector, &conn_iter) {
5916                 struct drm_connector_state *conn_state =
5917                         connector->base.state;
5918                 struct intel_crtc_state *crtc_state;
5919                 struct intel_crtc *crtc;
5920
5921                 if (!intel_dp_has_connector(intel_dp, conn_state))
5922                         continue;
5923
5924                 crtc = to_intel_crtc(conn_state->crtc);
5925                 if (!crtc)
5926                         continue;
5927
5928                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
5929                 if (ret)
5930                         break;
5931
5932                 crtc_state = to_intel_crtc_state(crtc->base.state);
5933
5934                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
5935
5936                 if (!crtc_state->hw.active)
5937                         continue;
5938
5939                 if (conn_state->commit &&
5940                     !try_wait_for_completion(&conn_state->commit->hw_done))
5941                         continue;
5942
5943                 *crtc_mask |= drm_crtc_mask(&crtc->base);
5944         }
5945         drm_connector_list_iter_end(&conn_iter);
5946
5947         if (!intel_dp_needs_link_retrain(intel_dp))
5948                 *crtc_mask = 0;
5949
5950         return ret;
5951 }
5952
5953 static bool intel_dp_is_connected(struct intel_dp *intel_dp)
5954 {
5955         struct intel_connector *connector = intel_dp->attached_connector;
5956
5957         return connector->base.status == connector_status_connected ||
5958                 intel_dp->is_mst;
5959 }
5960
5961 int intel_dp_retrain_link(struct intel_encoder *encoder,
5962                           struct drm_modeset_acquire_ctx *ctx)
5963 {
5964         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5965         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5966         struct intel_crtc *crtc;
5967         u32 crtc_mask;
5968         int ret;
5969
5970         if (!intel_dp_is_connected(intel_dp))
5971                 return 0;
5972
5973         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
5974                                ctx);
5975         if (ret)
5976                 return ret;
5977
5978         ret = intel_dp_prep_link_retrain(intel_dp, ctx, &crtc_mask);
5979         if (ret)
5980                 return ret;
5981
5982         if (crtc_mask == 0)
5983                 return 0;
5984
5985         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n",
5986                     encoder->base.base.id, encoder->base.name);
5987
5988         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
5989                 const struct intel_crtc_state *crtc_state =
5990                         to_intel_crtc_state(crtc->base.state);
5991
5992                 /* Suppress underruns caused by re-training */
5993                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
5994                 if (crtc_state->has_pch_encoder)
5995                         intel_set_pch_fifo_underrun_reporting(dev_priv,
5996                                                               intel_crtc_pch_transcoder(crtc), false);
5997         }
5998
5999         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
6000                 const struct intel_crtc_state *crtc_state =
6001                         to_intel_crtc_state(crtc->base.state);
6002
6003                 /* retrain on the MST master transcoder */
6004                 if (INTEL_GEN(dev_priv) >= 12 &&
6005                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
6006                     !intel_dp_mst_is_master_trans(crtc_state))
6007                         continue;
6008
6009                 intel_dp_start_link_train(intel_dp, crtc_state);
6010                 intel_dp_stop_link_train(intel_dp, crtc_state);
6011                 break;
6012         }
6013
6014         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
6015                 const struct intel_crtc_state *crtc_state =
6016                         to_intel_crtc_state(crtc->base.state);
6017
6018                 /* Keep underrun reporting disabled until things are stable */
6019                 intel_wait_for_vblank(dev_priv, crtc->pipe);
6020
6021                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
6022                 if (crtc_state->has_pch_encoder)
6023                         intel_set_pch_fifo_underrun_reporting(dev_priv,
6024                                                               intel_crtc_pch_transcoder(crtc), true);
6025         }
6026
6027         return 0;
6028 }
6029
6030 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp,
6031                                   struct drm_modeset_acquire_ctx *ctx,
6032                                   u32 *crtc_mask)
6033 {
6034         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6035         struct drm_connector_list_iter conn_iter;
6036         struct intel_connector *connector;
6037         int ret = 0;
6038
6039         *crtc_mask = 0;
6040
6041         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
6042         for_each_intel_connector_iter(connector, &conn_iter) {
6043                 struct drm_connector_state *conn_state =
6044                         connector->base.state;
6045                 struct intel_crtc_state *crtc_state;
6046                 struct intel_crtc *crtc;
6047
6048                 if (!intel_dp_has_connector(intel_dp, conn_state))
6049                         continue;
6050
6051                 crtc = to_intel_crtc(conn_state->crtc);
6052                 if (!crtc)
6053                         continue;
6054
6055                 ret = drm_modeset_lock(&crtc->base.mutex, ctx);
6056                 if (ret)
6057                         break;
6058
6059                 crtc_state = to_intel_crtc_state(crtc->base.state);
6060
6061                 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state));
6062
6063                 if (!crtc_state->hw.active)
6064                         continue;
6065
6066                 if (conn_state->commit &&
6067                     !try_wait_for_completion(&conn_state->commit->hw_done))
6068                         continue;
6069
6070                 *crtc_mask |= drm_crtc_mask(&crtc->base);
6071         }
6072         drm_connector_list_iter_end(&conn_iter);
6073
6074         return ret;
6075 }
6076
6077 static int intel_dp_do_phy_test(struct intel_encoder *encoder,
6078                                 struct drm_modeset_acquire_ctx *ctx)
6079 {
6080         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6081         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
6082         struct intel_crtc *crtc;
6083         u32 crtc_mask;
6084         int ret;
6085
6086         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
6087                                ctx);
6088         if (ret)
6089                 return ret;
6090
6091         ret = intel_dp_prep_phy_test(intel_dp, ctx, &crtc_mask);
6092         if (ret)
6093                 return ret;
6094
6095         if (crtc_mask == 0)
6096                 return 0;
6097
6098         drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n",
6099                     encoder->base.base.id, encoder->base.name);
6100
6101         for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) {
6102                 const struct intel_crtc_state *crtc_state =
6103                         to_intel_crtc_state(crtc->base.state);
6104
6105                 /* test on the MST master transcoder */
6106                 if (INTEL_GEN(dev_priv) >= 12 &&
6107                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) &&
6108                     !intel_dp_mst_is_master_trans(crtc_state))
6109                         continue;
6110
6111                 intel_dp_process_phy_request(intel_dp, crtc_state);
6112                 break;
6113         }
6114
6115         return 0;
6116 }
6117
6118 static void intel_dp_phy_test(struct intel_encoder *encoder)
6119 {
6120         struct drm_modeset_acquire_ctx ctx;
6121         int ret;
6122
6123         drm_modeset_acquire_init(&ctx, 0);
6124
6125         for (;;) {
6126                 ret = intel_dp_do_phy_test(encoder, &ctx);
6127
6128                 if (ret == -EDEADLK) {
6129                         drm_modeset_backoff(&ctx);
6130                         continue;
6131                 }
6132
6133                 break;
6134         }
6135
6136         drm_modeset_drop_locks(&ctx);
6137         drm_modeset_acquire_fini(&ctx);
6138         drm_WARN(encoder->base.dev, ret,
6139                  "Acquiring modeset locks failed with %i\n", ret);
6140 }
6141
6142 /*
6143  * If display is now connected check links status,
6144  * there has been known issues of link loss triggering
6145  * long pulse.
6146  *
6147  * Some sinks (eg. ASUS PB287Q) seem to perform some
6148  * weird HPD ping pong during modesets. So we can apparently
6149  * end up with HPD going low during a modeset, and then
6150  * going back up soon after. And once that happens we must
6151  * retrain the link to get a picture. That's in case no
6152  * userspace component reacted to intermittent HPD dip.
6153  */
6154 static enum intel_hotplug_state
6155 intel_dp_hotplug(struct intel_encoder *encoder,
6156                  struct intel_connector *connector)
6157 {
6158         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
6159         struct drm_modeset_acquire_ctx ctx;
6160         enum intel_hotplug_state state;
6161         int ret;
6162
6163         if (intel_dp->compliance.test_active &&
6164             intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
6165                 intel_dp_phy_test(encoder);
6166                 /* just do the PHY test and nothing else */
6167                 return INTEL_HOTPLUG_UNCHANGED;
6168         }
6169
6170         state = intel_encoder_hotplug(encoder, connector);
6171
6172         drm_modeset_acquire_init(&ctx, 0);
6173
6174         for (;;) {
6175                 ret = intel_dp_retrain_link(encoder, &ctx);
6176
6177                 if (ret == -EDEADLK) {
6178                         drm_modeset_backoff(&ctx);
6179                         continue;
6180                 }
6181
6182                 break;
6183         }
6184
6185         drm_modeset_drop_locks(&ctx);
6186         drm_modeset_acquire_fini(&ctx);
6187         drm_WARN(encoder->base.dev, ret,
6188                  "Acquiring modeset locks failed with %i\n", ret);
6189
6190         /*
6191          * Keeping it consistent with intel_ddi_hotplug() and
6192          * intel_hdmi_hotplug().
6193          */
6194         if (state == INTEL_HOTPLUG_UNCHANGED && !connector->hotplug_retries)
6195                 state = INTEL_HOTPLUG_RETRY;
6196
6197         return state;
6198 }
6199
6200 static void intel_dp_check_service_irq(struct intel_dp *intel_dp)
6201 {
6202         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6203         u8 val;
6204
6205         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
6206                 return;
6207
6208         if (drm_dp_dpcd_readb(&intel_dp->aux,
6209                               DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val)
6210                 return;
6211
6212         drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val);
6213
6214         if (val & DP_AUTOMATED_TEST_REQUEST)
6215                 intel_dp_handle_test_request(intel_dp);
6216
6217         if (val & DP_CP_IRQ)
6218                 intel_hdcp_handle_cp_irq(intel_dp->attached_connector);
6219
6220         if (val & DP_SINK_SPECIFIC_IRQ)
6221                 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n");
6222 }
6223
6224 /*
6225  * According to DP spec
6226  * 5.1.2:
6227  *  1. Read DPCD
6228  *  2. Configure link according to Receiver Capabilities
6229  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
6230  *  4. Check link status on receipt of hot-plug interrupt
6231  *
6232  * intel_dp_short_pulse -  handles short pulse interrupts
6233  * when full detection is not required.
6234  * Returns %true if short pulse is handled and full detection
6235  * is NOT required and %false otherwise.
6236  */
6237 static bool
6238 intel_dp_short_pulse(struct intel_dp *intel_dp)
6239 {
6240         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6241         u8 old_sink_count = intel_dp->sink_count;
6242         bool ret;
6243
6244         /*
6245          * Clearing compliance test variables to allow capturing
6246          * of values for next automated test request.
6247          */
6248         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
6249
6250         /*
6251          * Now read the DPCD to see if it's actually running
6252          * If the current value of sink count doesn't match with
6253          * the value that was stored earlier or dpcd read failed
6254          * we need to do full detection
6255          */
6256         ret = intel_dp_get_dpcd(intel_dp);
6257
6258         if ((old_sink_count != intel_dp->sink_count) || !ret) {
6259                 /* No need to proceed if we are going to do full detect */
6260                 return false;
6261         }
6262
6263         intel_dp_check_service_irq(intel_dp);
6264
6265         /* Handle CEC interrupts, if any */
6266         drm_dp_cec_irq(&intel_dp->aux);
6267
6268         /* defer to the hotplug work for link retraining if needed */
6269         if (intel_dp_needs_link_retrain(intel_dp))
6270                 return false;
6271
6272         intel_psr_short_pulse(intel_dp);
6273
6274         switch (intel_dp->compliance.test_type) {
6275         case DP_TEST_LINK_TRAINING:
6276                 drm_dbg_kms(&dev_priv->drm,
6277                             "Link Training Compliance Test requested\n");
6278                 /* Send a Hotplug Uevent to userspace to start modeset */
6279                 drm_kms_helper_hotplug_event(&dev_priv->drm);
6280                 break;
6281         case DP_TEST_LINK_PHY_TEST_PATTERN:
6282                 drm_dbg_kms(&dev_priv->drm,
6283                             "PHY test pattern Compliance Test requested\n");
6284                 /*
6285                  * Schedule long hpd to do the test
6286                  *
6287                  * FIXME get rid of the ad-hoc phy test modeset code
6288                  * and properly incorporate it into the normal modeset.
6289                  */
6290                 return false;
6291         }
6292
6293         return true;
6294 }
6295
6296 /* XXX this is probably wrong for multiple downstream ports */
6297 static enum drm_connector_status
6298 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
6299 {
6300         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6301         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6302         u8 *dpcd = intel_dp->dpcd;
6303         u8 type;
6304
6305         if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp)))
6306                 return connector_status_connected;
6307
6308         lspcon_resume(dig_port);
6309
6310         if (!intel_dp_get_dpcd(intel_dp))
6311                 return connector_status_disconnected;
6312
6313         /* if there's no downstream port, we're done */
6314         if (!drm_dp_is_branch(dpcd))
6315                 return connector_status_connected;
6316
6317         /* If we're HPD-aware, SINK_COUNT changes dynamically */
6318         if (intel_dp_has_sink_count(intel_dp) &&
6319             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
6320                 return intel_dp->sink_count ?
6321                 connector_status_connected : connector_status_disconnected;
6322         }
6323
6324         if (intel_dp_can_mst(intel_dp))
6325                 return connector_status_connected;
6326
6327         /* If no HPD, poke DDC gently */
6328         if (drm_probe_ddc(&intel_dp->aux.ddc))
6329                 return connector_status_connected;
6330
6331         /* Well we tried, say unknown for unreliable port types */
6332         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
6333                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
6334                 if (type == DP_DS_PORT_TYPE_VGA ||
6335                     type == DP_DS_PORT_TYPE_NON_EDID)
6336                         return connector_status_unknown;
6337         } else {
6338                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
6339                         DP_DWN_STRM_PORT_TYPE_MASK;
6340                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
6341                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
6342                         return connector_status_unknown;
6343         }
6344
6345         /* Anything else is out of spec, warn and ignore */
6346         drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n");
6347         return connector_status_disconnected;
6348 }
6349
6350 static enum drm_connector_status
6351 edp_detect(struct intel_dp *intel_dp)
6352 {
6353         return connector_status_connected;
6354 }
6355
6356 static bool ibx_digital_port_connected(struct intel_encoder *encoder)
6357 {
6358         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6359         u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
6360
6361         return intel_de_read(dev_priv, SDEISR) & bit;
6362 }
6363
6364 static bool g4x_digital_port_connected(struct intel_encoder *encoder)
6365 {
6366         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6367         u32 bit;
6368
6369         switch (encoder->hpd_pin) {
6370         case HPD_PORT_B:
6371                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
6372                 break;
6373         case HPD_PORT_C:
6374                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
6375                 break;
6376         case HPD_PORT_D:
6377                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
6378                 break;
6379         default:
6380                 MISSING_CASE(encoder->hpd_pin);
6381                 return false;
6382         }
6383
6384         return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
6385 }
6386
6387 static bool gm45_digital_port_connected(struct intel_encoder *encoder)
6388 {
6389         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6390         u32 bit;
6391
6392         switch (encoder->hpd_pin) {
6393         case HPD_PORT_B:
6394                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
6395                 break;
6396         case HPD_PORT_C:
6397                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
6398                 break;
6399         case HPD_PORT_D:
6400                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
6401                 break;
6402         default:
6403                 MISSING_CASE(encoder->hpd_pin);
6404                 return false;
6405         }
6406
6407         return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit;
6408 }
6409
6410 static bool ilk_digital_port_connected(struct intel_encoder *encoder)
6411 {
6412         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6413         u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
6414
6415         return intel_de_read(dev_priv, DEISR) & bit;
6416 }
6417
6418 /*
6419  * intel_digital_port_connected - is the specified port connected?
6420  * @encoder: intel_encoder
6421  *
6422  * In cases where there's a connector physically connected but it can't be used
6423  * by our hardware we also return false, since the rest of the driver should
6424  * pretty much treat the port as disconnected. This is relevant for type-C
6425  * (starting on ICL) where there's ownership involved.
6426  *
6427  * Return %true if port is connected, %false otherwise.
6428  */
6429 bool intel_digital_port_connected(struct intel_encoder *encoder)
6430 {
6431         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
6432         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
6433         bool is_connected = false;
6434         intel_wakeref_t wakeref;
6435
6436         with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref)
6437                 is_connected = dig_port->connected(encoder);
6438
6439         return is_connected;
6440 }
6441
6442 static struct edid *
6443 intel_dp_get_edid(struct intel_dp *intel_dp)
6444 {
6445         struct intel_connector *intel_connector = intel_dp->attached_connector;
6446
6447         /* use cached edid if we have one */
6448         if (intel_connector->edid) {
6449                 /* invalid edid */
6450                 if (IS_ERR(intel_connector->edid))
6451                         return NULL;
6452
6453                 return drm_edid_duplicate(intel_connector->edid);
6454         } else
6455                 return drm_get_edid(&intel_connector->base,
6456                                     &intel_dp->aux.ddc);
6457 }
6458
6459 static void
6460 intel_dp_update_dfp(struct intel_dp *intel_dp,
6461                     const struct edid *edid)
6462 {
6463         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6464         struct intel_connector *connector = intel_dp->attached_connector;
6465
6466         intel_dp->dfp.max_bpc =
6467                 drm_dp_downstream_max_bpc(intel_dp->dpcd,
6468                                           intel_dp->downstream_ports, edid);
6469
6470         intel_dp->dfp.max_dotclock =
6471                 drm_dp_downstream_max_dotclock(intel_dp->dpcd,
6472                                                intel_dp->downstream_ports);
6473
6474         intel_dp->dfp.min_tmds_clock =
6475                 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd,
6476                                                  intel_dp->downstream_ports,
6477                                                  edid);
6478         intel_dp->dfp.max_tmds_clock =
6479                 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd,
6480                                                  intel_dp->downstream_ports,
6481                                                  edid);
6482
6483         drm_dbg_kms(&i915->drm,
6484                     "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d\n",
6485                     connector->base.base.id, connector->base.name,
6486                     intel_dp->dfp.max_bpc,
6487                     intel_dp->dfp.max_dotclock,
6488                     intel_dp->dfp.min_tmds_clock,
6489                     intel_dp->dfp.max_tmds_clock);
6490 }
6491
6492 static void
6493 intel_dp_update_420(struct intel_dp *intel_dp)
6494 {
6495         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
6496         struct intel_connector *connector = intel_dp->attached_connector;
6497         bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420;
6498
6499         /* No YCbCr output support on gmch platforms */
6500         if (HAS_GMCH(i915))
6501                 return;
6502
6503         /*
6504          * ILK doesn't seem capable of DP YCbCr output. The
6505          * displayed image is severly corrupted. SNB+ is fine.
6506          */
6507         if (IS_GEN(i915, 5))
6508                 return;
6509
6510         is_branch = drm_dp_is_branch(intel_dp->dpcd);
6511         ycbcr_420_passthrough =
6512                 drm_dp_downstream_420_passthrough(intel_dp->dpcd,
6513                                                   intel_dp->downstream_ports);
6514         /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */
6515         ycbcr_444_to_420 =
6516                 dp_to_dig_port(intel_dp)->lspcon.active ||
6517                 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,
6518                                                         intel_dp->downstream_ports);
6519
6520         if (INTEL_GEN(i915) >= 11) {
6521                 /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */
6522                 intel_dp->dfp.ycbcr_444_to_420 =
6523                         ycbcr_444_to_420 && !ycbcr_420_passthrough;
6524
6525                 connector->base.ycbcr_420_allowed =
6526                         !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough;
6527         } else {
6528                 /* 4:4:4->4:2:0 conversion is the only way */
6529                 intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420;
6530
6531                 connector->base.ycbcr_420_allowed = ycbcr_444_to_420;
6532         }
6533
6534         drm_dbg_kms(&i915->drm,
6535                     "[CONNECTOR:%d:%s] YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",
6536                     connector->base.base.id, connector->base.name,
6537                     yesno(connector->base.ycbcr_420_allowed),
6538                     yesno(intel_dp->dfp.ycbcr_444_to_420));
6539 }
6540
6541 static void
6542 intel_dp_set_edid(struct intel_dp *intel_dp)
6543 {
6544         struct intel_connector *connector = intel_dp->attached_connector;
6545         struct edid *edid;
6546
6547         intel_dp_unset_edid(intel_dp);
6548         edid = intel_dp_get_edid(intel_dp);
6549         connector->detect_edid = edid;
6550
6551         intel_dp_update_dfp(intel_dp, edid);
6552         intel_dp_update_420(intel_dp);
6553
6554         if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
6555                 intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
6556                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
6557         }
6558
6559         drm_dp_cec_set_edid(&intel_dp->aux, edid);
6560         intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid);
6561 }
6562
6563 static void
6564 intel_dp_unset_edid(struct intel_dp *intel_dp)
6565 {
6566         struct intel_connector *connector = intel_dp->attached_connector;
6567
6568         drm_dp_cec_unset_edid(&intel_dp->aux);
6569         kfree(connector->detect_edid);
6570         connector->detect_edid = NULL;
6571
6572         intel_dp->has_hdmi_sink = false;
6573         intel_dp->has_audio = false;
6574         intel_dp->edid_quirks = 0;
6575
6576         intel_dp->dfp.max_bpc = 0;
6577         intel_dp->dfp.max_dotclock = 0;
6578         intel_dp->dfp.min_tmds_clock = 0;
6579         intel_dp->dfp.max_tmds_clock = 0;
6580
6581         intel_dp->dfp.ycbcr_444_to_420 = false;
6582         connector->base.ycbcr_420_allowed = false;
6583 }
6584
6585 static int
6586 intel_dp_detect(struct drm_connector *connector,
6587                 struct drm_modeset_acquire_ctx *ctx,
6588                 bool force)
6589 {
6590         struct drm_i915_private *dev_priv = to_i915(connector->dev);
6591         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6592         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6593         struct intel_encoder *encoder = &dig_port->base;
6594         enum drm_connector_status status;
6595
6596         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
6597                     connector->base.id, connector->name);
6598         drm_WARN_ON(&dev_priv->drm,
6599                     !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex));
6600
6601         if (!INTEL_DISPLAY_ENABLED(dev_priv))
6602                 return connector_status_disconnected;
6603
6604         /* Can't disconnect eDP */
6605         if (intel_dp_is_edp(intel_dp))
6606                 status = edp_detect(intel_dp);
6607         else if (intel_digital_port_connected(encoder))
6608                 status = intel_dp_detect_dpcd(intel_dp);
6609         else
6610                 status = connector_status_disconnected;
6611
6612         if (status == connector_status_disconnected) {
6613                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
6614                 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd));
6615
6616                 if (intel_dp->is_mst) {
6617                         drm_dbg_kms(&dev_priv->drm,
6618                                     "MST device may have disappeared %d vs %d\n",
6619                                     intel_dp->is_mst,
6620                                     intel_dp->mst_mgr.mst_state);
6621                         intel_dp->is_mst = false;
6622                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
6623                                                         intel_dp->is_mst);
6624                 }
6625
6626                 goto out;
6627         }
6628
6629         /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */
6630         if (INTEL_GEN(dev_priv) >= 11)
6631                 intel_dp_get_dsc_sink_cap(intel_dp);
6632
6633         intel_dp_configure_mst(intel_dp);
6634
6635         /*
6636          * TODO: Reset link params when switching to MST mode, until MST
6637          * supports link training fallback params.
6638          */
6639         if (intel_dp->reset_link_params || intel_dp->is_mst) {
6640                 /* Initial max link lane count */
6641                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
6642
6643                 /* Initial max link rate */
6644                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
6645
6646                 intel_dp->reset_link_params = false;
6647         }
6648
6649         intel_dp_print_rates(intel_dp);
6650
6651         if (intel_dp->is_mst) {
6652                 /*
6653                  * If we are in MST mode then this connector
6654                  * won't appear connected or have anything
6655                  * with EDID on it
6656                  */
6657                 status = connector_status_disconnected;
6658                 goto out;
6659         }
6660
6661         /*
6662          * Some external monitors do not signal loss of link synchronization
6663          * with an IRQ_HPD, so force a link status check.
6664          */
6665         if (!intel_dp_is_edp(intel_dp)) {
6666                 int ret;
6667
6668                 ret = intel_dp_retrain_link(encoder, ctx);
6669                 if (ret)
6670                         return ret;
6671         }
6672
6673         /*
6674          * Clearing NACK and defer counts to get their exact values
6675          * while reading EDID which are required by Compliance tests
6676          * 4.2.2.4 and 4.2.2.5
6677          */
6678         intel_dp->aux.i2c_nack_count = 0;
6679         intel_dp->aux.i2c_defer_count = 0;
6680
6681         intel_dp_set_edid(intel_dp);
6682         if (intel_dp_is_edp(intel_dp) ||
6683             to_intel_connector(connector)->detect_edid)
6684                 status = connector_status_connected;
6685
6686         intel_dp_check_service_irq(intel_dp);
6687
6688 out:
6689         if (status != connector_status_connected && !intel_dp->is_mst)
6690                 intel_dp_unset_edid(intel_dp);
6691
6692         /*
6693          * Make sure the refs for power wells enabled during detect are
6694          * dropped to avoid a new detect cycle triggered by HPD polling.
6695          */
6696         intel_display_power_flush_work(dev_priv);
6697
6698         if (!intel_dp_is_edp(intel_dp))
6699                 drm_dp_set_subconnector_property(connector,
6700                                                  status,
6701                                                  intel_dp->dpcd,
6702                                                  intel_dp->downstream_ports);
6703         return status;
6704 }
6705
6706 static void
6707 intel_dp_force(struct drm_connector *connector)
6708 {
6709         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6710         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6711         struct intel_encoder *intel_encoder = &dig_port->base;
6712         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
6713         enum intel_display_power_domain aux_domain =
6714                 intel_aux_power_domain(dig_port);
6715         intel_wakeref_t wakeref;
6716
6717         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
6718                     connector->base.id, connector->name);
6719         intel_dp_unset_edid(intel_dp);
6720
6721         if (connector->status != connector_status_connected)
6722                 return;
6723
6724         wakeref = intel_display_power_get(dev_priv, aux_domain);
6725
6726         intel_dp_set_edid(intel_dp);
6727
6728         intel_display_power_put(dev_priv, aux_domain, wakeref);
6729 }
6730
6731 static int intel_dp_get_modes(struct drm_connector *connector)
6732 {
6733         struct intel_connector *intel_connector = to_intel_connector(connector);
6734         struct edid *edid;
6735
6736         edid = intel_connector->detect_edid;
6737         if (edid) {
6738                 int ret = intel_connector_update_modes(connector, edid);
6739                 if (ret)
6740                         return ret;
6741         }
6742
6743         /* if eDP has no EDID, fall back to fixed mode */
6744         if (intel_dp_is_edp(intel_attached_dp(intel_connector)) &&
6745             intel_connector->panel.fixed_mode) {
6746                 struct drm_display_mode *mode;
6747
6748                 mode = drm_mode_duplicate(connector->dev,
6749                                           intel_connector->panel.fixed_mode);
6750                 if (mode) {
6751                         drm_mode_probed_add(connector, mode);
6752                         return 1;
6753                 }
6754         }
6755
6756         if (!edid) {
6757                 struct intel_dp *intel_dp = intel_attached_dp(intel_connector);
6758                 struct drm_display_mode *mode;
6759
6760                 mode = drm_dp_downstream_mode(connector->dev,
6761                                               intel_dp->dpcd,
6762                                               intel_dp->downstream_ports);
6763                 if (mode) {
6764                         drm_mode_probed_add(connector, mode);
6765                         return 1;
6766                 }
6767         }
6768
6769         return 0;
6770 }
6771
6772 static int
6773 intel_dp_connector_register(struct drm_connector *connector)
6774 {
6775         struct drm_i915_private *i915 = to_i915(connector->dev);
6776         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6777         int ret;
6778
6779         ret = intel_connector_register(connector);
6780         if (ret)
6781                 return ret;
6782
6783         drm_dbg_kms(&i915->drm, "registering %s bus for %s\n",
6784                     intel_dp->aux.name, connector->kdev->kobj.name);
6785
6786         intel_dp->aux.dev = connector->kdev;
6787         ret = drm_dp_aux_register(&intel_dp->aux);
6788         if (!ret)
6789                 drm_dp_cec_register_connector(&intel_dp->aux, connector);
6790         return ret;
6791 }
6792
6793 static void
6794 intel_dp_connector_unregister(struct drm_connector *connector)
6795 {
6796         struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
6797
6798         drm_dp_cec_unregister_connector(&intel_dp->aux);
6799         drm_dp_aux_unregister(&intel_dp->aux);
6800         intel_connector_unregister(connector);
6801 }
6802
6803 void intel_dp_encoder_flush_work(struct drm_encoder *encoder)
6804 {
6805         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
6806         struct intel_dp *intel_dp = &dig_port->dp;
6807
6808         intel_dp_mst_encoder_cleanup(dig_port);
6809         if (intel_dp_is_edp(intel_dp)) {
6810                 intel_wakeref_t wakeref;
6811
6812                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6813                 /*
6814                  * vdd might still be enabled do to the delayed vdd off.
6815                  * Make sure vdd is actually turned off here.
6816                  */
6817                 with_pps_lock(intel_dp, wakeref)
6818                         edp_panel_vdd_off_sync(intel_dp);
6819         }
6820
6821         intel_dp_aux_fini(intel_dp);
6822 }
6823
6824 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
6825 {
6826         intel_dp_encoder_flush_work(encoder);
6827
6828         drm_encoder_cleanup(encoder);
6829         kfree(enc_to_dig_port(to_intel_encoder(encoder)));
6830 }
6831
6832 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
6833 {
6834         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
6835         intel_wakeref_t wakeref;
6836
6837         if (!intel_dp_is_edp(intel_dp))
6838                 return;
6839
6840         /*
6841          * vdd might still be enabled do to the delayed vdd off.
6842          * Make sure vdd is actually turned off here.
6843          */
6844         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
6845         with_pps_lock(intel_dp, wakeref)
6846                 edp_panel_vdd_off_sync(intel_dp);
6847 }
6848
6849 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder)
6850 {
6851         struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder);
6852         intel_wakeref_t wakeref;
6853
6854         if (!intel_dp_is_edp(intel_dp))
6855                 return;
6856
6857         with_pps_lock(intel_dp, wakeref)
6858                 wait_panel_power_cycle(intel_dp);
6859 }
6860
6861 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
6862 {
6863         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6864         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
6865
6866         lockdep_assert_held(&dev_priv->pps_mutex);
6867
6868         if (!edp_have_panel_vdd(intel_dp))
6869                 return;
6870
6871         /*
6872          * The VDD bit needs a power domain reference, so if the bit is
6873          * already enabled when we boot or resume, grab this reference and
6874          * schedule a vdd off, so we don't hold on to the reference
6875          * indefinitely.
6876          */
6877         drm_dbg_kms(&dev_priv->drm,
6878                     "VDD left on by BIOS, adjusting state tracking\n");
6879         intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port));
6880
6881         edp_panel_vdd_schedule_off(intel_dp);
6882 }
6883
6884 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
6885 {
6886         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
6887         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
6888         enum pipe pipe;
6889
6890         if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg,
6891                                   encoder->port, &pipe))
6892                 return pipe;
6893
6894         return INVALID_PIPE;
6895 }
6896
6897 void intel_dp_encoder_reset(struct drm_encoder *encoder)
6898 {
6899         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
6900         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
6901         intel_wakeref_t wakeref;
6902
6903         if (!HAS_DDI(dev_priv))
6904                 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
6905
6906         intel_dp->reset_link_params = true;
6907
6908         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
6909             !intel_dp_is_edp(intel_dp))
6910                 return;
6911
6912         with_pps_lock(intel_dp, wakeref) {
6913                 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6914                         intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6915
6916                 if (intel_dp_is_edp(intel_dp)) {
6917                         /*
6918                          * Reinit the power sequencer, in case BIOS did
6919                          * something nasty with it.
6920                          */
6921                         intel_dp_pps_init(intel_dp);
6922                         intel_edp_panel_vdd_sanitize(intel_dp);
6923                 }
6924         }
6925 }
6926
6927 static int intel_modeset_tile_group(struct intel_atomic_state *state,
6928                                     int tile_group_id)
6929 {
6930         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6931         struct drm_connector_list_iter conn_iter;
6932         struct drm_connector *connector;
6933         int ret = 0;
6934
6935         drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter);
6936         drm_for_each_connector_iter(connector, &conn_iter) {
6937                 struct drm_connector_state *conn_state;
6938                 struct intel_crtc_state *crtc_state;
6939                 struct intel_crtc *crtc;
6940
6941                 if (!connector->has_tile ||
6942                     connector->tile_group->id != tile_group_id)
6943                         continue;
6944
6945                 conn_state = drm_atomic_get_connector_state(&state->base,
6946                                                             connector);
6947                 if (IS_ERR(conn_state)) {
6948                         ret = PTR_ERR(conn_state);
6949                         break;
6950                 }
6951
6952                 crtc = to_intel_crtc(conn_state->crtc);
6953
6954                 if (!crtc)
6955                         continue;
6956
6957                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6958                 crtc_state->uapi.mode_changed = true;
6959
6960                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
6961                 if (ret)
6962                         break;
6963         }
6964         drm_connector_list_iter_end(&conn_iter);
6965
6966         return ret;
6967 }
6968
6969 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)
6970 {
6971         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6972         struct intel_crtc *crtc;
6973
6974         if (transcoders == 0)
6975                 return 0;
6976
6977         for_each_intel_crtc(&dev_priv->drm, crtc) {
6978                 struct intel_crtc_state *crtc_state;
6979                 int ret;
6980
6981                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6982                 if (IS_ERR(crtc_state))
6983                         return PTR_ERR(crtc_state);
6984
6985                 if (!crtc_state->hw.enable)
6986                         continue;
6987
6988                 if (!(transcoders & BIT(crtc_state->cpu_transcoder)))
6989                         continue;
6990
6991                 crtc_state->uapi.mode_changed = true;
6992
6993                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
6994                 if (ret)
6995                         return ret;
6996
6997                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
6998                 if (ret)
6999                         return ret;
7000
7001                 transcoders &= ~BIT(crtc_state->cpu_transcoder);
7002         }
7003
7004         drm_WARN_ON(&dev_priv->drm, transcoders != 0);
7005
7006         return 0;
7007 }
7008
7009 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state,
7010                                       struct drm_connector *connector)
7011 {
7012         const struct drm_connector_state *old_conn_state =
7013                 drm_atomic_get_old_connector_state(&state->base, connector);
7014         const struct intel_crtc_state *old_crtc_state;
7015         struct intel_crtc *crtc;
7016         u8 transcoders;
7017
7018         crtc = to_intel_crtc(old_conn_state->crtc);
7019         if (!crtc)
7020                 return 0;
7021
7022         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
7023
7024         if (!old_crtc_state->hw.active)
7025                 return 0;
7026
7027         transcoders = old_crtc_state->sync_mode_slaves_mask;
7028         if (old_crtc_state->master_transcoder != INVALID_TRANSCODER)
7029                 transcoders |= BIT(old_crtc_state->master_transcoder);
7030
7031         return intel_modeset_affected_transcoders(state,
7032                                                   transcoders);
7033 }
7034
7035 static int intel_dp_connector_atomic_check(struct drm_connector *conn,
7036                                            struct drm_atomic_state *_state)
7037 {
7038         struct drm_i915_private *dev_priv = to_i915(conn->dev);
7039         struct intel_atomic_state *state = to_intel_atomic_state(_state);
7040         int ret;
7041
7042         ret = intel_digital_connector_atomic_check(conn, &state->base);
7043         if (ret)
7044                 return ret;
7045
7046         /*
7047          * We don't enable port sync on BDW due to missing w/as and
7048          * due to not having adjusted the modeset sequence appropriately.
7049          */
7050         if (INTEL_GEN(dev_priv) < 9)
7051                 return 0;
7052
7053         if (!intel_connector_needs_modeset(state, conn))
7054                 return 0;
7055
7056         if (conn->has_tile) {
7057                 ret = intel_modeset_tile_group(state, conn->tile_group->id);
7058                 if (ret)
7059                         return ret;
7060         }
7061
7062         return intel_modeset_synced_crtcs(state, conn);
7063 }
7064
7065 static const struct drm_connector_funcs intel_dp_connector_funcs = {
7066         .force = intel_dp_force,
7067         .fill_modes = drm_helper_probe_single_connector_modes,
7068         .atomic_get_property = intel_digital_connector_atomic_get_property,
7069         .atomic_set_property = intel_digital_connector_atomic_set_property,
7070         .late_register = intel_dp_connector_register,
7071         .early_unregister = intel_dp_connector_unregister,
7072         .destroy = intel_connector_destroy,
7073         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
7074         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
7075 };
7076
7077 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
7078         .detect_ctx = intel_dp_detect,
7079         .get_modes = intel_dp_get_modes,
7080         .mode_valid = intel_dp_mode_valid,
7081         .atomic_check = intel_dp_connector_atomic_check,
7082 };
7083
7084 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
7085         .reset = intel_dp_encoder_reset,
7086         .destroy = intel_dp_encoder_destroy,
7087 };
7088
7089 static bool intel_edp_have_power(struct intel_dp *intel_dp)
7090 {
7091         intel_wakeref_t wakeref;
7092         bool have_power = false;
7093
7094         with_pps_lock(intel_dp, wakeref) {
7095                 have_power = edp_have_panel_power(intel_dp) &&
7096                                                   edp_have_panel_vdd(intel_dp);
7097         }
7098
7099         return have_power;
7100 }
7101
7102 enum irqreturn
7103 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)
7104 {
7105         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
7106         struct intel_dp *intel_dp = &dig_port->dp;
7107
7108         if (dig_port->base.type == INTEL_OUTPUT_EDP &&
7109             (long_hpd || !intel_edp_have_power(intel_dp))) {
7110                 /*
7111                  * vdd off can generate a long/short pulse on eDP which
7112                  * would require vdd on to handle it, and thus we
7113                  * would end up in an endless cycle of
7114                  * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."
7115                  */
7116                 drm_dbg_kms(&i915->drm,
7117                             "ignoring %s hpd on eDP [ENCODER:%d:%s]\n",
7118                             long_hpd ? "long" : "short",
7119                             dig_port->base.base.base.id,
7120                             dig_port->base.base.name);
7121                 return IRQ_HANDLED;
7122         }
7123
7124         drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n",
7125                     dig_port->base.base.base.id,
7126                     dig_port->base.base.name,
7127                     long_hpd ? "long" : "short");
7128
7129         if (long_hpd) {
7130                 intel_dp->reset_link_params = true;
7131                 return IRQ_NONE;
7132         }
7133
7134         if (intel_dp->is_mst) {
7135                 if (!intel_dp_check_mst_status(intel_dp))
7136                         return IRQ_NONE;
7137         } else if (!intel_dp_short_pulse(intel_dp)) {
7138                 return IRQ_NONE;
7139         }
7140
7141         return IRQ_HANDLED;
7142 }
7143
7144 /* check the VBT to see whether the eDP is on another port */
7145 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port)
7146 {
7147         /*
7148          * eDP not supported on g4x. so bail out early just
7149          * for a bit extra safety in case the VBT is bonkers.
7150          */
7151         if (INTEL_GEN(dev_priv) < 5)
7152                 return false;
7153
7154         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
7155                 return true;
7156
7157         return intel_bios_is_port_edp(dev_priv, port);
7158 }
7159
7160 static void
7161 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
7162 {
7163         struct drm_i915_private *dev_priv = to_i915(connector->dev);
7164         enum port port = dp_to_dig_port(intel_dp)->base.port;
7165
7166         if (!intel_dp_is_edp(intel_dp))
7167                 drm_connector_attach_dp_subconnector_property(connector);
7168
7169         if (!IS_G4X(dev_priv) && port != PORT_A)
7170                 intel_attach_force_audio_property(connector);
7171
7172         intel_attach_broadcast_rgb_property(connector);
7173         if (HAS_GMCH(dev_priv))
7174                 drm_connector_attach_max_bpc_property(connector, 6, 10);
7175         else if (INTEL_GEN(dev_priv) >= 5)
7176                 drm_connector_attach_max_bpc_property(connector, 6, 12);
7177
7178         intel_attach_colorspace_property(connector);
7179
7180         if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 11)
7181                 drm_object_attach_property(&connector->base,
7182                                            connector->dev->mode_config.hdr_output_metadata_property,
7183                                            0);
7184
7185         if (intel_dp_is_edp(intel_dp)) {
7186                 u32 allowed_scalers;
7187
7188                 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN);
7189                 if (!HAS_GMCH(dev_priv))
7190                         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
7191
7192                 drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
7193
7194                 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
7195
7196         }
7197 }
7198
7199 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
7200 {
7201         intel_dp->panel_power_off_time = ktime_get_boottime();
7202         intel_dp->last_power_on = jiffies;
7203         intel_dp->last_backlight_off = jiffies;
7204 }
7205
7206 static void
7207 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq)
7208 {
7209         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7210         u32 pp_on, pp_off, pp_ctl;
7211         struct pps_registers regs;
7212
7213         intel_pps_get_registers(intel_dp, &regs);
7214
7215         pp_ctl = ilk_get_pp_control(intel_dp);
7216
7217         /* Ensure PPS is unlocked */
7218         if (!HAS_DDI(dev_priv))
7219                 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
7220
7221         pp_on = intel_de_read(dev_priv, regs.pp_on);
7222         pp_off = intel_de_read(dev_priv, regs.pp_off);
7223
7224         /* Pull timing values out of registers */
7225         seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
7226         seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
7227         seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off);
7228         seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off);
7229
7230         if (i915_mmio_reg_valid(regs.pp_div)) {
7231                 u32 pp_div;
7232
7233                 pp_div = intel_de_read(dev_priv, regs.pp_div);
7234
7235                 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000;
7236         } else {
7237                 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000;
7238         }
7239 }
7240
7241 static void
7242 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
7243 {
7244         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
7245                       state_name,
7246                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
7247 }
7248
7249 static void
7250 intel_pps_verify_state(struct intel_dp *intel_dp)
7251 {
7252         struct edp_power_seq hw;
7253         struct edp_power_seq *sw = &intel_dp->pps_delays;
7254
7255         intel_pps_readout_hw_state(intel_dp, &hw);
7256
7257         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
7258             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
7259                 DRM_ERROR("PPS state mismatch\n");
7260                 intel_pps_dump_state("sw", sw);
7261                 intel_pps_dump_state("hw", &hw);
7262         }
7263 }
7264
7265 static void
7266 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp)
7267 {
7268         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7269         struct edp_power_seq cur, vbt, spec,
7270                 *final = &intel_dp->pps_delays;
7271
7272         lockdep_assert_held(&dev_priv->pps_mutex);
7273
7274         /* already initialized? */
7275         if (final->t11_t12 != 0)
7276                 return;
7277
7278         intel_pps_readout_hw_state(intel_dp, &cur);
7279
7280         intel_pps_dump_state("cur", &cur);
7281
7282         vbt = dev_priv->vbt.edp.pps;
7283         /* On Toshiba Satellite P50-C-18C system the VBT T12 delay
7284          * of 500ms appears to be too short. Ocassionally the panel
7285          * just fails to power back on. Increasing the delay to 800ms
7286          * seems sufficient to avoid this problem.
7287          */
7288         if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) {
7289                 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10);
7290                 drm_dbg_kms(&dev_priv->drm,
7291                             "Increasing T12 panel delay as per the quirk to %d\n",
7292                             vbt.t11_t12);
7293         }
7294         /* T11_T12 delay is special and actually in units of 100ms, but zero
7295          * based in the hw (so we need to add 100 ms). But the sw vbt
7296          * table multiplies it with 1000 to make it in units of 100usec,
7297          * too. */
7298         vbt.t11_t12 += 100 * 10;
7299
7300         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
7301          * our hw here, which are all in 100usec. */
7302         spec.t1_t3 = 210 * 10;
7303         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
7304         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
7305         spec.t10 = 500 * 10;
7306         /* This one is special and actually in units of 100ms, but zero
7307          * based in the hw (so we need to add 100 ms). But the sw vbt
7308          * table multiplies it with 1000 to make it in units of 100usec,
7309          * too. */
7310         spec.t11_t12 = (510 + 100) * 10;
7311
7312         intel_pps_dump_state("vbt", &vbt);
7313
7314         /* Use the max of the register settings and vbt. If both are
7315          * unset, fall back to the spec limits. */
7316 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
7317                                        spec.field : \
7318                                        max(cur.field, vbt.field))
7319         assign_final(t1_t3);
7320         assign_final(t8);
7321         assign_final(t9);
7322         assign_final(t10);
7323         assign_final(t11_t12);
7324 #undef assign_final
7325
7326 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
7327         intel_dp->panel_power_up_delay = get_delay(t1_t3);
7328         intel_dp->backlight_on_delay = get_delay(t8);
7329         intel_dp->backlight_off_delay = get_delay(t9);
7330         intel_dp->panel_power_down_delay = get_delay(t10);
7331         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
7332 #undef get_delay
7333
7334         drm_dbg_kms(&dev_priv->drm,
7335                     "panel power up delay %d, power down delay %d, power cycle delay %d\n",
7336                     intel_dp->panel_power_up_delay,
7337                     intel_dp->panel_power_down_delay,
7338                     intel_dp->panel_power_cycle_delay);
7339
7340         drm_dbg_kms(&dev_priv->drm, "backlight on delay %d, off delay %d\n",
7341                     intel_dp->backlight_on_delay,
7342                     intel_dp->backlight_off_delay);
7343
7344         /*
7345          * We override the HW backlight delays to 1 because we do manual waits
7346          * on them. For T8, even BSpec recommends doing it. For T9, if we
7347          * don't do this, we'll end up waiting for the backlight off delay
7348          * twice: once when we do the manual sleep, and once when we disable
7349          * the panel and wait for the PP_STATUS bit to become zero.
7350          */
7351         final->t8 = 1;
7352         final->t9 = 1;
7353
7354         /*
7355          * HW has only a 100msec granularity for t11_t12 so round it up
7356          * accordingly.
7357          */
7358         final->t11_t12 = roundup(final->t11_t12, 100 * 10);
7359 }
7360
7361 static void
7362 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
7363                                               bool force_disable_vdd)
7364 {
7365         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7366         u32 pp_on, pp_off, port_sel = 0;
7367         int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000;
7368         struct pps_registers regs;
7369         enum port port = dp_to_dig_port(intel_dp)->base.port;
7370         const struct edp_power_seq *seq = &intel_dp->pps_delays;
7371
7372         lockdep_assert_held(&dev_priv->pps_mutex);
7373
7374         intel_pps_get_registers(intel_dp, &regs);
7375
7376         /*
7377          * On some VLV machines the BIOS can leave the VDD
7378          * enabled even on power sequencers which aren't
7379          * hooked up to any port. This would mess up the
7380          * power domain tracking the first time we pick
7381          * one of these power sequencers for use since
7382          * edp_panel_vdd_on() would notice that the VDD was
7383          * already on and therefore wouldn't grab the power
7384          * domain reference. Disable VDD first to avoid this.
7385          * This also avoids spuriously turning the VDD on as
7386          * soon as the new power sequencer gets initialized.
7387          */
7388         if (force_disable_vdd) {
7389                 u32 pp = ilk_get_pp_control(intel_dp);
7390
7391                 drm_WARN(&dev_priv->drm, pp & PANEL_POWER_ON,
7392                          "Panel power already on\n");
7393
7394                 if (pp & EDP_FORCE_VDD)
7395                         drm_dbg_kms(&dev_priv->drm,
7396                                     "VDD already on, disabling first\n");
7397
7398                 pp &= ~EDP_FORCE_VDD;
7399
7400                 intel_de_write(dev_priv, regs.pp_ctrl, pp);
7401         }
7402
7403         pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
7404                 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8);
7405         pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) |
7406                 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10);
7407
7408         /* Haswell doesn't have any port selection bits for the panel
7409          * power sequencer any more. */
7410         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7411                 port_sel = PANEL_PORT_SELECT_VLV(port);
7412         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
7413                 switch (port) {
7414                 case PORT_A:
7415                         port_sel = PANEL_PORT_SELECT_DPA;
7416                         break;
7417                 case PORT_C:
7418                         port_sel = PANEL_PORT_SELECT_DPC;
7419                         break;
7420                 case PORT_D:
7421                         port_sel = PANEL_PORT_SELECT_DPD;
7422                         break;
7423                 default:
7424                         MISSING_CASE(port);
7425                         break;
7426                 }
7427         }
7428
7429         pp_on |= port_sel;
7430
7431         intel_de_write(dev_priv, regs.pp_on, pp_on);
7432         intel_de_write(dev_priv, regs.pp_off, pp_off);
7433
7434         /*
7435          * Compute the divisor for the pp clock, simply match the Bspec formula.
7436          */
7437         if (i915_mmio_reg_valid(regs.pp_div)) {
7438                 intel_de_write(dev_priv, regs.pp_div,
7439                                REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)));
7440         } else {
7441                 u32 pp_ctl;
7442
7443                 pp_ctl = intel_de_read(dev_priv, regs.pp_ctrl);
7444                 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
7445                 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
7446                 intel_de_write(dev_priv, regs.pp_ctrl, pp_ctl);
7447         }
7448
7449         drm_dbg_kms(&dev_priv->drm,
7450                     "panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
7451                     intel_de_read(dev_priv, regs.pp_on),
7452                     intel_de_read(dev_priv, regs.pp_off),
7453                     i915_mmio_reg_valid(regs.pp_div) ?
7454                     intel_de_read(dev_priv, regs.pp_div) :
7455                     (intel_de_read(dev_priv, regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK));
7456 }
7457
7458 static void intel_dp_pps_init(struct intel_dp *intel_dp)
7459 {
7460         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7461
7462         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7463                 vlv_initial_power_sequencer_setup(intel_dp);
7464         } else {
7465                 intel_dp_init_panel_power_sequencer(intel_dp);
7466                 intel_dp_init_panel_power_sequencer_registers(intel_dp, false);
7467         }
7468 }
7469
7470 /**
7471  * intel_dp_set_drrs_state - program registers for RR switch to take effect
7472  * @dev_priv: i915 device
7473  * @crtc_state: a pointer to the active intel_crtc_state
7474  * @refresh_rate: RR to be programmed
7475  *
7476  * This function gets called when refresh rate (RR) has to be changed from
7477  * one frequency to another. Switches can be between high and low RR
7478  * supported by the panel or to any other RR based on media playback (in
7479  * this case, RR value needs to be passed from user space).
7480  *
7481  * The caller of this function needs to take a lock on dev_priv->drrs.
7482  */
7483 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
7484                                     const struct intel_crtc_state *crtc_state,
7485                                     int refresh_rate)
7486 {
7487         struct intel_dp *intel_dp = dev_priv->drrs.dp;
7488         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
7489         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
7490
7491         if (refresh_rate <= 0) {
7492                 drm_dbg_kms(&dev_priv->drm,
7493                             "Refresh rate should be positive non-zero.\n");
7494                 return;
7495         }
7496
7497         if (intel_dp == NULL) {
7498                 drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n");
7499                 return;
7500         }
7501
7502         if (!intel_crtc) {
7503                 drm_dbg_kms(&dev_priv->drm,
7504                             "DRRS: intel_crtc not initialized\n");
7505                 return;
7506         }
7507
7508         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
7509                 drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n");
7510                 return;
7511         }
7512
7513         if (drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode) ==
7514                         refresh_rate)
7515                 index = DRRS_LOW_RR;
7516
7517         if (index == dev_priv->drrs.refresh_rate_type) {
7518                 drm_dbg_kms(&dev_priv->drm,
7519                             "DRRS requested for previously set RR...ignoring\n");
7520                 return;
7521         }
7522
7523         if (!crtc_state->hw.active) {
7524                 drm_dbg_kms(&dev_priv->drm,
7525                             "eDP encoder disabled. CRTC not Active\n");
7526                 return;
7527         }
7528
7529         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
7530                 switch (index) {
7531                 case DRRS_HIGH_RR:
7532                         intel_dp_set_m_n(crtc_state, M1_N1);
7533                         break;
7534                 case DRRS_LOW_RR:
7535                         intel_dp_set_m_n(crtc_state, M2_N2);
7536                         break;
7537                 case DRRS_MAX_RR:
7538                 default:
7539                         drm_err(&dev_priv->drm,
7540                                 "Unsupported refreshrate type\n");
7541                 }
7542         } else if (INTEL_GEN(dev_priv) > 6) {
7543                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
7544                 u32 val;
7545
7546                 val = intel_de_read(dev_priv, reg);
7547                 if (index > DRRS_HIGH_RR) {
7548                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7549                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7550                         else
7551                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
7552                 } else {
7553                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
7554                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
7555                         else
7556                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
7557                 }
7558                 intel_de_write(dev_priv, reg, val);
7559         }
7560
7561         dev_priv->drrs.refresh_rate_type = index;
7562
7563         drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n",
7564                     refresh_rate);
7565 }
7566
7567 static void
7568 intel_edp_drrs_enable_locked(struct intel_dp *intel_dp)
7569 {
7570         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7571
7572         dev_priv->drrs.busy_frontbuffer_bits = 0;
7573         dev_priv->drrs.dp = intel_dp;
7574 }
7575
7576 /**
7577  * intel_edp_drrs_enable - init drrs struct if supported
7578  * @intel_dp: DP struct
7579  * @crtc_state: A pointer to the active crtc state.
7580  *
7581  * Initializes frontbuffer_bits and drrs.dp
7582  */
7583 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
7584                            const struct intel_crtc_state *crtc_state)
7585 {
7586         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7587
7588         if (!crtc_state->has_drrs)
7589                 return;
7590
7591         drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n");
7592
7593         mutex_lock(&dev_priv->drrs.mutex);
7594
7595         if (dev_priv->drrs.dp) {
7596                 drm_warn(&dev_priv->drm, "DRRS already enabled\n");
7597                 goto unlock;
7598         }
7599
7600         intel_edp_drrs_enable_locked(intel_dp);
7601
7602 unlock:
7603         mutex_unlock(&dev_priv->drrs.mutex);
7604 }
7605
7606 static void
7607 intel_edp_drrs_disable_locked(struct intel_dp *intel_dp,
7608                               const struct intel_crtc_state *crtc_state)
7609 {
7610         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7611
7612         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) {
7613                 int refresh;
7614
7615                 refresh = drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode);
7616                 intel_dp_set_drrs_state(dev_priv, crtc_state, refresh);
7617         }
7618
7619         dev_priv->drrs.dp = NULL;
7620 }
7621
7622 /**
7623  * intel_edp_drrs_disable - Disable DRRS
7624  * @intel_dp: DP struct
7625  * @old_crtc_state: Pointer to old crtc_state.
7626  *
7627  */
7628 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
7629                             const struct intel_crtc_state *old_crtc_state)
7630 {
7631         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7632
7633         if (!old_crtc_state->has_drrs)
7634                 return;
7635
7636         mutex_lock(&dev_priv->drrs.mutex);
7637         if (!dev_priv->drrs.dp) {
7638                 mutex_unlock(&dev_priv->drrs.mutex);
7639                 return;
7640         }
7641
7642         intel_edp_drrs_disable_locked(intel_dp, old_crtc_state);
7643         mutex_unlock(&dev_priv->drrs.mutex);
7644
7645         cancel_delayed_work_sync(&dev_priv->drrs.work);
7646 }
7647
7648 /**
7649  * intel_edp_drrs_update - Update DRRS state
7650  * @intel_dp: Intel DP
7651  * @crtc_state: new CRTC state
7652  *
7653  * This function will update DRRS states, disabling or enabling DRRS when
7654  * executing fastsets. For full modeset, intel_edp_drrs_disable() and
7655  * intel_edp_drrs_enable() should be called instead.
7656  */
7657 void
7658 intel_edp_drrs_update(struct intel_dp *intel_dp,
7659                       const struct intel_crtc_state *crtc_state)
7660 {
7661         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7662
7663         if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT)
7664                 return;
7665
7666         mutex_lock(&dev_priv->drrs.mutex);
7667
7668         /* New state matches current one? */
7669         if (crtc_state->has_drrs == !!dev_priv->drrs.dp)
7670                 goto unlock;
7671
7672         if (crtc_state->has_drrs)
7673                 intel_edp_drrs_enable_locked(intel_dp);
7674         else
7675                 intel_edp_drrs_disable_locked(intel_dp, crtc_state);
7676
7677 unlock:
7678         mutex_unlock(&dev_priv->drrs.mutex);
7679 }
7680
7681 static void intel_edp_drrs_downclock_work(struct work_struct *work)
7682 {
7683         struct drm_i915_private *dev_priv =
7684                 container_of(work, typeof(*dev_priv), drrs.work.work);
7685         struct intel_dp *intel_dp;
7686
7687         mutex_lock(&dev_priv->drrs.mutex);
7688
7689         intel_dp = dev_priv->drrs.dp;
7690
7691         if (!intel_dp)
7692                 goto unlock;
7693
7694         /*
7695          * The delayed work can race with an invalidate hence we need to
7696          * recheck.
7697          */
7698
7699         if (dev_priv->drrs.busy_frontbuffer_bits)
7700                 goto unlock;
7701
7702         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
7703                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
7704
7705                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7706                         drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode));
7707         }
7708
7709 unlock:
7710         mutex_unlock(&dev_priv->drrs.mutex);
7711 }
7712
7713 /**
7714  * intel_edp_drrs_invalidate - Disable Idleness DRRS
7715  * @dev_priv: i915 device
7716  * @frontbuffer_bits: frontbuffer plane tracking bits
7717  *
7718  * This function gets called everytime rendering on the given planes start.
7719  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
7720  *
7721  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
7722  */
7723 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
7724                                unsigned int frontbuffer_bits)
7725 {
7726         struct intel_dp *intel_dp;
7727         struct drm_crtc *crtc;
7728         enum pipe pipe;
7729
7730         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
7731                 return;
7732
7733         cancel_delayed_work(&dev_priv->drrs.work);
7734
7735         mutex_lock(&dev_priv->drrs.mutex);
7736
7737         intel_dp = dev_priv->drrs.dp;
7738         if (!intel_dp) {
7739                 mutex_unlock(&dev_priv->drrs.mutex);
7740                 return;
7741         }
7742
7743         crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
7744         pipe = to_intel_crtc(crtc)->pipe;
7745
7746         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
7747         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
7748
7749         /* invalidate means busy screen hence upclock */
7750         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7751                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7752                                         drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
7753
7754         mutex_unlock(&dev_priv->drrs.mutex);
7755 }
7756
7757 /**
7758  * intel_edp_drrs_flush - Restart Idleness DRRS
7759  * @dev_priv: i915 device
7760  * @frontbuffer_bits: frontbuffer plane tracking bits
7761  *
7762  * This function gets called every time rendering on the given planes has
7763  * completed or flip on a crtc is completed. So DRRS should be upclocked
7764  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
7765  * if no other planes are dirty.
7766  *
7767  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
7768  */
7769 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
7770                           unsigned int frontbuffer_bits)
7771 {
7772         struct intel_dp *intel_dp;
7773         struct drm_crtc *crtc;
7774         enum pipe pipe;
7775
7776         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
7777                 return;
7778
7779         cancel_delayed_work(&dev_priv->drrs.work);
7780
7781         mutex_lock(&dev_priv->drrs.mutex);
7782
7783         intel_dp = dev_priv->drrs.dp;
7784         if (!intel_dp) {
7785                 mutex_unlock(&dev_priv->drrs.mutex);
7786                 return;
7787         }
7788
7789         crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
7790         pipe = to_intel_crtc(crtc)->pipe;
7791
7792         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
7793         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
7794
7795         /* flush means busy screen hence upclock */
7796         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
7797                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
7798                                         drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode));
7799
7800         /*
7801          * flush also means no more activity hence schedule downclock, if all
7802          * other fbs are quiescent too
7803          */
7804         if (!dev_priv->drrs.busy_frontbuffer_bits)
7805                 schedule_delayed_work(&dev_priv->drrs.work,
7806                                 msecs_to_jiffies(1000));
7807         mutex_unlock(&dev_priv->drrs.mutex);
7808 }
7809
7810 /**
7811  * DOC: Display Refresh Rate Switching (DRRS)
7812  *
7813  * Display Refresh Rate Switching (DRRS) is a power conservation feature
7814  * which enables swtching between low and high refresh rates,
7815  * dynamically, based on the usage scenario. This feature is applicable
7816  * for internal panels.
7817  *
7818  * Indication that the panel supports DRRS is given by the panel EDID, which
7819  * would list multiple refresh rates for one resolution.
7820  *
7821  * DRRS is of 2 types - static and seamless.
7822  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
7823  * (may appear as a blink on screen) and is used in dock-undock scenario.
7824  * Seamless DRRS involves changing RR without any visual effect to the user
7825  * and can be used during normal system usage. This is done by programming
7826  * certain registers.
7827  *
7828  * Support for static/seamless DRRS may be indicated in the VBT based on
7829  * inputs from the panel spec.
7830  *
7831  * DRRS saves power by switching to low RR based on usage scenarios.
7832  *
7833  * The implementation is based on frontbuffer tracking implementation.  When
7834  * there is a disturbance on the screen triggered by user activity or a periodic
7835  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
7836  * no movement on screen, after a timeout of 1 second, a switch to low RR is
7837  * made.
7838  *
7839  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
7840  * and intel_edp_drrs_flush() are called.
7841  *
7842  * DRRS can be further extended to support other internal panels and also
7843  * the scenario of video playback wherein RR is set based on the rate
7844  * requested by userspace.
7845  */
7846
7847 /**
7848  * intel_dp_drrs_init - Init basic DRRS work and mutex.
7849  * @connector: eDP connector
7850  * @fixed_mode: preferred mode of panel
7851  *
7852  * This function is  called only once at driver load to initialize basic
7853  * DRRS stuff.
7854  *
7855  * Returns:
7856  * Downclock mode if panel supports it, else return NULL.
7857  * DRRS support is determined by the presence of downclock mode (apart
7858  * from VBT setting).
7859  */
7860 static struct drm_display_mode *
7861 intel_dp_drrs_init(struct intel_connector *connector,
7862                    struct drm_display_mode *fixed_mode)
7863 {
7864         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7865         struct drm_display_mode *downclock_mode = NULL;
7866
7867         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
7868         mutex_init(&dev_priv->drrs.mutex);
7869
7870         if (INTEL_GEN(dev_priv) <= 6) {
7871                 drm_dbg_kms(&dev_priv->drm,
7872                             "DRRS supported for Gen7 and above\n");
7873                 return NULL;
7874         }
7875
7876         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
7877                 drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n");
7878                 return NULL;
7879         }
7880
7881         downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode);
7882         if (!downclock_mode) {
7883                 drm_dbg_kms(&dev_priv->drm,
7884                             "Downclock mode is not found. DRRS not supported\n");
7885                 return NULL;
7886         }
7887
7888         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
7889
7890         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
7891         drm_dbg_kms(&dev_priv->drm,
7892                     "seamless DRRS supported for eDP panel.\n");
7893         return downclock_mode;
7894 }
7895
7896 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
7897                                      struct intel_connector *intel_connector)
7898 {
7899         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
7900         struct drm_device *dev = &dev_priv->drm;
7901         struct drm_connector *connector = &intel_connector->base;
7902         struct drm_display_mode *fixed_mode = NULL;
7903         struct drm_display_mode *downclock_mode = NULL;
7904         bool has_dpcd;
7905         enum pipe pipe = INVALID_PIPE;
7906         intel_wakeref_t wakeref;
7907         struct edid *edid;
7908
7909         if (!intel_dp_is_edp(intel_dp))
7910                 return true;
7911
7912         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work);
7913
7914         /*
7915          * On IBX/CPT we may get here with LVDS already registered. Since the
7916          * driver uses the only internal power sequencer available for both
7917          * eDP and LVDS bail out early in this case to prevent interfering
7918          * with an already powered-on LVDS power sequencer.
7919          */
7920         if (intel_get_lvds_encoder(dev_priv)) {
7921                 drm_WARN_ON(dev,
7922                             !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
7923                 drm_info(&dev_priv->drm,
7924                          "LVDS was detected, not registering eDP\n");
7925
7926                 return false;
7927         }
7928
7929         with_pps_lock(intel_dp, wakeref) {
7930                 intel_dp_init_panel_power_timestamps(intel_dp);
7931                 intel_dp_pps_init(intel_dp);
7932                 intel_edp_panel_vdd_sanitize(intel_dp);
7933         }
7934
7935         /* Cache DPCD and EDID for edp. */
7936         has_dpcd = intel_edp_init_dpcd(intel_dp);
7937
7938         if (!has_dpcd) {
7939                 /* if this fails, presume the device is a ghost */
7940                 drm_info(&dev_priv->drm,
7941                          "failed to retrieve link info, disabling eDP\n");
7942                 goto out_vdd_off;
7943         }
7944
7945         mutex_lock(&dev->mode_config.mutex);
7946         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
7947         if (edid) {
7948                 if (drm_add_edid_modes(connector, edid)) {
7949                         drm_connector_update_edid_property(connector, edid);
7950                         intel_dp->edid_quirks = drm_dp_get_edid_quirks(edid);
7951                 } else {
7952                         kfree(edid);
7953                         edid = ERR_PTR(-EINVAL);
7954                 }
7955         } else {
7956                 edid = ERR_PTR(-ENOENT);
7957         }
7958         intel_connector->edid = edid;
7959
7960         fixed_mode = intel_panel_edid_fixed_mode(intel_connector);
7961         if (fixed_mode)
7962                 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode);
7963
7964         /* fallback to VBT if available for eDP */
7965         if (!fixed_mode)
7966                 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector);
7967         mutex_unlock(&dev->mode_config.mutex);
7968
7969         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7970                 /*
7971                  * Figure out the current pipe for the initial backlight setup.
7972                  * If the current pipe isn't valid, try the PPS pipe, and if that
7973                  * fails just assume pipe A.
7974                  */
7975                 pipe = vlv_active_pipe(intel_dp);
7976
7977                 if (pipe != PIPE_A && pipe != PIPE_B)
7978                         pipe = intel_dp->pps_pipe;
7979
7980                 if (pipe != PIPE_A && pipe != PIPE_B)
7981                         pipe = PIPE_A;
7982
7983                 drm_dbg_kms(&dev_priv->drm,
7984                             "using pipe %c for initial backlight setup\n",
7985                             pipe_name(pipe));
7986         }
7987
7988         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
7989         intel_connector->panel.backlight.power = intel_edp_backlight_power;
7990         intel_panel_setup_backlight(connector, pipe);
7991
7992         if (fixed_mode) {
7993                 drm_connector_set_panel_orientation_with_quirk(connector,
7994                                 dev_priv->vbt.orientation,
7995                                 fixed_mode->hdisplay, fixed_mode->vdisplay);
7996         }
7997
7998         return true;
7999
8000 out_vdd_off:
8001         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
8002         /*
8003          * vdd might still be enabled do to the delayed vdd off.
8004          * Make sure vdd is actually turned off here.
8005          */
8006         with_pps_lock(intel_dp, wakeref)
8007                 edp_panel_vdd_off_sync(intel_dp);
8008
8009         return false;
8010 }
8011
8012 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
8013 {
8014         struct intel_connector *intel_connector;
8015         struct drm_connector *connector;
8016
8017         intel_connector = container_of(work, typeof(*intel_connector),
8018                                        modeset_retry_work);
8019         connector = &intel_connector->base;
8020         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
8021                       connector->name);
8022
8023         /* Grab the locks before changing connector property*/
8024         mutex_lock(&connector->dev->mode_config.mutex);
8025         /* Set connector link status to BAD and send a Uevent to notify
8026          * userspace to do a modeset.
8027          */
8028         drm_connector_set_link_status_property(connector,
8029                                                DRM_MODE_LINK_STATUS_BAD);
8030         mutex_unlock(&connector->dev->mode_config.mutex);
8031         /* Send Hotplug uevent so userspace can reprobe */
8032         drm_kms_helper_hotplug_event(connector->dev);
8033 }
8034
8035 bool
8036 intel_dp_init_connector(struct intel_digital_port *dig_port,
8037                         struct intel_connector *intel_connector)
8038 {
8039         struct drm_connector *connector = &intel_connector->base;
8040         struct intel_dp *intel_dp = &dig_port->dp;
8041         struct intel_encoder *intel_encoder = &dig_port->base;
8042         struct drm_device *dev = intel_encoder->base.dev;
8043         struct drm_i915_private *dev_priv = to_i915(dev);
8044         enum port port = intel_encoder->port;
8045         enum phy phy = intel_port_to_phy(dev_priv, port);
8046         int type;
8047
8048         /* Initialize the work for modeset in case of link train failure */
8049         INIT_WORK(&intel_connector->modeset_retry_work,
8050                   intel_dp_modeset_retry_work_fn);
8051
8052         if (drm_WARN(dev, dig_port->max_lanes < 1,
8053                      "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",
8054                      dig_port->max_lanes, intel_encoder->base.base.id,
8055                      intel_encoder->base.name))
8056                 return false;
8057
8058         intel_dp_set_source_rates(intel_dp);
8059
8060         intel_dp->reset_link_params = true;
8061         intel_dp->pps_pipe = INVALID_PIPE;
8062         intel_dp->active_pipe = INVALID_PIPE;
8063
8064         /* Preserve the current hw state. */
8065         intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
8066         intel_dp->attached_connector = intel_connector;
8067
8068         if (intel_dp_is_port_edp(dev_priv, port)) {
8069                 /*
8070                  * Currently we don't support eDP on TypeC ports, although in
8071                  * theory it could work on TypeC legacy ports.
8072                  */
8073                 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy));
8074                 type = DRM_MODE_CONNECTOR_eDP;
8075         } else {
8076                 type = DRM_MODE_CONNECTOR_DisplayPort;
8077         }
8078
8079         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
8080                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
8081
8082         /*
8083          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
8084          * for DP the encoder type can be set by the caller to
8085          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
8086          */
8087         if (type == DRM_MODE_CONNECTOR_eDP)
8088                 intel_encoder->type = INTEL_OUTPUT_EDP;
8089
8090         /* eDP only on port B and/or C on vlv/chv */
8091         if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) ||
8092                               IS_CHERRYVIEW(dev_priv)) &&
8093                         intel_dp_is_edp(intel_dp) &&
8094                         port != PORT_B && port != PORT_C))
8095                 return false;
8096
8097         drm_dbg_kms(&dev_priv->drm,
8098                     "Adding %s connector on [ENCODER:%d:%s]\n",
8099                     type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
8100                     intel_encoder->base.base.id, intel_encoder->base.name);
8101
8102         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
8103         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
8104
8105         if (!HAS_GMCH(dev_priv))
8106                 connector->interlace_allowed = true;
8107         connector->doublescan_allowed = 0;
8108
8109         intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
8110
8111         intel_dp_aux_init(intel_dp);
8112
8113         intel_connector_attach_encoder(intel_connector, intel_encoder);
8114
8115         if (HAS_DDI(dev_priv))
8116                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
8117         else
8118                 intel_connector->get_hw_state = intel_connector_get_hw_state;
8119
8120         /* init MST on ports that can support it */
8121         intel_dp_mst_encoder_init(dig_port,
8122                                   intel_connector->base.base.id);
8123
8124         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
8125                 intel_dp_aux_fini(intel_dp);
8126                 intel_dp_mst_encoder_cleanup(dig_port);
8127                 goto fail;
8128         }
8129
8130         intel_dp_add_properties(intel_dp, connector);
8131
8132         if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
8133                 int ret = intel_dp_init_hdcp(dig_port, intel_connector);
8134                 if (ret)
8135                         drm_dbg_kms(&dev_priv->drm,
8136                                     "HDCP init failed, skipping.\n");
8137         }
8138
8139         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
8140          * 0xd.  Failure to do so will result in spurious interrupts being
8141          * generated on the port when a cable is not attached.
8142          */
8143         if (IS_G45(dev_priv)) {
8144                 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA);
8145                 intel_de_write(dev_priv, PEG_BAND_GAP_DATA,
8146                                (temp & ~0xf) | 0xd);
8147         }
8148
8149         return true;
8150
8151 fail:
8152         drm_connector_cleanup(connector);
8153
8154         return false;
8155 }
8156
8157 bool intel_dp_init(struct drm_i915_private *dev_priv,
8158                    i915_reg_t output_reg,
8159                    enum port port)
8160 {
8161         struct intel_digital_port *dig_port;
8162         struct intel_encoder *intel_encoder;
8163         struct drm_encoder *encoder;
8164         struct intel_connector *intel_connector;
8165
8166         dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
8167         if (!dig_port)
8168                 return false;
8169
8170         intel_connector = intel_connector_alloc();
8171         if (!intel_connector)
8172                 goto err_connector_alloc;
8173
8174         intel_encoder = &dig_port->base;
8175         encoder = &intel_encoder->base;
8176
8177         mutex_init(&dig_port->hdcp_mutex);
8178
8179         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
8180                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
8181                              "DP %c", port_name(port)))
8182                 goto err_encoder_init;
8183
8184         intel_encoder->hotplug = intel_dp_hotplug;
8185         intel_encoder->compute_config = intel_dp_compute_config;
8186         intel_encoder->get_hw_state = intel_dp_get_hw_state;
8187         intel_encoder->get_config = intel_dp_get_config;
8188         intel_encoder->sync_state = intel_dp_sync_state;
8189         intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check;
8190         intel_encoder->update_pipe = intel_panel_update_backlight;
8191         intel_encoder->suspend = intel_dp_encoder_suspend;
8192         intel_encoder->shutdown = intel_dp_encoder_shutdown;
8193         if (IS_CHERRYVIEW(dev_priv)) {
8194                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
8195                 intel_encoder->pre_enable = chv_pre_enable_dp;
8196                 intel_encoder->enable = vlv_enable_dp;
8197                 intel_encoder->disable = vlv_disable_dp;
8198                 intel_encoder->post_disable = chv_post_disable_dp;
8199                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
8200         } else if (IS_VALLEYVIEW(dev_priv)) {
8201                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
8202                 intel_encoder->pre_enable = vlv_pre_enable_dp;
8203                 intel_encoder->enable = vlv_enable_dp;
8204                 intel_encoder->disable = vlv_disable_dp;
8205                 intel_encoder->post_disable = vlv_post_disable_dp;
8206         } else {
8207                 intel_encoder->pre_enable = g4x_pre_enable_dp;
8208                 intel_encoder->enable = g4x_enable_dp;
8209                 intel_encoder->disable = g4x_disable_dp;
8210                 intel_encoder->post_disable = g4x_post_disable_dp;
8211         }
8212
8213         if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
8214             (HAS_PCH_CPT(dev_priv) && port != PORT_A))
8215                 dig_port->dp.set_link_train = cpt_set_link_train;
8216         else
8217                 dig_port->dp.set_link_train = g4x_set_link_train;
8218
8219         if (IS_CHERRYVIEW(dev_priv))
8220                 dig_port->dp.set_signal_levels = chv_set_signal_levels;
8221         else if (IS_VALLEYVIEW(dev_priv))
8222                 dig_port->dp.set_signal_levels = vlv_set_signal_levels;
8223         else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A)
8224                 dig_port->dp.set_signal_levels = ivb_cpu_edp_set_signal_levels;
8225         else if (IS_GEN(dev_priv, 6) && port == PORT_A)
8226                 dig_port->dp.set_signal_levels = snb_cpu_edp_set_signal_levels;
8227         else
8228                 dig_port->dp.set_signal_levels = g4x_set_signal_levels;
8229
8230         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv) ||
8231             (HAS_PCH_SPLIT(dev_priv) && port != PORT_A)) {
8232                 dig_port->dp.preemph_max = intel_dp_preemph_max_3;
8233                 dig_port->dp.voltage_max = intel_dp_voltage_max_3;
8234         } else {
8235                 dig_port->dp.preemph_max = intel_dp_preemph_max_2;
8236                 dig_port->dp.voltage_max = intel_dp_voltage_max_2;
8237         }
8238
8239         dig_port->dp.output_reg = output_reg;
8240         dig_port->max_lanes = 4;
8241
8242         intel_encoder->type = INTEL_OUTPUT_DP;
8243         intel_encoder->power_domain = intel_port_to_power_domain(port);
8244         if (IS_CHERRYVIEW(dev_priv)) {
8245                 if (port == PORT_D)
8246                         intel_encoder->pipe_mask = BIT(PIPE_C);
8247                 else
8248                         intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B);
8249         } else {
8250                 intel_encoder->pipe_mask = ~0;
8251         }
8252         intel_encoder->cloneable = 0;
8253         intel_encoder->port = port;
8254         intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
8255
8256         dig_port->hpd_pulse = intel_dp_hpd_pulse;
8257
8258         if (HAS_GMCH(dev_priv)) {
8259                 if (IS_GM45(dev_priv))
8260                         dig_port->connected = gm45_digital_port_connected;
8261                 else
8262                         dig_port->connected = g4x_digital_port_connected;
8263         } else {
8264                 if (port == PORT_A)
8265                         dig_port->connected = ilk_digital_port_connected;
8266                 else
8267                         dig_port->connected = ibx_digital_port_connected;
8268         }
8269
8270         if (port != PORT_A)
8271                 intel_infoframe_init(dig_port);
8272
8273         dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
8274         if (!intel_dp_init_connector(dig_port, intel_connector))
8275                 goto err_init_connector;
8276
8277         return true;
8278
8279 err_init_connector:
8280         drm_encoder_cleanup(encoder);
8281 err_encoder_init:
8282         kfree(intel_connector);
8283 err_connector_alloc:
8284         kfree(dig_port);
8285         return false;
8286 }
8287
8288 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv)
8289 {
8290         struct intel_encoder *encoder;
8291
8292         for_each_intel_encoder(&dev_priv->drm, encoder) {
8293                 struct intel_dp *intel_dp;
8294
8295                 if (encoder->type != INTEL_OUTPUT_DDI)
8296                         continue;
8297
8298                 intel_dp = enc_to_intel_dp(encoder);
8299
8300                 if (!intel_dp->can_mst)
8301                         continue;
8302
8303                 if (intel_dp->is_mst)
8304                         drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr);
8305         }
8306 }
8307
8308 void intel_dp_mst_resume(struct drm_i915_private *dev_priv)
8309 {
8310         struct intel_encoder *encoder;
8311
8312         for_each_intel_encoder(&dev_priv->drm, encoder) {
8313                 struct intel_dp *intel_dp;
8314                 int ret;
8315
8316                 if (encoder->type != INTEL_OUTPUT_DDI)
8317                         continue;
8318
8319                 intel_dp = enc_to_intel_dp(encoder);
8320
8321                 if (!intel_dp->can_mst)
8322                         continue;
8323
8324                 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr,
8325                                                      true);
8326                 if (ret) {
8327                         intel_dp->is_mst = false;
8328                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
8329                                                         false);
8330                 }
8331         }
8332 }