drivers/gpu/drm/amd/amdgpu/nv.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/firmware.h>
  24 #include <linux/slab.h>
  25 #include <linux/module.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_atombios.h"
  30 #include "amdgpu_ih.h"
  31 #include "amdgpu_uvd.h"
  32 #include "amdgpu_vce.h"
  33 #include "amdgpu_ucode.h"
  34 #include "amdgpu_psp.h"
  35 #include "amdgpu_smu.h"
  36 #include "atom.h"
  37 #include "amd_pcie.h"
  38
  39 #include "gc/gc_10_1_0_offset.h"
  40 #include "gc/gc_10_1_0_sh_mask.h"
  41 #include "smuio/smuio_11_0_0_offset.h"
  42 #include "mp/mp_11_0_offset.h"
  43
  44 #include "soc15.h"
  45 #include "soc15_common.h"
  46 #include "gmc_v10_0.h"
  47 #include "gfxhub_v2_0.h"
  48 #include "mmhub_v2_0.h"
  49 #include "nbio_v2_3.h"
  50 #include "nbio_v7_2.h"
  51 #include "hdp_v5_0.h"
  52 #include "nv.h"
  53 #include "navi10_ih.h"
  54 #include "gfx_v10_0.h"
  55 #include "sdma_v5_0.h"
  56 #include "sdma_v5_2.h"
  57 #include "vcn_v2_0.h"
  58 #include "jpeg_v2_0.h"
  59 #include "vcn_v3_0.h"
  60 #include "jpeg_v3_0.h"
  61 #include "dce_virtual.h"
  62 #include "mes_v10_1.h"
  63 #include "mxgpu_nv.h"
  64
  65 static const struct amd_ip_funcs nv_common_ip_funcs;
  66
  67 /*
  68  * Indirect registers accessor
  69  */
  70 static u32 nv_pcie_rreg(struct amdgpu_device *adev, u32 reg)
  71 {
  72         unsigned long address, data;
  73         address = adev->nbio.funcs->get_pcie_index_offset(adev);
  74         data = adev->nbio.funcs->get_pcie_data_offset(adev);
  75
  76         return amdgpu_device_indirect_rreg(adev, address, data, reg);
  77 }
  78
  79 static void nv_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
  80 {
  81         unsigned long address, data;
  82
  83         address = adev->nbio.funcs->get_pcie_index_offset(adev);
  84         data = adev->nbio.funcs->get_pcie_data_offset(adev);
  85
  86         amdgpu_device_indirect_wreg(adev, address, data, reg, v);
  87 }
  88
  89 static u64 nv_pcie_rreg64(struct amdgpu_device *adev, u32 reg)
  90 {
  91         unsigned long address, data;
  92         address = adev->nbio.funcs->get_pcie_index_offset(adev);
  93         data = adev->nbio.funcs->get_pcie_data_offset(adev);
  94
  95         return amdgpu_device_indirect_rreg64(adev, address, data, reg);
  96 }
  97
  98 static u32 nv_pcie_port_rreg(struct amdgpu_device *adev, u32 reg)
  99 {
 100         unsigned long flags, address, data;
 101         u32 r;
 102         address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
 103         data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
 104
 105         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 106         WREG32(address, reg * 4);
 107         (void)RREG32(address);
 108         r = RREG32(data);
 109         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 110         return r;
 111 }
 112
 113 static void nv_pcie_wreg64(struct amdgpu_device *adev, u32 reg, u64 v)
 114 {
 115         unsigned long address, data;
 116
 117         address = adev->nbio.funcs->get_pcie_index_offset(adev);
 118         data = adev->nbio.funcs->get_pcie_data_offset(adev);
 119
 120         amdgpu_device_indirect_wreg64(adev, address, data, reg, v);
 121 }
 122
 123 static void nv_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 124 {
 125         unsigned long flags, address, data;
 126
 127         address = adev->nbio.funcs->get_pcie_port_index_offset(adev);
 128         data = adev->nbio.funcs->get_pcie_port_data_offset(adev);
 129
 130         spin_lock_irqsave(&adev->pcie_idx_lock, flags);
 131         WREG32(address, reg * 4);
 132         (void)RREG32(address);
 133         WREG32(data, v);
 134         (void)RREG32(data);
 135         spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 136 }
 137
 138 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
 139 {
 140         unsigned long flags, address, data;
 141         u32 r;
 142
 143         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 144         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 145
 146         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 147         WREG32(address, (reg));
 148         r = RREG32(data);
 149         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 150         return r;
 151 }
 152
 153 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 154 {
 155         unsigned long flags, address, data;
 156
 157         address = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_INDEX);
 158         data = SOC15_REG_OFFSET(GC, 0, mmDIDT_IND_DATA);
 159
 160         spin_lock_irqsave(&adev->didt_idx_lock, flags);
 161         WREG32(address, (reg));
 162         WREG32(data, (v));
 163         spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 164 }
 165
 166 static u32 nv_get_config_memsize(struct amdgpu_device *adev)
 167 {
 168         return adev->nbio.funcs->get_memsize(adev);
 169 }
 170
 171 static u32 nv_get_xclk(struct amdgpu_device *adev)
 172 {
 173         return adev->clock.spll.reference_freq;
 174 }
 175
 176
 177 void nv_grbm_select(struct amdgpu_device *adev,
 178                      u32 me, u32 pipe, u32 queue, u32 vmid)
 179 {
 180         u32 grbm_gfx_cntl = 0;
 181         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
 182         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
 183         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
 184         grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
 185
 186         WREG32(SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL), grbm_gfx_cntl);
 187 }
 188
 189 static void nv_vga_set_state(struct amdgpu_device *adev, bool state)
 190 {
 191         /* todo */
 192 }
 193
 194 static bool nv_read_disabled_bios(struct amdgpu_device *adev)
 195 {
 196         /* todo */
 197         return false;
 198 }
 199
 200 static bool nv_read_bios_from_rom(struct amdgpu_device *adev,
 201                                   u8 *bios, u32 length_bytes)
 202 {
 203         u32 *dw_ptr;
 204         u32 i, length_dw;
 205
 206         if (bios == NULL)
 207                 return false;
 208         if (length_bytes == 0)
 209                 return false;
 210         /* APU vbios image is part of sbios image */
 211         if (adev->flags & AMD_IS_APU)
 212                 return false;
 213
 214         dw_ptr = (u32 *)bios;
 215         length_dw = ALIGN(length_bytes, 4) / 4;
 216
 217         /* set rom index to 0 */
 218         WREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX), 0);
 219         /* read out the rom data */
 220         for (i = 0; i < length_dw; i++)
 221                 dw_ptr[i] = RREG32(SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA));
 222
 223         return true;
 224 }
 225
 226 static struct soc15_allowed_register_entry nv_allowed_read_registers[] = {
 227         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS)},
 228         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS2)},
 229         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE0)},
 230         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE1)},
 231         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE2)},
 232         { SOC15_REG_ENTRY(GC, 0, mmGRBM_STATUS_SE3)},
 233         { SOC15_REG_ENTRY(SDMA0, 0, mmSDMA0_STATUS_REG)},
 234         { SOC15_REG_ENTRY(SDMA1, 0, mmSDMA1_STATUS_REG)},
 235         { SOC15_REG_ENTRY(GC, 0, mmCP_STAT)},
 236         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT1)},
 237         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT2)},
 238         { SOC15_REG_ENTRY(GC, 0, mmCP_STALLED_STAT3)},
 239         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_BUSY_STAT)},
 240         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STALLED_STAT1)},
 241         { SOC15_REG_ENTRY(GC, 0, mmCP_CPF_STATUS)},
 242         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_BUSY_STAT)},
 243         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STALLED_STAT1)},
 244         { SOC15_REG_ENTRY(GC, 0, mmCP_CPC_STATUS)},
 245         { SOC15_REG_ENTRY(GC, 0, mmGB_ADDR_CONFIG)},
 246 };
 247
 248 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
 249                                          u32 sh_num, u32 reg_offset)
 250 {
 251         uint32_t val;
 252
 253         mutex_lock(&adev->grbm_idx_mutex);
 254         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 255                 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff);
 256
 257         val = RREG32(reg_offset);
 258
 259         if (se_num != 0xffffffff || sh_num != 0xffffffff)
 260                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 261         mutex_unlock(&adev->grbm_idx_mutex);
 262         return val;
 263 }
 264
 265 static uint32_t nv_get_register_value(struct amdgpu_device *adev,
 266                                       bool indexed, u32 se_num,
 267                                       u32 sh_num, u32 reg_offset)
 268 {
 269         if (indexed) {
 270                 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
 271         } else {
 272                 if (reg_offset == SOC15_REG_OFFSET(GC, 0, mmGB_ADDR_CONFIG))
 273                         return adev->gfx.config.gb_addr_config;
 274                 return RREG32(reg_offset);
 275         }
 276 }
 277
 278 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
 279                             u32 sh_num, u32 reg_offset, u32 *value)
 280 {
 281         uint32_t i;
 282         struct soc15_allowed_register_entry  *en;
 283
 284         *value = 0;
 285         for (i = 0; i < ARRAY_SIZE(nv_allowed_read_registers); i++) {
 286                 en = &nv_allowed_read_registers[i];
 287                 if ((i == 7 && (adev->sdma.num_instances == 1)) || /* some asics don't have SDMA1 */
 288                     reg_offset !=
 289                     (adev->reg_offset[en->hwip][en->inst][en->seg] + en->reg_offset))
 290                         continue;
 291
 292                 *value = nv_get_register_value(adev,
 293                                                nv_allowed_read_registers[i].grbm_indexed,
 294                                                se_num, sh_num, reg_offset);
 295                 return 0;
 296         }
 297         return -EINVAL;
 298 }
 299
 300 static int nv_asic_mode1_reset(struct amdgpu_device *adev)
 301 {
 302         u32 i;
 303         int ret = 0;
 304
 305         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 306
 307         /* disable BM */
 308         pci_clear_master(adev->pdev);
 309
 310         amdgpu_device_cache_pci_state(adev->pdev);
 311
 312         if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
 313                 dev_info(adev->dev, "GPU smu mode1 reset\n");
 314                 ret = amdgpu_dpm_mode1_reset(adev);
 315         } else {
 316                 dev_info(adev->dev, "GPU psp mode1 reset\n");
 317                 ret = psp_gpu_reset(adev);
 318         }
 319
 320         if (ret)
 321                 dev_err(adev->dev, "GPU mode1 reset failed\n");
 322         amdgpu_device_load_pci_state(adev->pdev);
 323
 324         /* wait for asic to come out of reset */
 325         for (i = 0; i < adev->usec_timeout; i++) {
 326                 u32 memsize = adev->nbio.funcs->get_memsize(adev);
 327
 328                 if (memsize != 0xffffffff)
 329                         break;
 330                 udelay(1);
 331         }
 332
 333         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 334
 335         return ret;
 336 }
 337
 338 static int nv_asic_mode2_reset(struct amdgpu_device *adev)
 339 {
 340         u32 i;
 341         int ret = 0;
 342
 343         amdgpu_atombios_scratch_regs_engine_hung(adev, true);
 344
 345         /* disable BM */
 346         pci_clear_master(adev->pdev);
 347
 348         amdgpu_device_cache_pci_state(adev->pdev);
 349
 350         ret = amdgpu_dpm_mode2_reset(adev);
 351         if (ret)
 352                 dev_err(adev->dev, "GPU mode2 reset failed\n");
 353
 354         amdgpu_device_load_pci_state(adev->pdev);
 355
 356         /* wait for asic to come out of reset */
 357         for (i = 0; i < adev->usec_timeout; i++) {
 358                 u32 memsize = adev->nbio.funcs->get_memsize(adev);
 359
 360                 if (memsize != 0xffffffff)
 361                         break;
 362                 udelay(1);
 363         }
 364
 365         amdgpu_atombios_scratch_regs_engine_hung(adev, false);
 366
 367         return ret;
 368 }
 369
 370 static bool nv_asic_supports_baco(struct amdgpu_device *adev)
 371 {
 372         struct smu_context *smu = &adev->smu;
 373
 374         if (smu_baco_is_support(smu))
 375                 return true;
 376         else
 377                 return false;
 378 }
 379
 380 static enum amd_reset_method
 381 nv_asic_reset_method(struct amdgpu_device *adev)
 382 {
 383         struct smu_context *smu = &adev->smu;
 384
 385         if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
 386             amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
 387             amdgpu_reset_method == AMD_RESET_METHOD_BACO)
 388                 return amdgpu_reset_method;
 389
 390         if (amdgpu_reset_method != -1)
 391                 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
 392                                   amdgpu_reset_method);
 393
 394         switch (adev->asic_type) {
 395         case CHIP_VANGOGH:
 396                 return AMD_RESET_METHOD_MODE2;
 397         case CHIP_SIENNA_CICHLID:
 398         case CHIP_NAVY_FLOUNDER:
 399         case CHIP_DIMGREY_CAVEFISH:
 400                 return AMD_RESET_METHOD_MODE1;
 401         default:
 402                 if (smu_baco_is_support(smu))
 403                         return AMD_RESET_METHOD_BACO;
 404                 else
 405                         return AMD_RESET_METHOD_MODE1;
 406         }
 407 }
 408
 409 static int nv_asic_reset(struct amdgpu_device *adev)
 410 {
 411         int ret = 0;
 412         struct smu_context *smu = &adev->smu;
 413
 414         switch (nv_asic_reset_method(adev)) {
 415         case AMD_RESET_METHOD_BACO:
 416                 dev_info(adev->dev, "BACO reset\n");
 417
 418                 ret = smu_baco_enter(smu);
 419                 if (ret)
 420                         return ret;
 421                 ret = smu_baco_exit(smu);
 422                 if (ret)
 423                         return ret;
 424                 break;
 425         case AMD_RESET_METHOD_MODE2:
 426                 dev_info(adev->dev, "MODE2 reset\n");
 427                 ret = nv_asic_mode2_reset(adev);
 428                 break;
 429         default:
 430                 dev_info(adev->dev, "MODE1 reset\n");
 431                 ret = nv_asic_mode1_reset(adev);
 432                 break;
 433         }
 434
 435         return ret;
 436 }
 437
 438 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
 439 {
 440         /* todo */
 441         return 0;
 442 }
 443
 444 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
 445 {
 446         /* todo */
 447         return 0;
 448 }
 449
 450 static void nv_pcie_gen3_enable(struct amdgpu_device *adev)
 451 {
 452         if (pci_is_root_bus(adev->pdev->bus))
 453                 return;
 454
 455         if (amdgpu_pcie_gen2 == 0)
 456                 return;
 457
 458         if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
 459                                         CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)))
 460                 return;
 461
 462         /* todo */
 463 }
 464
 465 static void nv_program_aspm(struct amdgpu_device *adev)
 466 {
 467
 468         if (amdgpu_aspm == 0)
 469                 return;
 470
 471         /* todo */
 472 }
 473
 474 static void nv_enable_doorbell_aperture(struct amdgpu_device *adev,
 475                                         bool enable)
 476 {
 477         adev->nbio.funcs->enable_doorbell_aperture(adev, enable);
 478         adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable);
 479 }
 480
 481 static const struct amdgpu_ip_block_version nv_common_ip_block =
 482 {
 483         .type = AMD_IP_BLOCK_TYPE_COMMON,
 484         .major = 1,
 485         .minor = 0,
 486         .rev = 0,
 487         .funcs = &nv_common_ip_funcs,
 488 };
 489
 490 static int nv_reg_base_init(struct amdgpu_device *adev)
 491 {
 492         int r;
 493
 494         if (amdgpu_discovery) {
 495                 r = amdgpu_discovery_reg_base_init(adev);
 496                 if (r) {
 497                         DRM_WARN("failed to init reg base from ip discovery table, "
 498                                         "fallback to legacy init method\n");
 499                         goto legacy_init;
 500                 }
 501
 502                 return 0;
 503         }
 504
 505 legacy_init:
 506         switch (adev->asic_type) {
 507         case CHIP_NAVI10:
 508                 navi10_reg_base_init(adev);
 509                 break;
 510         case CHIP_NAVI14:
 511                 navi14_reg_base_init(adev);
 512                 break;
 513         case CHIP_NAVI12:
 514                 navi12_reg_base_init(adev);
 515                 break;
 516         case CHIP_SIENNA_CICHLID:
 517         case CHIP_NAVY_FLOUNDER:
 518                 sienna_cichlid_reg_base_init(adev);
 519                 break;
 520         case CHIP_VANGOGH:
 521                 vangogh_reg_base_init(adev);
 522                 break;
 523         case CHIP_DIMGREY_CAVEFISH:
 524                 dimgrey_cavefish_reg_base_init(adev);
 525                 break;
 526         default:
 527                 return -EINVAL;
 528         }
 529
 530         return 0;
 531 }
 532
 533 void nv_set_virt_ops(struct amdgpu_device *adev)
 534 {
 535         adev->virt.ops = &xgpu_nv_virt_ops;
 536 }
 537
 538 static bool nv_is_headless_sku(struct pci_dev *pdev)
 539 {
 540         if ((pdev->device == 0x731E &&
 541             (pdev->revision == 0xC6 || pdev->revision == 0xC7)) ||
 542             (pdev->device == 0x7340 && pdev->revision == 0xC9))
 543                 return true;
 544         return false;
 545 }
 546
 547 int nv_set_ip_blocks(struct amdgpu_device *adev)
 548 {
 549         int r;
 550
 551         if (adev->flags & AMD_IS_APU) {
 552                 adev->nbio.funcs = &nbio_v7_2_funcs;
 553                 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg;
 554         } else {
 555                 adev->nbio.funcs = &nbio_v2_3_funcs;
 556                 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg;
 557         }
 558         adev->hdp.funcs = &hdp_v5_0_funcs;
 559
 560         if (adev->asic_type == CHIP_SIENNA_CICHLID)
 561                 adev->gmc.xgmi.supported = true;
 562
 563         /* Set IP register base before any HW register access */
 564         r = nv_reg_base_init(adev);
 565         if (r)
 566                 return r;
 567
 568         switch (adev->asic_type) {
 569         case CHIP_NAVI10:
 570         case CHIP_NAVI14:
 571                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 572                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 573                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 574                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 575                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 576                     !amdgpu_sriov_vf(adev))
 577                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 578                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 579                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 580 #if defined(CONFIG_DRM_AMD_DC)
 581                 else if (amdgpu_device_has_dc_support(adev))
 582                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 583 #endif
 584                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 585                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 586                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 587                     !amdgpu_sriov_vf(adev))
 588                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 589                 if (!nv_is_headless_sku(adev->pdev))
 590                         amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 591                 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 592                 if (adev->enable_mes)
 593                         amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
 594                 break;
 595         case CHIP_NAVI12:
 596                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 597                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 598                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 599                 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 600                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
 601                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 602                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 603                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 604 #if defined(CONFIG_DRM_AMD_DC)
 605                 else if (amdgpu_device_has_dc_support(adev))
 606                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 607 #endif
 608                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 609                 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
 610                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 611                     !amdgpu_sriov_vf(adev))
 612                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 613                 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
 614                 if (!amdgpu_sriov_vf(adev))
 615                         amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
 616                 break;
 617         case CHIP_SIENNA_CICHLID:
 618                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 619                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 620                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 621                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 622                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 623                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 624                     is_support_sw_smu(adev))
 625                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 626                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 627                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 628 #if defined(CONFIG_DRM_AMD_DC)
 629                 else if (amdgpu_device_has_dc_support(adev))
 630                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 631 #endif
 632                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 633                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 634                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 635                 if (!amdgpu_sriov_vf(adev))
 636                         amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 637
 638                 if (adev->enable_mes)
 639                         amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
 640                 break;
 641         case CHIP_NAVY_FLOUNDER:
 642                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 643                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 644                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 645                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 646                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 647                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 648                     is_support_sw_smu(adev))
 649                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 650                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 651                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 652 #if defined(CONFIG_DRM_AMD_DC)
 653                 else if (amdgpu_device_has_dc_support(adev))
 654                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 655 #endif
 656                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 657                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 658                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 659                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 660                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
 661                     is_support_sw_smu(adev))
 662                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 663                 break;
 664         case CHIP_VANGOGH:
 665                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 666                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 667                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 668                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 669                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 670                 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 671                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 672                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 673 #if defined(CONFIG_DRM_AMD_DC)
 674                 else if (amdgpu_device_has_dc_support(adev))
 675                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 676 #endif
 677                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 678                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 679                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 680                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 681                 break;
 682         case CHIP_DIMGREY_CAVEFISH:
 683                 amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
 684                 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
 685                 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
 686                 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
 687                         amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
 688                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
 689                     is_support_sw_smu(adev))
 690                         amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
 691                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
 692                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
 693 #if defined(CONFIG_DRM_AMD_DC)
 694                 else if (amdgpu_device_has_dc_support(adev))
 695                         amdgpu_device_ip_block_add(adev, &dm_ip_block);
 696 #endif
 697                 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
 698                 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block);
 699                 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block);
 700                 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block);
 701                 break;
 702         default:
 703                 return -EINVAL;
 704         }
 705
 706         return 0;
 707 }
 708
 709 static uint32_t nv_get_rev_id(struct amdgpu_device *adev)
 710 {
 711         return adev->nbio.funcs->get_rev_id(adev);
 712 }
 713
 714 static bool nv_need_full_reset(struct amdgpu_device *adev)
 715 {
 716         return true;
 717 }
 718
 719 static bool nv_need_reset_on_init(struct amdgpu_device *adev)
 720 {
 721         u32 sol_reg;
 722
 723         if (adev->flags & AMD_IS_APU)
 724                 return false;
 725
 726         /* Check sOS sign of life register to confirm sys driver and sOS
 727          * are already been loaded.
 728          */
 729         sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 730         if (sol_reg)
 731                 return true;
 732
 733         return false;
 734 }
 735
 736 static uint64_t nv_get_pcie_replay_count(struct amdgpu_device *adev)
 737 {
 738
 739         /* TODO
 740          * dummy implement for pcie_replay_count sysfs interface
 741          * */
 742
 743         return 0;
 744 }
 745
 746 static void nv_init_doorbell_index(struct amdgpu_device *adev)
 747 {
 748         adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
 749         adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
 750         adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
 751         adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
 752         adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
 753         adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
 754         adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
 755         adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
 756         adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
 757         adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
 758         adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
 759         adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
 760         adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
 761         adev->doorbell_index.mes_ring = AMDGPU_NAVI10_DOORBELL_MES_RING;
 762         adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
 763         adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
 764         adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
 765         adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
 766         adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
 767         adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
 768         adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
 769         adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
 770         adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
 771         adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
 772         adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
 773
 774         adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
 775         adev->doorbell_index.sdma_doorbell_range = 20;
 776 }
 777
 778 static void nv_pre_asic_init(struct amdgpu_device *adev)
 779 {
 780 }
 781
 782 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
 783                                        bool enter)
 784 {
 785         if (enter)
 786                 amdgpu_gfx_rlc_enter_safe_mode(adev);
 787         else
 788                 amdgpu_gfx_rlc_exit_safe_mode(adev);
 789
 790         if (adev->gfx.funcs->update_perfmon_mgcg)
 791                 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
 792
 793         /*
 794          * The ASPM function is not fully enabled and verified on
 795          * Navi yet. Temporarily skip this until ASPM enabled.
 796          */
 797 #if 0
 798         if (adev->nbio.funcs->enable_aspm)
 799                 adev->nbio.funcs->enable_aspm(adev, !enter);
 800 #endif
 801
 802         return 0;
 803 }
 804
 805 static const struct amdgpu_asic_funcs nv_asic_funcs =
 806 {
 807         .read_disabled_bios = &nv_read_disabled_bios,
 808         .read_bios_from_rom = &nv_read_bios_from_rom,
 809         .read_register = &nv_read_register,
 810         .reset = &nv_asic_reset,
 811         .reset_method = &nv_asic_reset_method,
 812         .set_vga_state = &nv_vga_set_state,
 813         .get_xclk = &nv_get_xclk,
 814         .set_uvd_clocks = &nv_set_uvd_clocks,
 815         .set_vce_clocks = &nv_set_vce_clocks,
 816         .get_config_memsize = &nv_get_config_memsize,
 817         .init_doorbell_index = &nv_init_doorbell_index,
 818         .need_full_reset = &nv_need_full_reset,
 819         .need_reset_on_init = &nv_need_reset_on_init,
 820         .get_pcie_replay_count = &nv_get_pcie_replay_count,
 821         .supports_baco = &nv_asic_supports_baco,
 822         .pre_asic_init = &nv_pre_asic_init,
 823         .update_umd_stable_pstate = &nv_update_umd_stable_pstate,
 824 };
 825
 826 static int nv_common_early_init(void *handle)
 827 {
 828 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
 829         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 830
 831         adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
 832         adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
 833         adev->smc_rreg = NULL;
 834         adev->smc_wreg = NULL;
 835         adev->pcie_rreg = &nv_pcie_rreg;
 836         adev->pcie_wreg = &nv_pcie_wreg;
 837         adev->pcie_rreg64 = &nv_pcie_rreg64;
 838         adev->pcie_wreg64 = &nv_pcie_wreg64;
 839         adev->pciep_rreg = &nv_pcie_port_rreg;
 840         adev->pciep_wreg = &nv_pcie_port_wreg;
 841
 842         /* TODO: will add them during VCN v2 implementation */
 843         adev->uvd_ctx_rreg = NULL;
 844         adev->uvd_ctx_wreg = NULL;
 845
 846         adev->didt_rreg = &nv_didt_rreg;
 847         adev->didt_wreg = &nv_didt_wreg;
 848
 849         adev->asic_funcs = &nv_asic_funcs;
 850
 851         adev->rev_id = nv_get_rev_id(adev);
 852         adev->external_rev_id = 0xff;
 853         switch (adev->asic_type) {
 854         case CHIP_NAVI10:
 855                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 856                         AMD_CG_SUPPORT_GFX_CGCG |
 857                         AMD_CG_SUPPORT_IH_CG |
 858                         AMD_CG_SUPPORT_HDP_MGCG |
 859                         AMD_CG_SUPPORT_HDP_LS |
 860                         AMD_CG_SUPPORT_SDMA_MGCG |
 861                         AMD_CG_SUPPORT_SDMA_LS |
 862                         AMD_CG_SUPPORT_MC_MGCG |
 863                         AMD_CG_SUPPORT_MC_LS |
 864                         AMD_CG_SUPPORT_ATHUB_MGCG |
 865                         AMD_CG_SUPPORT_ATHUB_LS |
 866                         AMD_CG_SUPPORT_VCN_MGCG |
 867                         AMD_CG_SUPPORT_JPEG_MGCG |
 868                         AMD_CG_SUPPORT_BIF_MGCG |
 869                         AMD_CG_SUPPORT_BIF_LS;
 870                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 871                         AMD_PG_SUPPORT_VCN_DPG |
 872                         AMD_PG_SUPPORT_JPEG |
 873                         AMD_PG_SUPPORT_ATHUB;
 874                 adev->external_rev_id = adev->rev_id + 0x1;
 875                 break;
 876         case CHIP_NAVI14:
 877                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 878                         AMD_CG_SUPPORT_GFX_CGCG |
 879                         AMD_CG_SUPPORT_IH_CG |
 880                         AMD_CG_SUPPORT_HDP_MGCG |
 881                         AMD_CG_SUPPORT_HDP_LS |
 882                         AMD_CG_SUPPORT_SDMA_MGCG |
 883                         AMD_CG_SUPPORT_SDMA_LS |
 884                         AMD_CG_SUPPORT_MC_MGCG |
 885                         AMD_CG_SUPPORT_MC_LS |
 886                         AMD_CG_SUPPORT_ATHUB_MGCG |
 887                         AMD_CG_SUPPORT_ATHUB_LS |
 888                         AMD_CG_SUPPORT_VCN_MGCG |
 889                         AMD_CG_SUPPORT_JPEG_MGCG |
 890                         AMD_CG_SUPPORT_BIF_MGCG |
 891                         AMD_CG_SUPPORT_BIF_LS;
 892                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 893                         AMD_PG_SUPPORT_JPEG |
 894                         AMD_PG_SUPPORT_VCN_DPG;
 895                 adev->external_rev_id = adev->rev_id + 20;
 896                 break;
 897         case CHIP_NAVI12:
 898                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 899                         AMD_CG_SUPPORT_GFX_MGLS |
 900                         AMD_CG_SUPPORT_GFX_CGCG |
 901                         AMD_CG_SUPPORT_GFX_CP_LS |
 902                         AMD_CG_SUPPORT_GFX_RLC_LS |
 903                         AMD_CG_SUPPORT_IH_CG |
 904                         AMD_CG_SUPPORT_HDP_MGCG |
 905                         AMD_CG_SUPPORT_HDP_LS |
 906                         AMD_CG_SUPPORT_SDMA_MGCG |
 907                         AMD_CG_SUPPORT_SDMA_LS |
 908                         AMD_CG_SUPPORT_MC_MGCG |
 909                         AMD_CG_SUPPORT_MC_LS |
 910                         AMD_CG_SUPPORT_ATHUB_MGCG |
 911                         AMD_CG_SUPPORT_ATHUB_LS |
 912                         AMD_CG_SUPPORT_VCN_MGCG |
 913                         AMD_CG_SUPPORT_JPEG_MGCG;
 914                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 915                         AMD_PG_SUPPORT_VCN_DPG |
 916                         AMD_PG_SUPPORT_JPEG |
 917                         AMD_PG_SUPPORT_ATHUB;
 918                 /* guest vm gets 0xffffffff when reading RCC_DEV0_EPF0_STRAP0,
 919                  * as a consequence, the rev_id and external_rev_id are wrong.
 920                  * workaround it by hardcoding rev_id to 0 (default value).
 921                  */
 922                 if (amdgpu_sriov_vf(adev))
 923                         adev->rev_id = 0;
 924                 adev->external_rev_id = adev->rev_id + 0xa;
 925                 break;
 926         case CHIP_SIENNA_CICHLID:
 927                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 928                         AMD_CG_SUPPORT_GFX_CGCG |
 929                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 930                         AMD_CG_SUPPORT_MC_MGCG |
 931                         AMD_CG_SUPPORT_VCN_MGCG |
 932                         AMD_CG_SUPPORT_JPEG_MGCG |
 933                         AMD_CG_SUPPORT_HDP_MGCG |
 934                         AMD_CG_SUPPORT_HDP_LS |
 935                         AMD_CG_SUPPORT_IH_CG |
 936                         AMD_CG_SUPPORT_MC_LS;
 937                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 938                         AMD_PG_SUPPORT_VCN_DPG |
 939                         AMD_PG_SUPPORT_JPEG |
 940                         AMD_PG_SUPPORT_ATHUB |
 941                         AMD_PG_SUPPORT_MMHUB;
 942                 if (amdgpu_sriov_vf(adev)) {
 943                         /* hypervisor control CG and PG enablement */
 944                         adev->cg_flags = 0;
 945                         adev->pg_flags = 0;
 946                 }
 947                 adev->external_rev_id = adev->rev_id + 0x28;
 948                 break;
 949         case CHIP_NAVY_FLOUNDER:
 950                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 951                         AMD_CG_SUPPORT_GFX_CGCG |
 952                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 953                         AMD_CG_SUPPORT_VCN_MGCG |
 954                         AMD_CG_SUPPORT_JPEG_MGCG |
 955                         AMD_CG_SUPPORT_MC_MGCG |
 956                         AMD_CG_SUPPORT_MC_LS |
 957                         AMD_CG_SUPPORT_HDP_MGCG |
 958                         AMD_CG_SUPPORT_HDP_LS |
 959                         AMD_CG_SUPPORT_IH_CG;
 960                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
 961                         AMD_PG_SUPPORT_VCN_DPG |
 962                         AMD_PG_SUPPORT_JPEG |
 963                         AMD_PG_SUPPORT_ATHUB |
 964                         AMD_PG_SUPPORT_MMHUB;
 965                 adev->external_rev_id = adev->rev_id + 0x32;
 966                 break;
 967
 968         case CHIP_VANGOGH:
 969                 adev->apu_flags |= AMD_APU_IS_VANGOGH;
 970                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 971                         AMD_CG_SUPPORT_GFX_MGLS |
 972                         AMD_CG_SUPPORT_GFX_CP_LS |
 973                         AMD_CG_SUPPORT_GFX_RLC_LS |
 974                         AMD_CG_SUPPORT_GFX_CGCG |
 975                         AMD_CG_SUPPORT_GFX_CGLS |
 976                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 977                         AMD_CG_SUPPORT_GFX_3D_CGLS |
 978                         AMD_CG_SUPPORT_MC_MGCG |
 979                         AMD_CG_SUPPORT_MC_LS |
 980                         AMD_CG_SUPPORT_GFX_FGCG |
 981                         AMD_CG_SUPPORT_VCN_MGCG |
 982                         AMD_CG_SUPPORT_JPEG_MGCG;
 983                 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
 984                         AMD_PG_SUPPORT_VCN |
 985                         AMD_PG_SUPPORT_VCN_DPG |
 986                         AMD_PG_SUPPORT_JPEG;
 987                 if (adev->apu_flags & AMD_APU_IS_VANGOGH)
 988                         adev->external_rev_id = adev->rev_id + 0x01;
 989                 break;
 990         case CHIP_DIMGREY_CAVEFISH:
 991                 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
 992                         AMD_CG_SUPPORT_GFX_CGCG |
 993                         AMD_CG_SUPPORT_GFX_3D_CGCG |
 994                         AMD_CG_SUPPORT_VCN_MGCG |
 995                         AMD_CG_SUPPORT_JPEG_MGCG |
 996                         AMD_CG_SUPPORT_MC_MGCG |
 997                         AMD_CG_SUPPORT_MC_LS |
 998                         AMD_CG_SUPPORT_HDP_MGCG |
 999                         AMD_CG_SUPPORT_HDP_LS |
1000                         AMD_CG_SUPPORT_IH_CG;
1001                 adev->pg_flags = AMD_PG_SUPPORT_VCN |
1002                         AMD_PG_SUPPORT_VCN_DPG |
1003                         AMD_PG_SUPPORT_JPEG |
1004                         AMD_PG_SUPPORT_ATHUB |
1005                         AMD_PG_SUPPORT_MMHUB;
1006                 adev->external_rev_id = adev->rev_id + 0x3c;
1007                 break;
1008         default:
1009                 /* FIXME: not supported yet */
1010                 return -EINVAL;
1011         }
1012
1013         if (amdgpu_sriov_vf(adev)) {
1014                 amdgpu_virt_init_setting(adev);
1015                 xgpu_nv_mailbox_set_irq_funcs(adev);
1016         }
1017
1018         return 0;
1019 }
1020
1021 static int nv_common_late_init(void *handle)
1022 {
1023         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1024
1025         if (amdgpu_sriov_vf(adev))
1026                 xgpu_nv_mailbox_get_irq(adev);
1027
1028         return 0;
1029 }
1030
1031 static int nv_common_sw_init(void *handle)
1032 {
1033         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1034
1035         if (amdgpu_sriov_vf(adev))
1036                 xgpu_nv_mailbox_add_irq_id(adev);
1037
1038         return 0;
1039 }
1040
1041 static int nv_common_sw_fini(void *handle)
1042 {
1043         return 0;
1044 }
1045
1046 static int nv_common_hw_init(void *handle)
1047 {
1048         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1049
1050         /* enable pcie gen2/3 link */
1051         nv_pcie_gen3_enable(adev);
1052         /* enable aspm */
1053         nv_program_aspm(adev);
1054         /* setup nbio registers */
1055         adev->nbio.funcs->init_registers(adev);
1056         /* remap HDP registers to a hole in mmio space,
1057          * for the purpose of expose those registers
1058          * to process space
1059          */
1060         if (adev->nbio.funcs->remap_hdp_registers)
1061                 adev->nbio.funcs->remap_hdp_registers(adev);
1062         /* enable the doorbell aperture */
1063         nv_enable_doorbell_aperture(adev, true);
1064
1065         return 0;
1066 }
1067
1068 static int nv_common_hw_fini(void *handle)
1069 {
1070         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1071
1072         /* disable the doorbell aperture */
1073         nv_enable_doorbell_aperture(adev, false);
1074
1075         return 0;
1076 }
1077
1078 static int nv_common_suspend(void *handle)
1079 {
1080         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1081
1082         return nv_common_hw_fini(adev);
1083 }
1084
1085 static int nv_common_resume(void *handle)
1086 {
1087         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1088
1089         return nv_common_hw_init(adev);
1090 }
1091
1092 static bool nv_common_is_idle(void *handle)
1093 {
1094         return true;
1095 }
1096
1097 static int nv_common_wait_for_idle(void *handle)
1098 {
1099         return 0;
1100 }
1101
1102 static int nv_common_soft_reset(void *handle)
1103 {
1104         return 0;
1105 }
1106
1107 static int nv_common_set_clockgating_state(void *handle,
1108                                            enum amd_clockgating_state state)
1109 {
1110         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1111
1112         if (amdgpu_sriov_vf(adev))
1113                 return 0;
1114
1115         switch (adev->asic_type) {
1116         case CHIP_NAVI10:
1117         case CHIP_NAVI14:
1118         case CHIP_NAVI12:
1119         case CHIP_SIENNA_CICHLID:
1120         case CHIP_NAVY_FLOUNDER:
1121         case CHIP_DIMGREY_CAVEFISH:
1122                 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1123                                 state == AMD_CG_STATE_GATE);
1124                 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1125                                 state == AMD_CG_STATE_GATE);
1126                 adev->hdp.funcs->update_clock_gating(adev,
1127                                 state == AMD_CG_STATE_GATE);
1128                 break;
1129         default:
1130                 break;
1131         }
1132         return 0;
1133 }
1134
1135 static int nv_common_set_powergating_state(void *handle,
1136                                            enum amd_powergating_state state)
1137 {
1138         /* TODO */
1139         return 0;
1140 }
1141
1142 static void nv_common_get_clockgating_state(void *handle, u32 *flags)
1143 {
1144         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1145
1146         if (amdgpu_sriov_vf(adev))
1147                 *flags = 0;
1148
1149         adev->nbio.funcs->get_clockgating_state(adev, flags);
1150
1151         adev->hdp.funcs->get_clock_gating_state(adev, flags);
1152
1153         return;
1154 }
1155
1156 static const struct amd_ip_funcs nv_common_ip_funcs = {
1157         .name = "nv_common",
1158         .early_init = nv_common_early_init,
1159         .late_init = nv_common_late_init,
1160         .sw_init = nv_common_sw_init,
1161         .sw_fini = nv_common_sw_fini,
1162         .hw_init = nv_common_hw_init,
1163         .hw_fini = nv_common_hw_fini,
1164         .suspend = nv_common_suspend,
1165         .resume = nv_common_resume,
1166         .is_idle = nv_common_is_idle,
1167         .wait_for_idle = nv_common_wait_for_idle,
1168         .soft_reset = nv_common_soft_reset,
1169         .set_clockgating_state = nv_common_set_clockgating_state,
1170         .set_powergating_state = nv_common_set_powergating_state,
1171         .get_clockgating_state = nv_common_get_clockgating_state,
1172 };