drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <linux/dma-mapping.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_psp.h"
  31 #include "amdgpu_ucode.h"
  32 #include "soc15_common.h"
  33 #include "psp_v3_1.h"
  34 #include "psp_v10_0.h"
  35 #include "psp_v11_0.h"
  36 #include "psp_v12_0.h"
  37 #include "psp_v13_0.h"
  38
  39 #include "amdgpu_ras.h"
  40 #include "amdgpu_securedisplay.h"
  41
  42 static int psp_sysfs_init(struct amdgpu_device *adev);
  43 static void psp_sysfs_fini(struct amdgpu_device *adev);
  44
  45 static int psp_load_smu_fw(struct psp_context *psp);
  46
  47 /*
  48  * Due to DF Cstate management centralized to PMFW, the firmware
  49  * loading sequence will be updated as below:
  50  *   - Load KDB
  51  *   - Load SYS_DRV
  52  *   - Load tOS
  53  *   - Load PMFW
  54  *   - Setup TMR
  55  *   - Load other non-psp fw
  56  *   - Load ASD
  57  *   - Load XGMI/RAS/HDCP/DTM TA if any
  58  *
  59  * This new sequence is required for
  60  *   - Arcturus and onwards
  61  *   - Navi12 and onwards
  62  */
  63 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
  64 {
  65         struct amdgpu_device *adev = psp->adev;
  66
  67         psp->pmfw_centralized_cstate_management = false;
  68
  69         if (amdgpu_sriov_vf(adev))
  70                 return;
  71
  72         if (adev->flags & AMD_IS_APU)
  73                 return;
  74
  75         if ((adev->asic_type >= CHIP_ARCTURUS) ||
  76             (adev->asic_type >= CHIP_NAVI12))
  77                 psp->pmfw_centralized_cstate_management = true;
  78 }
  79
  80 static int psp_early_init(void *handle)
  81 {
  82         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  83         struct psp_context *psp = &adev->psp;
  84
  85         switch (adev->asic_type) {
  86         case CHIP_VEGA10:
  87         case CHIP_VEGA12:
  88                 psp_v3_1_set_psp_funcs(psp);
  89                 psp->autoload_supported = false;
  90                 break;
  91         case CHIP_RAVEN:
  92                 psp_v10_0_set_psp_funcs(psp);
  93                 psp->autoload_supported = false;
  94                 break;
  95         case CHIP_VEGA20:
  96         case CHIP_ARCTURUS:
  97                 psp_v11_0_set_psp_funcs(psp);
  98                 psp->autoload_supported = false;
  99                 break;
 100         case CHIP_NAVI10:
 101         case CHIP_NAVI14:
 102         case CHIP_NAVI12:
 103         case CHIP_SIENNA_CICHLID:
 104         case CHIP_NAVY_FLOUNDER:
 105         case CHIP_VANGOGH:
 106         case CHIP_DIMGREY_CAVEFISH:
 107                 psp_v11_0_set_psp_funcs(psp);
 108                 psp->autoload_supported = true;
 109                 break;
 110         case CHIP_RENOIR:
 111                 psp_v12_0_set_psp_funcs(psp);
 112                 break;
 113         case CHIP_ALDEBARAN:
 114                 psp_v13_0_set_psp_funcs(psp);
 115                 break;
 116         default:
 117                 return -EINVAL;
 118         }
 119
 120         psp->adev = adev;
 121
 122         psp_check_pmfw_centralized_cstate_management(psp);
 123
 124         return 0;
 125 }
 126
 127 static void psp_memory_training_fini(struct psp_context *psp)
 128 {
 129         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 130
 131         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
 132         kfree(ctx->sys_cache);
 133         ctx->sys_cache = NULL;
 134 }
 135
 136 static int psp_memory_training_init(struct psp_context *psp)
 137 {
 138         int ret;
 139         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 140
 141         if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
 142                 DRM_DEBUG("memory training is not supported!\n");
 143                 return 0;
 144         }
 145
 146         ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
 147         if (ctx->sys_cache == NULL) {
 148                 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
 149                 ret = -ENOMEM;
 150                 goto Err_out;
 151         }
 152
 153         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
 154                   ctx->train_data_size,
 155                   ctx->p2c_train_data_offset,
 156                   ctx->c2p_train_data_offset);
 157         ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
 158         return 0;
 159
 160 Err_out:
 161         psp_memory_training_fini(psp);
 162         return ret;
 163 }
 164
 165 static int psp_sw_init(void *handle)
 166 {
 167         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 168         struct psp_context *psp = &adev->psp;
 169         int ret;
 170
 171         if (!amdgpu_sriov_vf(adev)) {
 172                 ret = psp_init_microcode(psp);
 173                 if (ret) {
 174                         DRM_ERROR("Failed to load psp firmware!\n");
 175                         return ret;
 176                 }
 177         }
 178
 179         ret = psp_memory_training_init(psp);
 180         if (ret) {
 181                 DRM_ERROR("Failed to initialize memory training!\n");
 182                 return ret;
 183         }
 184         ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
 185         if (ret) {
 186                 DRM_ERROR("Failed to process memory training!\n");
 187                 return ret;
 188         }
 189
 190         if (adev->asic_type == CHIP_NAVI10 || adev->asic_type == CHIP_SIENNA_CICHLID) {
 191                 ret= psp_sysfs_init(adev);
 192                 if (ret) {
 193                         return ret;
 194                 }
 195         }
 196
 197         return 0;
 198 }
 199
 200 static int psp_sw_fini(void *handle)
 201 {
 202         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 203
 204         psp_memory_training_fini(&adev->psp);
 205         if (adev->psp.sos_fw) {
 206                 release_firmware(adev->psp.sos_fw);
 207                 adev->psp.sos_fw = NULL;
 208         }
 209         if (adev->psp.asd_fw) {
 210                 release_firmware(adev->psp.asd_fw);
 211                 adev->psp.asd_fw = NULL;
 212         }
 213         if (adev->psp.ta_fw) {
 214                 release_firmware(adev->psp.ta_fw);
 215                 adev->psp.ta_fw = NULL;
 216         }
 217
 218         if (adev->asic_type == CHIP_NAVI10 ||
 219             adev->asic_type == CHIP_SIENNA_CICHLID)
 220                 psp_sysfs_fini(adev);
 221
 222         return 0;
 223 }
 224
 225 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 226                  uint32_t reg_val, uint32_t mask, bool check_changed)
 227 {
 228         uint32_t val;
 229         int i;
 230         struct amdgpu_device *adev = psp->adev;
 231
 232         if (psp->adev->in_pci_err_recovery)
 233                 return 0;
 234
 235         for (i = 0; i < adev->usec_timeout; i++) {
 236                 val = RREG32(reg_index);
 237                 if (check_changed) {
 238                         if (val != reg_val)
 239                                 return 0;
 240                 } else {
 241                         if ((val & mask) == reg_val)
 242                                 return 0;
 243                 }
 244                 udelay(1);
 245         }
 246
 247         return -ETIME;
 248 }
 249
 250 static int
 251 psp_cmd_submit_buf(struct psp_context *psp,
 252                    struct amdgpu_firmware_info *ucode,
 253                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 254 {
 255         int ret;
 256         int index;
 257         int timeout = 20000;
 258         bool ras_intr = false;
 259         bool skip_unsupport = false;
 260
 261         if (psp->adev->in_pci_err_recovery)
 262                 return 0;
 263
 264         mutex_lock(&psp->mutex);
 265
 266         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 267
 268         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 269
 270         index = atomic_inc_return(&psp->fence_value);
 271         ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
 272         if (ret) {
 273                 atomic_dec(&psp->fence_value);
 274                 mutex_unlock(&psp->mutex);
 275                 return ret;
 276         }
 277
 278         amdgpu_asic_invalidate_hdp(psp->adev, NULL);
 279         while (*((unsigned int *)psp->fence_buf) != index) {
 280                 if (--timeout == 0)
 281                         break;
 282                 /*
 283                  * Shouldn't wait for timeout when err_event_athub occurs,
 284                  * because gpu reset thread triggered and lock resource should
 285                  * be released for psp resume sequence.
 286                  */
 287                 ras_intr = amdgpu_ras_intr_triggered();
 288                 if (ras_intr)
 289                         break;
 290                 usleep_range(10, 100);
 291                 amdgpu_asic_invalidate_hdp(psp->adev, NULL);
 292         }
 293
 294         /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
 295         skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
 296                 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
 297
 298         memcpy((void*)&cmd->resp, (void*)&psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
 299
 300         /* In some cases, psp response status is not 0 even there is no
 301          * problem while the command is submitted. Some version of PSP FW
 302          * doesn't write 0 to that field.
 303          * So here we would like to only print a warning instead of an error
 304          * during psp initialization to avoid breaking hw_init and it doesn't
 305          * return -EINVAL.
 306          */
 307         if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
 308                 if (ucode)
 309                         DRM_WARN("failed to load ucode id (%d) ",
 310                                   ucode->ucode_id);
 311                 DRM_WARN("psp command (0x%X) failed and response status is (0x%X)\n",
 312                          psp->cmd_buf_mem->cmd_id,
 313                          psp->cmd_buf_mem->resp.status);
 314                 if (!timeout) {
 315                         mutex_unlock(&psp->mutex);
 316                         return -EINVAL;
 317                 }
 318         }
 319
 320         if (ucode) {
 321                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 322                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 323         }
 324         mutex_unlock(&psp->mutex);
 325
 326         return ret;
 327 }
 328
 329 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 330                                  struct psp_gfx_cmd_resp *cmd,
 331                                  uint64_t tmr_mc, uint32_t size)
 332 {
 333         if (amdgpu_sriov_vf(psp->adev))
 334                 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 335         else
 336                 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 337         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 338         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 339         cmd->cmd.cmd_setup_tmr.buf_size = size;
 340 }
 341
 342 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 343                                       uint64_t pri_buf_mc, uint32_t size)
 344 {
 345         cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
 346         cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
 347         cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
 348         cmd->cmd.cmd_load_toc.toc_size = size;
 349 }
 350
 351 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
 352 static int psp_load_toc(struct psp_context *psp,
 353                         uint32_t *tmr_size)
 354 {
 355         int ret;
 356         struct psp_gfx_cmd_resp *cmd;
 357
 358         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 359         if (!cmd)
 360                 return -ENOMEM;
 361         /* Copy toc to psp firmware private buffer */
 362         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 363         memcpy(psp->fw_pri_buf, psp->toc_start_addr, psp->toc_bin_size);
 364
 365         psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc_bin_size);
 366
 367         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 368                                  psp->fence_buf_mc_addr);
 369         if (!ret)
 370                 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
 371         kfree(cmd);
 372         return ret;
 373 }
 374
 375 /* Set up Trusted Memory Region */
 376 static int psp_tmr_init(struct psp_context *psp)
 377 {
 378         int ret;
 379         int tmr_size;
 380         void *tmr_buf;
 381         void **pptr;
 382
 383         /*
 384          * According to HW engineer, they prefer the TMR address be "naturally
 385          * aligned" , e.g. the start address be an integer divide of TMR size.
 386          *
 387          * Note: this memory need be reserved till the driver
 388          * uninitializes.
 389          */
 390         tmr_size = PSP_TMR_SIZE(psp->adev);
 391
 392         /* For ASICs support RLC autoload, psp will parse the toc
 393          * and calculate the total size of TMR needed */
 394         if (!amdgpu_sriov_vf(psp->adev) &&
 395             psp->toc_start_addr &&
 396             psp->toc_bin_size &&
 397             psp->fw_pri_buf) {
 398                 ret = psp_load_toc(psp, &tmr_size);
 399                 if (ret) {
 400                         DRM_ERROR("Failed to load toc\n");
 401                         return ret;
 402                 }
 403         }
 404
 405         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 406         ret = amdgpu_bo_create_kernel(psp->adev, tmr_size, PSP_TMR_SIZE(psp->adev),
 407                                       AMDGPU_GEM_DOMAIN_VRAM,
 408                                       &psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 409
 410         /* workaround the tmr_mc_addr:
 411          * PSP requires an address in FB aperture. Right now driver produce
 412          * tmr_mc_addr in the GART aperture. Convert it back to FB aperture
 413          * for PSP. Will revert it after we get a fix from PSP FW.
 414          */
 415         if (psp->adev->asic_type == CHIP_ALDEBARAN) {
 416                 psp->tmr_mc_addr -= psp->adev->gmc.fb_start;
 417                 psp->tmr_mc_addr += psp->adev->gmc.fb_start_original;
 418         }
 419
 420         return ret;
 421 }
 422
 423 static int psp_clear_vf_fw(struct psp_context *psp)
 424 {
 425         int ret;
 426         struct psp_gfx_cmd_resp *cmd;
 427
 428         if (!amdgpu_sriov_vf(psp->adev) || psp->adev->asic_type != CHIP_NAVI12)
 429                 return 0;
 430
 431         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 432         if (!cmd)
 433                 return -ENOMEM;
 434
 435         cmd->cmd_id = GFX_CMD_ID_CLEAR_VF_FW;
 436
 437         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 438         kfree(cmd);
 439
 440         return ret;
 441 }
 442
 443 static bool psp_skip_tmr(struct psp_context *psp)
 444 {
 445         switch (psp->adev->asic_type) {
 446         case CHIP_NAVI12:
 447         case CHIP_SIENNA_CICHLID:
 448                 return true;
 449         default:
 450                 return false;
 451         }
 452 }
 453
 454 static int psp_tmr_load(struct psp_context *psp)
 455 {
 456         int ret;
 457         struct psp_gfx_cmd_resp *cmd;
 458
 459         /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
 460          * Already set up by host driver.
 461          */
 462         if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
 463                 return 0;
 464
 465         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 466         if (!cmd)
 467                 return -ENOMEM;
 468
 469         psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr,
 470                              amdgpu_bo_size(psp->tmr_bo));
 471         DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
 472                  amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
 473
 474         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 475                                  psp->fence_buf_mc_addr);
 476
 477         kfree(cmd);
 478
 479         return ret;
 480 }
 481
 482 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
 483                                         struct psp_gfx_cmd_resp *cmd)
 484 {
 485         if (amdgpu_sriov_vf(psp->adev))
 486                 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
 487         else
 488                 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
 489 }
 490
 491 static int psp_tmr_unload(struct psp_context *psp)
 492 {
 493         int ret;
 494         struct psp_gfx_cmd_resp *cmd;
 495
 496         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 497         if (!cmd)
 498                 return -ENOMEM;
 499
 500         psp_prep_tmr_unload_cmd_buf(psp, cmd);
 501         DRM_INFO("free PSP TMR buffer\n");
 502
 503         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 504                                  psp->fence_buf_mc_addr);
 505
 506         kfree(cmd);
 507
 508         return ret;
 509 }
 510
 511 static int psp_tmr_terminate(struct psp_context *psp)
 512 {
 513         int ret;
 514         void *tmr_buf;
 515         void **pptr;
 516
 517         ret = psp_tmr_unload(psp);
 518         if (ret)
 519                 return ret;
 520
 521         /* free TMR memory buffer */
 522         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 523         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 524
 525         return 0;
 526 }
 527
 528 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
 529                                         uint64_t *output_ptr)
 530 {
 531         int ret;
 532         struct psp_gfx_cmd_resp *cmd;
 533
 534         if (!output_ptr)
 535                 return -EINVAL;
 536
 537         if (amdgpu_sriov_vf(psp->adev))
 538                 return 0;
 539
 540         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 541         if (!cmd)
 542                 return -ENOMEM;
 543
 544         cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
 545
 546         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 547                                  psp->fence_buf_mc_addr);
 548
 549         if (!ret) {
 550                 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
 551                               ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
 552         }
 553
 554         kfree(cmd);
 555
 556         return ret;
 557 }
 558
 559 static int psp_boot_config_set(struct amdgpu_device *adev)
 560 {
 561         struct psp_context *psp = &adev->psp;
 562         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 563
 564         if (adev->asic_type != CHIP_SIENNA_CICHLID)
 565                 return 0;
 566
 567         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 568
 569         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 570         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
 571         cmd->cmd.boot_cfg.boot_config = BOOT_CONFIG_GECC;
 572         cmd->cmd.boot_cfg.boot_config_valid = BOOT_CONFIG_GECC;
 573
 574         return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 575 }
 576
 577 static int psp_rl_load(struct amdgpu_device *adev)
 578 {
 579         struct psp_context *psp = &adev->psp;
 580         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 581
 582         if (psp->rl_bin_size == 0)
 583                 return 0;
 584
 585         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 586         memcpy(psp->fw_pri_buf, psp->rl_start_addr, psp->rl_bin_size);
 587
 588         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 589
 590         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
 591         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
 592         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
 593         cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl_bin_size;
 594         cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
 595
 596         return psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 597 }
 598
 599 static void psp_prep_asd_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 600                                 uint64_t asd_mc, uint32_t size)
 601 {
 602         cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
 603         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
 604         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
 605         cmd->cmd.cmd_load_ta.app_len = size;
 606
 607         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = 0;
 608         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = 0;
 609         cmd->cmd.cmd_load_ta.cmd_buf_len = 0;
 610 }
 611
 612 static int psp_asd_load(struct psp_context *psp)
 613 {
 614         int ret;
 615         struct psp_gfx_cmd_resp *cmd;
 616
 617         /* If PSP version doesn't match ASD version, asd loading will be failed.
 618          * add workaround to bypass it for sriov now.
 619          * TODO: add version check to make it common
 620          */
 621         if (amdgpu_sriov_vf(psp->adev) || !psp->asd_ucode_size)
 622                 return 0;
 623
 624         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 625         if (!cmd)
 626                 return -ENOMEM;
 627
 628         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 629         memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
 630
 631         psp_prep_asd_load_cmd_buf(cmd, psp->fw_pri_mc_addr,
 632                                   psp->asd_ucode_size);
 633
 634         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 635                                  psp->fence_buf_mc_addr);
 636         if (!ret) {
 637                 psp->asd_context.asd_initialized = true;
 638                 psp->asd_context.session_id = cmd->resp.session_id;
 639         }
 640
 641         kfree(cmd);
 642
 643         return ret;
 644 }
 645
 646 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 647                                        uint32_t session_id)
 648 {
 649         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
 650         cmd->cmd.cmd_unload_ta.session_id = session_id;
 651 }
 652
 653 static int psp_asd_unload(struct psp_context *psp)
 654 {
 655         int ret;
 656         struct psp_gfx_cmd_resp *cmd;
 657
 658         if (amdgpu_sriov_vf(psp->adev))
 659                 return 0;
 660
 661         if (!psp->asd_context.asd_initialized)
 662                 return 0;
 663
 664         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 665         if (!cmd)
 666                 return -ENOMEM;
 667
 668         psp_prep_ta_unload_cmd_buf(cmd, psp->asd_context.session_id);
 669
 670         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 671                                  psp->fence_buf_mc_addr);
 672         if (!ret)
 673                 psp->asd_context.asd_initialized = false;
 674
 675         kfree(cmd);
 676
 677         return ret;
 678 }
 679
 680 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 681                 uint32_t id, uint32_t value)
 682 {
 683         cmd->cmd_id = GFX_CMD_ID_PROG_REG;
 684         cmd->cmd.cmd_setup_reg_prog.reg_value = value;
 685         cmd->cmd.cmd_setup_reg_prog.reg_id = id;
 686 }
 687
 688 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
 689                 uint32_t value)
 690 {
 691         struct psp_gfx_cmd_resp *cmd = NULL;
 692         int ret = 0;
 693
 694         if (reg >= PSP_REG_LAST)
 695                 return -EINVAL;
 696
 697         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 698         if (!cmd)
 699                 return -ENOMEM;
 700
 701         psp_prep_reg_prog_cmd_buf(cmd, reg, value);
 702         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 703
 704         kfree(cmd);
 705         return ret;
 706 }
 707
 708 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 709                                      uint64_t ta_bin_mc,
 710                                      uint32_t ta_bin_size,
 711                                      uint64_t ta_shared_mc,
 712                                      uint32_t ta_shared_size)
 713 {
 714         cmd->cmd_id                             = GFX_CMD_ID_LOAD_TA;
 715         cmd->cmd.cmd_load_ta.app_phy_addr_lo    = lower_32_bits(ta_bin_mc);
 716         cmd->cmd.cmd_load_ta.app_phy_addr_hi    = upper_32_bits(ta_bin_mc);
 717         cmd->cmd.cmd_load_ta.app_len            = ta_bin_size;
 718
 719         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(ta_shared_mc);
 720         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(ta_shared_mc);
 721         cmd->cmd.cmd_load_ta.cmd_buf_len         = ta_shared_size;
 722 }
 723
 724 static int psp_xgmi_init_shared_buf(struct psp_context *psp)
 725 {
 726         int ret;
 727
 728         /*
 729          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 730          * physical) for xgmi ta <-> Driver
 731          */
 732         ret = amdgpu_bo_create_kernel(psp->adev, PSP_XGMI_SHARED_MEM_SIZE,
 733                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 734                                       &psp->xgmi_context.xgmi_shared_bo,
 735                                       &psp->xgmi_context.xgmi_shared_mc_addr,
 736                                       &psp->xgmi_context.xgmi_shared_buf);
 737
 738         return ret;
 739 }
 740
 741 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 742                                        uint32_t ta_cmd_id,
 743                                        uint32_t session_id)
 744 {
 745         cmd->cmd_id                             = GFX_CMD_ID_INVOKE_CMD;
 746         cmd->cmd.cmd_invoke_cmd.session_id      = session_id;
 747         cmd->cmd.cmd_invoke_cmd.ta_cmd_id       = ta_cmd_id;
 748 }
 749
 750 static int psp_ta_invoke(struct psp_context *psp,
 751                   uint32_t ta_cmd_id,
 752                   uint32_t session_id)
 753 {
 754         int ret;
 755         struct psp_gfx_cmd_resp *cmd;
 756
 757         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 758         if (!cmd)
 759                 return -ENOMEM;
 760
 761         psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, session_id);
 762
 763         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 764                                  psp->fence_buf_mc_addr);
 765
 766         kfree(cmd);
 767
 768         return ret;
 769 }
 770
 771 static int psp_xgmi_load(struct psp_context *psp)
 772 {
 773         int ret;
 774         struct psp_gfx_cmd_resp *cmd;
 775
 776         /*
 777          * TODO: bypass the loading in sriov for now
 778          */
 779
 780         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 781         if (!cmd)
 782                 return -ENOMEM;
 783
 784         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 785         memcpy(psp->fw_pri_buf, psp->ta_xgmi_start_addr, psp->ta_xgmi_ucode_size);
 786
 787         psp_prep_ta_load_cmd_buf(cmd,
 788                                  psp->fw_pri_mc_addr,
 789                                  psp->ta_xgmi_ucode_size,
 790                                  psp->xgmi_context.xgmi_shared_mc_addr,
 791                                  PSP_XGMI_SHARED_MEM_SIZE);
 792
 793         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 794                                  psp->fence_buf_mc_addr);
 795
 796         if (!ret) {
 797                 psp->xgmi_context.initialized = 1;
 798                 psp->xgmi_context.session_id = cmd->resp.session_id;
 799         }
 800
 801         kfree(cmd);
 802
 803         return ret;
 804 }
 805
 806 static int psp_xgmi_unload(struct psp_context *psp)
 807 {
 808         int ret;
 809         struct psp_gfx_cmd_resp *cmd;
 810         struct amdgpu_device *adev = psp->adev;
 811
 812         /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
 813         if (adev->asic_type == CHIP_ARCTURUS ||
 814                 (adev->asic_type == CHIP_ALDEBARAN && adev->gmc.xgmi.connected_to_cpu))
 815                 return 0;
 816
 817         /*
 818          * TODO: bypass the unloading in sriov for now
 819          */
 820
 821         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 822         if (!cmd)
 823                 return -ENOMEM;
 824
 825         psp_prep_ta_unload_cmd_buf(cmd, psp->xgmi_context.session_id);
 826
 827         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 828                                  psp->fence_buf_mc_addr);
 829
 830         kfree(cmd);
 831
 832         return ret;
 833 }
 834
 835 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
 836 {
 837         return psp_ta_invoke(psp, ta_cmd_id, psp->xgmi_context.session_id);
 838 }
 839
 840 int psp_xgmi_terminate(struct psp_context *psp)
 841 {
 842         int ret;
 843
 844         if (!psp->xgmi_context.initialized)
 845                 return 0;
 846
 847         ret = psp_xgmi_unload(psp);
 848         if (ret)
 849                 return ret;
 850
 851         psp->xgmi_context.initialized = 0;
 852
 853         /* free xgmi shared memory */
 854         amdgpu_bo_free_kernel(&psp->xgmi_context.xgmi_shared_bo,
 855                         &psp->xgmi_context.xgmi_shared_mc_addr,
 856                         &psp->xgmi_context.xgmi_shared_buf);
 857
 858         return 0;
 859 }
 860
 861 int psp_xgmi_initialize(struct psp_context *psp)
 862 {
 863         struct ta_xgmi_shared_memory *xgmi_cmd;
 864         int ret;
 865
 866         if (!psp->adev->psp.ta_fw ||
 867             !psp->adev->psp.ta_xgmi_ucode_size ||
 868             !psp->adev->psp.ta_xgmi_start_addr)
 869                 return -ENOENT;
 870
 871         if (!psp->xgmi_context.initialized) {
 872                 ret = psp_xgmi_init_shared_buf(psp);
 873                 if (ret)
 874                         return ret;
 875         }
 876
 877         /* Load XGMI TA */
 878         ret = psp_xgmi_load(psp);
 879         if (ret)
 880                 return ret;
 881
 882         /* Initialize XGMI session */
 883         xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.xgmi_shared_buf);
 884         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 885         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
 886
 887         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 888
 889         return ret;
 890 }
 891
 892 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
 893 {
 894         struct ta_xgmi_shared_memory *xgmi_cmd;
 895         int ret;
 896
 897         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf;
 898         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 899
 900         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
 901
 902         /* Invoke xgmi ta to get hive id */
 903         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 904         if (ret)
 905                 return ret;
 906
 907         *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
 908
 909         return 0;
 910 }
 911
 912 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
 913 {
 914         struct ta_xgmi_shared_memory *xgmi_cmd;
 915         int ret;
 916
 917         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf;
 918         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 919
 920         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
 921
 922         /* Invoke xgmi ta to get the node id */
 923         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
 924         if (ret)
 925                 return ret;
 926
 927         *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
 928
 929         return 0;
 930 }
 931
 932 int psp_xgmi_get_topology_info(struct psp_context *psp,
 933                                int number_devices,
 934                                struct psp_xgmi_topology_info *topology)
 935 {
 936         struct ta_xgmi_shared_memory *xgmi_cmd;
 937         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
 938         struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
 939         int i;
 940         int ret;
 941
 942         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
 943                 return -EINVAL;
 944
 945         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf;
 946         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 947
 948         /* Fill in the shared memory with topology information as input */
 949         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
 950         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
 951         topology_info_input->num_nodes = number_devices;
 952
 953         for (i = 0; i < topology_info_input->num_nodes; i++) {
 954                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
 955                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
 956                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
 957                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
 958         }
 959
 960         /* Invoke xgmi ta to get the topology information */
 961         ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
 962         if (ret)
 963                 return ret;
 964
 965         /* Read the output topology information from the shared memory */
 966         topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
 967         topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
 968         for (i = 0; i < topology->num_nodes; i++) {
 969                 topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
 970                 topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
 971                 topology->nodes[i].is_sharing_enabled = topology_info_output->nodes[i].is_sharing_enabled;
 972                 topology->nodes[i].sdma_engine = topology_info_output->nodes[i].sdma_engine;
 973         }
 974
 975         return 0;
 976 }
 977
 978 int psp_xgmi_set_topology_info(struct psp_context *psp,
 979                                int number_devices,
 980                                struct psp_xgmi_topology_info *topology)
 981 {
 982         struct ta_xgmi_shared_memory *xgmi_cmd;
 983         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
 984         int i;
 985
 986         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
 987                 return -EINVAL;
 988
 989         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.xgmi_shared_buf;
 990         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
 991
 992         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
 993         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
 994         topology_info_input->num_nodes = number_devices;
 995
 996         for (i = 0; i < topology_info_input->num_nodes; i++) {
 997                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
 998                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
 999                 topology_info_input->nodes[i].is_sharing_enabled = 1;
1000                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1001         }
1002
1003         /* Invoke xgmi ta to set topology information */
1004         return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
1005 }
1006
1007 // ras begin
1008 static int psp_ras_init_shared_buf(struct psp_context *psp)
1009 {
1010         int ret;
1011
1012         /*
1013          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1014          * physical) for ras ta <-> Driver
1015          */
1016         ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAS_SHARED_MEM_SIZE,
1017                         PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1018                         &psp->ras.ras_shared_bo,
1019                         &psp->ras.ras_shared_mc_addr,
1020                         &psp->ras.ras_shared_buf);
1021
1022         return ret;
1023 }
1024
1025 static int psp_ras_load(struct psp_context *psp)
1026 {
1027         int ret;
1028         struct psp_gfx_cmd_resp *cmd;
1029         struct ta_ras_shared_memory *ras_cmd;
1030
1031         /*
1032          * TODO: bypass the loading in sriov for now
1033          */
1034         if (amdgpu_sriov_vf(psp->adev))
1035                 return 0;
1036
1037         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1038         if (!cmd)
1039                 return -ENOMEM;
1040
1041         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1042         memcpy(psp->fw_pri_buf, psp->ta_ras_start_addr, psp->ta_ras_ucode_size);
1043
1044         psp_prep_ta_load_cmd_buf(cmd,
1045                                  psp->fw_pri_mc_addr,
1046                                  psp->ta_ras_ucode_size,
1047                                  psp->ras.ras_shared_mc_addr,
1048                                  PSP_RAS_SHARED_MEM_SIZE);
1049
1050         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1051                         psp->fence_buf_mc_addr);
1052
1053         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1054
1055         if (!ret) {
1056                 psp->ras.session_id = cmd->resp.session_id;
1057
1058                 if (!ras_cmd->ras_status)
1059                         psp->ras.ras_initialized = true;
1060                 else
1061                         dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1062         }
1063
1064         if (ret || ras_cmd->ras_status)
1065                 amdgpu_ras_fini(psp->adev);
1066
1067         kfree(cmd);
1068
1069         return ret;
1070 }
1071
1072 static int psp_ras_unload(struct psp_context *psp)
1073 {
1074         int ret;
1075         struct psp_gfx_cmd_resp *cmd;
1076
1077         /*
1078          * TODO: bypass the unloading in sriov for now
1079          */
1080         if (amdgpu_sriov_vf(psp->adev))
1081                 return 0;
1082
1083         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1084         if (!cmd)
1085                 return -ENOMEM;
1086
1087         psp_prep_ta_unload_cmd_buf(cmd, psp->ras.session_id);
1088
1089         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1090                         psp->fence_buf_mc_addr);
1091
1092         kfree(cmd);
1093
1094         return ret;
1095 }
1096
1097 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1098 {
1099         struct ta_ras_shared_memory *ras_cmd;
1100         int ret;
1101
1102         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1103
1104         /*
1105          * TODO: bypass the loading in sriov for now
1106          */
1107         if (amdgpu_sriov_vf(psp->adev))
1108                 return 0;
1109
1110         ret = psp_ta_invoke(psp, ta_cmd_id, psp->ras.session_id);
1111
1112         if (amdgpu_ras_intr_triggered())
1113                 return ret;
1114
1115         if (ras_cmd->if_version > RAS_TA_HOST_IF_VER)
1116         {
1117                 DRM_WARN("RAS: Unsupported Interface");
1118                 return -EINVAL;
1119         }
1120
1121         if (!ret) {
1122                 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1123                         dev_warn(psp->adev->dev, "ECC switch disabled\n");
1124
1125                         ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1126                 }
1127                 else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1128                         dev_warn(psp->adev->dev,
1129                                  "RAS internal register access blocked\n");
1130         }
1131
1132         return ret;
1133 }
1134
1135 int psp_ras_enable_features(struct psp_context *psp,
1136                 union ta_ras_cmd_input *info, bool enable)
1137 {
1138         struct ta_ras_shared_memory *ras_cmd;
1139         int ret;
1140
1141         if (!psp->ras.ras_initialized)
1142                 return -EINVAL;
1143
1144         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1145         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1146
1147         if (enable)
1148                 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1149         else
1150                 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1151
1152         ras_cmd->ras_in_message = *info;
1153
1154         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1155         if (ret)
1156                 return -EINVAL;
1157
1158         return ras_cmd->ras_status;
1159 }
1160
1161 static int psp_ras_terminate(struct psp_context *psp)
1162 {
1163         int ret;
1164
1165         /*
1166          * TODO: bypass the terminate in sriov for now
1167          */
1168         if (amdgpu_sriov_vf(psp->adev))
1169                 return 0;
1170
1171         if (!psp->ras.ras_initialized)
1172                 return 0;
1173
1174         ret = psp_ras_unload(psp);
1175         if (ret)
1176                 return ret;
1177
1178         psp->ras.ras_initialized = false;
1179
1180         /* free ras shared memory */
1181         amdgpu_bo_free_kernel(&psp->ras.ras_shared_bo,
1182                         &psp->ras.ras_shared_mc_addr,
1183                         &psp->ras.ras_shared_buf);
1184
1185         return 0;
1186 }
1187
1188 static int psp_ras_initialize(struct psp_context *psp)
1189 {
1190         int ret;
1191
1192         /*
1193          * TODO: bypass the initialize in sriov for now
1194          */
1195         if (amdgpu_sriov_vf(psp->adev))
1196                 return 0;
1197
1198         if (!psp->adev->psp.ta_ras_ucode_size ||
1199             !psp->adev->psp.ta_ras_start_addr) {
1200                 dev_info(psp->adev->dev, "RAS: optional ras ta ucode is not available\n");
1201                 return 0;
1202         }
1203
1204         if (!psp->ras.ras_initialized) {
1205                 ret = psp_ras_init_shared_buf(psp);
1206                 if (ret)
1207                         return ret;
1208         }
1209
1210         ret = psp_ras_load(psp);
1211         if (ret)
1212                 return ret;
1213
1214         return 0;
1215 }
1216
1217 int psp_ras_trigger_error(struct psp_context *psp,
1218                           struct ta_ras_trigger_error_input *info)
1219 {
1220         struct ta_ras_shared_memory *ras_cmd;
1221         int ret;
1222
1223         if (!psp->ras.ras_initialized)
1224                 return -EINVAL;
1225
1226         ras_cmd = (struct ta_ras_shared_memory *)psp->ras.ras_shared_buf;
1227         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1228
1229         ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1230         ras_cmd->ras_in_message.trigger_error = *info;
1231
1232         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1233         if (ret)
1234                 return -EINVAL;
1235
1236         /* If err_event_athub occurs error inject was successful, however
1237            return status from TA is no long reliable */
1238         if (amdgpu_ras_intr_triggered())
1239                 return 0;
1240
1241         return ras_cmd->ras_status;
1242 }
1243 // ras end
1244
1245 // HDCP start
1246 static int psp_hdcp_init_shared_buf(struct psp_context *psp)
1247 {
1248         int ret;
1249
1250         /*
1251          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1252          * physical) for hdcp ta <-> Driver
1253          */
1254         ret = amdgpu_bo_create_kernel(psp->adev, PSP_HDCP_SHARED_MEM_SIZE,
1255                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1256                                       &psp->hdcp_context.hdcp_shared_bo,
1257                                       &psp->hdcp_context.hdcp_shared_mc_addr,
1258                                       &psp->hdcp_context.hdcp_shared_buf);
1259
1260         return ret;
1261 }
1262
1263 static int psp_hdcp_load(struct psp_context *psp)
1264 {
1265         int ret;
1266         struct psp_gfx_cmd_resp *cmd;
1267
1268         /*
1269          * TODO: bypass the loading in sriov for now
1270          */
1271         if (amdgpu_sriov_vf(psp->adev))
1272                 return 0;
1273
1274         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1275         if (!cmd)
1276                 return -ENOMEM;
1277
1278         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1279         memcpy(psp->fw_pri_buf, psp->ta_hdcp_start_addr,
1280                psp->ta_hdcp_ucode_size);
1281
1282         psp_prep_ta_load_cmd_buf(cmd,
1283                                  psp->fw_pri_mc_addr,
1284                                  psp->ta_hdcp_ucode_size,
1285                                  psp->hdcp_context.hdcp_shared_mc_addr,
1286                                  PSP_HDCP_SHARED_MEM_SIZE);
1287
1288         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1289
1290         if (!ret) {
1291                 psp->hdcp_context.hdcp_initialized = true;
1292                 psp->hdcp_context.session_id = cmd->resp.session_id;
1293                 mutex_init(&psp->hdcp_context.mutex);
1294         }
1295
1296         kfree(cmd);
1297
1298         return ret;
1299 }
1300 static int psp_hdcp_initialize(struct psp_context *psp)
1301 {
1302         int ret;
1303
1304         /*
1305          * TODO: bypass the initialize in sriov for now
1306          */
1307         if (amdgpu_sriov_vf(psp->adev))
1308                 return 0;
1309
1310         if (!psp->adev->psp.ta_hdcp_ucode_size ||
1311             !psp->adev->psp.ta_hdcp_start_addr) {
1312                 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1313                 return 0;
1314         }
1315
1316         if (!psp->hdcp_context.hdcp_initialized) {
1317                 ret = psp_hdcp_init_shared_buf(psp);
1318                 if (ret)
1319                         return ret;
1320         }
1321
1322         ret = psp_hdcp_load(psp);
1323         if (ret)
1324                 return ret;
1325
1326         return 0;
1327 }
1328
1329 static int psp_hdcp_unload(struct psp_context *psp)
1330 {
1331         int ret;
1332         struct psp_gfx_cmd_resp *cmd;
1333
1334         /*
1335          * TODO: bypass the unloading in sriov for now
1336          */
1337         if (amdgpu_sriov_vf(psp->adev))
1338                 return 0;
1339
1340         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1341         if (!cmd)
1342                 return -ENOMEM;
1343
1344         psp_prep_ta_unload_cmd_buf(cmd, psp->hdcp_context.session_id);
1345
1346         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1347
1348         kfree(cmd);
1349
1350         return ret;
1351 }
1352
1353 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1354 {
1355         /*
1356          * TODO: bypass the loading in sriov for now
1357          */
1358         if (amdgpu_sriov_vf(psp->adev))
1359                 return 0;
1360
1361         return psp_ta_invoke(psp, ta_cmd_id, psp->hdcp_context.session_id);
1362 }
1363
1364 static int psp_hdcp_terminate(struct psp_context *psp)
1365 {
1366         int ret;
1367
1368         /*
1369          * TODO: bypass the terminate in sriov for now
1370          */
1371         if (amdgpu_sriov_vf(psp->adev))
1372                 return 0;
1373
1374         if (!psp->hdcp_context.hdcp_initialized) {
1375                 if (psp->hdcp_context.hdcp_shared_buf)
1376                         goto out;
1377                 else
1378                         return 0;
1379         }
1380
1381         ret = psp_hdcp_unload(psp);
1382         if (ret)
1383                 return ret;
1384
1385         psp->hdcp_context.hdcp_initialized = false;
1386
1387 out:
1388         /* free hdcp shared memory */
1389         amdgpu_bo_free_kernel(&psp->hdcp_context.hdcp_shared_bo,
1390                               &psp->hdcp_context.hdcp_shared_mc_addr,
1391                               &psp->hdcp_context.hdcp_shared_buf);
1392
1393         return 0;
1394 }
1395 // HDCP end
1396
1397 // DTM start
1398 static int psp_dtm_init_shared_buf(struct psp_context *psp)
1399 {
1400         int ret;
1401
1402         /*
1403          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1404          * physical) for dtm ta <-> Driver
1405          */
1406         ret = amdgpu_bo_create_kernel(psp->adev, PSP_DTM_SHARED_MEM_SIZE,
1407                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1408                                       &psp->dtm_context.dtm_shared_bo,
1409                                       &psp->dtm_context.dtm_shared_mc_addr,
1410                                       &psp->dtm_context.dtm_shared_buf);
1411
1412         return ret;
1413 }
1414
1415 static int psp_dtm_load(struct psp_context *psp)
1416 {
1417         int ret;
1418         struct psp_gfx_cmd_resp *cmd;
1419
1420         /*
1421          * TODO: bypass the loading in sriov for now
1422          */
1423         if (amdgpu_sriov_vf(psp->adev))
1424                 return 0;
1425
1426         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1427         if (!cmd)
1428                 return -ENOMEM;
1429
1430         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1431         memcpy(psp->fw_pri_buf, psp->ta_dtm_start_addr, psp->ta_dtm_ucode_size);
1432
1433         psp_prep_ta_load_cmd_buf(cmd,
1434                                  psp->fw_pri_mc_addr,
1435                                  psp->ta_dtm_ucode_size,
1436                                  psp->dtm_context.dtm_shared_mc_addr,
1437                                  PSP_DTM_SHARED_MEM_SIZE);
1438
1439         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1440
1441         if (!ret) {
1442                 psp->dtm_context.dtm_initialized = true;
1443                 psp->dtm_context.session_id = cmd->resp.session_id;
1444                 mutex_init(&psp->dtm_context.mutex);
1445         }
1446
1447         kfree(cmd);
1448
1449         return ret;
1450 }
1451
1452 static int psp_dtm_initialize(struct psp_context *psp)
1453 {
1454         int ret;
1455
1456         /*
1457          * TODO: bypass the initialize in sriov for now
1458          */
1459         if (amdgpu_sriov_vf(psp->adev))
1460                 return 0;
1461
1462         if (!psp->adev->psp.ta_dtm_ucode_size ||
1463             !psp->adev->psp.ta_dtm_start_addr) {
1464                 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1465                 return 0;
1466         }
1467
1468         if (!psp->dtm_context.dtm_initialized) {
1469                 ret = psp_dtm_init_shared_buf(psp);
1470                 if (ret)
1471                         return ret;
1472         }
1473
1474         ret = psp_dtm_load(psp);
1475         if (ret)
1476                 return ret;
1477
1478         return 0;
1479 }
1480
1481 static int psp_dtm_unload(struct psp_context *psp)
1482 {
1483         int ret;
1484         struct psp_gfx_cmd_resp *cmd;
1485
1486         /*
1487          * TODO: bypass the unloading in sriov for now
1488          */
1489         if (amdgpu_sriov_vf(psp->adev))
1490                 return 0;
1491
1492         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1493         if (!cmd)
1494                 return -ENOMEM;
1495
1496         psp_prep_ta_unload_cmd_buf(cmd, psp->dtm_context.session_id);
1497
1498         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1499
1500         kfree(cmd);
1501
1502         return ret;
1503 }
1504
1505 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1506 {
1507         /*
1508          * TODO: bypass the loading in sriov for now
1509          */
1510         if (amdgpu_sriov_vf(psp->adev))
1511                 return 0;
1512
1513         return psp_ta_invoke(psp, ta_cmd_id, psp->dtm_context.session_id);
1514 }
1515
1516 static int psp_dtm_terminate(struct psp_context *psp)
1517 {
1518         int ret;
1519
1520         /*
1521          * TODO: bypass the terminate in sriov for now
1522          */
1523         if (amdgpu_sriov_vf(psp->adev))
1524                 return 0;
1525
1526         if (!psp->dtm_context.dtm_initialized) {
1527                 if (psp->dtm_context.dtm_shared_buf)
1528                         goto out;
1529                 else
1530                         return 0;
1531         }
1532
1533         ret = psp_dtm_unload(psp);
1534         if (ret)
1535                 return ret;
1536
1537         psp->dtm_context.dtm_initialized = false;
1538
1539 out:
1540         /* free hdcp shared memory */
1541         amdgpu_bo_free_kernel(&psp->dtm_context.dtm_shared_bo,
1542                               &psp->dtm_context.dtm_shared_mc_addr,
1543                               &psp->dtm_context.dtm_shared_buf);
1544
1545         return 0;
1546 }
1547 // DTM end
1548
1549 // RAP start
1550 static int psp_rap_init_shared_buf(struct psp_context *psp)
1551 {
1552         int ret;
1553
1554         /*
1555          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1556          * physical) for rap ta <-> Driver
1557          */
1558         ret = amdgpu_bo_create_kernel(psp->adev, PSP_RAP_SHARED_MEM_SIZE,
1559                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1560                                       &psp->rap_context.rap_shared_bo,
1561                                       &psp->rap_context.rap_shared_mc_addr,
1562                                       &psp->rap_context.rap_shared_buf);
1563
1564         return ret;
1565 }
1566
1567 static int psp_rap_load(struct psp_context *psp)
1568 {
1569         int ret;
1570         struct psp_gfx_cmd_resp *cmd;
1571
1572         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1573         if (!cmd)
1574                 return -ENOMEM;
1575
1576         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1577         memcpy(psp->fw_pri_buf, psp->ta_rap_start_addr, psp->ta_rap_ucode_size);
1578
1579         psp_prep_ta_load_cmd_buf(cmd,
1580                                  psp->fw_pri_mc_addr,
1581                                  psp->ta_rap_ucode_size,
1582                                  psp->rap_context.rap_shared_mc_addr,
1583                                  PSP_RAP_SHARED_MEM_SIZE);
1584
1585         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1586
1587         if (!ret) {
1588                 psp->rap_context.rap_initialized = true;
1589                 psp->rap_context.session_id = cmd->resp.session_id;
1590                 mutex_init(&psp->rap_context.mutex);
1591         }
1592
1593         kfree(cmd);
1594
1595         return ret;
1596 }
1597
1598 static int psp_rap_unload(struct psp_context *psp)
1599 {
1600         int ret;
1601         struct psp_gfx_cmd_resp *cmd;
1602
1603         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1604         if (!cmd)
1605                 return -ENOMEM;
1606
1607         psp_prep_ta_unload_cmd_buf(cmd, psp->rap_context.session_id);
1608
1609         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1610
1611         kfree(cmd);
1612
1613         return ret;
1614 }
1615
1616 static int psp_rap_initialize(struct psp_context *psp)
1617 {
1618         int ret;
1619         enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1620
1621         /*
1622          * TODO: bypass the initialize in sriov for now
1623          */
1624         if (amdgpu_sriov_vf(psp->adev))
1625                 return 0;
1626
1627         if (!psp->adev->psp.ta_rap_ucode_size ||
1628             !psp->adev->psp.ta_rap_start_addr) {
1629                 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1630                 return 0;
1631         }
1632
1633         if (!psp->rap_context.rap_initialized) {
1634                 ret = psp_rap_init_shared_buf(psp);
1635                 if (ret)
1636                         return ret;
1637         }
1638
1639         ret = psp_rap_load(psp);
1640         if (ret)
1641                 return ret;
1642
1643         ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1644         if (ret || status != TA_RAP_STATUS__SUCCESS) {
1645                 psp_rap_unload(psp);
1646
1647                 amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo,
1648                               &psp->rap_context.rap_shared_mc_addr,
1649                               &psp->rap_context.rap_shared_buf);
1650
1651                 psp->rap_context.rap_initialized = false;
1652
1653                 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1654                          ret, status);
1655
1656                 return ret;
1657         }
1658
1659         return 0;
1660 }
1661
1662 static int psp_rap_terminate(struct psp_context *psp)
1663 {
1664         int ret;
1665
1666         if (!psp->rap_context.rap_initialized)
1667                 return 0;
1668
1669         ret = psp_rap_unload(psp);
1670
1671         psp->rap_context.rap_initialized = false;
1672
1673         /* free rap shared memory */
1674         amdgpu_bo_free_kernel(&psp->rap_context.rap_shared_bo,
1675                               &psp->rap_context.rap_shared_mc_addr,
1676                               &psp->rap_context.rap_shared_buf);
1677
1678         return ret;
1679 }
1680
1681 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1682 {
1683         struct ta_rap_shared_memory *rap_cmd;
1684         int ret = 0;
1685
1686         if (!psp->rap_context.rap_initialized)
1687                 return 0;
1688
1689         if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1690             ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1691                 return -EINVAL;
1692
1693         mutex_lock(&psp->rap_context.mutex);
1694
1695         rap_cmd = (struct ta_rap_shared_memory *)
1696                   psp->rap_context.rap_shared_buf;
1697         memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1698
1699         rap_cmd->cmd_id = ta_cmd_id;
1700         rap_cmd->validation_method_id = METHOD_A;
1701
1702         ret = psp_ta_invoke(psp, rap_cmd->cmd_id, psp->rap_context.session_id);
1703         if (ret)
1704                 goto out_unlock;
1705
1706         if (status)
1707                 *status = rap_cmd->rap_status;
1708
1709 out_unlock:
1710         mutex_unlock(&psp->rap_context.mutex);
1711
1712         return ret;
1713 }
1714 // RAP end
1715
1716 /* securedisplay start */
1717 static int psp_securedisplay_init_shared_buf(struct psp_context *psp)
1718 {
1719         int ret;
1720
1721         /*
1722          * Allocate 16k memory aligned to 4k from Frame Buffer (local
1723          * physical) for sa ta <-> Driver
1724          */
1725         ret = amdgpu_bo_create_kernel(psp->adev, PSP_SECUREDISPLAY_SHARED_MEM_SIZE,
1726                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1727                                       &psp->securedisplay_context.securedisplay_shared_bo,
1728                                       &psp->securedisplay_context.securedisplay_shared_mc_addr,
1729                                       &psp->securedisplay_context.securedisplay_shared_buf);
1730
1731         return ret;
1732 }
1733
1734 static int psp_securedisplay_load(struct psp_context *psp)
1735 {
1736         int ret;
1737         struct psp_gfx_cmd_resp *cmd;
1738
1739         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1740         if (!cmd)
1741                 return -ENOMEM;
1742
1743         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
1744         memcpy(psp->fw_pri_buf, psp->ta_securedisplay_start_addr, psp->ta_securedisplay_ucode_size);
1745
1746         psp_prep_ta_load_cmd_buf(cmd,
1747                                  psp->fw_pri_mc_addr,
1748                                  psp->ta_securedisplay_ucode_size,
1749                                  psp->securedisplay_context.securedisplay_shared_mc_addr,
1750                                  PSP_SECUREDISPLAY_SHARED_MEM_SIZE);
1751
1752         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1753
1754         if (ret)
1755                 goto failed;
1756
1757         psp->securedisplay_context.securedisplay_initialized = true;
1758         psp->securedisplay_context.session_id = cmd->resp.session_id;
1759         mutex_init(&psp->securedisplay_context.mutex);
1760
1761 failed:
1762         kfree(cmd);
1763         return ret;
1764 }
1765
1766 static int psp_securedisplay_unload(struct psp_context *psp)
1767 {
1768         int ret;
1769         struct psp_gfx_cmd_resp *cmd;
1770
1771         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
1772         if (!cmd)
1773                 return -ENOMEM;
1774
1775         psp_prep_ta_unload_cmd_buf(cmd, psp->securedisplay_context.session_id);
1776
1777         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1778
1779         kfree(cmd);
1780
1781         return ret;
1782 }
1783
1784 static int psp_securedisplay_initialize(struct psp_context *psp)
1785 {
1786         int ret;
1787         struct securedisplay_cmd *securedisplay_cmd;
1788
1789         /*
1790          * TODO: bypass the initialize in sriov for now
1791          */
1792         if (amdgpu_sriov_vf(psp->adev))
1793                 return 0;
1794
1795         if (!psp->adev->psp.ta_securedisplay_ucode_size ||
1796             !psp->adev->psp.ta_securedisplay_start_addr) {
1797                 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
1798                 return 0;
1799         }
1800
1801         if (!psp->securedisplay_context.securedisplay_initialized) {
1802                 ret = psp_securedisplay_init_shared_buf(psp);
1803                 if (ret)
1804                         return ret;
1805         }
1806
1807         ret = psp_securedisplay_load(psp);
1808         if (ret)
1809                 return ret;
1810
1811         psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
1812                         TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1813
1814         ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
1815         if (ret) {
1816                 psp_securedisplay_unload(psp);
1817
1818                 amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo,
1819                               &psp->securedisplay_context.securedisplay_shared_mc_addr,
1820                               &psp->securedisplay_context.securedisplay_shared_buf);
1821
1822                 psp->securedisplay_context.securedisplay_initialized = false;
1823
1824                 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
1825                 return -EINVAL;
1826         }
1827
1828         if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
1829                 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
1830                 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
1831                         securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
1832         }
1833
1834         return 0;
1835 }
1836
1837 static int psp_securedisplay_terminate(struct psp_context *psp)
1838 {
1839         int ret;
1840
1841         /*
1842          * TODO:bypass the terminate in sriov for now
1843          */
1844         if (amdgpu_sriov_vf(psp->adev))
1845                 return 0;
1846
1847         if (!psp->securedisplay_context.securedisplay_initialized)
1848                 return 0;
1849
1850         ret = psp_securedisplay_unload(psp);
1851         if (ret)
1852                 return ret;
1853
1854         psp->securedisplay_context.securedisplay_initialized = false;
1855
1856         /* free securedisplay shared memory */
1857         amdgpu_bo_free_kernel(&psp->securedisplay_context.securedisplay_shared_bo,
1858                               &psp->securedisplay_context.securedisplay_shared_mc_addr,
1859                               &psp->securedisplay_context.securedisplay_shared_buf);
1860
1861         return ret;
1862 }
1863
1864 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1865 {
1866         int ret;
1867
1868         if (!psp->securedisplay_context.securedisplay_initialized)
1869                 return -EINVAL;
1870
1871         if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
1872             ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
1873                 return -EINVAL;
1874
1875         mutex_lock(&psp->securedisplay_context.mutex);
1876
1877         ret = psp_ta_invoke(psp, ta_cmd_id, psp->securedisplay_context.session_id);
1878
1879         mutex_unlock(&psp->securedisplay_context.mutex);
1880
1881         return ret;
1882 }
1883 /* SECUREDISPLAY end */
1884
1885 static int psp_hw_start(struct psp_context *psp)
1886 {
1887         struct amdgpu_device *adev = psp->adev;
1888         int ret;
1889
1890         if (!amdgpu_sriov_vf(adev)) {
1891                 if (psp->kdb_bin_size &&
1892                     (psp->funcs->bootloader_load_kdb != NULL)) {
1893                         ret = psp_bootloader_load_kdb(psp);
1894                         if (ret) {
1895                                 DRM_ERROR("PSP load kdb failed!\n");
1896                                 return ret;
1897                         }
1898                 }
1899
1900                 if (psp->spl_bin_size) {
1901                         ret = psp_bootloader_load_spl(psp);
1902                         if (ret) {
1903                                 DRM_ERROR("PSP load spl failed!\n");
1904                                 return ret;
1905                         }
1906                 }
1907
1908                 ret = psp_bootloader_load_sysdrv(psp);
1909                 if (ret) {
1910                         DRM_ERROR("PSP load sysdrv failed!\n");
1911                         return ret;
1912                 }
1913
1914                 ret = psp_bootloader_load_sos(psp);
1915                 if (ret) {
1916                         DRM_ERROR("PSP load sos failed!\n");
1917                         return ret;
1918                 }
1919         }
1920
1921         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
1922         if (ret) {
1923                 DRM_ERROR("PSP create ring failed!\n");
1924                 return ret;
1925         }
1926
1927         ret = psp_clear_vf_fw(psp);
1928         if (ret) {
1929                 DRM_ERROR("PSP clear vf fw!\n");
1930                 return ret;
1931         }
1932
1933         ret = psp_boot_config_set(adev);
1934         if (ret) {
1935                 DRM_WARN("PSP set boot config@\n");
1936         }
1937
1938         ret = psp_tmr_init(psp);
1939         if (ret) {
1940                 DRM_ERROR("PSP tmr init failed!\n");
1941                 return ret;
1942         }
1943
1944         /*
1945          * For ASICs with DF Cstate management centralized
1946          * to PMFW, TMR setup should be performed after PMFW
1947          * loaded and before other non-psp firmware loaded.
1948          */
1949         if (psp->pmfw_centralized_cstate_management) {
1950                 ret = psp_load_smu_fw(psp);
1951                 if (ret)
1952                         return ret;
1953         }
1954
1955         ret = psp_tmr_load(psp);
1956         if (ret) {
1957                 DRM_ERROR("PSP load tmr failed!\n");
1958                 return ret;
1959         }
1960
1961         return 0;
1962 }
1963
1964 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
1965                            enum psp_gfx_fw_type *type)
1966 {
1967         switch (ucode->ucode_id) {
1968         case AMDGPU_UCODE_ID_SDMA0:
1969                 *type = GFX_FW_TYPE_SDMA0;
1970                 break;
1971         case AMDGPU_UCODE_ID_SDMA1:
1972                 *type = GFX_FW_TYPE_SDMA1;
1973                 break;
1974         case AMDGPU_UCODE_ID_SDMA2:
1975                 *type = GFX_FW_TYPE_SDMA2;
1976                 break;
1977         case AMDGPU_UCODE_ID_SDMA3:
1978                 *type = GFX_FW_TYPE_SDMA3;
1979                 break;
1980         case AMDGPU_UCODE_ID_SDMA4:
1981                 *type = GFX_FW_TYPE_SDMA4;
1982                 break;
1983         case AMDGPU_UCODE_ID_SDMA5:
1984                 *type = GFX_FW_TYPE_SDMA5;
1985                 break;
1986         case AMDGPU_UCODE_ID_SDMA6:
1987                 *type = GFX_FW_TYPE_SDMA6;
1988                 break;
1989         case AMDGPU_UCODE_ID_SDMA7:
1990                 *type = GFX_FW_TYPE_SDMA7;
1991                 break;
1992         case AMDGPU_UCODE_ID_CP_MES:
1993                 *type = GFX_FW_TYPE_CP_MES;
1994                 break;
1995         case AMDGPU_UCODE_ID_CP_MES_DATA:
1996                 *type = GFX_FW_TYPE_MES_STACK;
1997                 break;
1998         case AMDGPU_UCODE_ID_CP_CE:
1999                 *type = GFX_FW_TYPE_CP_CE;
2000                 break;
2001         case AMDGPU_UCODE_ID_CP_PFP:
2002                 *type = GFX_FW_TYPE_CP_PFP;
2003                 break;
2004         case AMDGPU_UCODE_ID_CP_ME:
2005                 *type = GFX_FW_TYPE_CP_ME;
2006                 break;
2007         case AMDGPU_UCODE_ID_CP_MEC1:
2008                 *type = GFX_FW_TYPE_CP_MEC;
2009                 break;
2010         case AMDGPU_UCODE_ID_CP_MEC1_JT:
2011                 *type = GFX_FW_TYPE_CP_MEC_ME1;
2012                 break;
2013         case AMDGPU_UCODE_ID_CP_MEC2:
2014                 *type = GFX_FW_TYPE_CP_MEC;
2015                 break;
2016         case AMDGPU_UCODE_ID_CP_MEC2_JT:
2017                 *type = GFX_FW_TYPE_CP_MEC_ME2;
2018                 break;
2019         case AMDGPU_UCODE_ID_RLC_G:
2020                 *type = GFX_FW_TYPE_RLC_G;
2021                 break;
2022         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2023                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2024                 break;
2025         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2026                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2027                 break;
2028         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2029                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2030                 break;
2031         case AMDGPU_UCODE_ID_RLC_IRAM:
2032                 *type = GFX_FW_TYPE_RLC_IRAM;
2033                 break;
2034         case AMDGPU_UCODE_ID_RLC_DRAM:
2035                 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2036                 break;
2037         case AMDGPU_UCODE_ID_SMC:
2038                 *type = GFX_FW_TYPE_SMU;
2039                 break;
2040         case AMDGPU_UCODE_ID_UVD:
2041                 *type = GFX_FW_TYPE_UVD;
2042                 break;
2043         case AMDGPU_UCODE_ID_UVD1:
2044                 *type = GFX_FW_TYPE_UVD1;
2045                 break;
2046         case AMDGPU_UCODE_ID_VCE:
2047                 *type = GFX_FW_TYPE_VCE;
2048                 break;
2049         case AMDGPU_UCODE_ID_VCN:
2050                 *type = GFX_FW_TYPE_VCN;
2051                 break;
2052         case AMDGPU_UCODE_ID_VCN1:
2053                 *type = GFX_FW_TYPE_VCN1;
2054                 break;
2055         case AMDGPU_UCODE_ID_DMCU_ERAM:
2056                 *type = GFX_FW_TYPE_DMCU_ERAM;
2057                 break;
2058         case AMDGPU_UCODE_ID_DMCU_INTV:
2059                 *type = GFX_FW_TYPE_DMCU_ISR;
2060                 break;
2061         case AMDGPU_UCODE_ID_VCN0_RAM:
2062                 *type = GFX_FW_TYPE_VCN0_RAM;
2063                 break;
2064         case AMDGPU_UCODE_ID_VCN1_RAM:
2065                 *type = GFX_FW_TYPE_VCN1_RAM;
2066                 break;
2067         case AMDGPU_UCODE_ID_DMCUB:
2068                 *type = GFX_FW_TYPE_DMUB;
2069                 break;
2070         case AMDGPU_UCODE_ID_MAXIMUM:
2071         default:
2072                 return -EINVAL;
2073         }
2074
2075         return 0;
2076 }
2077
2078 static void psp_print_fw_hdr(struct psp_context *psp,
2079                              struct amdgpu_firmware_info *ucode)
2080 {
2081         struct amdgpu_device *adev = psp->adev;
2082         struct common_firmware_header *hdr;
2083
2084         switch (ucode->ucode_id) {
2085         case AMDGPU_UCODE_ID_SDMA0:
2086         case AMDGPU_UCODE_ID_SDMA1:
2087         case AMDGPU_UCODE_ID_SDMA2:
2088         case AMDGPU_UCODE_ID_SDMA3:
2089         case AMDGPU_UCODE_ID_SDMA4:
2090         case AMDGPU_UCODE_ID_SDMA5:
2091         case AMDGPU_UCODE_ID_SDMA6:
2092         case AMDGPU_UCODE_ID_SDMA7:
2093                 hdr = (struct common_firmware_header *)
2094                         adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2095                 amdgpu_ucode_print_sdma_hdr(hdr);
2096                 break;
2097         case AMDGPU_UCODE_ID_CP_CE:
2098                 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2099                 amdgpu_ucode_print_gfx_hdr(hdr);
2100                 break;
2101         case AMDGPU_UCODE_ID_CP_PFP:
2102                 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2103                 amdgpu_ucode_print_gfx_hdr(hdr);
2104                 break;
2105         case AMDGPU_UCODE_ID_CP_ME:
2106                 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2107                 amdgpu_ucode_print_gfx_hdr(hdr);
2108                 break;
2109         case AMDGPU_UCODE_ID_CP_MEC1:
2110                 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2111                 amdgpu_ucode_print_gfx_hdr(hdr);
2112                 break;
2113         case AMDGPU_UCODE_ID_RLC_G:
2114                 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2115                 amdgpu_ucode_print_rlc_hdr(hdr);
2116                 break;
2117         case AMDGPU_UCODE_ID_SMC:
2118                 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2119                 amdgpu_ucode_print_smc_hdr(hdr);
2120                 break;
2121         default:
2122                 break;
2123         }
2124 }
2125
2126 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
2127                                        struct psp_gfx_cmd_resp *cmd)
2128 {
2129         int ret;
2130         uint64_t fw_mem_mc_addr = ucode->mc_addr;
2131
2132         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
2133
2134         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2135         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2136         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2137         cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2138
2139         ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2140         if (ret)
2141                 DRM_ERROR("Unknown firmware type\n");
2142
2143         return ret;
2144 }
2145
2146 static int psp_execute_np_fw_load(struct psp_context *psp,
2147                                   struct amdgpu_firmware_info *ucode)
2148 {
2149         int ret = 0;
2150
2151         ret = psp_prep_load_ip_fw_cmd_buf(ucode, psp->cmd);
2152         if (ret)
2153                 return ret;
2154
2155         ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
2156                                  psp->fence_buf_mc_addr);
2157
2158         return ret;
2159 }
2160
2161 static int psp_load_smu_fw(struct psp_context *psp)
2162 {
2163         int ret;
2164         struct amdgpu_device *adev = psp->adev;
2165         struct amdgpu_firmware_info *ucode =
2166                         &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2167         struct amdgpu_ras *ras = psp->ras.ras;
2168
2169         if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2170                 return 0;
2171
2172         if ((amdgpu_in_reset(adev) &&
2173              ras && ras->supported &&
2174              (adev->asic_type == CHIP_ARCTURUS ||
2175               adev->asic_type == CHIP_VEGA20)) ||
2176              (adev->in_runpm &&
2177               adev->asic_type >= CHIP_NAVI10 &&
2178               adev->asic_type <= CHIP_NAVI12)) {
2179                 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2180                 if (ret) {
2181                         DRM_WARN("Failed to set MP1 state prepare for reload\n");
2182                 }
2183         }
2184
2185         ret = psp_execute_np_fw_load(psp, ucode);
2186
2187         if (ret)
2188                 DRM_ERROR("PSP load smu failed!\n");
2189
2190         return ret;
2191 }
2192
2193 static bool fw_load_skip_check(struct psp_context *psp,
2194                                struct amdgpu_firmware_info *ucode)
2195 {
2196         if (!ucode->fw)
2197                 return true;
2198
2199         if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2200             (psp_smu_reload_quirk(psp) ||
2201              psp->autoload_supported ||
2202              psp->pmfw_centralized_cstate_management))
2203                 return true;
2204
2205         if (amdgpu_sriov_vf(psp->adev) &&
2206            (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
2207             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
2208             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2
2209             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3
2210             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA4
2211             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA5
2212             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA6
2213             || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA7
2214             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G
2215             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
2216             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
2217             || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
2218             || ucode->ucode_id == AMDGPU_UCODE_ID_SMC))
2219                 /*skip ucode loading in SRIOV VF */
2220                 return true;
2221
2222         if (psp->autoload_supported &&
2223             (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2224              ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2225                 /* skip mec JT when autoload is enabled */
2226                 return true;
2227
2228         return false;
2229 }
2230
2231 int psp_load_fw_list(struct psp_context *psp,
2232                      struct amdgpu_firmware_info **ucode_list, int ucode_count)
2233 {
2234         int ret = 0, i;
2235         struct amdgpu_firmware_info *ucode;
2236
2237         for (i = 0; i < ucode_count; ++i) {
2238                 ucode = ucode_list[i];
2239                 psp_print_fw_hdr(psp, ucode);
2240                 ret = psp_execute_np_fw_load(psp, ucode);
2241                 if (ret)
2242                         return ret;
2243         }
2244         return ret;
2245 }
2246
2247 static int psp_np_fw_load(struct psp_context *psp)
2248 {
2249         int i, ret;
2250         struct amdgpu_firmware_info *ucode;
2251         struct amdgpu_device *adev = psp->adev;
2252
2253         if (psp->autoload_supported &&
2254             !psp->pmfw_centralized_cstate_management) {
2255                 ret = psp_load_smu_fw(psp);
2256                 if (ret)
2257                         return ret;
2258         }
2259
2260         for (i = 0; i < adev->firmware.max_ucodes; i++) {
2261                 ucode = &adev->firmware.ucode[i];
2262
2263                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2264                     !fw_load_skip_check(psp, ucode)) {
2265                         ret = psp_load_smu_fw(psp);
2266                         if (ret)
2267                                 return ret;
2268                         continue;
2269                 }
2270
2271                 if (fw_load_skip_check(psp, ucode))
2272                         continue;
2273
2274                 if (psp->autoload_supported &&
2275                     (adev->asic_type >= CHIP_SIENNA_CICHLID &&
2276                      adev->asic_type <= CHIP_DIMGREY_CAVEFISH) &&
2277                     (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2278                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2279                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2280                         /* PSP only receive one SDMA fw for sienna_cichlid,
2281                          * as all four sdma fw are same */
2282                         continue;
2283
2284                 psp_print_fw_hdr(psp, ucode);
2285
2286                 ret = psp_execute_np_fw_load(psp, ucode);
2287                 if (ret)
2288                         return ret;
2289
2290                 /* Start rlc autoload after psp recieved all the gfx firmware */
2291                 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2292                     AMDGPU_UCODE_ID_CP_MEC2 : AMDGPU_UCODE_ID_RLC_G)) {
2293                         ret = psp_rlc_autoload_start(psp);
2294                         if (ret) {
2295                                 DRM_ERROR("Failed to start rlc autoload\n");
2296                                 return ret;
2297                         }
2298                 }
2299         }
2300
2301         return 0;
2302 }
2303
2304 static int psp_load_fw(struct amdgpu_device *adev)
2305 {
2306         int ret;
2307         struct psp_context *psp = &adev->psp;
2308
2309         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2310                 psp_ring_stop(psp, PSP_RING_TYPE__KM); /* should not destroy ring, only stop */
2311                 goto skip_memalloc;
2312         }
2313
2314         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
2315         if (!psp->cmd)
2316                 return -ENOMEM;
2317
2318         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
2319                                         AMDGPU_GEM_DOMAIN_GTT,
2320                                         &psp->fw_pri_bo,
2321                                         &psp->fw_pri_mc_addr,
2322                                         &psp->fw_pri_buf);
2323         if (ret)
2324                 goto failed;
2325
2326         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
2327                                         AMDGPU_GEM_DOMAIN_VRAM,
2328                                         &psp->fence_buf_bo,
2329                                         &psp->fence_buf_mc_addr,
2330                                         &psp->fence_buf);
2331         if (ret)
2332                 goto failed;
2333
2334         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
2335                                       AMDGPU_GEM_DOMAIN_VRAM,
2336                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
2337                                       (void **)&psp->cmd_buf_mem);
2338         if (ret)
2339                 goto failed;
2340
2341         memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2342
2343         ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2344         if (ret) {
2345                 DRM_ERROR("PSP ring init failed!\n");
2346                 goto failed;
2347         }
2348
2349 skip_memalloc:
2350         ret = psp_hw_start(psp);
2351         if (ret)
2352                 goto failed;
2353
2354         ret = psp_np_fw_load(psp);
2355         if (ret)
2356                 goto failed;
2357
2358         ret = psp_asd_load(psp);
2359         if (ret) {
2360                 DRM_ERROR("PSP load asd failed!\n");
2361                 return ret;
2362         }
2363
2364         ret = psp_rl_load(adev);
2365         if (ret) {
2366                 DRM_ERROR("PSP load RL failed!\n");
2367                 return ret;
2368         }
2369
2370         if (psp->adev->psp.ta_fw) {
2371                 ret = psp_ras_initialize(psp);
2372                 if (ret)
2373                         dev_err(psp->adev->dev,
2374                                         "RAS: Failed to initialize RAS\n");
2375
2376                 ret = psp_hdcp_initialize(psp);
2377                 if (ret)
2378                         dev_err(psp->adev->dev,
2379                                 "HDCP: Failed to initialize HDCP\n");
2380
2381                 ret = psp_dtm_initialize(psp);
2382                 if (ret)
2383                         dev_err(psp->adev->dev,
2384                                 "DTM: Failed to initialize DTM\n");
2385
2386                 ret = psp_rap_initialize(psp);
2387                 if (ret)
2388                         dev_err(psp->adev->dev,
2389                                 "RAP: Failed to initialize RAP\n");
2390
2391                 ret = psp_securedisplay_initialize(psp);
2392                 if (ret)
2393                         dev_err(psp->adev->dev,
2394                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2395         }
2396
2397         return 0;
2398
2399 failed:
2400         /*
2401          * all cleanup jobs (xgmi terminate, ras terminate,
2402          * ring destroy, cmd/fence/fw buffers destory,
2403          * psp->cmd destory) are delayed to psp_hw_fini
2404          */
2405         return ret;
2406 }
2407
2408 static int psp_hw_init(void *handle)
2409 {
2410         int ret;
2411         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2412
2413         mutex_lock(&adev->firmware.mutex);
2414         /*
2415          * This sequence is just used on hw_init only once, no need on
2416          * resume.
2417          */
2418         ret = amdgpu_ucode_init_bo(adev);
2419         if (ret)
2420                 goto failed;
2421
2422         ret = psp_load_fw(adev);
2423         if (ret) {
2424                 DRM_ERROR("PSP firmware loading failed\n");
2425                 goto failed;
2426         }
2427
2428         mutex_unlock(&adev->firmware.mutex);
2429         return 0;
2430
2431 failed:
2432         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2433         mutex_unlock(&adev->firmware.mutex);
2434         return -EINVAL;
2435 }
2436
2437 static int psp_hw_fini(void *handle)
2438 {
2439         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2440         struct psp_context *psp = &adev->psp;
2441         int ret;
2442
2443         if (psp->adev->psp.ta_fw) {
2444                 psp_ras_terminate(psp);
2445                 psp_securedisplay_terminate(psp);
2446                 psp_rap_terminate(psp);
2447                 psp_dtm_terminate(psp);
2448                 psp_hdcp_terminate(psp);
2449         }
2450
2451         psp_asd_unload(psp);
2452         ret = psp_clear_vf_fw(psp);
2453         if (ret) {
2454                 DRM_ERROR("PSP clear vf fw!\n");
2455                 return ret;
2456         }
2457
2458         psp_tmr_terminate(psp);
2459         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2460
2461         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
2462                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
2463         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
2464                               &psp->fence_buf_mc_addr, &psp->fence_buf);
2465         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
2466                               (void **)&psp->cmd_buf_mem);
2467
2468         kfree(psp->cmd);
2469         psp->cmd = NULL;
2470
2471         return 0;
2472 }
2473
2474 static int psp_suspend(void *handle)
2475 {
2476         int ret;
2477         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2478         struct psp_context *psp = &adev->psp;
2479
2480         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2481             psp->xgmi_context.initialized == 1) {
2482                 ret = psp_xgmi_terminate(psp);
2483                 if (ret) {
2484                         DRM_ERROR("Failed to terminate xgmi ta\n");
2485                         return ret;
2486                 }
2487         }
2488
2489         if (psp->adev->psp.ta_fw) {
2490                 ret = psp_ras_terminate(psp);
2491                 if (ret) {
2492                         DRM_ERROR("Failed to terminate ras ta\n");
2493                         return ret;
2494                 }
2495                 ret = psp_hdcp_terminate(psp);
2496                 if (ret) {
2497                         DRM_ERROR("Failed to terminate hdcp ta\n");
2498                         return ret;
2499                 }
2500                 ret = psp_dtm_terminate(psp);
2501                 if (ret) {
2502                         DRM_ERROR("Failed to terminate dtm ta\n");
2503                         return ret;
2504                 }
2505                 ret = psp_rap_terminate(psp);
2506                 if (ret) {
2507                         DRM_ERROR("Failed to terminate rap ta\n");
2508                         return ret;
2509                 }
2510                 ret = psp_securedisplay_terminate(psp);
2511                 if (ret) {
2512                         DRM_ERROR("Failed to terminate securedisplay ta\n");
2513                         return ret;
2514                 }
2515         }
2516
2517         ret = psp_asd_unload(psp);
2518         if (ret) {
2519                 DRM_ERROR("Failed to unload asd\n");
2520                 return ret;
2521         }
2522
2523         ret = psp_tmr_terminate(psp);
2524         if (ret) {
2525                 DRM_ERROR("Failed to terminate tmr\n");
2526                 return ret;
2527         }
2528
2529         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2530         if (ret) {
2531                 DRM_ERROR("PSP ring stop failed\n");
2532                 return ret;
2533         }
2534
2535         return 0;
2536 }
2537
2538 static int psp_resume(void *handle)
2539 {
2540         int ret;
2541         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2542         struct psp_context *psp = &adev->psp;
2543
2544         DRM_INFO("PSP is resuming...\n");
2545
2546         ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2547         if (ret) {
2548                 DRM_ERROR("Failed to process memory training!\n");
2549                 return ret;
2550         }
2551
2552         mutex_lock(&adev->firmware.mutex);
2553
2554         ret = psp_hw_start(psp);
2555         if (ret)
2556                 goto failed;
2557
2558         ret = psp_np_fw_load(psp);
2559         if (ret)
2560                 goto failed;
2561
2562         ret = psp_asd_load(psp);
2563         if (ret) {
2564                 DRM_ERROR("PSP load asd failed!\n");
2565                 goto failed;
2566         }
2567
2568         if (adev->gmc.xgmi.num_physical_nodes > 1) {
2569                 ret = psp_xgmi_initialize(psp);
2570                 /* Warning the XGMI seesion initialize failure
2571                  * Instead of stop driver initialization
2572                  */
2573                 if (ret)
2574                         dev_err(psp->adev->dev,
2575                                 "XGMI: Failed to initialize XGMI session\n");
2576         }
2577
2578         if (psp->adev->psp.ta_fw) {
2579                 ret = psp_ras_initialize(psp);
2580                 if (ret)
2581                         dev_err(psp->adev->dev,
2582                                         "RAS: Failed to initialize RAS\n");
2583
2584                 ret = psp_hdcp_initialize(psp);
2585                 if (ret)
2586                         dev_err(psp->adev->dev,
2587                                 "HDCP: Failed to initialize HDCP\n");
2588
2589                 ret = psp_dtm_initialize(psp);
2590                 if (ret)
2591                         dev_err(psp->adev->dev,
2592                                 "DTM: Failed to initialize DTM\n");
2593
2594                 ret = psp_rap_initialize(psp);
2595                 if (ret)
2596                         dev_err(psp->adev->dev,
2597                                 "RAP: Failed to initialize RAP\n");
2598
2599                 ret = psp_securedisplay_initialize(psp);
2600                 if (ret)
2601                         dev_err(psp->adev->dev,
2602                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2603         }
2604
2605         mutex_unlock(&adev->firmware.mutex);
2606
2607         return 0;
2608
2609 failed:
2610         DRM_ERROR("PSP resume failed\n");
2611         mutex_unlock(&adev->firmware.mutex);
2612         return ret;
2613 }
2614
2615 int psp_gpu_reset(struct amdgpu_device *adev)
2616 {
2617         int ret;
2618
2619         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2620                 return 0;
2621
2622         mutex_lock(&adev->psp.mutex);
2623         ret = psp_mode1_reset(&adev->psp);
2624         mutex_unlock(&adev->psp.mutex);
2625
2626         return ret;
2627 }
2628
2629 int psp_rlc_autoload_start(struct psp_context *psp)
2630 {
2631         int ret;
2632         struct psp_gfx_cmd_resp *cmd;
2633
2634         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
2635         if (!cmd)
2636                 return -ENOMEM;
2637
2638         cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2639
2640         ret = psp_cmd_submit_buf(psp, NULL, cmd,
2641                                  psp->fence_buf_mc_addr);
2642         kfree(cmd);
2643         return ret;
2644 }
2645
2646 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2647                         uint64_t cmd_gpu_addr, int cmd_size)
2648 {
2649         struct amdgpu_firmware_info ucode = {0};
2650
2651         ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2652                 AMDGPU_UCODE_ID_VCN0_RAM;
2653         ucode.mc_addr = cmd_gpu_addr;
2654         ucode.ucode_size = cmd_size;
2655
2656         return psp_execute_np_fw_load(&adev->psp, &ucode);
2657 }
2658
2659 int psp_ring_cmd_submit(struct psp_context *psp,
2660                         uint64_t cmd_buf_mc_addr,
2661                         uint64_t fence_mc_addr,
2662                         int index)
2663 {
2664         unsigned int psp_write_ptr_reg = 0;
2665         struct psp_gfx_rb_frame *write_frame;
2666         struct psp_ring *ring = &psp->km_ring;
2667         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2668         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2669                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2670         struct amdgpu_device *adev = psp->adev;
2671         uint32_t ring_size_dw = ring->ring_size / 4;
2672         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2673
2674         /* KM (GPCOM) prepare write pointer */
2675         psp_write_ptr_reg = psp_ring_get_wptr(psp);
2676
2677         /* Update KM RB frame pointer to new frame */
2678         /* write_frame ptr increments by size of rb_frame in bytes */
2679         /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2680         if ((psp_write_ptr_reg % ring_size_dw) == 0)
2681                 write_frame = ring_buffer_start;
2682         else
2683                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2684         /* Check invalid write_frame ptr address */
2685         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2686                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2687                           ring_buffer_start, ring_buffer_end, write_frame);
2688                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2689                 return -EINVAL;
2690         }
2691
2692         /* Initialize KM RB frame */
2693         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2694
2695         /* Update KM RB frame */
2696         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2697         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2698         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2699         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2700         write_frame->fence_value = index;
2701         amdgpu_asic_flush_hdp(adev, NULL);
2702
2703         /* Update the write Pointer in DWORDs */
2704         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2705         psp_ring_set_wptr(psp, psp_write_ptr_reg);
2706         return 0;
2707 }
2708
2709 int psp_init_asd_microcode(struct psp_context *psp,
2710                            const char *chip_name)
2711 {
2712         struct amdgpu_device *adev = psp->adev;
2713         char fw_name[PSP_FW_NAME_LEN];
2714         const struct psp_firmware_header_v1_0 *asd_hdr;
2715         int err = 0;
2716
2717         if (!chip_name) {
2718                 dev_err(adev->dev, "invalid chip name for asd microcode\n");
2719                 return -EINVAL;
2720         }
2721
2722         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
2723         err = request_firmware(&adev->psp.asd_fw, fw_name, adev->dev);
2724         if (err)
2725                 goto out;
2726
2727         err = amdgpu_ucode_validate(adev->psp.asd_fw);
2728         if (err)
2729                 goto out;
2730
2731         asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2732         adev->psp.asd_fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
2733         adev->psp.asd_feature_version = le32_to_cpu(asd_hdr->ucode_feature_version);
2734         adev->psp.asd_ucode_size = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
2735         adev->psp.asd_start_addr = (uint8_t *)asd_hdr +
2736                                 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
2737         return 0;
2738 out:
2739         dev_err(adev->dev, "fail to initialize asd microcode\n");
2740         release_firmware(adev->psp.asd_fw);
2741         adev->psp.asd_fw = NULL;
2742         return err;
2743 }
2744
2745 int psp_init_toc_microcode(struct psp_context *psp,
2746                            const char *chip_name)
2747 {
2748         struct amdgpu_device *adev = psp->adev;
2749         char fw_name[30];
2750         const struct psp_firmware_header_v1_0 *toc_hdr;
2751         int err = 0;
2752
2753         if (!chip_name) {
2754                 dev_err(adev->dev, "invalid chip name for toc microcode\n");
2755                 return -EINVAL;
2756         }
2757
2758         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
2759         err = request_firmware(&adev->psp.toc_fw, fw_name, adev->dev);
2760         if (err)
2761                 goto out;
2762
2763         err = amdgpu_ucode_validate(adev->psp.toc_fw);
2764         if (err)
2765                 goto out;
2766
2767         toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
2768         adev->psp.toc_fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
2769         adev->psp.toc_feature_version = le32_to_cpu(toc_hdr->ucode_feature_version);
2770         adev->psp.toc_bin_size = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
2771         adev->psp.toc_start_addr = (uint8_t *)toc_hdr +
2772                                 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
2773         return 0;
2774 out:
2775         dev_err(adev->dev, "fail to request/validate toc microcode\n");
2776         release_firmware(adev->psp.toc_fw);
2777         adev->psp.toc_fw = NULL;
2778         return err;
2779 }
2780
2781 int psp_init_sos_microcode(struct psp_context *psp,
2782                            const char *chip_name)
2783 {
2784         struct amdgpu_device *adev = psp->adev;
2785         char fw_name[PSP_FW_NAME_LEN];
2786         const struct psp_firmware_header_v1_0 *sos_hdr;
2787         const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
2788         const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
2789         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
2790         int err = 0;
2791
2792         if (!chip_name) {
2793                 dev_err(adev->dev, "invalid chip name for sos microcode\n");
2794                 return -EINVAL;
2795         }
2796
2797         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
2798         err = request_firmware(&adev->psp.sos_fw, fw_name, adev->dev);
2799         if (err)
2800                 goto out;
2801
2802         err = amdgpu_ucode_validate(adev->psp.sos_fw);
2803         if (err)
2804                 goto out;
2805
2806         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
2807         amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
2808
2809         switch (sos_hdr->header.header_version_major) {
2810         case 1:
2811                 adev->psp.sos_fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
2812                 adev->psp.sos_feature_version = le32_to_cpu(sos_hdr->ucode_feature_version);
2813                 adev->psp.sos_bin_size = le32_to_cpu(sos_hdr->sos_size_bytes);
2814                 adev->psp.sys_bin_size = le32_to_cpu(sos_hdr->sos_offset_bytes);
2815                 adev->psp.sys_start_addr = (uint8_t *)sos_hdr +
2816                                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
2817                 adev->psp.sos_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2818                                 le32_to_cpu(sos_hdr->sos_offset_bytes);
2819                 if (sos_hdr->header.header_version_minor == 1) {
2820                         sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
2821                         adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_1->toc_size_bytes);
2822                         adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2823                                         le32_to_cpu(sos_hdr_v1_1->toc_offset_bytes);
2824                         adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_1->kdb_size_bytes);
2825                         adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2826                                         le32_to_cpu(sos_hdr_v1_1->kdb_offset_bytes);
2827                 }
2828                 if (sos_hdr->header.header_version_minor == 2) {
2829                         sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
2830                         adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_2->kdb_size_bytes);
2831                         adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2832                                                     le32_to_cpu(sos_hdr_v1_2->kdb_offset_bytes);
2833                 }
2834                 if (sos_hdr->header.header_version_minor == 3) {
2835                         sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
2836                         adev->psp.toc_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.toc_size_bytes);
2837                         adev->psp.toc_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2838                                 le32_to_cpu(sos_hdr_v1_3->v1_1.toc_offset_bytes);
2839                         adev->psp.kdb_bin_size = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_size_bytes);
2840                         adev->psp.kdb_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2841                                 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb_offset_bytes);
2842                         adev->psp.spl_bin_size = le32_to_cpu(sos_hdr_v1_3->spl_size_bytes);
2843                         adev->psp.spl_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2844                                 le32_to_cpu(sos_hdr_v1_3->spl_offset_bytes);
2845                         adev->psp.rl_bin_size = le32_to_cpu(sos_hdr_v1_3->rl_size_bytes);
2846                         adev->psp.rl_start_addr = (uint8_t *)adev->psp.sys_start_addr +
2847                                 le32_to_cpu(sos_hdr_v1_3->rl_offset_bytes);
2848                 }
2849                 break;
2850         default:
2851                 dev_err(adev->dev,
2852                         "unsupported psp sos firmware\n");
2853                 err = -EINVAL;
2854                 goto out;
2855         }
2856
2857         return 0;
2858 out:
2859         dev_err(adev->dev,
2860                 "failed to init sos firmware\n");
2861         release_firmware(adev->psp.sos_fw);
2862         adev->psp.sos_fw = NULL;
2863
2864         return err;
2865 }
2866
2867 static int parse_ta_bin_descriptor(struct psp_context *psp,
2868                                    const struct ta_fw_bin_desc *desc,
2869                                    const struct ta_firmware_header_v2_0 *ta_hdr)
2870 {
2871         uint8_t *ucode_start_addr  = NULL;
2872
2873         if (!psp || !desc || !ta_hdr)
2874                 return -EINVAL;
2875
2876         ucode_start_addr  = (uint8_t *)ta_hdr +
2877                             le32_to_cpu(desc->offset_bytes) +
2878                             le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
2879
2880         switch (desc->fw_type) {
2881         case TA_FW_TYPE_PSP_ASD:
2882                 psp->asd_fw_version        = le32_to_cpu(desc->fw_version);
2883                 psp->asd_feature_version   = le32_to_cpu(desc->fw_version);
2884                 psp->asd_ucode_size        = le32_to_cpu(desc->size_bytes);
2885                 psp->asd_start_addr        = ucode_start_addr;
2886                 break;
2887         case TA_FW_TYPE_PSP_XGMI:
2888                 psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version);
2889                 psp->ta_xgmi_ucode_size    = le32_to_cpu(desc->size_bytes);
2890                 psp->ta_xgmi_start_addr    = ucode_start_addr;
2891                 break;
2892         case TA_FW_TYPE_PSP_RAS:
2893                 psp->ta_ras_ucode_version  = le32_to_cpu(desc->fw_version);
2894                 psp->ta_ras_ucode_size     = le32_to_cpu(desc->size_bytes);
2895                 psp->ta_ras_start_addr     = ucode_start_addr;
2896                 break;
2897         case TA_FW_TYPE_PSP_HDCP:
2898                 psp->ta_hdcp_ucode_version = le32_to_cpu(desc->fw_version);
2899                 psp->ta_hdcp_ucode_size    = le32_to_cpu(desc->size_bytes);
2900                 psp->ta_hdcp_start_addr    = ucode_start_addr;
2901                 break;
2902         case TA_FW_TYPE_PSP_DTM:
2903                 psp->ta_dtm_ucode_version  = le32_to_cpu(desc->fw_version);
2904                 psp->ta_dtm_ucode_size     = le32_to_cpu(desc->size_bytes);
2905                 psp->ta_dtm_start_addr     = ucode_start_addr;
2906                 break;
2907         case TA_FW_TYPE_PSP_RAP:
2908                 psp->ta_rap_ucode_version  = le32_to_cpu(desc->fw_version);
2909                 psp->ta_rap_ucode_size     = le32_to_cpu(desc->size_bytes);
2910                 psp->ta_rap_start_addr     = ucode_start_addr;
2911                 break;
2912         case TA_FW_TYPE_PSP_SECUREDISPLAY:
2913                 psp->ta_securedisplay_ucode_version  = le32_to_cpu(desc->fw_version);
2914                 psp->ta_securedisplay_ucode_size     = le32_to_cpu(desc->size_bytes);
2915                 psp->ta_securedisplay_start_addr     = ucode_start_addr;
2916                 break;
2917         default:
2918                 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
2919                 break;
2920         }
2921
2922         return 0;
2923 }
2924
2925 int psp_init_ta_microcode(struct psp_context *psp,
2926                           const char *chip_name)
2927 {
2928         struct amdgpu_device *adev = psp->adev;
2929         char fw_name[PSP_FW_NAME_LEN];
2930         const struct ta_firmware_header_v2_0 *ta_hdr;
2931         int err = 0;
2932         int ta_index = 0;
2933
2934         if (!chip_name) {
2935                 dev_err(adev->dev, "invalid chip name for ta microcode\n");
2936                 return -EINVAL;
2937         }
2938
2939         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
2940         err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
2941         if (err)
2942                 goto out;
2943
2944         err = amdgpu_ucode_validate(adev->psp.ta_fw);
2945         if (err)
2946                 goto out;
2947
2948         ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
2949
2950         if (le16_to_cpu(ta_hdr->header.header_version_major) != 2) {
2951                 dev_err(adev->dev, "unsupported TA header version\n");
2952                 err = -EINVAL;
2953                 goto out;
2954         }
2955
2956         if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_TA_PACKAGING) {
2957                 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
2958                 err = -EINVAL;
2959                 goto out;
2960         }
2961
2962         for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
2963                 err = parse_ta_bin_descriptor(psp,
2964                                               &ta_hdr->ta_fw_bin[ta_index],
2965                                               ta_hdr);
2966                 if (err)
2967                         goto out;
2968         }
2969
2970         return 0;
2971 out:
2972         dev_err(adev->dev, "fail to initialize ta microcode\n");
2973         release_firmware(adev->psp.ta_fw);
2974         adev->psp.ta_fw = NULL;
2975         return err;
2976 }
2977
2978 static int psp_set_clockgating_state(void *handle,
2979                                      enum amd_clockgating_state state)
2980 {
2981         return 0;
2982 }
2983
2984 static int psp_set_powergating_state(void *handle,
2985                                      enum amd_powergating_state state)
2986 {
2987         return 0;
2988 }
2989
2990 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
2991                                          struct device_attribute *attr,
2992                                          char *buf)
2993 {
2994         struct drm_device *ddev = dev_get_drvdata(dev);
2995         struct amdgpu_device *adev = drm_to_adev(ddev);
2996         uint32_t fw_ver;
2997         int ret;
2998
2999         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3000                 DRM_INFO("PSP block is not ready yet.");
3001                 return -EBUSY;
3002         }
3003
3004         mutex_lock(&adev->psp.mutex);
3005         ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3006         mutex_unlock(&adev->psp.mutex);
3007
3008         if (ret) {
3009                 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
3010                 return ret;
3011         }
3012
3013         return sysfs_emit(buf, "%x\n", fw_ver);
3014 }
3015
3016 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3017                                                        struct device_attribute *attr,
3018                                                        const char *buf,
3019                                                        size_t count)
3020 {
3021         struct drm_device *ddev = dev_get_drvdata(dev);
3022         struct amdgpu_device *adev = drm_to_adev(ddev);
3023         void *cpu_addr;
3024         dma_addr_t dma_addr;
3025         int ret;
3026         char fw_name[100];
3027         const struct firmware *usbc_pd_fw;
3028
3029         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3030                 DRM_INFO("PSP block is not ready yet.");
3031                 return -EBUSY;
3032         }
3033
3034         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3035         ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3036         if (ret)
3037                 goto fail;
3038
3039         /* We need contiguous physical mem to place the FW  for psp to access */
3040         cpu_addr = dma_alloc_coherent(adev->dev, usbc_pd_fw->size, &dma_addr, GFP_KERNEL);
3041
3042         ret = dma_mapping_error(adev->dev, dma_addr);
3043         if (ret)
3044                 goto rel_buf;
3045
3046         memcpy_toio(cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3047
3048         /*
3049          * x86 specific workaround.
3050          * Without it the buffer is invisible in PSP.
3051          *
3052          * TODO Remove once PSP starts snooping CPU cache
3053          */
3054 #ifdef CONFIG_X86
3055         clflush_cache_range(cpu_addr, (usbc_pd_fw->size & ~(L1_CACHE_BYTES - 1)));
3056 #endif
3057
3058         mutex_lock(&adev->psp.mutex);
3059         ret = psp_load_usbc_pd_fw(&adev->psp, dma_addr);
3060         mutex_unlock(&adev->psp.mutex);
3061
3062 rel_buf:
3063         dma_free_coherent(adev->dev, usbc_pd_fw->size, cpu_addr, dma_addr);
3064         release_firmware(usbc_pd_fw);
3065
3066 fail:
3067         if (ret) {
3068                 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3069                 return ret;
3070         }
3071
3072         return count;
3073 }
3074
3075 static DEVICE_ATTR(usbc_pd_fw, S_IRUGO | S_IWUSR,
3076                    psp_usbc_pd_fw_sysfs_read,
3077                    psp_usbc_pd_fw_sysfs_write);
3078
3079
3080
3081 const struct amd_ip_funcs psp_ip_funcs = {
3082         .name = "psp",
3083         .early_init = psp_early_init,
3084         .late_init = NULL,
3085         .sw_init = psp_sw_init,
3086         .sw_fini = psp_sw_fini,
3087         .hw_init = psp_hw_init,
3088         .hw_fini = psp_hw_fini,
3089         .suspend = psp_suspend,
3090         .resume = psp_resume,
3091         .is_idle = NULL,
3092         .check_soft_reset = NULL,
3093         .wait_for_idle = NULL,
3094         .soft_reset = NULL,
3095         .set_clockgating_state = psp_set_clockgating_state,
3096         .set_powergating_state = psp_set_powergating_state,
3097 };
3098
3099 static int psp_sysfs_init(struct amdgpu_device *adev)
3100 {
3101         int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);
3102
3103         if (ret)
3104                 DRM_ERROR("Failed to create USBC PD FW control file!");
3105
3106         return ret;
3107 }
3108
3109 static void psp_sysfs_fini(struct amdgpu_device *adev)
3110 {
3111         device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
3112 }
3113
3114 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
3115 {
3116         .type = AMD_IP_BLOCK_TYPE_PSP,
3117         .major = 3,
3118         .minor = 1,
3119         .rev = 0,
3120         .funcs = &psp_ip_funcs,
3121 };
3122
3123 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
3124 {
3125         .type = AMD_IP_BLOCK_TYPE_PSP,
3126         .major = 10,
3127         .minor = 0,
3128         .rev = 0,
3129         .funcs = &psp_ip_funcs,
3130 };
3131
3132 const struct amdgpu_ip_block_version psp_v11_0_ip_block =
3133 {
3134         .type = AMD_IP_BLOCK_TYPE_PSP,
3135         .major = 11,
3136         .minor = 0,
3137         .rev = 0,
3138         .funcs = &psp_ip_funcs,
3139 };
3140
3141 const struct amdgpu_ip_block_version psp_v12_0_ip_block =
3142 {
3143         .type = AMD_IP_BLOCK_TYPE_PSP,
3144         .major = 12,
3145         .minor = 0,
3146         .rev = 0,
3147         .funcs = &psp_ip_funcs,
3148 };
3149
3150 const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3151         .type = AMD_IP_BLOCK_TYPE_PSP,
3152         .major = 13,
3153         .minor = 0,
3154         .rev = 0,
3155         .funcs = &psp_ip_funcs,
3156 };