2 * Marvell 88E6xxx Switch Global 2 Scratch & Misc Registers support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2017 National Instruments
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
18 /* Offset 0x1A: Scratch and Misc. Register */
19 static int mv88e6xxx_g2_scratch_read(struct mv88e6xxx_chip *chip, int reg,
25 err = mv88e6xxx_g2_write(chip, MV88E6XXX_G2_SCRATCH_MISC_MISC,
30 err = mv88e6xxx_g2_read(chip, MV88E6XXX_G2_SCRATCH_MISC_MISC, &value);
34 *data = (value & MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK);
39 static int mv88e6xxx_g2_scratch_write(struct mv88e6xxx_chip *chip, int reg,
42 u16 value = (reg << 8) | data;
44 return mv88e6xxx_g2_update(chip, MV88E6XXX_G2_SCRATCH_MISC_MISC, value);
48 * mv88e6xxx_g2_scratch_gpio_get_bit - get a bit
49 * @chip: chip private data
53 static int mv88e6xxx_g2_scratch_get_bit(struct mv88e6xxx_chip *chip,
54 int base_reg, unsigned int offset,
57 int reg = base_reg + (offset / 8);
58 u8 mask = (1 << (offset & 0x7));
62 err = mv88e6xxx_g2_scratch_read(chip, reg, &val);
66 *set = !!(mask & val);
72 * mv88e6xxx_g2_scratch_gpio_set_bit - set (or clear) a bit
73 * @chip: chip private data
75 * @set: set if true, clear if false
77 * Helper function for dealing with the direction and data registers.
79 static int mv88e6xxx_g2_scratch_set_bit(struct mv88e6xxx_chip *chip,
80 int base_reg, unsigned int offset,
83 int reg = base_reg + (offset / 8);
84 u8 mask = (1 << (offset & 0x7));
88 err = mv88e6xxx_g2_scratch_read(chip, reg, &val);
97 return mv88e6xxx_g2_scratch_write(chip, reg, val);
101 * mv88e6352_g2_scratch_gpio_get_data - get data on gpio pin
102 * @chip: chip private data
105 * Return: 0 for low, 1 for high, negative error
107 static int mv88e6352_g2_scratch_gpio_get_data(struct mv88e6xxx_chip *chip,
113 err = mv88e6xxx_g2_scratch_get_bit(chip,
114 MV88E6352_G2_SCRATCH_GPIO_DATA0,
123 * mv88e6352_g2_scratch_gpio_set_data - set data on gpio pin
124 * @chip: chip private data
126 * @value: value to set
128 static int mv88e6352_g2_scratch_gpio_set_data(struct mv88e6xxx_chip *chip,
129 unsigned int pin, int value)
131 u8 mask = (1 << (pin & 0x7));
132 int offset = (pin / 8);
135 reg = MV88E6352_G2_SCRATCH_GPIO_DATA0 + offset;
138 chip->gpio_data[offset] |= mask;
140 chip->gpio_data[offset] &= ~mask;
142 return mv88e6xxx_g2_scratch_write(chip, reg, chip->gpio_data[offset]);
146 * mv88e6352_g2_scratch_gpio_get_dir - get direction of gpio pin
147 * @chip: chip private data
150 * Return: 0 for output, 1 for input (same as GPIOF_DIR_XXX).
152 static int mv88e6352_g2_scratch_gpio_get_dir(struct mv88e6xxx_chip *chip,
158 err = mv88e6xxx_g2_scratch_get_bit(chip,
159 MV88E6352_G2_SCRATCH_GPIO_DIR0,
168 * mv88e6352_g2_scratch_gpio_set_dir - set direction of gpio pin
169 * @chip: chip private data
172 static int mv88e6352_g2_scratch_gpio_set_dir(struct mv88e6xxx_chip *chip,
173 unsigned int pin, bool input)
175 int value = (input ? MV88E6352_G2_SCRATCH_GPIO_DIR_IN :
176 MV88E6352_G2_SCRATCH_GPIO_DIR_OUT);
178 return mv88e6xxx_g2_scratch_set_bit(chip,
179 MV88E6352_G2_SCRATCH_GPIO_DIR0,
184 * mv88e6352_g2_scratch_gpio_get_pctl - get pin control setting
185 * @chip: chip private data
187 * @func: function number
189 * Note that the function numbers themselves may vary by chipset.
191 static int mv88e6352_g2_scratch_gpio_get_pctl(struct mv88e6xxx_chip *chip,
192 unsigned int pin, int *func)
194 int reg = MV88E6352_G2_SCRATCH_GPIO_PCTL0 + (pin / 2);
195 int offset = (pin & 0x1) ? 4 : 0;
196 u8 mask = (0x7 << offset);
200 err = mv88e6xxx_g2_scratch_read(chip, reg, &val);
204 *func = (val & mask) >> offset;
210 * mv88e6352_g2_scratch_gpio_set_pctl - set pin control setting
211 * @chip: chip private data
213 * @func: function number
215 static int mv88e6352_g2_scratch_gpio_set_pctl(struct mv88e6xxx_chip *chip,
216 unsigned int pin, int func)
218 int reg = MV88E6352_G2_SCRATCH_GPIO_PCTL0 + (pin / 2);
219 int offset = (pin & 0x1) ? 4 : 0;
220 u8 mask = (0x7 << offset);
224 err = mv88e6xxx_g2_scratch_read(chip, reg, &val);
228 val = (val & ~mask) | ((func & mask) << offset);
230 return mv88e6xxx_g2_scratch_write(chip, reg, val);
233 const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops = {
234 .get_data = mv88e6352_g2_scratch_gpio_get_data,
235 .set_data = mv88e6352_g2_scratch_gpio_set_data,
236 .get_dir = mv88e6352_g2_scratch_gpio_get_dir,
237 .set_dir = mv88e6352_g2_scratch_gpio_set_dir,
238 .get_pctl = mv88e6352_g2_scratch_gpio_get_pctl,
239 .set_pctl = mv88e6352_g2_scratch_gpio_set_pctl,
243 * mv88e6xxx_g2_gpio_set_smi - set gpio muxing for external smi
244 * @chip: chip private data
245 * @external: set mux for external smi, or free for gpio usage
247 * Some mv88e6xxx models have GPIO pins that may be configured as
248 * an external SMI interface, or they may be made free for other
251 int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
254 int misc_cfg = MV88E6352_G2_SCRATCH_MISC_CFG;
255 int config_data1 = MV88E6352_G2_SCRATCH_CONFIG_DATA1;
256 int config_data2 = MV88E6352_G2_SCRATCH_CONFIG_DATA2;
262 err = mv88e6xxx_g2_scratch_read(chip, config_data2, &val);
266 p0_mode = val & MV88E6352_G2_SCRATCH_CONFIG_DATA2_P0_MODE_MASK;
268 if (p0_mode == 0x01 || p0_mode == 0x02)
271 err = mv88e6xxx_g2_scratch_read(chip, config_data1, &val);
275 no_cpu = !!(val & MV88E6352_G2_SCRATCH_CONFIG_DATA1_NO_CPU);
277 err = mv88e6xxx_g2_scratch_read(chip, misc_cfg, &val);
281 /* NO_CPU being 0 inverts the meaning of the bit */
283 external = !external;
286 val |= MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI;
288 val &= ~MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI;
290 return mv88e6xxx_g2_scratch_write(chip, misc_cfg, val);