2 * Copyright © 2012-2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 #include <linux/pm_runtime.h>
30 #include <linux/vgaarb.h>
33 #include "intel_drv.h"
38 * The i915 driver supports dynamic enabling and disabling of entire hardware
39 * blocks at runtime. This is especially important on the display side where
40 * software is supposed to control many power gates manually on recent hardware,
41 * since on the GT side a lot of the power management is done by the hardware.
42 * But even there some manual control at the device level is required.
44 * Since i915 supports a diverse set of platforms with a unified codebase and
45 * hardware engineers just love to shuffle functionality around between power
46 * domains there's a sizeable amount of indirection required. This file provides
47 * generic functions to the driver for grabbing and releasing references for
48 * abstract power domains. It then maps those to the actual power wells
49 * present for a given platform.
52 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
54 i < (power_domains)->power_well_count && \
55 ((power_well) = &(power_domains)->power_wells[i]); \
57 for_each_if ((power_well)->domains & (domain_mask))
59 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
60 for (i = (power_domains)->power_well_count - 1; \
61 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
63 for_each_if ((power_well)->domains & (domain_mask))
65 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
69 intel_display_power_domain_str(enum intel_display_power_domain domain)
72 case POWER_DOMAIN_PIPE_A:
74 case POWER_DOMAIN_PIPE_B:
76 case POWER_DOMAIN_PIPE_C:
78 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
79 return "PIPE_A_PANEL_FITTER";
80 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
81 return "PIPE_B_PANEL_FITTER";
82 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
83 return "PIPE_C_PANEL_FITTER";
84 case POWER_DOMAIN_TRANSCODER_A:
85 return "TRANSCODER_A";
86 case POWER_DOMAIN_TRANSCODER_B:
87 return "TRANSCODER_B";
88 case POWER_DOMAIN_TRANSCODER_C:
89 return "TRANSCODER_C";
90 case POWER_DOMAIN_TRANSCODER_EDP:
91 return "TRANSCODER_EDP";
92 case POWER_DOMAIN_TRANSCODER_DSI_A:
93 return "TRANSCODER_DSI_A";
94 case POWER_DOMAIN_TRANSCODER_DSI_C:
95 return "TRANSCODER_DSI_C";
96 case POWER_DOMAIN_PORT_DDI_A_LANES:
97 return "PORT_DDI_A_LANES";
98 case POWER_DOMAIN_PORT_DDI_B_LANES:
99 return "PORT_DDI_B_LANES";
100 case POWER_DOMAIN_PORT_DDI_C_LANES:
101 return "PORT_DDI_C_LANES";
102 case POWER_DOMAIN_PORT_DDI_D_LANES:
103 return "PORT_DDI_D_LANES";
104 case POWER_DOMAIN_PORT_DDI_E_LANES:
105 return "PORT_DDI_E_LANES";
106 case POWER_DOMAIN_PORT_DSI:
108 case POWER_DOMAIN_PORT_CRT:
110 case POWER_DOMAIN_PORT_OTHER:
112 case POWER_DOMAIN_VGA:
114 case POWER_DOMAIN_AUDIO:
116 case POWER_DOMAIN_PLLS:
118 case POWER_DOMAIN_AUX_A:
120 case POWER_DOMAIN_AUX_B:
122 case POWER_DOMAIN_AUX_C:
124 case POWER_DOMAIN_AUX_D:
126 case POWER_DOMAIN_GMBUS:
128 case POWER_DOMAIN_INIT:
130 case POWER_DOMAIN_MODESET:
133 MISSING_CASE(domain);
138 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
139 struct i915_power_well *power_well)
141 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
142 power_well->ops->enable(dev_priv, power_well);
143 power_well->hw_enabled = true;
146 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
147 struct i915_power_well *power_well)
149 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
150 power_well->hw_enabled = false;
151 power_well->ops->disable(dev_priv, power_well);
155 * We should only use the power well if we explicitly asked the hardware to
156 * enable it, so check if it's enabled and also check if we've requested it to
159 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
160 struct i915_power_well *power_well)
162 return I915_READ(HSW_PWR_WELL_DRIVER) ==
163 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
167 * __intel_display_power_is_enabled - unlocked check for a power domain
168 * @dev_priv: i915 device instance
169 * @domain: power domain to check
171 * This is the unlocked version of intel_display_power_is_enabled() and should
172 * only be used from error capture and recovery code where deadlocks are
176 * True when the power domain is enabled, false otherwise.
178 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
179 enum intel_display_power_domain domain)
181 struct i915_power_domains *power_domains;
182 struct i915_power_well *power_well;
186 if (dev_priv->pm.suspended)
189 power_domains = &dev_priv->power_domains;
193 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
194 if (power_well->always_on)
197 if (!power_well->hw_enabled) {
207 * intel_display_power_is_enabled - check for a power domain
208 * @dev_priv: i915 device instance
209 * @domain: power domain to check
211 * This function can be used to check the hw power domain state. It is mostly
212 * used in hardware state readout functions. Everywhere else code should rely
213 * upon explicit power domain reference counting to ensure that the hardware
214 * block is powered up before accessing it.
216 * Callers must hold the relevant modesetting locks to ensure that concurrent
217 * threads can't disable the power well while the caller tries to read a few
221 * True when the power domain is enabled, false otherwise.
223 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
224 enum intel_display_power_domain domain)
226 struct i915_power_domains *power_domains;
229 power_domains = &dev_priv->power_domains;
231 mutex_lock(&power_domains->lock);
232 ret = __intel_display_power_is_enabled(dev_priv, domain);
233 mutex_unlock(&power_domains->lock);
239 * intel_display_set_init_power - set the initial power domain state
240 * @dev_priv: i915 device instance
241 * @enable: whether to enable or disable the initial power domain state
243 * For simplicity our driver load/unload and system suspend/resume code assumes
244 * that all power domains are always enabled. This functions controls the state
245 * of this little hack. While the initial power domain state is enabled runtime
246 * pm is effectively disabled.
248 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
251 if (dev_priv->power_domains.init_power_on == enable)
255 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
257 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
259 dev_priv->power_domains.init_power_on = enable;
263 * Starting with Haswell, we have a "Power Down Well" that can be turned off
264 * when not needed anymore. We have 4 registers that can request the power well
265 * to be enabled, and it will only be disabled if none of the registers is
266 * requesting it to be enabled.
268 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
270 struct drm_device *dev = dev_priv->dev;
273 * After we re-enable the power well, if we touch VGA register 0x3d5
274 * we'll get unclaimed register interrupts. This stops after we write
275 * anything to the VGA MSR register. The vgacon module uses this
276 * register all the time, so if we unbind our driver and, as a
277 * consequence, bind vgacon, we'll get stuck in an infinite loop at
278 * console_unlock(). So make here we touch the VGA MSR register, making
279 * sure vgacon can keep working normally without triggering interrupts
280 * and error messages.
282 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
283 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
284 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
286 if (IS_BROADWELL(dev))
287 gen8_irq_power_well_post_enable(dev_priv,
288 1 << PIPE_C | 1 << PIPE_B);
291 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv)
293 if (IS_BROADWELL(dev_priv))
294 gen8_irq_power_well_pre_disable(dev_priv,
295 1 << PIPE_C | 1 << PIPE_B);
298 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
299 struct i915_power_well *power_well)
301 struct drm_device *dev = dev_priv->dev;
304 * After we re-enable the power well, if we touch VGA register 0x3d5
305 * we'll get unclaimed register interrupts. This stops after we write
306 * anything to the VGA MSR register. The vgacon module uses this
307 * register all the time, so if we unbind our driver and, as a
308 * consequence, bind vgacon, we'll get stuck in an infinite loop at
309 * console_unlock(). So make here we touch the VGA MSR register, making
310 * sure vgacon can keep working normally without triggering interrupts
311 * and error messages.
313 if (power_well->data == SKL_DISP_PW_2) {
314 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
315 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
316 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
318 gen8_irq_power_well_post_enable(dev_priv,
319 1 << PIPE_C | 1 << PIPE_B);
323 static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
324 struct i915_power_well *power_well)
326 if (power_well->data == SKL_DISP_PW_2)
327 gen8_irq_power_well_pre_disable(dev_priv,
328 1 << PIPE_C | 1 << PIPE_B);
331 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
332 struct i915_power_well *power_well, bool enable)
334 bool is_enabled, enable_requested;
337 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
338 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
339 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
342 if (!enable_requested)
343 I915_WRITE(HSW_PWR_WELL_DRIVER,
344 HSW_PWR_WELL_ENABLE_REQUEST);
347 DRM_DEBUG_KMS("Enabling power well\n");
348 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
349 HSW_PWR_WELL_STATE_ENABLED), 20))
350 DRM_ERROR("Timeout enabling power well\n");
351 hsw_power_well_post_enable(dev_priv);
355 if (enable_requested) {
356 hsw_power_well_pre_disable(dev_priv);
357 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
358 POSTING_READ(HSW_PWR_WELL_DRIVER);
359 DRM_DEBUG_KMS("Requesting to disable the power well\n");
364 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
365 BIT(POWER_DOMAIN_TRANSCODER_A) | \
366 BIT(POWER_DOMAIN_PIPE_B) | \
367 BIT(POWER_DOMAIN_TRANSCODER_B) | \
368 BIT(POWER_DOMAIN_PIPE_C) | \
369 BIT(POWER_DOMAIN_TRANSCODER_C) | \
370 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
371 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
372 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
373 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
374 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
375 BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \
376 BIT(POWER_DOMAIN_AUX_B) | \
377 BIT(POWER_DOMAIN_AUX_C) | \
378 BIT(POWER_DOMAIN_AUX_D) | \
379 BIT(POWER_DOMAIN_AUDIO) | \
380 BIT(POWER_DOMAIN_VGA) | \
381 BIT(POWER_DOMAIN_INIT))
382 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \
383 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
384 BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \
385 BIT(POWER_DOMAIN_INIT))
386 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \
387 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
388 BIT(POWER_DOMAIN_INIT))
389 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \
390 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
391 BIT(POWER_DOMAIN_INIT))
392 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
393 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
394 BIT(POWER_DOMAIN_INIT))
395 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
396 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
397 BIT(POWER_DOMAIN_MODESET) | \
398 BIT(POWER_DOMAIN_AUX_A) | \
399 BIT(POWER_DOMAIN_INIT))
400 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
401 (POWER_DOMAIN_MASK & ~( \
402 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
403 SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) | \
404 BIT(POWER_DOMAIN_INIT))
406 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
407 BIT(POWER_DOMAIN_TRANSCODER_A) | \
408 BIT(POWER_DOMAIN_PIPE_B) | \
409 BIT(POWER_DOMAIN_TRANSCODER_B) | \
410 BIT(POWER_DOMAIN_PIPE_C) | \
411 BIT(POWER_DOMAIN_TRANSCODER_C) | \
412 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
413 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
414 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
415 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
416 BIT(POWER_DOMAIN_AUX_B) | \
417 BIT(POWER_DOMAIN_AUX_C) | \
418 BIT(POWER_DOMAIN_AUDIO) | \
419 BIT(POWER_DOMAIN_VGA) | \
420 BIT(POWER_DOMAIN_GMBUS) | \
421 BIT(POWER_DOMAIN_INIT))
422 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
423 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
424 BIT(POWER_DOMAIN_MODESET) | \
425 BIT(POWER_DOMAIN_AUX_A) | \
426 BIT(POWER_DOMAIN_INIT))
427 #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
428 (POWER_DOMAIN_MASK & ~( \
429 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
430 BIT(POWER_DOMAIN_INIT))
432 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
434 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
435 "DC9 already programmed to be enabled.\n");
436 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
437 "DC5 still not disabled to enable DC9.\n");
438 WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
439 WARN_ONCE(intel_irqs_enabled(dev_priv),
440 "Interrupts not disabled yet.\n");
443 * TODO: check for the following to verify the conditions to enter DC9
444 * state are satisfied:
445 * 1] Check relevant display engine registers to verify if mode set
446 * disable sequence was followed.
447 * 2] Check if display uninitialize sequence is initialized.
451 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
453 WARN_ONCE(intel_irqs_enabled(dev_priv),
454 "Interrupts not disabled yet.\n");
455 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
456 "DC5 still not disabled.\n");
459 * TODO: check for the following to verify DC9 state was indeed
460 * entered before programming to disable it:
461 * 1] Check relevant display engine registers to verify if mode
462 * set disable sequence was followed.
463 * 2] Check if display uninitialize sequence is initialized.
467 static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
474 I915_WRITE(DC_STATE_EN, state);
476 /* It has been observed that disabling the dc6 state sometimes
477 * doesn't stick and dmc keeps returning old value. Make sure
478 * the write really sticks enough times and also force rewrite until
479 * we are confident that state is exactly what we want.
482 v = I915_READ(DC_STATE_EN);
485 I915_WRITE(DC_STATE_EN, state);
488 } else if (rereads++ > 5) {
492 } while (rewrites < 100);
495 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n",
498 /* Most of the times we need one retry, avoid spam */
500 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
504 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
509 mask = DC_STATE_EN_UPTO_DC5;
510 if (IS_BROXTON(dev_priv))
511 mask |= DC_STATE_EN_DC9;
513 mask |= DC_STATE_EN_UPTO_DC6;
515 if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
516 state &= dev_priv->csr.allowed_dc_mask;
518 val = I915_READ(DC_STATE_EN);
519 DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
522 /* Check if DMC is ignoring our DC state requests */
523 if ((val & mask) != dev_priv->csr.dc_state)
524 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
525 dev_priv->csr.dc_state, val & mask);
530 gen9_write_dc_state(dev_priv, val);
532 dev_priv->csr.dc_state = val & mask;
535 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
537 assert_can_enable_dc9(dev_priv);
539 DRM_DEBUG_KMS("Enabling DC9\n");
541 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
544 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
546 assert_can_disable_dc9(dev_priv);
548 DRM_DEBUG_KMS("Disabling DC9\n");
550 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
553 static void assert_csr_loaded(struct drm_i915_private *dev_priv)
555 WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
556 "CSR program storage start is NULL\n");
557 WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
558 WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
561 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
563 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
566 WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
568 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
569 "DC5 already programmed to be enabled.\n");
570 assert_rpm_wakelock_held(dev_priv);
572 assert_csr_loaded(dev_priv);
575 static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
577 assert_can_enable_dc5(dev_priv);
579 DRM_DEBUG_KMS("Enabling DC5\n");
581 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
584 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
586 WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
587 "Backlight is not disabled.\n");
588 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
589 "DC6 already programmed to be enabled.\n");
591 assert_csr_loaded(dev_priv);
594 void skl_enable_dc6(struct drm_i915_private *dev_priv)
596 assert_can_enable_dc6(dev_priv);
598 DRM_DEBUG_KMS("Enabling DC6\n");
600 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
604 void skl_disable_dc6(struct drm_i915_private *dev_priv)
606 DRM_DEBUG_KMS("Disabling DC6\n");
608 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
612 gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv,
613 struct i915_power_well *power_well)
615 enum skl_disp_power_wells power_well_id = power_well->data;
619 mask = SKL_POWER_WELL_REQ(power_well_id);
621 val = I915_READ(HSW_PWR_WELL_KVMR);
622 if (WARN_ONCE(val & mask, "Clearing unexpected KVMR request for %s\n",
624 I915_WRITE(HSW_PWR_WELL_KVMR, val & ~mask);
626 val = I915_READ(HSW_PWR_WELL_BIOS);
627 val |= I915_READ(HSW_PWR_WELL_DEBUG);
633 * DMC is known to force on the request bits for power well 1 on SKL
634 * and BXT and the misc IO power well on SKL but we don't expect any
635 * other request bits to be set, so WARN for those.
637 if (power_well_id == SKL_DISP_PW_1 ||
638 (IS_SKYLAKE(dev_priv) && power_well_id == SKL_DISP_PW_MISC_IO))
639 DRM_DEBUG_DRIVER("Clearing auxiliary requests for %s forced on "
640 "by DMC\n", power_well->name);
642 WARN_ONCE(1, "Clearing unexpected auxiliary requests for %s\n",
645 I915_WRITE(HSW_PWR_WELL_BIOS, val & ~mask);
646 I915_WRITE(HSW_PWR_WELL_DEBUG, val & ~mask);
649 static void skl_set_power_well(struct drm_i915_private *dev_priv,
650 struct i915_power_well *power_well, bool enable)
652 uint32_t tmp, fuse_status;
653 uint32_t req_mask, state_mask;
654 bool is_enabled, enable_requested, check_fuse_status = false;
656 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
657 fuse_status = I915_READ(SKL_FUSE_STATUS);
659 switch (power_well->data) {
661 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
662 SKL_FUSE_PG0_DIST_STATUS), 1)) {
663 DRM_ERROR("PG0 not enabled\n");
668 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
669 DRM_ERROR("PG1 in disabled state\n");
673 case SKL_DISP_PW_DDI_A_E:
674 case SKL_DISP_PW_DDI_B:
675 case SKL_DISP_PW_DDI_C:
676 case SKL_DISP_PW_DDI_D:
677 case SKL_DISP_PW_MISC_IO:
680 WARN(1, "Unknown power well %lu\n", power_well->data);
684 req_mask = SKL_POWER_WELL_REQ(power_well->data);
685 enable_requested = tmp & req_mask;
686 state_mask = SKL_POWER_WELL_STATE(power_well->data);
687 is_enabled = tmp & state_mask;
689 if (!enable && enable_requested)
690 skl_power_well_pre_disable(dev_priv, power_well);
693 if (!enable_requested) {
694 WARN((tmp & state_mask) &&
695 !I915_READ(HSW_PWR_WELL_BIOS),
696 "Invalid for power well status to be enabled, unless done by the BIOS, \
697 when request is to disable!\n");
698 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
702 DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
703 check_fuse_status = true;
706 if (enable_requested) {
707 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
708 POSTING_READ(HSW_PWR_WELL_DRIVER);
709 DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
712 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
713 gen9_sanitize_power_well_requests(dev_priv, power_well);
716 if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable,
718 DRM_ERROR("%s %s timeout\n",
719 power_well->name, enable ? "enable" : "disable");
721 if (check_fuse_status) {
722 if (power_well->data == SKL_DISP_PW_1) {
723 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
724 SKL_FUSE_PG1_DIST_STATUS), 1))
725 DRM_ERROR("PG1 distributing status timeout\n");
726 } else if (power_well->data == SKL_DISP_PW_2) {
727 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
728 SKL_FUSE_PG2_DIST_STATUS), 1))
729 DRM_ERROR("PG2 distributing status timeout\n");
733 if (enable && !is_enabled)
734 skl_power_well_post_enable(dev_priv, power_well);
737 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
738 struct i915_power_well *power_well)
740 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
743 * We're taking over the BIOS, so clear any requests made by it since
744 * the driver is in charge now.
746 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
747 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
750 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
751 struct i915_power_well *power_well)
753 hsw_set_power_well(dev_priv, power_well, true);
756 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
757 struct i915_power_well *power_well)
759 hsw_set_power_well(dev_priv, power_well, false);
762 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
763 struct i915_power_well *power_well)
765 uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
766 SKL_POWER_WELL_STATE(power_well->data);
768 return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
771 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
772 struct i915_power_well *power_well)
774 skl_set_power_well(dev_priv, power_well, power_well->count > 0);
776 /* Clear any request made by BIOS as driver is taking over */
777 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
780 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
781 struct i915_power_well *power_well)
783 skl_set_power_well(dev_priv, power_well, true);
786 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
787 struct i915_power_well *power_well)
789 skl_set_power_well(dev_priv, power_well, false);
792 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
793 struct i915_power_well *power_well)
795 return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
798 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
799 struct i915_power_well *power_well)
801 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
804 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
805 struct i915_power_well *power_well)
807 if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
808 skl_enable_dc6(dev_priv);
809 else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
810 gen9_enable_dc5(dev_priv);
813 static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
814 struct i915_power_well *power_well)
816 if (power_well->count > 0)
817 gen9_dc_off_power_well_enable(dev_priv, power_well);
819 gen9_dc_off_power_well_disable(dev_priv, power_well);
822 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
823 struct i915_power_well *power_well)
827 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
828 struct i915_power_well *power_well)
833 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
834 struct i915_power_well *power_well, bool enable)
836 enum punit_power_well power_well_id = power_well->data;
841 mask = PUNIT_PWRGT_MASK(power_well_id);
842 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
843 PUNIT_PWRGT_PWR_GATE(power_well_id);
845 mutex_lock(&dev_priv->rps.hw_lock);
848 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
853 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
856 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
858 if (wait_for(COND, 100))
859 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
861 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
866 mutex_unlock(&dev_priv->rps.hw_lock);
869 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
870 struct i915_power_well *power_well)
872 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
875 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
876 struct i915_power_well *power_well)
878 vlv_set_power_well(dev_priv, power_well, true);
881 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
882 struct i915_power_well *power_well)
884 vlv_set_power_well(dev_priv, power_well, false);
887 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
888 struct i915_power_well *power_well)
890 int power_well_id = power_well->data;
891 bool enabled = false;
896 mask = PUNIT_PWRGT_MASK(power_well_id);
897 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
899 mutex_lock(&dev_priv->rps.hw_lock);
901 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
903 * We only ever set the power-on and power-gate states, anything
904 * else is unexpected.
906 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
907 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
912 * A transient state at this point would mean some unexpected party
913 * is poking at the power controls too.
915 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
916 WARN_ON(ctrl != state);
918 mutex_unlock(&dev_priv->rps.hw_lock);
923 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
925 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
928 * Disable trickle feed and enable pnd deadline calculation
930 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
931 I915_WRITE(CBR1_VLV, 0);
934 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
939 * Enable the CRI clock source so we can get at the
940 * display and the reference clock for VGA
941 * hotplug / manual detection. Supposedly DSI also
942 * needs the ref clock up and running.
944 * CHV DPLL B/C have some issues if VGA mode is enabled.
946 for_each_pipe(dev_priv->dev, pipe) {
947 u32 val = I915_READ(DPLL(pipe));
949 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
951 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
953 I915_WRITE(DPLL(pipe), val);
956 vlv_init_display_clock_gating(dev_priv);
958 spin_lock_irq(&dev_priv->irq_lock);
959 valleyview_enable_display_irqs(dev_priv);
960 spin_unlock_irq(&dev_priv->irq_lock);
963 * During driver initialization/resume we can avoid restoring the
964 * part of the HW/SW state that will be inited anyway explicitly.
966 if (dev_priv->power_domains.initializing)
969 intel_hpd_init(dev_priv);
971 i915_redisable_vga_power_on(dev_priv->dev);
974 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
976 spin_lock_irq(&dev_priv->irq_lock);
977 valleyview_disable_display_irqs(dev_priv);
978 spin_unlock_irq(&dev_priv->irq_lock);
980 /* make sure we're done processing display irqs */
981 synchronize_irq(dev_priv->dev->irq);
983 vlv_power_sequencer_reset(dev_priv);
986 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
987 struct i915_power_well *power_well)
989 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
991 vlv_set_power_well(dev_priv, power_well, true);
993 vlv_display_power_well_init(dev_priv);
996 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
997 struct i915_power_well *power_well)
999 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
1001 vlv_display_power_well_deinit(dev_priv);
1003 vlv_set_power_well(dev_priv, power_well, false);
1006 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1007 struct i915_power_well *power_well)
1009 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1011 /* since ref/cri clock was enabled */
1012 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1014 vlv_set_power_well(dev_priv, power_well, true);
1017 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1018 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1019 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1020 * b. The other bits such as sfr settings / modesel may all
1023 * This should only be done on init and resume from S3 with
1024 * both PLLs disabled, or we risk losing DPIO and PLL
1027 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1030 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1031 struct i915_power_well *power_well)
1035 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1037 for_each_pipe(dev_priv, pipe)
1038 assert_pll_disabled(dev_priv, pipe);
1040 /* Assert common reset */
1041 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
1043 vlv_set_power_well(dev_priv, power_well, false);
1046 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
1048 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
1051 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1054 for (i = 0; i < power_domains->power_well_count; i++) {
1055 struct i915_power_well *power_well;
1057 power_well = &power_domains->power_wells[i];
1058 if (power_well->data == power_well_id)
1065 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1067 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1069 struct i915_power_well *cmn_bc =
1070 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1071 struct i915_power_well *cmn_d =
1072 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1073 u32 phy_control = dev_priv->chv_phy_control;
1075 u32 phy_status_mask = 0xffffffff;
1079 * The BIOS can leave the PHY is some weird state
1080 * where it doesn't fully power down some parts.
1081 * Disable the asserts until the PHY has been fully
1082 * reset (ie. the power well has been disabled at
1085 if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1086 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1087 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1088 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1089 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1090 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1091 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1093 if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1094 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1095 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1096 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1098 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1099 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1101 /* this assumes override is only used to enable lanes */
1102 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1103 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1105 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1106 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1108 /* CL1 is on whenever anything is on in either channel */
1109 if (BITS_SET(phy_control,
1110 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1111 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1112 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1115 * The DPLLB check accounts for the pipe B + port A usage
1116 * with CL2 powered up but all the lanes in the second channel
1119 if (BITS_SET(phy_control,
1120 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1121 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1122 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1124 if (BITS_SET(phy_control,
1125 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1126 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1127 if (BITS_SET(phy_control,
1128 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1129 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1131 if (BITS_SET(phy_control,
1132 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1133 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1134 if (BITS_SET(phy_control,
1135 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1136 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1139 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1140 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1142 /* this assumes override is only used to enable lanes */
1143 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1144 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1146 if (BITS_SET(phy_control,
1147 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1148 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1150 if (BITS_SET(phy_control,
1151 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1152 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1153 if (BITS_SET(phy_control,
1154 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1155 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1158 phy_status &= phy_status_mask;
1161 * The PHY may be busy with some initial calibration and whatnot,
1162 * so the power state can take a while to actually change.
1164 if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10))
1165 WARN(phy_status != tmp,
1166 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1167 tmp, phy_status, dev_priv->chv_phy_control);
1172 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1173 struct i915_power_well *power_well)
1179 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1180 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1182 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1190 /* since ref/cri clock was enabled */
1191 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1192 vlv_set_power_well(dev_priv, power_well, true);
1194 /* Poll for phypwrgood signal */
1195 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
1196 DRM_ERROR("Display PHY %d is not power up\n", phy);
1198 mutex_lock(&dev_priv->sb_lock);
1200 /* Enable dynamic power down */
1201 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1202 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1203 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1204 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1206 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1207 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1208 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1209 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1212 * Force the non-existing CL2 off. BXT does this
1213 * too, so maybe it saves some power even though
1214 * CL2 doesn't exist?
1216 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1217 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1218 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1221 mutex_unlock(&dev_priv->sb_lock);
1223 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1224 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1226 DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1227 phy, dev_priv->chv_phy_control);
1229 assert_chv_phy_status(dev_priv);
1232 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1233 struct i915_power_well *power_well)
1237 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1238 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1240 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1242 assert_pll_disabled(dev_priv, PIPE_A);
1243 assert_pll_disabled(dev_priv, PIPE_B);
1246 assert_pll_disabled(dev_priv, PIPE_C);
1249 dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1250 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1252 vlv_set_power_well(dev_priv, power_well, false);
1254 DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1255 phy, dev_priv->chv_phy_control);
1257 /* PHY is fully reset now, so we can enable the PHY state asserts */
1258 dev_priv->chv_phy_assert[phy] = true;
1260 assert_chv_phy_status(dev_priv);
1263 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1264 enum dpio_channel ch, bool override, unsigned int mask)
1266 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1267 u32 reg, val, expected, actual;
1270 * The BIOS can leave the PHY is some weird state
1271 * where it doesn't fully power down some parts.
1272 * Disable the asserts until the PHY has been fully
1273 * reset (ie. the power well has been disabled at
1276 if (!dev_priv->chv_phy_assert[phy])
1280 reg = _CHV_CMN_DW0_CH0;
1282 reg = _CHV_CMN_DW6_CH1;
1284 mutex_lock(&dev_priv->sb_lock);
1285 val = vlv_dpio_read(dev_priv, pipe, reg);
1286 mutex_unlock(&dev_priv->sb_lock);
1289 * This assumes !override is only used when the port is disabled.
1290 * All lanes should power down even without the override when
1291 * the port is disabled.
1293 if (!override || mask == 0xf) {
1294 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1296 * If CH1 common lane is not active anymore
1297 * (eg. for pipe B DPLL) the entire channel will
1298 * shut down, which causes the common lane registers
1299 * to read as 0. That means we can't actually check
1300 * the lane power down status bits, but as the entire
1301 * register reads as 0 it's a good indication that the
1302 * channel is indeed entirely powered down.
1304 if (ch == DPIO_CH1 && val == 0)
1306 } else if (mask != 0x0) {
1307 expected = DPIO_ANYDL_POWERDOWN;
1313 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1315 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1316 actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1318 WARN(actual != expected,
1319 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1320 !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1321 !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1325 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1326 enum dpio_channel ch, bool override)
1328 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1331 mutex_lock(&power_domains->lock);
1333 was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1335 if (override == was_override)
1339 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1341 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1343 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1345 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1346 phy, ch, dev_priv->chv_phy_control);
1348 assert_chv_phy_status(dev_priv);
1351 mutex_unlock(&power_domains->lock);
1353 return was_override;
1356 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1357 bool override, unsigned int mask)
1359 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1360 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1361 enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1362 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1364 mutex_lock(&power_domains->lock);
1366 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1367 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1370 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1372 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1374 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1376 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1377 phy, ch, mask, dev_priv->chv_phy_control);
1379 assert_chv_phy_status(dev_priv);
1381 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1383 mutex_unlock(&power_domains->lock);
1386 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1387 struct i915_power_well *power_well)
1389 enum pipe pipe = power_well->data;
1393 mutex_lock(&dev_priv->rps.hw_lock);
1395 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1397 * We only ever set the power-on and power-gate states, anything
1398 * else is unexpected.
1400 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1401 enabled = state == DP_SSS_PWR_ON(pipe);
1404 * A transient state at this point would mean some unexpected party
1405 * is poking at the power controls too.
1407 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1408 WARN_ON(ctrl << 16 != state);
1410 mutex_unlock(&dev_priv->rps.hw_lock);
1415 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1416 struct i915_power_well *power_well,
1419 enum pipe pipe = power_well->data;
1423 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1425 mutex_lock(&dev_priv->rps.hw_lock);
1428 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1433 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1434 ctrl &= ~DP_SSC_MASK(pipe);
1435 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1436 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1438 if (wait_for(COND, 100))
1439 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1441 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1446 mutex_unlock(&dev_priv->rps.hw_lock);
1449 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1450 struct i915_power_well *power_well)
1452 WARN_ON_ONCE(power_well->data != PIPE_A);
1454 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1457 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1458 struct i915_power_well *power_well)
1460 WARN_ON_ONCE(power_well->data != PIPE_A);
1462 chv_set_pipe_power_well(dev_priv, power_well, true);
1464 vlv_display_power_well_init(dev_priv);
1467 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1468 struct i915_power_well *power_well)
1470 WARN_ON_ONCE(power_well->data != PIPE_A);
1472 vlv_display_power_well_deinit(dev_priv);
1474 chv_set_pipe_power_well(dev_priv, power_well, false);
1478 __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
1479 enum intel_display_power_domain domain)
1481 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1482 struct i915_power_well *power_well;
1485 for_each_power_well(i, power_well, BIT(domain), power_domains) {
1486 if (!power_well->count++)
1487 intel_power_well_enable(dev_priv, power_well);
1490 power_domains->domain_use_count[domain]++;
1494 * intel_display_power_get - grab a power domain reference
1495 * @dev_priv: i915 device instance
1496 * @domain: power domain to reference
1498 * This function grabs a power domain reference for @domain and ensures that the
1499 * power domain and all its parents are powered up. Therefore users should only
1500 * grab a reference to the innermost power domain they need.
1502 * Any power domain reference obtained by this function must have a symmetric
1503 * call to intel_display_power_put() to release the reference again.
1505 void intel_display_power_get(struct drm_i915_private *dev_priv,
1506 enum intel_display_power_domain domain)
1508 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1510 intel_runtime_pm_get(dev_priv);
1512 mutex_lock(&power_domains->lock);
1514 __intel_display_power_get_domain(dev_priv, domain);
1516 mutex_unlock(&power_domains->lock);
1520 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
1521 * @dev_priv: i915 device instance
1522 * @domain: power domain to reference
1524 * This function grabs a power domain reference for @domain and ensures that the
1525 * power domain and all its parents are powered up. Therefore users should only
1526 * grab a reference to the innermost power domain they need.
1528 * Any power domain reference obtained by this function must have a symmetric
1529 * call to intel_display_power_put() to release the reference again.
1531 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1532 enum intel_display_power_domain domain)
1534 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1537 if (!intel_runtime_pm_get_if_in_use(dev_priv))
1540 mutex_lock(&power_domains->lock);
1542 if (__intel_display_power_is_enabled(dev_priv, domain)) {
1543 __intel_display_power_get_domain(dev_priv, domain);
1549 mutex_unlock(&power_domains->lock);
1552 intel_runtime_pm_put(dev_priv);
1558 * intel_display_power_put - release a power domain reference
1559 * @dev_priv: i915 device instance
1560 * @domain: power domain to reference
1562 * This function drops the power domain reference obtained by
1563 * intel_display_power_get() and might power down the corresponding hardware
1564 * block right away if this is the last reference.
1566 void intel_display_power_put(struct drm_i915_private *dev_priv,
1567 enum intel_display_power_domain domain)
1569 struct i915_power_domains *power_domains;
1570 struct i915_power_well *power_well;
1573 power_domains = &dev_priv->power_domains;
1575 mutex_lock(&power_domains->lock);
1577 WARN(!power_domains->domain_use_count[domain],
1578 "Use count on domain %s is already zero\n",
1579 intel_display_power_domain_str(domain));
1580 power_domains->domain_use_count[domain]--;
1582 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
1583 WARN(!power_well->count,
1584 "Use count on power well %s is already zero",
1587 if (!--power_well->count)
1588 intel_power_well_disable(dev_priv, power_well);
1591 mutex_unlock(&power_domains->lock);
1593 intel_runtime_pm_put(dev_priv);
1596 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
1597 BIT(POWER_DOMAIN_PIPE_A) | \
1598 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
1599 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
1600 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1601 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1602 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
1603 BIT(POWER_DOMAIN_PORT_CRT) | \
1604 BIT(POWER_DOMAIN_PLLS) | \
1605 BIT(POWER_DOMAIN_AUX_A) | \
1606 BIT(POWER_DOMAIN_AUX_B) | \
1607 BIT(POWER_DOMAIN_AUX_C) | \
1608 BIT(POWER_DOMAIN_AUX_D) | \
1609 BIT(POWER_DOMAIN_GMBUS) | \
1610 BIT(POWER_DOMAIN_INIT))
1611 #define HSW_DISPLAY_POWER_DOMAINS ( \
1612 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
1613 BIT(POWER_DOMAIN_INIT))
1615 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
1616 HSW_ALWAYS_ON_POWER_DOMAINS | \
1617 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
1618 #define BDW_DISPLAY_POWER_DOMAINS ( \
1619 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
1620 BIT(POWER_DOMAIN_INIT))
1622 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
1623 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
1625 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
1626 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1627 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1628 BIT(POWER_DOMAIN_PORT_CRT) | \
1629 BIT(POWER_DOMAIN_AUX_B) | \
1630 BIT(POWER_DOMAIN_AUX_C) | \
1631 BIT(POWER_DOMAIN_INIT))
1633 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
1634 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1635 BIT(POWER_DOMAIN_AUX_B) | \
1636 BIT(POWER_DOMAIN_INIT))
1638 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
1639 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1640 BIT(POWER_DOMAIN_AUX_B) | \
1641 BIT(POWER_DOMAIN_INIT))
1643 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
1644 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1645 BIT(POWER_DOMAIN_AUX_C) | \
1646 BIT(POWER_DOMAIN_INIT))
1648 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
1649 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1650 BIT(POWER_DOMAIN_AUX_C) | \
1651 BIT(POWER_DOMAIN_INIT))
1653 #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
1654 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1655 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1656 BIT(POWER_DOMAIN_AUX_B) | \
1657 BIT(POWER_DOMAIN_AUX_C) | \
1658 BIT(POWER_DOMAIN_INIT))
1660 #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
1661 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
1662 BIT(POWER_DOMAIN_AUX_D) | \
1663 BIT(POWER_DOMAIN_INIT))
1665 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1666 .sync_hw = i9xx_always_on_power_well_noop,
1667 .enable = i9xx_always_on_power_well_noop,
1668 .disable = i9xx_always_on_power_well_noop,
1669 .is_enabled = i9xx_always_on_power_well_enabled,
1672 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1673 .sync_hw = chv_pipe_power_well_sync_hw,
1674 .enable = chv_pipe_power_well_enable,
1675 .disable = chv_pipe_power_well_disable,
1676 .is_enabled = chv_pipe_power_well_enabled,
1679 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1680 .sync_hw = vlv_power_well_sync_hw,
1681 .enable = chv_dpio_cmn_power_well_enable,
1682 .disable = chv_dpio_cmn_power_well_disable,
1683 .is_enabled = vlv_power_well_enabled,
1686 static struct i915_power_well i9xx_always_on_power_well[] = {
1688 .name = "always-on",
1690 .domains = POWER_DOMAIN_MASK,
1691 .ops = &i9xx_always_on_power_well_ops,
1695 static const struct i915_power_well_ops hsw_power_well_ops = {
1696 .sync_hw = hsw_power_well_sync_hw,
1697 .enable = hsw_power_well_enable,
1698 .disable = hsw_power_well_disable,
1699 .is_enabled = hsw_power_well_enabled,
1702 static const struct i915_power_well_ops skl_power_well_ops = {
1703 .sync_hw = skl_power_well_sync_hw,
1704 .enable = skl_power_well_enable,
1705 .disable = skl_power_well_disable,
1706 .is_enabled = skl_power_well_enabled,
1709 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
1710 .sync_hw = gen9_dc_off_power_well_sync_hw,
1711 .enable = gen9_dc_off_power_well_enable,
1712 .disable = gen9_dc_off_power_well_disable,
1713 .is_enabled = gen9_dc_off_power_well_enabled,
1716 static struct i915_power_well hsw_power_wells[] = {
1718 .name = "always-on",
1720 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
1721 .ops = &i9xx_always_on_power_well_ops,
1725 .domains = HSW_DISPLAY_POWER_DOMAINS,
1726 .ops = &hsw_power_well_ops,
1730 static struct i915_power_well bdw_power_wells[] = {
1732 .name = "always-on",
1734 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
1735 .ops = &i9xx_always_on_power_well_ops,
1739 .domains = BDW_DISPLAY_POWER_DOMAINS,
1740 .ops = &hsw_power_well_ops,
1744 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1745 .sync_hw = vlv_power_well_sync_hw,
1746 .enable = vlv_display_power_well_enable,
1747 .disable = vlv_display_power_well_disable,
1748 .is_enabled = vlv_power_well_enabled,
1751 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1752 .sync_hw = vlv_power_well_sync_hw,
1753 .enable = vlv_dpio_cmn_power_well_enable,
1754 .disable = vlv_dpio_cmn_power_well_disable,
1755 .is_enabled = vlv_power_well_enabled,
1758 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1759 .sync_hw = vlv_power_well_sync_hw,
1760 .enable = vlv_power_well_enable,
1761 .disable = vlv_power_well_disable,
1762 .is_enabled = vlv_power_well_enabled,
1765 static struct i915_power_well vlv_power_wells[] = {
1767 .name = "always-on",
1769 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1770 .ops = &i9xx_always_on_power_well_ops,
1771 .data = PUNIT_POWER_WELL_ALWAYS_ON,
1775 .domains = VLV_DISPLAY_POWER_DOMAINS,
1776 .data = PUNIT_POWER_WELL_DISP2D,
1777 .ops = &vlv_display_power_well_ops,
1780 .name = "dpio-tx-b-01",
1781 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1782 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1783 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1784 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1785 .ops = &vlv_dpio_power_well_ops,
1786 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1789 .name = "dpio-tx-b-23",
1790 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1791 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1792 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1793 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1794 .ops = &vlv_dpio_power_well_ops,
1795 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1798 .name = "dpio-tx-c-01",
1799 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1800 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1801 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1802 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1803 .ops = &vlv_dpio_power_well_ops,
1804 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1807 .name = "dpio-tx-c-23",
1808 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1809 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1810 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1811 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1812 .ops = &vlv_dpio_power_well_ops,
1813 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1816 .name = "dpio-common",
1817 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1818 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1819 .ops = &vlv_dpio_cmn_power_well_ops,
1823 static struct i915_power_well chv_power_wells[] = {
1825 .name = "always-on",
1827 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1828 .ops = &i9xx_always_on_power_well_ops,
1833 * Pipe A power well is the new disp2d well. Pipe B and C
1834 * power wells don't actually exist. Pipe A power well is
1835 * required for any pipe to work.
1837 .domains = VLV_DISPLAY_POWER_DOMAINS,
1839 .ops = &chv_pipe_power_well_ops,
1842 .name = "dpio-common-bc",
1843 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
1844 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1845 .ops = &chv_dpio_cmn_power_well_ops,
1848 .name = "dpio-common-d",
1849 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
1850 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
1851 .ops = &chv_dpio_cmn_power_well_ops,
1855 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
1858 struct i915_power_well *power_well;
1861 power_well = lookup_power_well(dev_priv, power_well_id);
1862 ret = power_well->ops->is_enabled(dev_priv, power_well);
1867 static struct i915_power_well skl_power_wells[] = {
1869 .name = "always-on",
1871 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1872 .ops = &i9xx_always_on_power_well_ops,
1873 .data = SKL_DISP_PW_ALWAYS_ON,
1876 .name = "power well 1",
1877 /* Handled by the DMC firmware */
1879 .ops = &skl_power_well_ops,
1880 .data = SKL_DISP_PW_1,
1883 .name = "MISC IO power well",
1884 /* Handled by the DMC firmware */
1886 .ops = &skl_power_well_ops,
1887 .data = SKL_DISP_PW_MISC_IO,
1891 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
1892 .ops = &gen9_dc_off_power_well_ops,
1893 .data = SKL_DISP_PW_DC_OFF,
1896 .name = "power well 2",
1897 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1898 .ops = &skl_power_well_ops,
1899 .data = SKL_DISP_PW_2,
1902 .name = "DDI A/E power well",
1903 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
1904 .ops = &skl_power_well_ops,
1905 .data = SKL_DISP_PW_DDI_A_E,
1908 .name = "DDI B power well",
1909 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
1910 .ops = &skl_power_well_ops,
1911 .data = SKL_DISP_PW_DDI_B,
1914 .name = "DDI C power well",
1915 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
1916 .ops = &skl_power_well_ops,
1917 .data = SKL_DISP_PW_DDI_C,
1920 .name = "DDI D power well",
1921 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
1922 .ops = &skl_power_well_ops,
1923 .data = SKL_DISP_PW_DDI_D,
1927 static struct i915_power_well bxt_power_wells[] = {
1929 .name = "always-on",
1931 .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1932 .ops = &i9xx_always_on_power_well_ops,
1935 .name = "power well 1",
1937 .ops = &skl_power_well_ops,
1938 .data = SKL_DISP_PW_1,
1942 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
1943 .ops = &gen9_dc_off_power_well_ops,
1944 .data = SKL_DISP_PW_DC_OFF,
1947 .name = "power well 2",
1948 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1949 .ops = &skl_power_well_ops,
1950 .data = SKL_DISP_PW_2,
1955 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
1956 int disable_power_well)
1958 if (disable_power_well >= 0)
1959 return !!disable_power_well;
1961 if (IS_BROXTON(dev_priv)) {
1962 DRM_DEBUG_KMS("Disabling display power well support\n");
1969 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
1976 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1979 } else if (IS_BROXTON(dev_priv)) {
1982 * DC9 has a separate HW flow from the rest of the DC states,
1983 * not depending on the DMC firmware. It's needed by system
1984 * suspend/resume, so allow it unconditionally.
1986 mask = DC_STATE_EN_DC9;
1992 if (!i915.disable_power_well)
1995 if (enable_dc >= 0 && enable_dc <= max_dc) {
1996 requested_dc = enable_dc;
1997 } else if (enable_dc == -1) {
1998 requested_dc = max_dc;
1999 } else if (enable_dc > max_dc && enable_dc <= 2) {
2000 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
2002 requested_dc = max_dc;
2004 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc);
2005 requested_dc = max_dc;
2008 if (requested_dc > 1)
2009 mask |= DC_STATE_EN_UPTO_DC6;
2010 if (requested_dc > 0)
2011 mask |= DC_STATE_EN_UPTO_DC5;
2013 DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
2018 #define set_power_wells(power_domains, __power_wells) ({ \
2019 (power_domains)->power_wells = (__power_wells); \
2020 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
2024 * intel_power_domains_init - initializes the power domain structures
2025 * @dev_priv: i915 device instance
2027 * Initializes the power domain structures for @dev_priv depending upon the
2028 * supported platform.
2030 int intel_power_domains_init(struct drm_i915_private *dev_priv)
2032 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2034 i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
2035 i915.disable_power_well);
2036 dev_priv->csr.allowed_dc_mask = get_allowed_dc_mask(dev_priv,
2039 BUILD_BUG_ON(POWER_DOMAIN_NUM > 31);
2041 mutex_init(&power_domains->lock);
2044 * The enabling order will be from lower to higher indexed wells,
2045 * the disabling order is reversed.
2047 if (IS_HASWELL(dev_priv)) {
2048 set_power_wells(power_domains, hsw_power_wells);
2049 } else if (IS_BROADWELL(dev_priv)) {
2050 set_power_wells(power_domains, bdw_power_wells);
2051 } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2052 set_power_wells(power_domains, skl_power_wells);
2053 } else if (IS_BROXTON(dev_priv)) {
2054 set_power_wells(power_domains, bxt_power_wells);
2055 } else if (IS_CHERRYVIEW(dev_priv)) {
2056 set_power_wells(power_domains, chv_power_wells);
2057 } else if (IS_VALLEYVIEW(dev_priv)) {
2058 set_power_wells(power_domains, vlv_power_wells);
2060 set_power_wells(power_domains, i9xx_always_on_power_well);
2067 * intel_power_domains_fini - finalizes the power domain structures
2068 * @dev_priv: i915 device instance
2070 * Finalizes the power domain structures for @dev_priv depending upon the
2071 * supported platform. This function also disables runtime pm and ensures that
2072 * the device stays powered up so that the driver can be reloaded.
2074 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
2076 struct device *device = &dev_priv->dev->pdev->dev;
2079 * The i915.ko module is still not prepared to be loaded when
2080 * the power well is not enabled, so just enable it in case
2081 * we're going to unload/reload.
2082 * The following also reacquires the RPM reference the core passed
2083 * to the driver during loading, which is dropped in
2084 * intel_runtime_pm_enable(). We have to hand back the control of the
2085 * device to the core with this reference held.
2087 intel_display_set_init_power(dev_priv, true);
2089 /* Remove the refcount we took to keep power well support disabled. */
2090 if (!i915.disable_power_well)
2091 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2094 * Remove the refcount we took in intel_runtime_pm_enable() in case
2095 * the platform doesn't support runtime PM.
2097 if (!HAS_RUNTIME_PM(dev_priv))
2098 pm_runtime_put(device);
2101 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
2103 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2104 struct i915_power_well *power_well;
2107 mutex_lock(&power_domains->lock);
2108 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
2109 power_well->ops->sync_hw(dev_priv, power_well);
2110 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
2113 mutex_unlock(&power_domains->lock);
2116 static void skl_display_core_init(struct drm_i915_private *dev_priv,
2119 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2120 struct i915_power_well *well;
2123 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2125 /* enable PCH reset handshake */
2126 val = I915_READ(HSW_NDE_RSTWRN_OPT);
2127 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
2129 /* enable PG1 and Misc I/O */
2130 mutex_lock(&power_domains->lock);
2132 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2133 intel_power_well_enable(dev_priv, well);
2135 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2136 intel_power_well_enable(dev_priv, well);
2138 mutex_unlock(&power_domains->lock);
2143 skl_init_cdclk(dev_priv);
2145 if (dev_priv->csr.dmc_payload)
2146 intel_csr_load_program(dev_priv);
2149 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
2151 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2152 struct i915_power_well *well;
2154 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2156 skl_uninit_cdclk(dev_priv);
2158 /* The spec doesn't call for removing the reset handshake flag */
2159 /* disable PG1 and Misc I/O */
2161 mutex_lock(&power_domains->lock);
2163 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
2164 intel_power_well_disable(dev_priv, well);
2166 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2167 intel_power_well_disable(dev_priv, well);
2169 mutex_unlock(&power_domains->lock);
2172 void bxt_display_core_init(struct drm_i915_private *dev_priv,
2175 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2176 struct i915_power_well *well;
2179 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2182 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
2183 * or else the reset will hang because there is no PCH to respond.
2184 * Move the handshake programming to initialization sequence.
2185 * Previously was left up to BIOS.
2187 val = I915_READ(HSW_NDE_RSTWRN_OPT);
2188 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
2189 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
2192 mutex_lock(&power_domains->lock);
2194 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2195 intel_power_well_enable(dev_priv, well);
2197 mutex_unlock(&power_domains->lock);
2199 broxton_init_cdclk(dev_priv);
2200 broxton_ddi_phy_init(dev_priv);
2202 if (resume && dev_priv->csr.dmc_payload)
2203 intel_csr_load_program(dev_priv);
2206 void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
2208 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2209 struct i915_power_well *well;
2211 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2213 broxton_ddi_phy_uninit(dev_priv);
2214 broxton_uninit_cdclk(dev_priv);
2216 /* The spec doesn't call for removing the reset handshake flag */
2219 mutex_lock(&power_domains->lock);
2221 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
2222 intel_power_well_disable(dev_priv, well);
2224 mutex_unlock(&power_domains->lock);
2227 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
2229 struct i915_power_well *cmn_bc =
2230 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2231 struct i915_power_well *cmn_d =
2232 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
2235 * DISPLAY_PHY_CONTROL can get corrupted if read. As a
2236 * workaround never ever read DISPLAY_PHY_CONTROL, and
2237 * instead maintain a shadow copy ourselves. Use the actual
2238 * power well state and lane status to reconstruct the
2239 * expected initial value.
2241 dev_priv->chv_phy_control =
2242 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
2243 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
2244 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
2245 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
2246 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
2249 * If all lanes are disabled we leave the override disabled
2250 * with all power down bits cleared to match the state we
2251 * would use after disabling the port. Otherwise enable the
2252 * override and set the lane powerdown bits accding to the
2253 * current lane status.
2255 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
2256 uint32_t status = I915_READ(DPLL(PIPE_A));
2259 mask = status & DPLL_PORTB_READY_MASK;
2263 dev_priv->chv_phy_control |=
2264 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
2266 dev_priv->chv_phy_control |=
2267 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
2269 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
2273 dev_priv->chv_phy_control |=
2274 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
2276 dev_priv->chv_phy_control |=
2277 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
2279 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
2281 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
2283 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
2286 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
2287 uint32_t status = I915_READ(DPIO_PHY_STATUS);
2290 mask = status & DPLL_PORTD_READY_MASK;
2295 dev_priv->chv_phy_control |=
2296 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
2298 dev_priv->chv_phy_control |=
2299 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
2301 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
2303 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
2305 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
2308 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
2310 DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
2311 dev_priv->chv_phy_control);
2314 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
2316 struct i915_power_well *cmn =
2317 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2318 struct i915_power_well *disp2d =
2319 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
2321 /* If the display might be already active skip this */
2322 if (cmn->ops->is_enabled(dev_priv, cmn) &&
2323 disp2d->ops->is_enabled(dev_priv, disp2d) &&
2324 I915_READ(DPIO_CTL) & DPIO_CMNRST)
2327 DRM_DEBUG_KMS("toggling display PHY side reset\n");
2329 /* cmnlane needs DPLL registers */
2330 disp2d->ops->enable(dev_priv, disp2d);
2333 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
2334 * Need to assert and de-assert PHY SB reset by gating the
2335 * common lane power, then un-gating it.
2336 * Simply ungating isn't enough to reset the PHY enough to get
2337 * ports and lanes running.
2339 cmn->ops->disable(dev_priv, cmn);
2343 * intel_power_domains_init_hw - initialize hardware power domain state
2344 * @dev_priv: i915 device instance
2346 * This function initializes the hardware power domain state and enables all
2347 * power domains using intel_display_set_init_power().
2349 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
2351 struct drm_device *dev = dev_priv->dev;
2352 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2354 power_domains->initializing = true;
2356 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
2357 skl_display_core_init(dev_priv, resume);
2358 } else if (IS_BROXTON(dev)) {
2359 bxt_display_core_init(dev_priv, resume);
2360 } else if (IS_CHERRYVIEW(dev)) {
2361 mutex_lock(&power_domains->lock);
2362 chv_phy_control_init(dev_priv);
2363 mutex_unlock(&power_domains->lock);
2364 } else if (IS_VALLEYVIEW(dev)) {
2365 mutex_lock(&power_domains->lock);
2366 vlv_cmnlane_wa(dev_priv);
2367 mutex_unlock(&power_domains->lock);
2370 /* For now, we need the power well to be always enabled. */
2371 intel_display_set_init_power(dev_priv, true);
2372 /* Disable power support if the user asked so. */
2373 if (!i915.disable_power_well)
2374 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
2375 intel_power_domains_sync_hw(dev_priv);
2376 power_domains->initializing = false;
2380 * intel_power_domains_suspend - suspend power domain state
2381 * @dev_priv: i915 device instance
2383 * This function prepares the hardware power domain state before entering
2384 * system suspend. It must be paired with intel_power_domains_init_hw().
2386 void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
2389 * Even if power well support was disabled we still want to disable
2390 * power wells while we are system suspended.
2392 if (!i915.disable_power_well)
2393 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2395 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
2396 skl_display_core_uninit(dev_priv);
2397 else if (IS_BROXTON(dev_priv))
2398 bxt_display_core_uninit(dev_priv);
2402 * intel_runtime_pm_get - grab a runtime pm reference
2403 * @dev_priv: i915 device instance
2405 * This function grabs a device-level runtime pm reference (mostly used for GEM
2406 * code to ensure the GTT or GT is on) and ensures that it is powered up.
2408 * Any runtime pm reference obtained by this function must have a symmetric
2409 * call to intel_runtime_pm_put() to release the reference again.
2411 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
2413 struct drm_device *dev = dev_priv->dev;
2414 struct device *device = &dev->pdev->dev;
2416 pm_runtime_get_sync(device);
2418 atomic_inc(&dev_priv->pm.wakeref_count);
2419 assert_rpm_wakelock_held(dev_priv);
2423 * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use
2424 * @dev_priv: i915 device instance
2426 * This function grabs a device-level runtime pm reference if the device is
2427 * already in use and ensures that it is powered up.
2429 * Any runtime pm reference obtained by this function must have a symmetric
2430 * call to intel_runtime_pm_put() to release the reference again.
2432 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv)
2434 struct drm_device *dev = dev_priv->dev;
2435 struct device *device = &dev->pdev->dev;
2437 if (IS_ENABLED(CONFIG_PM)) {
2438 int ret = pm_runtime_get_if_in_use(device);
2441 * In cases runtime PM is disabled by the RPM core and we get
2442 * an -EINVAL return value we are not supposed to call this
2443 * function, since the power state is undefined. This applies
2444 * atm to the late/early system suspend/resume handlers.
2446 WARN_ON_ONCE(ret < 0);
2451 atomic_inc(&dev_priv->pm.wakeref_count);
2452 assert_rpm_wakelock_held(dev_priv);
2458 * intel_runtime_pm_get_noresume - grab a runtime pm reference
2459 * @dev_priv: i915 device instance
2461 * This function grabs a device-level runtime pm reference (mostly used for GEM
2462 * code to ensure the GTT or GT is on).
2464 * It will _not_ power up the device but instead only check that it's powered
2465 * on. Therefore it is only valid to call this functions from contexts where
2466 * the device is known to be powered up and where trying to power it up would
2467 * result in hilarity and deadlocks. That pretty much means only the system
2468 * suspend/resume code where this is used to grab runtime pm references for
2469 * delayed setup down in work items.
2471 * Any runtime pm reference obtained by this function must have a symmetric
2472 * call to intel_runtime_pm_put() to release the reference again.
2474 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
2476 struct drm_device *dev = dev_priv->dev;
2477 struct device *device = &dev->pdev->dev;
2479 assert_rpm_wakelock_held(dev_priv);
2480 pm_runtime_get_noresume(device);
2482 atomic_inc(&dev_priv->pm.wakeref_count);
2486 * intel_runtime_pm_put - release a runtime pm reference
2487 * @dev_priv: i915 device instance
2489 * This function drops the device-level runtime pm reference obtained by
2490 * intel_runtime_pm_get() and might power down the corresponding
2491 * hardware block right away if this is the last reference.
2493 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
2495 struct drm_device *dev = dev_priv->dev;
2496 struct device *device = &dev->pdev->dev;
2498 assert_rpm_wakelock_held(dev_priv);
2499 if (atomic_dec_and_test(&dev_priv->pm.wakeref_count))
2500 atomic_inc(&dev_priv->pm.atomic_seq);
2502 pm_runtime_mark_last_busy(device);
2503 pm_runtime_put_autosuspend(device);
2507 * intel_runtime_pm_enable - enable runtime pm
2508 * @dev_priv: i915 device instance
2510 * This function enables runtime pm at the end of the driver load sequence.
2512 * Note that this function does currently not enable runtime pm for the
2513 * subordinate display power domains. That is only done on the first modeset
2514 * using intel_display_set_init_power().
2516 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
2518 struct drm_device *dev = dev_priv->dev;
2519 struct device *device = &dev->pdev->dev;
2521 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
2522 pm_runtime_mark_last_busy(device);
2525 * Take a permanent reference to disable the RPM functionality and drop
2526 * it only when unloading the driver. Use the low level get/put helpers,
2527 * so the driver's own RPM reference tracking asserts also work on
2528 * platforms without RPM support.
2530 if (!HAS_RUNTIME_PM(dev)) {
2531 pm_runtime_dont_use_autosuspend(device);
2532 pm_runtime_get_sync(device);
2534 pm_runtime_use_autosuspend(device);
2538 * The core calls the driver load handler with an RPM reference held.
2539 * We drop that here and will reacquire it during unloading in
2540 * intel_power_domains_fini().
2542 pm_runtime_put_autosuspend(device);