drivers/platform/x86/intel/pmc/mtl.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * This file contains platform specific structure definitions
   4  * and init function used by Meteor Lake PCH.
   5  *
   6  * Copyright (c) 2022, Intel Corporation.
   7  * All Rights Reserved.
   8  *
   9  */
  10
  11 #include <linux/pci.h>
  12 #include "core.h"
  13
  14 const struct pmc_reg_map mtl_reg_map = {
  15         .pfear_sts = ext_tgl_pfear_map,
  16         .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
  17         .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
  18         .ltr_show_sts = adl_ltr_show_map,
  19         .msr_sts = msr_map,
  20         .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
  21         .regmap_length = CNP_PMC_MMIO_REG_LEN,
  22         .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
  23         .ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
  24         .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
  25         .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
  26         .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED,
  27         .lpm_num_modes = ADL_LPM_NUM_MODES,
  28         .lpm_num_maps = ADL_LPM_NUM_MAPS,
  29         .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
  30         .etr3_offset = ETR3_OFFSET,
  31         .lpm_sts_latch_en_offset = MTL_LPM_STATUS_LATCH_EN_OFFSET,
  32         .lpm_priority_offset = MTL_LPM_PRI_OFFSET,
  33         .lpm_en_offset = MTL_LPM_EN_OFFSET,
  34         .lpm_residency_offset = MTL_LPM_RESIDENCY_OFFSET,
  35         .lpm_sts = adl_lpm_maps,
  36         .lpm_status_offset = MTL_LPM_STATUS_OFFSET,
  37         .lpm_live_status_offset = MTL_LPM_LIVE_STATUS_OFFSET,
  38 };
  39
  40 void mtl_core_configure(struct pmc_dev *pmcdev)
  41 {
  42         /* Due to a hardware limitation, the GBE LTR blocks PC10
  43          * when a cable is attached. Tell the PMC to ignore it.
  44          */
  45         dev_dbg(&pmcdev->pdev->dev, "ignoring GBE LTR\n");
  46         pmc_core_send_ltr_ignore(pmcdev, 3);
  47 }
  48
  49 #define MTL_GNA_PCI_DEV 0x7e4c
  50 #define MTL_IPU_PCI_DEV 0x7d19
  51 #define MTL_VPU_PCI_DEV 0x7d1d
  52 static void mtl_set_device_d3(unsigned int device)
  53 {
  54         struct pci_dev *pcidev;
  55
  56         pcidev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
  57         if (pcidev) {
  58                 if (!device_trylock(&pcidev->dev)) {
  59                         pci_dev_put(pcidev);
  60                         return;
  61                 }
  62                 if (!pcidev->dev.driver) {
  63                         dev_info(&pcidev->dev, "Setting to D3hot\n");
  64                         pci_set_power_state(pcidev, PCI_D3hot);
  65                 }
  66                 device_unlock(&pcidev->dev);
  67                 pci_dev_put(pcidev);
  68         }
  69 }
  70
  71 void mtl_core_init(struct pmc_dev *pmcdev)
  72 {
  73         pmcdev->map = &mtl_reg_map;
  74         pmcdev->core_configure = mtl_core_configure;
  75
  76         /*
  77          * Set power state of select devices that do not have drivers to D3
  78          * so that they do not block Package C entry.
  79          */
  80         mtl_set_device_d3(MTL_GNA_PCI_DEV);
  81         mtl_set_device_d3(MTL_IPU_PCI_DEV);
  82         mtl_set_device_d3(MTL_VPU_PCI_DEV);
  83 }