drivers/platform/x86/intel/pmc/icl.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * This file contains platform specific structure definitions
   4  * and init function used by Ice Lake PCH.
   5  *
   6  * Copyright (c) 2022, Intel Corporation.
   7  * All Rights Reserved.
   8  *
   9  */
  10
  11 #include "core.h"
  12
  13 const struct pmc_bit_map icl_pfear_map[] = {
  14         {"RES_65",              BIT(0)},
  15         {"RES_66",              BIT(1)},
  16         {"RES_67",              BIT(2)},
  17         {"TAM",                 BIT(3)},
  18         {"GBETSN",              BIT(4)},
  19         {"TBTLSX",              BIT(5)},
  20         {"RES_71",              BIT(6)},
  21         {"RES_72",              BIT(7)},
  22         {}
  23 };
  24
  25 const struct pmc_bit_map *ext_icl_pfear_map[] = {
  26         /*
  27          * Check intel_pmc_core_ids[] users of icl_reg_map for
  28          * a list of core SoCs using this.
  29          */
  30         cnp_pfear_map,
  31         icl_pfear_map,
  32         NULL
  33 };
  34
  35 const struct pmc_reg_map icl_reg_map = {
  36         .pfear_sts = ext_icl_pfear_map,
  37         .slp_s0_offset = CNP_PMC_SLP_S0_RES_COUNTER_OFFSET,
  38         .slp_s0_res_counter_step = ICL_PMC_SLP_S0_RES_COUNTER_STEP,
  39         .slps0_dbg_maps = cnp_slps0_dbg_maps,
  40         .ltr_show_sts = cnp_ltr_show_map,
  41         .msr_sts = msr_map,
  42         .slps0_dbg_offset = CNP_PMC_SLPS0_DBG_OFFSET,
  43         .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
  44         .regmap_length = CNP_PMC_MMIO_REG_LEN,
  45         .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
  46         .ppfear_buckets = ICL_PPFEAR_NUM_ENTRIES,
  47         .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
  48         .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
  49         .ltr_ignore_max = ICL_NUM_IP_IGN_ALLOWED,
  50         .etr3_offset = ETR3_OFFSET,
  51 };
  52
  53 void icl_core_init(struct pmc_dev *pmcdev)
  54 {
  55         pmcdev->map = &icl_reg_map;
  56 }