drivers/platform/x86/intel/pmc/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Intel Core SoC Power Management Controller Driver
   4  *
   5  * Copyright (c) 2016, Intel Corporation.
   6  * All Rights Reserved.
   7  *
   8  * Authors: Rajneesh Bhardwaj <[email protected]>
   9  *          Vishwanath Somayaji <[email protected]>
  10  */
  11
  12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13
  14 #include <linux/bitfield.h>
  15 #include <linux/debugfs.h>
  16 #include <linux/delay.h>
  17 #include <linux/dmi.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/pci.h>
  21 #include <linux/slab.h>
  22 #include <linux/suspend.h>
  23
  24 #include <asm/cpu_device_id.h>
  25 #include <asm/intel-family.h>
  26 #include <asm/msr.h>
  27 #include <asm/tsc.h>
  28
  29 #include "core.h"
  30
  31 /* Maximum number of modes supported by platfoms that has low power mode capability */
  32 const char *pmc_lpm_modes[] = {
  33         "S0i2.0",
  34         "S0i2.1",
  35         "S0i2.2",
  36         "S0i3.0",
  37         "S0i3.1",
  38         "S0i3.2",
  39         "S0i3.3",
  40         "S0i3.4",
  41         NULL
  42 };
  43
  44 /* PKGC MSRs are common across Intel Core SoCs */
  45 const struct pmc_bit_map msr_map[] = {
  46         {"Package C2",                  MSR_PKG_C2_RESIDENCY},
  47         {"Package C3",                  MSR_PKG_C3_RESIDENCY},
  48         {"Package C6",                  MSR_PKG_C6_RESIDENCY},
  49         {"Package C7",                  MSR_PKG_C7_RESIDENCY},
  50         {"Package C8",                  MSR_PKG_C8_RESIDENCY},
  51         {"Package C9",                  MSR_PKG_C9_RESIDENCY},
  52         {"Package C10",                 MSR_PKG_C10_RESIDENCY},
  53         {}
  54 };
  55
  56 static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
  57 {
  58         return readl(pmcdev->regbase + reg_offset);
  59 }
  60
  61 static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int reg_offset,
  62                                       u32 val)
  63 {
  64         writel(val, pmcdev->regbase + reg_offset);
  65 }
  66
  67 static inline u64 pmc_core_adjust_slp_s0_step(struct pmc_dev *pmcdev, u32 value)
  68 {
  69         /*
  70          * ADL PCH does not have the SLP_S0 counter and LPM Residency counters are
  71          * used as a workaround which uses 30.5 usec tick. All other client
  72          * programs have the legacy SLP_S0 residency counter that is using the 122
  73          * usec tick.
  74          */
  75         const int lpm_adj_x2 = pmcdev->map->lpm_res_counter_step_x2;
  76
  77         if (pmcdev->map == &adl_reg_map)
  78                 return (u64)value * GET_X2_COUNTER((u64)lpm_adj_x2);
  79         else
  80                 return (u64)value * pmcdev->map->slp_s0_res_counter_step;
  81 }
  82
  83 static int set_etr3(struct pmc_dev *pmcdev)
  84 {
  85         const struct pmc_reg_map *map = pmcdev->map;
  86         u32 reg;
  87         int err;
  88
  89         if (!map->etr3_offset)
  90                 return -EOPNOTSUPP;
  91
  92         mutex_lock(&pmcdev->lock);
  93
  94         /* check if CF9 is locked */
  95         reg = pmc_core_reg_read(pmcdev, map->etr3_offset);
  96         if (reg & ETR3_CF9LOCK) {
  97                 err = -EACCES;
  98                 goto out_unlock;
  99         }
 100
 101         /* write CF9 global reset bit */
 102         reg |= ETR3_CF9GR;
 103         pmc_core_reg_write(pmcdev, map->etr3_offset, reg);
 104
 105         reg = pmc_core_reg_read(pmcdev, map->etr3_offset);
 106         if (!(reg & ETR3_CF9GR)) {
 107                 err = -EIO;
 108                 goto out_unlock;
 109         }
 110
 111         err = 0;
 112
 113 out_unlock:
 114         mutex_unlock(&pmcdev->lock);
 115         return err;
 116 }
 117 static umode_t etr3_is_visible(struct kobject *kobj,
 118                                 struct attribute *attr,
 119                                 int idx)
 120 {
 121         struct device *dev = kobj_to_dev(kobj);
 122         struct pmc_dev *pmcdev = dev_get_drvdata(dev);
 123         const struct pmc_reg_map *map = pmcdev->map;
 124         u32 reg;
 125
 126         mutex_lock(&pmcdev->lock);
 127         reg = pmc_core_reg_read(pmcdev, map->etr3_offset);
 128         mutex_unlock(&pmcdev->lock);
 129
 130         return reg & ETR3_CF9LOCK ? attr->mode & (SYSFS_PREALLOC | 0444) : attr->mode;
 131 }
 132
 133 static ssize_t etr3_show(struct device *dev,
 134                                  struct device_attribute *attr, char *buf)
 135 {
 136         struct pmc_dev *pmcdev = dev_get_drvdata(dev);
 137         const struct pmc_reg_map *map = pmcdev->map;
 138         u32 reg;
 139
 140         if (!map->etr3_offset)
 141                 return -EOPNOTSUPP;
 142
 143         mutex_lock(&pmcdev->lock);
 144
 145         reg = pmc_core_reg_read(pmcdev, map->etr3_offset);
 146         reg &= ETR3_CF9GR | ETR3_CF9LOCK;
 147
 148         mutex_unlock(&pmcdev->lock);
 149
 150         return sysfs_emit(buf, "0x%08x", reg);
 151 }
 152
 153 static ssize_t etr3_store(struct device *dev,
 154                                   struct device_attribute *attr,
 155                                   const char *buf, size_t len)
 156 {
 157         struct pmc_dev *pmcdev = dev_get_drvdata(dev);
 158         int err;
 159         u32 reg;
 160
 161         err = kstrtouint(buf, 16, &reg);
 162         if (err)
 163                 return err;
 164
 165         /* allow only CF9 writes */
 166         if (reg != ETR3_CF9GR)
 167                 return -EINVAL;
 168
 169         err = set_etr3(pmcdev);
 170         if (err)
 171                 return err;
 172
 173         return len;
 174 }
 175 static DEVICE_ATTR_RW(etr3);
 176
 177 static struct attribute *pmc_attrs[] = {
 178         &dev_attr_etr3.attr,
 179         NULL
 180 };
 181
 182 static const struct attribute_group pmc_attr_group = {
 183         .attrs = pmc_attrs,
 184         .is_visible = etr3_is_visible,
 185 };
 186
 187 static const struct attribute_group *pmc_dev_groups[] = {
 188         &pmc_attr_group,
 189         NULL
 190 };
 191
 192 static int pmc_core_dev_state_get(void *data, u64 *val)
 193 {
 194         struct pmc_dev *pmcdev = data;
 195         const struct pmc_reg_map *map = pmcdev->map;
 196         u32 value;
 197
 198         value = pmc_core_reg_read(pmcdev, map->slp_s0_offset);
 199         *val = pmc_core_adjust_slp_s0_step(pmcdev, value);
 200
 201         return 0;
 202 }
 203
 204 DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_dev_state, pmc_core_dev_state_get, NULL, "%llu\n");
 205
 206 static int pmc_core_check_read_lock_bit(struct pmc_dev *pmcdev)
 207 {
 208         u32 value;
 209
 210         value = pmc_core_reg_read(pmcdev, pmcdev->map->pm_cfg_offset);
 211         return value & BIT(pmcdev->map->pm_read_disable_bit);
 212 }
 213
 214 static void pmc_core_slps0_display(struct pmc_dev *pmcdev, struct device *dev,
 215                                    struct seq_file *s)
 216 {
 217         const struct pmc_bit_map **maps = pmcdev->map->slps0_dbg_maps;
 218         const struct pmc_bit_map *map;
 219         int offset = pmcdev->map->slps0_dbg_offset;
 220         u32 data;
 221
 222         while (*maps) {
 223                 map = *maps;
 224                 data = pmc_core_reg_read(pmcdev, offset);
 225                 offset += 4;
 226                 while (map->name) {
 227                         if (dev)
 228                                 dev_info(dev, "SLP_S0_DBG: %-32s\tState: %s\n",
 229                                         map->name,
 230                                         data & map->bit_mask ? "Yes" : "No");
 231                         if (s)
 232                                 seq_printf(s, "SLP_S0_DBG: %-32s\tState: %s\n",
 233                                            map->name,
 234                                            data & map->bit_mask ? "Yes" : "No");
 235                         ++map;
 236                 }
 237                 ++maps;
 238         }
 239 }
 240
 241 static int pmc_core_lpm_get_arr_size(const struct pmc_bit_map **maps)
 242 {
 243         int idx;
 244
 245         for (idx = 0; maps[idx]; idx++)
 246                 ;/* Nothing */
 247
 248         return idx;
 249 }
 250
 251 static void pmc_core_lpm_display(struct pmc_dev *pmcdev, struct device *dev,
 252                                  struct seq_file *s, u32 offset,
 253                                  const char *str,
 254                                  const struct pmc_bit_map **maps)
 255 {
 256         int index, idx, len = 32, bit_mask, arr_size;
 257         u32 *lpm_regs;
 258
 259         arr_size = pmc_core_lpm_get_arr_size(maps);
 260         lpm_regs = kmalloc_array(arr_size, sizeof(*lpm_regs), GFP_KERNEL);
 261         if (!lpm_regs)
 262                 return;
 263
 264         for (index = 0; index < arr_size; index++) {
 265                 lpm_regs[index] = pmc_core_reg_read(pmcdev, offset);
 266                 offset += 4;
 267         }
 268
 269         for (idx = 0; idx < arr_size; idx++) {
 270                 if (dev)
 271                         dev_info(dev, "\nLPM_%s_%d:\t0x%x\n", str, idx,
 272                                 lpm_regs[idx]);
 273                 if (s)
 274                         seq_printf(s, "\nLPM_%s_%d:\t0x%x\n", str, idx,
 275                                    lpm_regs[idx]);
 276                 for (index = 0; maps[idx][index].name && index < len; index++) {
 277                         bit_mask = maps[idx][index].bit_mask;
 278                         if (dev)
 279                                 dev_info(dev, "%-30s %-30d\n",
 280                                         maps[idx][index].name,
 281                                         lpm_regs[idx] & bit_mask ? 1 : 0);
 282                         if (s)
 283                                 seq_printf(s, "%-30s %-30d\n",
 284                                            maps[idx][index].name,
 285                                            lpm_regs[idx] & bit_mask ? 1 : 0);
 286                 }
 287         }
 288
 289         kfree(lpm_regs);
 290 }
 291
 292 static bool slps0_dbg_latch;
 293
 294 static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset)
 295 {
 296         return readb(pmcdev->regbase + offset);
 297 }
 298
 299 static void pmc_core_display_map(struct seq_file *s, int index, int idx, int ip,
 300                                  u8 pf_reg, const struct pmc_bit_map **pf_map)
 301 {
 302         seq_printf(s, "PCH IP: %-2d - %-32s\tState: %s\n",
 303                    ip, pf_map[idx][index].name,
 304                    pf_map[idx][index].bit_mask & pf_reg ? "Off" : "On");
 305 }
 306
 307 static int pmc_core_ppfear_show(struct seq_file *s, void *unused)
 308 {
 309         struct pmc_dev *pmcdev = s->private;
 310         const struct pmc_bit_map **maps = pmcdev->map->pfear_sts;
 311         u8 pf_regs[PPFEAR_MAX_NUM_ENTRIES];
 312         int index, iter, idx, ip = 0;
 313
 314         iter = pmcdev->map->ppfear0_offset;
 315
 316         for (index = 0; index < pmcdev->map->ppfear_buckets &&
 317              index < PPFEAR_MAX_NUM_ENTRIES; index++, iter++)
 318                 pf_regs[index] = pmc_core_reg_read_byte(pmcdev, iter);
 319
 320         for (idx = 0; maps[idx]; idx++) {
 321                 for (index = 0; maps[idx][index].name &&
 322                      index < pmcdev->map->ppfear_buckets * 8; ip++, index++)
 323                         pmc_core_display_map(s, index, idx, ip,
 324                                              pf_regs[index / 8], maps);
 325         }
 326
 327         return 0;
 328 }
 329 DEFINE_SHOW_ATTRIBUTE(pmc_core_ppfear);
 330
 331 /* This function should return link status, 0 means ready */
 332 static int pmc_core_mtpmc_link_status(struct pmc_dev *pmcdev)
 333 {
 334         u32 value;
 335
 336         value = pmc_core_reg_read(pmcdev, SPT_PMC_PM_STS_OFFSET);
 337         return value & BIT(SPT_PMC_MSG_FULL_STS_BIT);
 338 }
 339
 340 static int pmc_core_send_msg(struct pmc_dev *pmcdev, u32 *addr_xram)
 341 {
 342         u32 dest;
 343         int timeout;
 344
 345         for (timeout = NUM_RETRIES; timeout > 0; timeout--) {
 346                 if (pmc_core_mtpmc_link_status(pmcdev) == 0)
 347                         break;
 348                 msleep(5);
 349         }
 350
 351         if (timeout <= 0 && pmc_core_mtpmc_link_status(pmcdev))
 352                 return -EBUSY;
 353
 354         dest = (*addr_xram & MTPMC_MASK) | (1U << 1);
 355         pmc_core_reg_write(pmcdev, SPT_PMC_MTPMC_OFFSET, dest);
 356         return 0;
 357 }
 358
 359 static int pmc_core_mphy_pg_show(struct seq_file *s, void *unused)
 360 {
 361         struct pmc_dev *pmcdev = s->private;
 362         const struct pmc_bit_map *map = pmcdev->map->mphy_sts;
 363         u32 mphy_core_reg_low, mphy_core_reg_high;
 364         u32 val_low, val_high;
 365         int index, err = 0;
 366
 367         if (pmcdev->pmc_xram_read_bit) {
 368                 seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
 369                 return 0;
 370         }
 371
 372         mphy_core_reg_low  = (SPT_PMC_MPHY_CORE_STS_0 << 16);
 373         mphy_core_reg_high = (SPT_PMC_MPHY_CORE_STS_1 << 16);
 374
 375         mutex_lock(&pmcdev->lock);
 376
 377         if (pmc_core_send_msg(pmcdev, &mphy_core_reg_low) != 0) {
 378                 err = -EBUSY;
 379                 goto out_unlock;
 380         }
 381
 382         msleep(10);
 383         val_low = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
 384
 385         if (pmc_core_send_msg(pmcdev, &mphy_core_reg_high) != 0) {
 386                 err = -EBUSY;
 387                 goto out_unlock;
 388         }
 389
 390         msleep(10);
 391         val_high = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
 392
 393         for (index = 0; index < 8 && map[index].name; index++) {
 394                 seq_printf(s, "%-32s\tState: %s\n",
 395                            map[index].name,
 396                            map[index].bit_mask & val_low ? "Not power gated" :
 397                            "Power gated");
 398         }
 399
 400         for (index = 8; map[index].name; index++) {
 401                 seq_printf(s, "%-32s\tState: %s\n",
 402                            map[index].name,
 403                            map[index].bit_mask & val_high ? "Not power gated" :
 404                            "Power gated");
 405         }
 406
 407 out_unlock:
 408         mutex_unlock(&pmcdev->lock);
 409         return err;
 410 }
 411 DEFINE_SHOW_ATTRIBUTE(pmc_core_mphy_pg);
 412
 413 static int pmc_core_pll_show(struct seq_file *s, void *unused)
 414 {
 415         struct pmc_dev *pmcdev = s->private;
 416         const struct pmc_bit_map *map = pmcdev->map->pll_sts;
 417         u32 mphy_common_reg, val;
 418         int index, err = 0;
 419
 420         if (pmcdev->pmc_xram_read_bit) {
 421                 seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
 422                 return 0;
 423         }
 424
 425         mphy_common_reg  = (SPT_PMC_MPHY_COM_STS_0 << 16);
 426         mutex_lock(&pmcdev->lock);
 427
 428         if (pmc_core_send_msg(pmcdev, &mphy_common_reg) != 0) {
 429                 err = -EBUSY;
 430                 goto out_unlock;
 431         }
 432
 433         /* Observed PMC HW response latency for MTPMC-MFPMC is ~10 ms */
 434         msleep(10);
 435         val = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
 436
 437         for (index = 0; map[index].name ; index++) {
 438                 seq_printf(s, "%-32s\tState: %s\n",
 439                            map[index].name,
 440                            map[index].bit_mask & val ? "Active" : "Idle");
 441         }
 442
 443 out_unlock:
 444         mutex_unlock(&pmcdev->lock);
 445         return err;
 446 }
 447 DEFINE_SHOW_ATTRIBUTE(pmc_core_pll);
 448
 449 int pmc_core_send_ltr_ignore(struct pmc_dev *pmcdev, u32 value)
 450 {
 451         const struct pmc_reg_map *map = pmcdev->map;
 452         u32 reg;
 453         int err = 0;
 454
 455         mutex_lock(&pmcdev->lock);
 456
 457         if (value > map->ltr_ignore_max) {
 458                 err = -EINVAL;
 459                 goto out_unlock;
 460         }
 461
 462         reg = pmc_core_reg_read(pmcdev, map->ltr_ignore_offset);
 463         reg |= BIT(value);
 464         pmc_core_reg_write(pmcdev, map->ltr_ignore_offset, reg);
 465
 466 out_unlock:
 467         mutex_unlock(&pmcdev->lock);
 468
 469         return err;
 470 }
 471
 472 static ssize_t pmc_core_ltr_ignore_write(struct file *file,
 473                                          const char __user *userbuf,
 474                                          size_t count, loff_t *ppos)
 475 {
 476         struct seq_file *s = file->private_data;
 477         struct pmc_dev *pmcdev = s->private;
 478         u32 buf_size, value;
 479         int err;
 480
 481         buf_size = min_t(u32, count, 64);
 482
 483         err = kstrtou32_from_user(userbuf, buf_size, 10, &value);
 484         if (err)
 485                 return err;
 486
 487         err = pmc_core_send_ltr_ignore(pmcdev, value);
 488
 489         return err == 0 ? count : err;
 490 }
 491
 492 static int pmc_core_ltr_ignore_show(struct seq_file *s, void *unused)
 493 {
 494         return 0;
 495 }
 496
 497 static int pmc_core_ltr_ignore_open(struct inode *inode, struct file *file)
 498 {
 499         return single_open(file, pmc_core_ltr_ignore_show, inode->i_private);
 500 }
 501
 502 static const struct file_operations pmc_core_ltr_ignore_ops = {
 503         .open           = pmc_core_ltr_ignore_open,
 504         .read           = seq_read,
 505         .write          = pmc_core_ltr_ignore_write,
 506         .llseek         = seq_lseek,
 507         .release        = single_release,
 508 };
 509
 510 static void pmc_core_slps0_dbg_latch(struct pmc_dev *pmcdev, bool reset)
 511 {
 512         const struct pmc_reg_map *map = pmcdev->map;
 513         u32 fd;
 514
 515         mutex_lock(&pmcdev->lock);
 516
 517         if (!reset && !slps0_dbg_latch)
 518                 goto out_unlock;
 519
 520         fd = pmc_core_reg_read(pmcdev, map->slps0_dbg_offset);
 521         if (reset)
 522                 fd &= ~CNP_PMC_LATCH_SLPS0_EVENTS;
 523         else
 524                 fd |= CNP_PMC_LATCH_SLPS0_EVENTS;
 525         pmc_core_reg_write(pmcdev, map->slps0_dbg_offset, fd);
 526
 527         slps0_dbg_latch = false;
 528
 529 out_unlock:
 530         mutex_unlock(&pmcdev->lock);
 531 }
 532
 533 static int pmc_core_slps0_dbg_show(struct seq_file *s, void *unused)
 534 {
 535         struct pmc_dev *pmcdev = s->private;
 536
 537         pmc_core_slps0_dbg_latch(pmcdev, false);
 538         pmc_core_slps0_display(pmcdev, NULL, s);
 539         pmc_core_slps0_dbg_latch(pmcdev, true);
 540
 541         return 0;
 542 }
 543 DEFINE_SHOW_ATTRIBUTE(pmc_core_slps0_dbg);
 544
 545 static u32 convert_ltr_scale(u32 val)
 546 {
 547         /*
 548          * As per PCIE specification supporting document
 549          * ECN_LatencyTolnReporting_14Aug08.pdf the Latency
 550          * Tolerance Reporting data payload is encoded in a
 551          * 3 bit scale and 10 bit value fields. Values are
 552          * multiplied by the indicated scale to yield an absolute time
 553          * value, expressible in a range from 1 nanosecond to
 554          * 2^25*(2^10-1) = 34,326,183,936 nanoseconds.
 555          *
 556          * scale encoding is as follows:
 557          *
 558          * ----------------------------------------------
 559          * |scale factor        |       Multiplier (ns) |
 560          * ----------------------------------------------
 561          * |    0               |       1               |
 562          * |    1               |       32              |
 563          * |    2               |       1024            |
 564          * |    3               |       32768           |
 565          * |    4               |       1048576         |
 566          * |    5               |       33554432        |
 567          * |    6               |       Invalid         |
 568          * |    7               |       Invalid         |
 569          * ----------------------------------------------
 570          */
 571         if (val > 5) {
 572                 pr_warn("Invalid LTR scale factor.\n");
 573                 return 0;
 574         }
 575
 576         return 1U << (5 * val);
 577 }
 578
 579 static int pmc_core_ltr_show(struct seq_file *s, void *unused)
 580 {
 581         struct pmc_dev *pmcdev = s->private;
 582         const struct pmc_bit_map *map = pmcdev->map->ltr_show_sts;
 583         u64 decoded_snoop_ltr, decoded_non_snoop_ltr;
 584         u32 ltr_raw_data, scale, val;
 585         u16 snoop_ltr, nonsnoop_ltr;
 586         int index;
 587
 588         for (index = 0; map[index].name ; index++) {
 589                 decoded_snoop_ltr = decoded_non_snoop_ltr = 0;
 590                 ltr_raw_data = pmc_core_reg_read(pmcdev,
 591                                                  map[index].bit_mask);
 592                 snoop_ltr = ltr_raw_data & ~MTPMC_MASK;
 593                 nonsnoop_ltr = (ltr_raw_data >> 0x10) & ~MTPMC_MASK;
 594
 595                 if (FIELD_GET(LTR_REQ_NONSNOOP, ltr_raw_data)) {
 596                         scale = FIELD_GET(LTR_DECODED_SCALE, nonsnoop_ltr);
 597                         val = FIELD_GET(LTR_DECODED_VAL, nonsnoop_ltr);
 598                         decoded_non_snoop_ltr = val * convert_ltr_scale(scale);
 599                 }
 600
 601                 if (FIELD_GET(LTR_REQ_SNOOP, ltr_raw_data)) {
 602                         scale = FIELD_GET(LTR_DECODED_SCALE, snoop_ltr);
 603                         val = FIELD_GET(LTR_DECODED_VAL, snoop_ltr);
 604                         decoded_snoop_ltr = val * convert_ltr_scale(scale);
 605                 }
 606
 607                 seq_printf(s, "%-32s\tLTR: RAW: 0x%-16x\tNon-Snoop(ns): %-16llu\tSnoop(ns): %-16llu\n",
 608                            map[index].name, ltr_raw_data,
 609                            decoded_non_snoop_ltr,
 610                            decoded_snoop_ltr);
 611         }
 612         return 0;
 613 }
 614 DEFINE_SHOW_ATTRIBUTE(pmc_core_ltr);
 615
 616 static inline u64 adjust_lpm_residency(struct pmc_dev *pmcdev, u32 offset,
 617                                        const int lpm_adj_x2)
 618 {
 619         u64 lpm_res = pmc_core_reg_read(pmcdev, offset);
 620
 621         return GET_X2_COUNTER((u64)lpm_adj_x2 * lpm_res);
 622 }
 623
 624 static int pmc_core_substate_res_show(struct seq_file *s, void *unused)
 625 {
 626         struct pmc_dev *pmcdev = s->private;
 627         const int lpm_adj_x2 = pmcdev->map->lpm_res_counter_step_x2;
 628         u32 offset = pmcdev->map->lpm_residency_offset;
 629         int i, mode;
 630
 631         seq_printf(s, "%-10s %-15s\n", "Substate", "Residency");
 632
 633         pmc_for_each_mode(i, mode, pmcdev) {
 634                 seq_printf(s, "%-10s %-15llu\n", pmc_lpm_modes[mode],
 635                            adjust_lpm_residency(pmcdev, offset + (4 * mode), lpm_adj_x2));
 636         }
 637
 638         return 0;
 639 }
 640 DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_res);
 641
 642 static int pmc_core_substate_sts_regs_show(struct seq_file *s, void *unused)
 643 {
 644         struct pmc_dev *pmcdev = s->private;
 645         const struct pmc_bit_map **maps = pmcdev->map->lpm_sts;
 646         u32 offset = pmcdev->map->lpm_status_offset;
 647
 648         pmc_core_lpm_display(pmcdev, NULL, s, offset, "STATUS", maps);
 649
 650         return 0;
 651 }
 652 DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_sts_regs);
 653
 654 static int pmc_core_substate_l_sts_regs_show(struct seq_file *s, void *unused)
 655 {
 656         struct pmc_dev *pmcdev = s->private;
 657         const struct pmc_bit_map **maps = pmcdev->map->lpm_sts;
 658         u32 offset = pmcdev->map->lpm_live_status_offset;
 659
 660         pmc_core_lpm_display(pmcdev, NULL, s, offset, "LIVE_STATUS", maps);
 661
 662         return 0;
 663 }
 664 DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_l_sts_regs);
 665
 666 static void pmc_core_substate_req_header_show(struct seq_file *s)
 667 {
 668         struct pmc_dev *pmcdev = s->private;
 669         int i, mode;
 670
 671         seq_printf(s, "%30s |", "Element");
 672         pmc_for_each_mode(i, mode, pmcdev)
 673                 seq_printf(s, " %9s |", pmc_lpm_modes[mode]);
 674
 675         seq_printf(s, " %9s |\n", "Status");
 676 }
 677
 678 static int pmc_core_substate_req_regs_show(struct seq_file *s, void *unused)
 679 {
 680         struct pmc_dev *pmcdev = s->private;
 681         const struct pmc_bit_map **maps = pmcdev->map->lpm_sts;
 682         const struct pmc_bit_map *map;
 683         const int num_maps = pmcdev->map->lpm_num_maps;
 684         u32 sts_offset = pmcdev->map->lpm_status_offset;
 685         u32 *lpm_req_regs = pmcdev->lpm_req_regs;
 686         int mp;
 687
 688         /* Display the header */
 689         pmc_core_substate_req_header_show(s);
 690
 691         /* Loop over maps */
 692         for (mp = 0; mp < num_maps; mp++) {
 693                 u32 req_mask = 0;
 694                 u32 lpm_status;
 695                 int mode, idx, i, len = 32;
 696
 697                 /*
 698                  * Capture the requirements and create a mask so that we only
 699                  * show an element if it's required for at least one of the
 700                  * enabled low power modes
 701                  */
 702                 pmc_for_each_mode(idx, mode, pmcdev)
 703                         req_mask |= lpm_req_regs[mp + (mode * num_maps)];
 704
 705                 /* Get the last latched status for this map */
 706                 lpm_status = pmc_core_reg_read(pmcdev, sts_offset + (mp * 4));
 707
 708                 /*  Loop over elements in this map */
 709                 map = maps[mp];
 710                 for (i = 0; map[i].name && i < len; i++) {
 711                         u32 bit_mask = map[i].bit_mask;
 712
 713                         if (!(bit_mask & req_mask))
 714                                 /*
 715                                  * Not required for any enabled states
 716                                  * so don't display
 717                                  */
 718                                 continue;
 719
 720                         /* Display the element name in the first column */
 721                         seq_printf(s, "%30s |", map[i].name);
 722
 723                         /* Loop over the enabled states and display if required */
 724                         pmc_for_each_mode(idx, mode, pmcdev) {
 725                                 if (lpm_req_regs[mp + (mode * num_maps)] & bit_mask)
 726                                         seq_printf(s, " %9s |",
 727                                                    "Required");
 728                                 else
 729                                         seq_printf(s, " %9s |", " ");
 730                         }
 731
 732                         /* In Status column, show the last captured state of this agent */
 733                         if (lpm_status & bit_mask)
 734                                 seq_printf(s, " %9s |", "Yes");
 735                         else
 736                                 seq_printf(s, " %9s |", " ");
 737
 738                         seq_puts(s, "\n");
 739                 }
 740         }
 741
 742         return 0;
 743 }
 744 DEFINE_SHOW_ATTRIBUTE(pmc_core_substate_req_regs);
 745
 746 static int pmc_core_lpm_latch_mode_show(struct seq_file *s, void *unused)
 747 {
 748         struct pmc_dev *pmcdev = s->private;
 749         bool c10;
 750         u32 reg;
 751         int idx, mode;
 752
 753         reg = pmc_core_reg_read(pmcdev, pmcdev->map->lpm_sts_latch_en_offset);
 754         if (reg & LPM_STS_LATCH_MODE) {
 755                 seq_puts(s, "c10");
 756                 c10 = false;
 757         } else {
 758                 seq_puts(s, "[c10]");
 759                 c10 = true;
 760         }
 761
 762         pmc_for_each_mode(idx, mode, pmcdev) {
 763                 if ((BIT(mode) & reg) && !c10)
 764                         seq_printf(s, " [%s]", pmc_lpm_modes[mode]);
 765                 else
 766                         seq_printf(s, " %s", pmc_lpm_modes[mode]);
 767         }
 768
 769         seq_puts(s, " clear\n");
 770
 771         return 0;
 772 }
 773
 774 static ssize_t pmc_core_lpm_latch_mode_write(struct file *file,
 775                                              const char __user *userbuf,
 776                                              size_t count, loff_t *ppos)
 777 {
 778         struct seq_file *s = file->private_data;
 779         struct pmc_dev *pmcdev = s->private;
 780         bool clear = false, c10 = false;
 781         unsigned char buf[8];
 782         int idx, m, mode;
 783         u32 reg;
 784
 785         if (count > sizeof(buf) - 1)
 786                 return -EINVAL;
 787         if (copy_from_user(buf, userbuf, count))
 788                 return -EFAULT;
 789         buf[count] = '\0';
 790
 791         /*
 792          * Allowed strings are:
 793          *      Any enabled substate, e.g. 'S0i2.0'
 794          *      'c10'
 795          *      'clear'
 796          */
 797         mode = sysfs_match_string(pmc_lpm_modes, buf);
 798
 799         /* Check string matches enabled mode */
 800         pmc_for_each_mode(idx, m, pmcdev)
 801                 if (mode == m)
 802                         break;
 803
 804         if (mode != m || mode < 0) {
 805                 if (sysfs_streq(buf, "clear"))
 806                         clear = true;
 807                 else if (sysfs_streq(buf, "c10"))
 808                         c10 = true;
 809                 else
 810                         return -EINVAL;
 811         }
 812
 813         if (clear) {
 814                 mutex_lock(&pmcdev->lock);
 815
 816                 reg = pmc_core_reg_read(pmcdev, pmcdev->map->etr3_offset);
 817                 reg |= ETR3_CLEAR_LPM_EVENTS;
 818                 pmc_core_reg_write(pmcdev, pmcdev->map->etr3_offset, reg);
 819
 820                 mutex_unlock(&pmcdev->lock);
 821
 822                 return count;
 823         }
 824
 825         if (c10) {
 826                 mutex_lock(&pmcdev->lock);
 827
 828                 reg = pmc_core_reg_read(pmcdev, pmcdev->map->lpm_sts_latch_en_offset);
 829                 reg &= ~LPM_STS_LATCH_MODE;
 830                 pmc_core_reg_write(pmcdev, pmcdev->map->lpm_sts_latch_en_offset, reg);
 831
 832                 mutex_unlock(&pmcdev->lock);
 833
 834                 return count;
 835         }
 836
 837         /*
 838          * For LPM mode latching we set the latch enable bit and selected mode
 839          * and clear everything else.
 840          */
 841         reg = LPM_STS_LATCH_MODE | BIT(mode);
 842         mutex_lock(&pmcdev->lock);
 843         pmc_core_reg_write(pmcdev, pmcdev->map->lpm_sts_latch_en_offset, reg);
 844         mutex_unlock(&pmcdev->lock);
 845
 846         return count;
 847 }
 848 DEFINE_PMC_CORE_ATTR_WRITE(pmc_core_lpm_latch_mode);
 849
 850 static int pmc_core_pkgc_show(struct seq_file *s, void *unused)
 851 {
 852         struct pmc_dev *pmcdev = s->private;
 853         const struct pmc_bit_map *map = pmcdev->map->msr_sts;
 854         u64 pcstate_count;
 855         int index;
 856
 857         for (index = 0; map[index].name ; index++) {
 858                 if (rdmsrl_safe(map[index].bit_mask, &pcstate_count))
 859                         continue;
 860
 861                 pcstate_count *= 1000;
 862                 do_div(pcstate_count, tsc_khz);
 863                 seq_printf(s, "%-8s : %llu\n", map[index].name,
 864                            pcstate_count);
 865         }
 866
 867         return 0;
 868 }
 869 DEFINE_SHOW_ATTRIBUTE(pmc_core_pkgc);
 870
 871 static bool pmc_core_pri_verify(u32 lpm_pri, u8 *mode_order)
 872 {
 873         int i, j;
 874
 875         if (!lpm_pri)
 876                 return false;
 877         /*
 878          * Each byte contains the priority level for 2 modes (7:4 and 3:0).
 879          * In a 32 bit register this allows for describing 8 modes. Store the
 880          * levels and look for values out of range.
 881          */
 882         for (i = 0; i < 8; i++) {
 883                 int level = lpm_pri & GENMASK(3, 0);
 884
 885                 if (level >= LPM_MAX_NUM_MODES)
 886                         return false;
 887
 888                 mode_order[i] = level;
 889                 lpm_pri >>= 4;
 890         }
 891
 892         /* Check that we have unique values */
 893         for (i = 0; i < LPM_MAX_NUM_MODES - 1; i++)
 894                 for (j = i + 1; j < LPM_MAX_NUM_MODES; j++)
 895                         if (mode_order[i] == mode_order[j])
 896                                 return false;
 897
 898         return true;
 899 }
 900
 901 static void pmc_core_get_low_power_modes(struct platform_device *pdev)
 902 {
 903         struct pmc_dev *pmcdev = platform_get_drvdata(pdev);
 904         u8 pri_order[LPM_MAX_NUM_MODES] = LPM_DEFAULT_PRI;
 905         u8 mode_order[LPM_MAX_NUM_MODES];
 906         u32 lpm_pri;
 907         u32 lpm_en;
 908         int mode, i, p;
 909
 910         /* Use LPM Maps to indicate support for substates */
 911         if (!pmcdev->map->lpm_num_maps)
 912                 return;
 913
 914         lpm_en = pmc_core_reg_read(pmcdev, pmcdev->map->lpm_en_offset);
 915         /* For MTL, BIT 31 is not an lpm mode but a enable bit.
 916          * Lower byte is enough to cover the number of lpm modes for all
 917          * platforms and hence mask the upper 3 bytes.
 918          */
 919         pmcdev->num_lpm_modes = hweight32(lpm_en & 0xFF);
 920
 921         /* Read 32 bit LPM_PRI register */
 922         lpm_pri = pmc_core_reg_read(pmcdev, pmcdev->map->lpm_priority_offset);
 923
 924
 925         /*
 926          * If lpm_pri value passes verification, then override the default
 927          * modes here. Otherwise stick with the default.
 928          */
 929         if (pmc_core_pri_verify(lpm_pri, mode_order))
 930                 /* Get list of modes in priority order */
 931                 for (mode = 0; mode < LPM_MAX_NUM_MODES; mode++)
 932                         pri_order[mode_order[mode]] = mode;
 933         else
 934                 dev_warn(&pdev->dev, "Assuming a default substate order for this platform\n");
 935
 936         /*
 937          * Loop through all modes from lowest to highest priority,
 938          * and capture all enabled modes in order
 939          */
 940         i = 0;
 941         for (p = LPM_MAX_NUM_MODES - 1; p >= 0; p--) {
 942                 int mode = pri_order[p];
 943
 944                 if (!(BIT(mode) & lpm_en))
 945                         continue;
 946
 947                 pmcdev->lpm_en_modes[i++] = mode;
 948         }
 949 }
 950
 951 static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
 952 {
 953         debugfs_remove_recursive(pmcdev->dbgfs_dir);
 954 }
 955
 956 static void pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
 957 {
 958         struct dentry *dir;
 959
 960         dir = debugfs_create_dir("pmc_core", NULL);
 961         pmcdev->dbgfs_dir = dir;
 962
 963         debugfs_create_file("slp_s0_residency_usec", 0444, dir, pmcdev,
 964                             &pmc_core_dev_state);
 965
 966         if (pmcdev->map->pfear_sts)
 967                 debugfs_create_file("pch_ip_power_gating_status", 0444, dir,
 968                                     pmcdev, &pmc_core_ppfear_fops);
 969
 970         debugfs_create_file("ltr_ignore", 0644, dir, pmcdev,
 971                             &pmc_core_ltr_ignore_ops);
 972
 973         debugfs_create_file("ltr_show", 0444, dir, pmcdev, &pmc_core_ltr_fops);
 974
 975         debugfs_create_file("package_cstate_show", 0444, dir, pmcdev,
 976                             &pmc_core_pkgc_fops);
 977
 978         if (pmcdev->map->pll_sts)
 979                 debugfs_create_file("pll_status", 0444, dir, pmcdev,
 980                                     &pmc_core_pll_fops);
 981
 982         if (pmcdev->map->mphy_sts)
 983                 debugfs_create_file("mphy_core_lanes_power_gating_status",
 984                                     0444, dir, pmcdev,
 985                                     &pmc_core_mphy_pg_fops);
 986
 987         if (pmcdev->map->slps0_dbg_maps) {
 988                 debugfs_create_file("slp_s0_debug_status", 0444,
 989                                     dir, pmcdev,
 990                                     &pmc_core_slps0_dbg_fops);
 991
 992                 debugfs_create_bool("slp_s0_dbg_latch", 0644,
 993                                     dir, &slps0_dbg_latch);
 994         }
 995
 996         if (pmcdev->map->lpm_en_offset) {
 997                 debugfs_create_file("substate_residencies", 0444,
 998                                     pmcdev->dbgfs_dir, pmcdev,
 999                                     &pmc_core_substate_res_fops);
1000         }
1001
1002         if (pmcdev->map->lpm_status_offset) {
1003                 debugfs_create_file("substate_status_registers", 0444,
1004                                     pmcdev->dbgfs_dir, pmcdev,
1005                                     &pmc_core_substate_sts_regs_fops);
1006                 debugfs_create_file("substate_live_status_registers", 0444,
1007                                     pmcdev->dbgfs_dir, pmcdev,
1008                                     &pmc_core_substate_l_sts_regs_fops);
1009                 debugfs_create_file("lpm_latch_mode", 0644,
1010                                     pmcdev->dbgfs_dir, pmcdev,
1011                                     &pmc_core_lpm_latch_mode_fops);
1012         }
1013
1014         if (pmcdev->lpm_req_regs) {
1015                 debugfs_create_file("substate_requirements", 0444,
1016                                     pmcdev->dbgfs_dir, pmcdev,
1017                                     &pmc_core_substate_req_regs_fops);
1018         }
1019 }
1020
1021 static const struct x86_cpu_id intel_pmc_core_ids[] = {
1022         X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L,           spt_core_init),
1023         X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE,             spt_core_init),
1024         X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L,          spt_core_init),
1025         X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE,            spt_core_init),
1026         X86_MATCH_INTEL_FAM6_MODEL(CANNONLAKE_L,        cnp_core_init),
1027         X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L,           icl_core_init),
1028         X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_NNPI,        icl_core_init),
1029         X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE,           cnp_core_init),
1030         X86_MATCH_INTEL_FAM6_MODEL(COMETLAKE_L,         cnp_core_init),
1031         X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L,         tgl_core_init),
1032         X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE,           tgl_core_init),
1033         X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT,        tgl_core_init),
1034         X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L,      icl_core_init),
1035         X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE,          tgl_core_init),
1036         X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L,         tgl_core_init),
1037         X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_N,         tgl_core_init),
1038         X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE,           adl_core_init),
1039         X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_P,        tgl_core_init),
1040         X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE,          adl_core_init),
1041         X86_MATCH_INTEL_FAM6_MODEL(RAPTORLAKE_S,        adl_core_init),
1042         X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE,          mtl_core_init),
1043         X86_MATCH_INTEL_FAM6_MODEL(METEORLAKE_L,        mtl_core_init),
1044         {}
1045 };
1046
1047 MODULE_DEVICE_TABLE(x86cpu, intel_pmc_core_ids);
1048
1049 static const struct pci_device_id pmc_pci_ids[] = {
1050         { PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID) },
1051         { }
1052 };
1053
1054 /*
1055  * This quirk can be used on those platforms where
1056  * the platform BIOS enforces 24Mhz crystal to shutdown
1057  * before PMC can assert SLP_S0#.
1058  */
1059 static bool xtal_ignore;
1060 static int quirk_xtal_ignore(const struct dmi_system_id *id)
1061 {
1062         xtal_ignore = true;
1063         return 0;
1064 }
1065
1066 static void pmc_core_xtal_ignore(struct pmc_dev *pmcdev)
1067 {
1068         u32 value;
1069
1070         value = pmc_core_reg_read(pmcdev, pmcdev->map->pm_vric1_offset);
1071         /* 24MHz Crystal Shutdown Qualification Disable */
1072         value |= SPT_PMC_VRIC1_XTALSDQDIS;
1073         /* Low Voltage Mode Enable */
1074         value &= ~SPT_PMC_VRIC1_SLPS0LVEN;
1075         pmc_core_reg_write(pmcdev, pmcdev->map->pm_vric1_offset, value);
1076 }
1077
1078 static const struct dmi_system_id pmc_core_dmi_table[]  = {
1079         {
1080         .callback = quirk_xtal_ignore,
1081         .ident = "HP Elite x2 1013 G3",
1082         .matches = {
1083                 DMI_MATCH(DMI_SYS_VENDOR, "HP"),
1084                 DMI_MATCH(DMI_PRODUCT_NAME, "HP Elite x2 1013 G3"),
1085                 },
1086         },
1087         {}
1088 };
1089
1090 static void pmc_core_do_dmi_quirks(struct pmc_dev *pmcdev)
1091 {
1092         dmi_check_system(pmc_core_dmi_table);
1093
1094         if (xtal_ignore)
1095                 pmc_core_xtal_ignore(pmcdev);
1096 }
1097
1098 static int pmc_core_probe(struct platform_device *pdev)
1099 {
1100         static bool device_initialized;
1101         struct pmc_dev *pmcdev;
1102         const struct x86_cpu_id *cpu_id;
1103         void (*core_init)(struct pmc_dev *pmcdev);
1104         u64 slp_s0_addr;
1105
1106         if (device_initialized)
1107                 return -ENODEV;
1108
1109         pmcdev = devm_kzalloc(&pdev->dev, sizeof(*pmcdev), GFP_KERNEL);
1110         if (!pmcdev)
1111                 return -ENOMEM;
1112
1113         platform_set_drvdata(pdev, pmcdev);
1114         pmcdev->pdev = pdev;
1115
1116         cpu_id = x86_match_cpu(intel_pmc_core_ids);
1117         if (!cpu_id)
1118                 return -ENODEV;
1119
1120         core_init = (void  (*)(struct pmc_dev *))cpu_id->driver_data;
1121
1122         /*
1123          * Coffee Lake has CPU ID of Kaby Lake and Cannon Lake PCH. So here
1124          * Sunrisepoint PCH regmap can't be used. Use Cannon Lake PCH regmap
1125          * in this case.
1126          */
1127         if (core_init == spt_core_init && !pci_dev_present(pmc_pci_ids))
1128                 core_init = cnp_core_init;
1129
1130         mutex_init(&pmcdev->lock);
1131         core_init(pmcdev);
1132
1133
1134         if (lpit_read_residency_count_address(&slp_s0_addr)) {
1135                 pmcdev->base_addr = PMC_BASE_ADDR_DEFAULT;
1136
1137                 if (page_is_ram(PHYS_PFN(pmcdev->base_addr)))
1138                         return -ENODEV;
1139         } else {
1140                 pmcdev->base_addr = slp_s0_addr - pmcdev->map->slp_s0_offset;
1141         }
1142
1143         pmcdev->regbase = ioremap(pmcdev->base_addr,
1144                                   pmcdev->map->regmap_length);
1145         if (!pmcdev->regbase)
1146                 return -ENOMEM;
1147
1148         if (pmcdev->core_configure)
1149                 pmcdev->core_configure(pmcdev);
1150
1151         pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit(pmcdev);
1152         pmc_core_get_low_power_modes(pdev);
1153         pmc_core_do_dmi_quirks(pmcdev);
1154
1155         pmc_core_dbgfs_register(pmcdev);
1156         pm_report_max_hw_sleep(FIELD_MAX(SLP_S0_RES_COUNTER_MASK) *
1157                                pmc_core_adjust_slp_s0_step(pmcdev, 1));
1158
1159         device_initialized = true;
1160         dev_info(&pdev->dev, " initialized\n");
1161
1162         return 0;
1163 }
1164
1165 static void pmc_core_remove(struct platform_device *pdev)
1166 {
1167         struct pmc_dev *pmcdev = platform_get_drvdata(pdev);
1168
1169         pmc_core_dbgfs_unregister(pmcdev);
1170         platform_set_drvdata(pdev, NULL);
1171         mutex_destroy(&pmcdev->lock);
1172         iounmap(pmcdev->regbase);
1173 }
1174
1175 static bool warn_on_s0ix_failures;
1176 module_param(warn_on_s0ix_failures, bool, 0644);
1177 MODULE_PARM_DESC(warn_on_s0ix_failures, "Check and warn for S0ix failures");
1178
1179 static __maybe_unused int pmc_core_suspend(struct device *dev)
1180 {
1181         struct pmc_dev *pmcdev = dev_get_drvdata(dev);
1182
1183         /* Check if the syspend will actually use S0ix */
1184         if (pm_suspend_via_firmware())
1185                 return 0;
1186
1187         /* Save PC10 residency for checking later */
1188         if (rdmsrl_safe(MSR_PKG_C10_RESIDENCY, &pmcdev->pc10_counter))
1189                 return -EIO;
1190
1191         /* Save S0ix residency for checking later */
1192         if (pmc_core_dev_state_get(pmcdev, &pmcdev->s0ix_counter))
1193                 return -EIO;
1194
1195         return 0;
1196 }
1197
1198 static inline bool pmc_core_is_pc10_failed(struct pmc_dev *pmcdev)
1199 {
1200         u64 pc10_counter;
1201
1202         if (rdmsrl_safe(MSR_PKG_C10_RESIDENCY, &pc10_counter))
1203                 return false;
1204
1205         if (pc10_counter == pmcdev->pc10_counter)
1206                 return true;
1207
1208         return false;
1209 }
1210
1211 static inline bool pmc_core_is_s0ix_failed(struct pmc_dev *pmcdev)
1212 {
1213         u64 s0ix_counter;
1214
1215         if (pmc_core_dev_state_get(pmcdev, &s0ix_counter))
1216                 return false;
1217
1218         pm_report_hw_sleep_time((u32)(s0ix_counter - pmcdev->s0ix_counter));
1219
1220         if (s0ix_counter == pmcdev->s0ix_counter)
1221                 return true;
1222
1223         return false;
1224 }
1225
1226 static __maybe_unused int pmc_core_resume(struct device *dev)
1227 {
1228         struct pmc_dev *pmcdev = dev_get_drvdata(dev);
1229         const struct pmc_bit_map **maps = pmcdev->map->lpm_sts;
1230         int offset = pmcdev->map->lpm_status_offset;
1231
1232         /* Check if the syspend used S0ix */
1233         if (pm_suspend_via_firmware())
1234                 return 0;
1235
1236         if (!pmc_core_is_s0ix_failed(pmcdev))
1237                 return 0;
1238
1239         if (!warn_on_s0ix_failures)
1240                 return 0;
1241
1242         if (pmc_core_is_pc10_failed(pmcdev)) {
1243                 /* S0ix failed because of PC10 entry failure */
1244                 dev_info(dev, "CPU did not enter PC10!!! (PC10 cnt=0x%llx)\n",
1245                          pmcdev->pc10_counter);
1246                 return 0;
1247         }
1248
1249         /* The real interesting case - S0ix failed - lets ask PMC why. */
1250         dev_warn(dev, "CPU did not enter SLP_S0!!! (S0ix cnt=%llu)\n",
1251                  pmcdev->s0ix_counter);
1252         if (pmcdev->map->slps0_dbg_maps)
1253                 pmc_core_slps0_display(pmcdev, dev, NULL);
1254         if (pmcdev->map->lpm_sts)
1255                 pmc_core_lpm_display(pmcdev, dev, NULL, offset, "STATUS", maps);
1256
1257         return 0;
1258 }
1259
1260 static const struct dev_pm_ops pmc_core_pm_ops = {
1261         SET_LATE_SYSTEM_SLEEP_PM_OPS(pmc_core_suspend, pmc_core_resume)
1262 };
1263
1264 static const struct acpi_device_id pmc_core_acpi_ids[] = {
1265         {"INT33A1", 0}, /* _HID for Intel Power Engine, _CID PNP0D80*/
1266         { }
1267 };
1268 MODULE_DEVICE_TABLE(acpi, pmc_core_acpi_ids);
1269
1270 static struct platform_driver pmc_core_driver = {
1271         .driver = {
1272                 .name = "intel_pmc_core",
1273                 .acpi_match_table = ACPI_PTR(pmc_core_acpi_ids),
1274                 .pm = &pmc_core_pm_ops,
1275                 .dev_groups = pmc_dev_groups,
1276         },
1277         .probe = pmc_core_probe,
1278         .remove_new = pmc_core_remove,
1279 };
1280
1281 module_platform_driver(pmc_core_driver);
1282
1283 MODULE_LICENSE("GPL v2");
1284 MODULE_DESCRIPTION("Intel PMC Core Driver");