drivers/clk/qcom/gcc-msm8660.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2013, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/kernel.h>
   7 #include <linux/bitops.h>
   8 #include <linux/err.h>
   9 #include <linux/platform_device.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_device.h>
  13 #include <linux/clk-provider.h>
  14 #include <linux/regmap.h>
  15 #include <linux/reset-controller.h>
  16
  17 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
  18 #include <dt-bindings/reset/qcom,gcc-msm8660.h>
  19
  20 #include "common.h"
  21 #include "clk-regmap.h"
  22 #include "clk-pll.h"
  23 #include "clk-rcg.h"
  24 #include "clk-branch.h"
  25 #include "reset.h"
  26
  27 static struct clk_pll pll8 = {
  28         .l_reg = 0x3144,
  29         .m_reg = 0x3148,
  30         .n_reg = 0x314c,
  31         .config_reg = 0x3154,
  32         .mode_reg = 0x3140,
  33         .status_reg = 0x3158,
  34         .status_bit = 16,
  35         .clkr.hw.init = &(struct clk_init_data){
  36                 .name = "pll8",
  37                 .parent_data = &(const struct clk_parent_data){
  38                         .fw_name = "pxo", .name = "pxo_board",
  39                 },
  40                 .num_parents = 1,
  41                 .ops = &clk_pll_ops,
  42         },
  43 };
  44
  45 static struct clk_regmap pll8_vote = {
  46         .enable_reg = 0x34c0,
  47         .enable_mask = BIT(8),
  48         .hw.init = &(struct clk_init_data){
  49                 .name = "pll8_vote",
  50                 .parent_hws = (const struct clk_hw*[]){
  51                         &pll8.clkr.hw
  52                 },
  53                 .num_parents = 1,
  54                 .ops = &clk_pll_vote_ops,
  55         },
  56 };
  57
  58 enum {
  59         P_PXO,
  60         P_PLL8,
  61         P_CXO,
  62 };
  63
  64 static const struct parent_map gcc_pxo_pll8_map[] = {
  65         { P_PXO, 0 },
  66         { P_PLL8, 3 }
  67 };
  68
  69 static const struct clk_parent_data gcc_pxo_pll8[] = {
  70         { .fw_name = "pxo", .name = "pxo_board" },
  71         { .hw = &pll8_vote.hw },
  72 };
  73
  74 static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
  75         { P_PXO, 0 },
  76         { P_PLL8, 3 },
  77         { P_CXO, 5 }
  78 };
  79
  80 static const struct clk_parent_data gcc_pxo_pll8_cxo[] = {
  81         { .fw_name = "pxo", .name = "pxo_board" },
  82         { .hw = &pll8_vote.hw },
  83         { .fw_name = "cxo", .name = "cxo_board" },
  84 };
  85
  86 static struct freq_tbl clk_tbl_gsbi_uart[] = {
  87         {  1843200, P_PLL8, 2,  6, 625 },
  88         {  3686400, P_PLL8, 2, 12, 625 },
  89         {  7372800, P_PLL8, 2, 24, 625 },
  90         { 14745600, P_PLL8, 2, 48, 625 },
  91         { 16000000, P_PLL8, 4,  1,   6 },
  92         { 24000000, P_PLL8, 4,  1,   4 },
  93         { 32000000, P_PLL8, 4,  1,   3 },
  94         { 40000000, P_PLL8, 1,  5,  48 },
  95         { 46400000, P_PLL8, 1, 29, 240 },
  96         { 48000000, P_PLL8, 4,  1,   2 },
  97         { 51200000, P_PLL8, 1,  2,  15 },
  98         { 56000000, P_PLL8, 1,  7,  48 },
  99         { 58982400, P_PLL8, 1, 96, 625 },
 100         { 64000000, P_PLL8, 2,  1,   3 },
 101         { }
 102 };
 103
 104 static struct clk_rcg gsbi1_uart_src = {
 105         .ns_reg = 0x29d4,
 106         .md_reg = 0x29d0,
 107         .mn = {
 108                 .mnctr_en_bit = 8,
 109                 .mnctr_reset_bit = 7,
 110                 .mnctr_mode_shift = 5,
 111                 .n_val_shift = 16,
 112                 .m_val_shift = 16,
 113                 .width = 16,
 114         },
 115         .p = {
 116                 .pre_div_shift = 3,
 117                 .pre_div_width = 2,
 118         },
 119         .s = {
 120                 .src_sel_shift = 0,
 121                 .parent_map = gcc_pxo_pll8_map,
 122         },
 123         .freq_tbl = clk_tbl_gsbi_uart,
 124         .clkr = {
 125                 .enable_reg = 0x29d4,
 126                 .enable_mask = BIT(11),
 127                 .hw.init = &(struct clk_init_data){
 128                         .name = "gsbi1_uart_src",
 129                         .parent_data = gcc_pxo_pll8,
 130                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 131                         .ops = &clk_rcg_ops,
 132                         .flags = CLK_SET_PARENT_GATE,
 133                 },
 134         },
 135 };
 136
 137 static struct clk_branch gsbi1_uart_clk = {
 138         .halt_reg = 0x2fcc,
 139         .halt_bit = 10,
 140         .clkr = {
 141                 .enable_reg = 0x29d4,
 142                 .enable_mask = BIT(9),
 143                 .hw.init = &(struct clk_init_data){
 144                         .name = "gsbi1_uart_clk",
 145                         .parent_hws = (const struct clk_hw*[]){
 146                                 &gsbi1_uart_src.clkr.hw
 147                         },
 148                         .num_parents = 1,
 149                         .ops = &clk_branch_ops,
 150                         .flags = CLK_SET_RATE_PARENT,
 151                 },
 152         },
 153 };
 154
 155 static struct clk_rcg gsbi2_uart_src = {
 156         .ns_reg = 0x29f4,
 157         .md_reg = 0x29f0,
 158         .mn = {
 159                 .mnctr_en_bit = 8,
 160                 .mnctr_reset_bit = 7,
 161                 .mnctr_mode_shift = 5,
 162                 .n_val_shift = 16,
 163                 .m_val_shift = 16,
 164                 .width = 16,
 165         },
 166         .p = {
 167                 .pre_div_shift = 3,
 168                 .pre_div_width = 2,
 169         },
 170         .s = {
 171                 .src_sel_shift = 0,
 172                 .parent_map = gcc_pxo_pll8_map,
 173         },
 174         .freq_tbl = clk_tbl_gsbi_uart,
 175         .clkr = {
 176                 .enable_reg = 0x29f4,
 177                 .enable_mask = BIT(11),
 178                 .hw.init = &(struct clk_init_data){
 179                         .name = "gsbi2_uart_src",
 180                         .parent_data = gcc_pxo_pll8,
 181                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 182                         .ops = &clk_rcg_ops,
 183                         .flags = CLK_SET_PARENT_GATE,
 184                 },
 185         },
 186 };
 187
 188 static struct clk_branch gsbi2_uart_clk = {
 189         .halt_reg = 0x2fcc,
 190         .halt_bit = 6,
 191         .clkr = {
 192                 .enable_reg = 0x29f4,
 193                 .enable_mask = BIT(9),
 194                 .hw.init = &(struct clk_init_data){
 195                         .name = "gsbi2_uart_clk",
 196                         .parent_hws = (const struct clk_hw*[]){
 197                                 &gsbi2_uart_src.clkr.hw
 198                         },
 199                         .num_parents = 1,
 200                         .ops = &clk_branch_ops,
 201                         .flags = CLK_SET_RATE_PARENT,
 202                 },
 203         },
 204 };
 205
 206 static struct clk_rcg gsbi3_uart_src = {
 207         .ns_reg = 0x2a14,
 208         .md_reg = 0x2a10,
 209         .mn = {
 210                 .mnctr_en_bit = 8,
 211                 .mnctr_reset_bit = 7,
 212                 .mnctr_mode_shift = 5,
 213                 .n_val_shift = 16,
 214                 .m_val_shift = 16,
 215                 .width = 16,
 216         },
 217         .p = {
 218                 .pre_div_shift = 3,
 219                 .pre_div_width = 2,
 220         },
 221         .s = {
 222                 .src_sel_shift = 0,
 223                 .parent_map = gcc_pxo_pll8_map,
 224         },
 225         .freq_tbl = clk_tbl_gsbi_uart,
 226         .clkr = {
 227                 .enable_reg = 0x2a14,
 228                 .enable_mask = BIT(11),
 229                 .hw.init = &(struct clk_init_data){
 230                         .name = "gsbi3_uart_src",
 231                         .parent_data = gcc_pxo_pll8,
 232                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 233                         .ops = &clk_rcg_ops,
 234                         .flags = CLK_SET_PARENT_GATE,
 235                 },
 236         },
 237 };
 238
 239 static struct clk_branch gsbi3_uart_clk = {
 240         .halt_reg = 0x2fcc,
 241         .halt_bit = 2,
 242         .clkr = {
 243                 .enable_reg = 0x2a14,
 244                 .enable_mask = BIT(9),
 245                 .hw.init = &(struct clk_init_data){
 246                         .name = "gsbi3_uart_clk",
 247                         .parent_hws = (const struct clk_hw*[]){
 248                                 &gsbi3_uart_src.clkr.hw
 249                         },
 250                         .num_parents = 1,
 251                         .ops = &clk_branch_ops,
 252                         .flags = CLK_SET_RATE_PARENT,
 253                 },
 254         },
 255 };
 256
 257 static struct clk_rcg gsbi4_uart_src = {
 258         .ns_reg = 0x2a34,
 259         .md_reg = 0x2a30,
 260         .mn = {
 261                 .mnctr_en_bit = 8,
 262                 .mnctr_reset_bit = 7,
 263                 .mnctr_mode_shift = 5,
 264                 .n_val_shift = 16,
 265                 .m_val_shift = 16,
 266                 .width = 16,
 267         },
 268         .p = {
 269                 .pre_div_shift = 3,
 270                 .pre_div_width = 2,
 271         },
 272         .s = {
 273                 .src_sel_shift = 0,
 274                 .parent_map = gcc_pxo_pll8_map,
 275         },
 276         .freq_tbl = clk_tbl_gsbi_uart,
 277         .clkr = {
 278                 .enable_reg = 0x2a34,
 279                 .enable_mask = BIT(11),
 280                 .hw.init = &(struct clk_init_data){
 281                         .name = "gsbi4_uart_src",
 282                         .parent_data = gcc_pxo_pll8,
 283                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 284                         .ops = &clk_rcg_ops,
 285                         .flags = CLK_SET_PARENT_GATE,
 286                 },
 287         },
 288 };
 289
 290 static struct clk_branch gsbi4_uart_clk = {
 291         .halt_reg = 0x2fd0,
 292         .halt_bit = 26,
 293         .clkr = {
 294                 .enable_reg = 0x2a34,
 295                 .enable_mask = BIT(9),
 296                 .hw.init = &(struct clk_init_data){
 297                         .name = "gsbi4_uart_clk",
 298                         .parent_hws = (const struct clk_hw*[]){
 299                                 &gsbi4_uart_src.clkr.hw
 300                         },
 301                         .num_parents = 1,
 302                         .ops = &clk_branch_ops,
 303                         .flags = CLK_SET_RATE_PARENT,
 304                 },
 305         },
 306 };
 307
 308 static struct clk_rcg gsbi5_uart_src = {
 309         .ns_reg = 0x2a54,
 310         .md_reg = 0x2a50,
 311         .mn = {
 312                 .mnctr_en_bit = 8,
 313                 .mnctr_reset_bit = 7,
 314                 .mnctr_mode_shift = 5,
 315                 .n_val_shift = 16,
 316                 .m_val_shift = 16,
 317                 .width = 16,
 318         },
 319         .p = {
 320                 .pre_div_shift = 3,
 321                 .pre_div_width = 2,
 322         },
 323         .s = {
 324                 .src_sel_shift = 0,
 325                 .parent_map = gcc_pxo_pll8_map,
 326         },
 327         .freq_tbl = clk_tbl_gsbi_uart,
 328         .clkr = {
 329                 .enable_reg = 0x2a54,
 330                 .enable_mask = BIT(11),
 331                 .hw.init = &(struct clk_init_data){
 332                         .name = "gsbi5_uart_src",
 333                         .parent_data = gcc_pxo_pll8,
 334                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 335                         .ops = &clk_rcg_ops,
 336                         .flags = CLK_SET_PARENT_GATE,
 337                 },
 338         },
 339 };
 340
 341 static struct clk_branch gsbi5_uart_clk = {
 342         .halt_reg = 0x2fd0,
 343         .halt_bit = 22,
 344         .clkr = {
 345                 .enable_reg = 0x2a54,
 346                 .enable_mask = BIT(9),
 347                 .hw.init = &(struct clk_init_data){
 348                         .name = "gsbi5_uart_clk",
 349                         .parent_hws = (const struct clk_hw*[]){
 350                                 &gsbi5_uart_src.clkr.hw
 351                         },
 352                         .num_parents = 1,
 353                         .ops = &clk_branch_ops,
 354                         .flags = CLK_SET_RATE_PARENT,
 355                 },
 356         },
 357 };
 358
 359 static struct clk_rcg gsbi6_uart_src = {
 360         .ns_reg = 0x2a74,
 361         .md_reg = 0x2a70,
 362         .mn = {
 363                 .mnctr_en_bit = 8,
 364                 .mnctr_reset_bit = 7,
 365                 .mnctr_mode_shift = 5,
 366                 .n_val_shift = 16,
 367                 .m_val_shift = 16,
 368                 .width = 16,
 369         },
 370         .p = {
 371                 .pre_div_shift = 3,
 372                 .pre_div_width = 2,
 373         },
 374         .s = {
 375                 .src_sel_shift = 0,
 376                 .parent_map = gcc_pxo_pll8_map,
 377         },
 378         .freq_tbl = clk_tbl_gsbi_uart,
 379         .clkr = {
 380                 .enable_reg = 0x2a74,
 381                 .enable_mask = BIT(11),
 382                 .hw.init = &(struct clk_init_data){
 383                         .name = "gsbi6_uart_src",
 384                         .parent_data = gcc_pxo_pll8,
 385                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 386                         .ops = &clk_rcg_ops,
 387                         .flags = CLK_SET_PARENT_GATE,
 388                 },
 389         },
 390 };
 391
 392 static struct clk_branch gsbi6_uart_clk = {
 393         .halt_reg = 0x2fd0,
 394         .halt_bit = 18,
 395         .clkr = {
 396                 .enable_reg = 0x2a74,
 397                 .enable_mask = BIT(9),
 398                 .hw.init = &(struct clk_init_data){
 399                         .name = "gsbi6_uart_clk",
 400                         .parent_hws = (const struct clk_hw*[]){
 401                                 &gsbi6_uart_src.clkr.hw
 402                         },
 403                         .num_parents = 1,
 404                         .ops = &clk_branch_ops,
 405                         .flags = CLK_SET_RATE_PARENT,
 406                 },
 407         },
 408 };
 409
 410 static struct clk_rcg gsbi7_uart_src = {
 411         .ns_reg = 0x2a94,
 412         .md_reg = 0x2a90,
 413         .mn = {
 414                 .mnctr_en_bit = 8,
 415                 .mnctr_reset_bit = 7,
 416                 .mnctr_mode_shift = 5,
 417                 .n_val_shift = 16,
 418                 .m_val_shift = 16,
 419                 .width = 16,
 420         },
 421         .p = {
 422                 .pre_div_shift = 3,
 423                 .pre_div_width = 2,
 424         },
 425         .s = {
 426                 .src_sel_shift = 0,
 427                 .parent_map = gcc_pxo_pll8_map,
 428         },
 429         .freq_tbl = clk_tbl_gsbi_uart,
 430         .clkr = {
 431                 .enable_reg = 0x2a94,
 432                 .enable_mask = BIT(11),
 433                 .hw.init = &(struct clk_init_data){
 434                         .name = "gsbi7_uart_src",
 435                         .parent_data = gcc_pxo_pll8,
 436                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 437                         .ops = &clk_rcg_ops,
 438                         .flags = CLK_SET_PARENT_GATE,
 439                 },
 440         },
 441 };
 442
 443 static struct clk_branch gsbi7_uart_clk = {
 444         .halt_reg = 0x2fd0,
 445         .halt_bit = 14,
 446         .clkr = {
 447                 .enable_reg = 0x2a94,
 448                 .enable_mask = BIT(9),
 449                 .hw.init = &(struct clk_init_data){
 450                         .name = "gsbi7_uart_clk",
 451                         .parent_hws = (const struct clk_hw*[]){
 452                                 &gsbi7_uart_src.clkr.hw
 453                         },
 454                         .num_parents = 1,
 455                         .ops = &clk_branch_ops,
 456                         .flags = CLK_SET_RATE_PARENT,
 457                 },
 458         },
 459 };
 460
 461 static struct clk_rcg gsbi8_uart_src = {
 462         .ns_reg = 0x2ab4,
 463         .md_reg = 0x2ab0,
 464         .mn = {
 465                 .mnctr_en_bit = 8,
 466                 .mnctr_reset_bit = 7,
 467                 .mnctr_mode_shift = 5,
 468                 .n_val_shift = 16,
 469                 .m_val_shift = 16,
 470                 .width = 16,
 471         },
 472         .p = {
 473                 .pre_div_shift = 3,
 474                 .pre_div_width = 2,
 475         },
 476         .s = {
 477                 .src_sel_shift = 0,
 478                 .parent_map = gcc_pxo_pll8_map,
 479         },
 480         .freq_tbl = clk_tbl_gsbi_uart,
 481         .clkr = {
 482                 .enable_reg = 0x2ab4,
 483                 .enable_mask = BIT(11),
 484                 .hw.init = &(struct clk_init_data){
 485                         .name = "gsbi8_uart_src",
 486                         .parent_data = gcc_pxo_pll8,
 487                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 488                         .ops = &clk_rcg_ops,
 489                         .flags = CLK_SET_PARENT_GATE,
 490                 },
 491         },
 492 };
 493
 494 static struct clk_branch gsbi8_uart_clk = {
 495         .halt_reg = 0x2fd0,
 496         .halt_bit = 10,
 497         .clkr = {
 498                 .enable_reg = 0x2ab4,
 499                 .enable_mask = BIT(9),
 500                 .hw.init = &(struct clk_init_data){
 501                         .name = "gsbi8_uart_clk",
 502                         .parent_hws = (const struct clk_hw*[]){
 503                                 &gsbi8_uart_src.clkr.hw
 504                         },
 505                         .num_parents = 1,
 506                         .ops = &clk_branch_ops,
 507                         .flags = CLK_SET_RATE_PARENT,
 508                 },
 509         },
 510 };
 511
 512 static struct clk_rcg gsbi9_uart_src = {
 513         .ns_reg = 0x2ad4,
 514         .md_reg = 0x2ad0,
 515         .mn = {
 516                 .mnctr_en_bit = 8,
 517                 .mnctr_reset_bit = 7,
 518                 .mnctr_mode_shift = 5,
 519                 .n_val_shift = 16,
 520                 .m_val_shift = 16,
 521                 .width = 16,
 522         },
 523         .p = {
 524                 .pre_div_shift = 3,
 525                 .pre_div_width = 2,
 526         },
 527         .s = {
 528                 .src_sel_shift = 0,
 529                 .parent_map = gcc_pxo_pll8_map,
 530         },
 531         .freq_tbl = clk_tbl_gsbi_uart,
 532         .clkr = {
 533                 .enable_reg = 0x2ad4,
 534                 .enable_mask = BIT(11),
 535                 .hw.init = &(struct clk_init_data){
 536                         .name = "gsbi9_uart_src",
 537                         .parent_data = gcc_pxo_pll8,
 538                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 539                         .ops = &clk_rcg_ops,
 540                         .flags = CLK_SET_PARENT_GATE,
 541                 },
 542         },
 543 };
 544
 545 static struct clk_branch gsbi9_uart_clk = {
 546         .halt_reg = 0x2fd0,
 547         .halt_bit = 6,
 548         .clkr = {
 549                 .enable_reg = 0x2ad4,
 550                 .enable_mask = BIT(9),
 551                 .hw.init = &(struct clk_init_data){
 552                         .name = "gsbi9_uart_clk",
 553                         .parent_hws = (const struct clk_hw*[]){
 554                                 &gsbi9_uart_src.clkr.hw
 555                         },
 556                         .num_parents = 1,
 557                         .ops = &clk_branch_ops,
 558                         .flags = CLK_SET_RATE_PARENT,
 559                 },
 560         },
 561 };
 562
 563 static struct clk_rcg gsbi10_uart_src = {
 564         .ns_reg = 0x2af4,
 565         .md_reg = 0x2af0,
 566         .mn = {
 567                 .mnctr_en_bit = 8,
 568                 .mnctr_reset_bit = 7,
 569                 .mnctr_mode_shift = 5,
 570                 .n_val_shift = 16,
 571                 .m_val_shift = 16,
 572                 .width = 16,
 573         },
 574         .p = {
 575                 .pre_div_shift = 3,
 576                 .pre_div_width = 2,
 577         },
 578         .s = {
 579                 .src_sel_shift = 0,
 580                 .parent_map = gcc_pxo_pll8_map,
 581         },
 582         .freq_tbl = clk_tbl_gsbi_uart,
 583         .clkr = {
 584                 .enable_reg = 0x2af4,
 585                 .enable_mask = BIT(11),
 586                 .hw.init = &(struct clk_init_data){
 587                         .name = "gsbi10_uart_src",
 588                         .parent_data = gcc_pxo_pll8,
 589                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 590                         .ops = &clk_rcg_ops,
 591                         .flags = CLK_SET_PARENT_GATE,
 592                 },
 593         },
 594 };
 595
 596 static struct clk_branch gsbi10_uart_clk = {
 597         .halt_reg = 0x2fd0,
 598         .halt_bit = 2,
 599         .clkr = {
 600                 .enable_reg = 0x2af4,
 601                 .enable_mask = BIT(9),
 602                 .hw.init = &(struct clk_init_data){
 603                         .name = "gsbi10_uart_clk",
 604                         .parent_hws = (const struct clk_hw*[]){
 605                                 &gsbi10_uart_src.clkr.hw
 606                         },
 607                         .num_parents = 1,
 608                         .ops = &clk_branch_ops,
 609                         .flags = CLK_SET_RATE_PARENT,
 610                 },
 611         },
 612 };
 613
 614 static struct clk_rcg gsbi11_uart_src = {
 615         .ns_reg = 0x2b14,
 616         .md_reg = 0x2b10,
 617         .mn = {
 618                 .mnctr_en_bit = 8,
 619                 .mnctr_reset_bit = 7,
 620                 .mnctr_mode_shift = 5,
 621                 .n_val_shift = 16,
 622                 .m_val_shift = 16,
 623                 .width = 16,
 624         },
 625         .p = {
 626                 .pre_div_shift = 3,
 627                 .pre_div_width = 2,
 628         },
 629         .s = {
 630                 .src_sel_shift = 0,
 631                 .parent_map = gcc_pxo_pll8_map,
 632         },
 633         .freq_tbl = clk_tbl_gsbi_uart,
 634         .clkr = {
 635                 .enable_reg = 0x2b14,
 636                 .enable_mask = BIT(11),
 637                 .hw.init = &(struct clk_init_data){
 638                         .name = "gsbi11_uart_src",
 639                         .parent_data = gcc_pxo_pll8,
 640                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 641                         .ops = &clk_rcg_ops,
 642                         .flags = CLK_SET_PARENT_GATE,
 643                 },
 644         },
 645 };
 646
 647 static struct clk_branch gsbi11_uart_clk = {
 648         .halt_reg = 0x2fd4,
 649         .halt_bit = 17,
 650         .clkr = {
 651                 .enable_reg = 0x2b14,
 652                 .enable_mask = BIT(9),
 653                 .hw.init = &(struct clk_init_data){
 654                         .name = "gsbi11_uart_clk",
 655                         .parent_hws = (const struct clk_hw*[]){
 656                                 &gsbi11_uart_src.clkr.hw
 657                         },
 658                         .num_parents = 1,
 659                         .ops = &clk_branch_ops,
 660                         .flags = CLK_SET_RATE_PARENT,
 661                 },
 662         },
 663 };
 664
 665 static struct clk_rcg gsbi12_uart_src = {
 666         .ns_reg = 0x2b34,
 667         .md_reg = 0x2b30,
 668         .mn = {
 669                 .mnctr_en_bit = 8,
 670                 .mnctr_reset_bit = 7,
 671                 .mnctr_mode_shift = 5,
 672                 .n_val_shift = 16,
 673                 .m_val_shift = 16,
 674                 .width = 16,
 675         },
 676         .p = {
 677                 .pre_div_shift = 3,
 678                 .pre_div_width = 2,
 679         },
 680         .s = {
 681                 .src_sel_shift = 0,
 682                 .parent_map = gcc_pxo_pll8_map,
 683         },
 684         .freq_tbl = clk_tbl_gsbi_uart,
 685         .clkr = {
 686                 .enable_reg = 0x2b34,
 687                 .enable_mask = BIT(11),
 688                 .hw.init = &(struct clk_init_data){
 689                         .name = "gsbi12_uart_src",
 690                         .parent_data = gcc_pxo_pll8,
 691                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 692                         .ops = &clk_rcg_ops,
 693                         .flags = CLK_SET_PARENT_GATE,
 694                 },
 695         },
 696 };
 697
 698 static struct clk_branch gsbi12_uart_clk = {
 699         .halt_reg = 0x2fd4,
 700         .halt_bit = 13,
 701         .clkr = {
 702                 .enable_reg = 0x2b34,
 703                 .enable_mask = BIT(9),
 704                 .hw.init = &(struct clk_init_data){
 705                         .name = "gsbi12_uart_clk",
 706                         .parent_hws = (const struct clk_hw*[]){
 707                                 &gsbi12_uart_src.clkr.hw
 708                         },
 709                         .num_parents = 1,
 710                         .ops = &clk_branch_ops,
 711                         .flags = CLK_SET_RATE_PARENT,
 712                 },
 713         },
 714 };
 715
 716 static struct freq_tbl clk_tbl_gsbi_qup[] = {
 717         {  1100000, P_PXO,  1, 2, 49 },
 718         {  5400000, P_PXO,  1, 1,  5 },
 719         { 10800000, P_PXO,  1, 2,  5 },
 720         { 15060000, P_PLL8, 1, 2, 51 },
 721         { 24000000, P_PLL8, 4, 1,  4 },
 722         { 25600000, P_PLL8, 1, 1, 15 },
 723         { 27000000, P_PXO,  1, 0,  0 },
 724         { 48000000, P_PLL8, 4, 1,  2 },
 725         { 51200000, P_PLL8, 1, 2, 15 },
 726         { }
 727 };
 728
 729 static struct clk_rcg gsbi1_qup_src = {
 730         .ns_reg = 0x29cc,
 731         .md_reg = 0x29c8,
 732         .mn = {
 733                 .mnctr_en_bit = 8,
 734                 .mnctr_reset_bit = 7,
 735                 .mnctr_mode_shift = 5,
 736                 .n_val_shift = 16,
 737                 .m_val_shift = 16,
 738                 .width = 8,
 739         },
 740         .p = {
 741                 .pre_div_shift = 3,
 742                 .pre_div_width = 2,
 743         },
 744         .s = {
 745                 .src_sel_shift = 0,
 746                 .parent_map = gcc_pxo_pll8_map,
 747         },
 748         .freq_tbl = clk_tbl_gsbi_qup,
 749         .clkr = {
 750                 .enable_reg = 0x29cc,
 751                 .enable_mask = BIT(11),
 752                 .hw.init = &(struct clk_init_data){
 753                         .name = "gsbi1_qup_src",
 754                         .parent_data = gcc_pxo_pll8,
 755                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 756                         .ops = &clk_rcg_ops,
 757                         .flags = CLK_SET_PARENT_GATE,
 758                 },
 759         },
 760 };
 761
 762 static struct clk_branch gsbi1_qup_clk = {
 763         .halt_reg = 0x2fcc,
 764         .halt_bit = 9,
 765         .clkr = {
 766                 .enable_reg = 0x29cc,
 767                 .enable_mask = BIT(9),
 768                 .hw.init = &(struct clk_init_data){
 769                         .name = "gsbi1_qup_clk",
 770                         .parent_hws = (const struct clk_hw*[]){
 771                                 &gsbi1_qup_src.clkr.hw
 772                         },
 773                         .num_parents = 1,
 774                         .ops = &clk_branch_ops,
 775                         .flags = CLK_SET_RATE_PARENT,
 776                 },
 777         },
 778 };
 779
 780 static struct clk_rcg gsbi2_qup_src = {
 781         .ns_reg = 0x29ec,
 782         .md_reg = 0x29e8,
 783         .mn = {
 784                 .mnctr_en_bit = 8,
 785                 .mnctr_reset_bit = 7,
 786                 .mnctr_mode_shift = 5,
 787                 .n_val_shift = 16,
 788                 .m_val_shift = 16,
 789                 .width = 8,
 790         },
 791         .p = {
 792                 .pre_div_shift = 3,
 793                 .pre_div_width = 2,
 794         },
 795         .s = {
 796                 .src_sel_shift = 0,
 797                 .parent_map = gcc_pxo_pll8_map,
 798         },
 799         .freq_tbl = clk_tbl_gsbi_qup,
 800         .clkr = {
 801                 .enable_reg = 0x29ec,
 802                 .enable_mask = BIT(11),
 803                 .hw.init = &(struct clk_init_data){
 804                         .name = "gsbi2_qup_src",
 805                         .parent_data = gcc_pxo_pll8,
 806                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 807                         .ops = &clk_rcg_ops,
 808                         .flags = CLK_SET_PARENT_GATE,
 809                 },
 810         },
 811 };
 812
 813 static struct clk_branch gsbi2_qup_clk = {
 814         .halt_reg = 0x2fcc,
 815         .halt_bit = 4,
 816         .clkr = {
 817                 .enable_reg = 0x29ec,
 818                 .enable_mask = BIT(9),
 819                 .hw.init = &(struct clk_init_data){
 820                         .name = "gsbi2_qup_clk",
 821                         .parent_hws = (const struct clk_hw*[]){
 822                                 &gsbi2_qup_src.clkr.hw
 823                         },
 824                         .num_parents = 1,
 825                         .ops = &clk_branch_ops,
 826                         .flags = CLK_SET_RATE_PARENT,
 827                 },
 828         },
 829 };
 830
 831 static struct clk_rcg gsbi3_qup_src = {
 832         .ns_reg = 0x2a0c,
 833         .md_reg = 0x2a08,
 834         .mn = {
 835                 .mnctr_en_bit = 8,
 836                 .mnctr_reset_bit = 7,
 837                 .mnctr_mode_shift = 5,
 838                 .n_val_shift = 16,
 839                 .m_val_shift = 16,
 840                 .width = 8,
 841         },
 842         .p = {
 843                 .pre_div_shift = 3,
 844                 .pre_div_width = 2,
 845         },
 846         .s = {
 847                 .src_sel_shift = 0,
 848                 .parent_map = gcc_pxo_pll8_map,
 849         },
 850         .freq_tbl = clk_tbl_gsbi_qup,
 851         .clkr = {
 852                 .enable_reg = 0x2a0c,
 853                 .enable_mask = BIT(11),
 854                 .hw.init = &(struct clk_init_data){
 855                         .name = "gsbi3_qup_src",
 856                         .parent_data = gcc_pxo_pll8,
 857                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 858                         .ops = &clk_rcg_ops,
 859                         .flags = CLK_SET_PARENT_GATE,
 860                 },
 861         },
 862 };
 863
 864 static struct clk_branch gsbi3_qup_clk = {
 865         .halt_reg = 0x2fcc,
 866         .halt_bit = 0,
 867         .clkr = {
 868                 .enable_reg = 0x2a0c,
 869                 .enable_mask = BIT(9),
 870                 .hw.init = &(struct clk_init_data){
 871                         .name = "gsbi3_qup_clk",
 872                         .parent_hws = (const struct clk_hw*[]){
 873                                 &gsbi3_qup_src.clkr.hw
 874                         },
 875                         .num_parents = 1,
 876                         .ops = &clk_branch_ops,
 877                         .flags = CLK_SET_RATE_PARENT,
 878                 },
 879         },
 880 };
 881
 882 static struct clk_rcg gsbi4_qup_src = {
 883         .ns_reg = 0x2a2c,
 884         .md_reg = 0x2a28,
 885         .mn = {
 886                 .mnctr_en_bit = 8,
 887                 .mnctr_reset_bit = 7,
 888                 .mnctr_mode_shift = 5,
 889                 .n_val_shift = 16,
 890                 .m_val_shift = 16,
 891                 .width = 8,
 892         },
 893         .p = {
 894                 .pre_div_shift = 3,
 895                 .pre_div_width = 2,
 896         },
 897         .s = {
 898                 .src_sel_shift = 0,
 899                 .parent_map = gcc_pxo_pll8_map,
 900         },
 901         .freq_tbl = clk_tbl_gsbi_qup,
 902         .clkr = {
 903                 .enable_reg = 0x2a2c,
 904                 .enable_mask = BIT(11),
 905                 .hw.init = &(struct clk_init_data){
 906                         .name = "gsbi4_qup_src",
 907                         .parent_data = gcc_pxo_pll8,
 908                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 909                         .ops = &clk_rcg_ops,
 910                         .flags = CLK_SET_PARENT_GATE,
 911                 },
 912         },
 913 };
 914
 915 static struct clk_branch gsbi4_qup_clk = {
 916         .halt_reg = 0x2fd0,
 917         .halt_bit = 24,
 918         .clkr = {
 919                 .enable_reg = 0x2a2c,
 920                 .enable_mask = BIT(9),
 921                 .hw.init = &(struct clk_init_data){
 922                         .name = "gsbi4_qup_clk",
 923                         .parent_hws = (const struct clk_hw*[]){
 924                                 &gsbi4_qup_src.clkr.hw
 925                         },
 926                         .num_parents = 1,
 927                         .ops = &clk_branch_ops,
 928                         .flags = CLK_SET_RATE_PARENT,
 929                 },
 930         },
 931 };
 932
 933 static struct clk_rcg gsbi5_qup_src = {
 934         .ns_reg = 0x2a4c,
 935         .md_reg = 0x2a48,
 936         .mn = {
 937                 .mnctr_en_bit = 8,
 938                 .mnctr_reset_bit = 7,
 939                 .mnctr_mode_shift = 5,
 940                 .n_val_shift = 16,
 941                 .m_val_shift = 16,
 942                 .width = 8,
 943         },
 944         .p = {
 945                 .pre_div_shift = 3,
 946                 .pre_div_width = 2,
 947         },
 948         .s = {
 949                 .src_sel_shift = 0,
 950                 .parent_map = gcc_pxo_pll8_map,
 951         },
 952         .freq_tbl = clk_tbl_gsbi_qup,
 953         .clkr = {
 954                 .enable_reg = 0x2a4c,
 955                 .enable_mask = BIT(11),
 956                 .hw.init = &(struct clk_init_data){
 957                         .name = "gsbi5_qup_src",
 958                         .parent_data = gcc_pxo_pll8,
 959                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
 960                         .ops = &clk_rcg_ops,
 961                         .flags = CLK_SET_PARENT_GATE,
 962                 },
 963         },
 964 };
 965
 966 static struct clk_branch gsbi5_qup_clk = {
 967         .halt_reg = 0x2fd0,
 968         .halt_bit = 20,
 969         .clkr = {
 970                 .enable_reg = 0x2a4c,
 971                 .enable_mask = BIT(9),
 972                 .hw.init = &(struct clk_init_data){
 973                         .name = "gsbi5_qup_clk",
 974                         .parent_hws = (const struct clk_hw*[]){
 975                                 &gsbi5_qup_src.clkr.hw
 976                         },
 977                         .num_parents = 1,
 978                         .ops = &clk_branch_ops,
 979                         .flags = CLK_SET_RATE_PARENT,
 980                 },
 981         },
 982 };
 983
 984 static struct clk_rcg gsbi6_qup_src = {
 985         .ns_reg = 0x2a6c,
 986         .md_reg = 0x2a68,
 987         .mn = {
 988                 .mnctr_en_bit = 8,
 989                 .mnctr_reset_bit = 7,
 990                 .mnctr_mode_shift = 5,
 991                 .n_val_shift = 16,
 992                 .m_val_shift = 16,
 993                 .width = 8,
 994         },
 995         .p = {
 996                 .pre_div_shift = 3,
 997                 .pre_div_width = 2,
 998         },
 999         .s = {
1000                 .src_sel_shift = 0,
1001                 .parent_map = gcc_pxo_pll8_map,
1002         },
1003         .freq_tbl = clk_tbl_gsbi_qup,
1004         .clkr = {
1005                 .enable_reg = 0x2a6c,
1006                 .enable_mask = BIT(11),
1007                 .hw.init = &(struct clk_init_data){
1008                         .name = "gsbi6_qup_src",
1009                         .parent_data = gcc_pxo_pll8,
1010                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1011                         .ops = &clk_rcg_ops,
1012                         .flags = CLK_SET_PARENT_GATE,
1013                 },
1014         },
1015 };
1016
1017 static struct clk_branch gsbi6_qup_clk = {
1018         .halt_reg = 0x2fd0,
1019         .halt_bit = 16,
1020         .clkr = {
1021                 .enable_reg = 0x2a6c,
1022                 .enable_mask = BIT(9),
1023                 .hw.init = &(struct clk_init_data){
1024                         .name = "gsbi6_qup_clk",
1025                         .parent_hws = (const struct clk_hw*[]){
1026                                 &gsbi6_qup_src.clkr.hw
1027                         },
1028                         .num_parents = 1,
1029                         .ops = &clk_branch_ops,
1030                         .flags = CLK_SET_RATE_PARENT,
1031                 },
1032         },
1033 };
1034
1035 static struct clk_rcg gsbi7_qup_src = {
1036         .ns_reg = 0x2a8c,
1037         .md_reg = 0x2a88,
1038         .mn = {
1039                 .mnctr_en_bit = 8,
1040                 .mnctr_reset_bit = 7,
1041                 .mnctr_mode_shift = 5,
1042                 .n_val_shift = 16,
1043                 .m_val_shift = 16,
1044                 .width = 8,
1045         },
1046         .p = {
1047                 .pre_div_shift = 3,
1048                 .pre_div_width = 2,
1049         },
1050         .s = {
1051                 .src_sel_shift = 0,
1052                 .parent_map = gcc_pxo_pll8_map,
1053         },
1054         .freq_tbl = clk_tbl_gsbi_qup,
1055         .clkr = {
1056                 .enable_reg = 0x2a8c,
1057                 .enable_mask = BIT(11),
1058                 .hw.init = &(struct clk_init_data){
1059                         .name = "gsbi7_qup_src",
1060                         .parent_data = gcc_pxo_pll8,
1061                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1062                         .ops = &clk_rcg_ops,
1063                         .flags = CLK_SET_PARENT_GATE,
1064                 },
1065         },
1066 };
1067
1068 static struct clk_branch gsbi7_qup_clk = {
1069         .halt_reg = 0x2fd0,
1070         .halt_bit = 12,
1071         .clkr = {
1072                 .enable_reg = 0x2a8c,
1073                 .enable_mask = BIT(9),
1074                 .hw.init = &(struct clk_init_data){
1075                         .name = "gsbi7_qup_clk",
1076                         .parent_hws = (const struct clk_hw*[]){
1077                                 &gsbi7_qup_src.clkr.hw
1078                         },
1079                         .num_parents = 1,
1080                         .ops = &clk_branch_ops,
1081                         .flags = CLK_SET_RATE_PARENT,
1082                 },
1083         },
1084 };
1085
1086 static struct clk_rcg gsbi8_qup_src = {
1087         .ns_reg = 0x2aac,
1088         .md_reg = 0x2aa8,
1089         .mn = {
1090                 .mnctr_en_bit = 8,
1091                 .mnctr_reset_bit = 7,
1092                 .mnctr_mode_shift = 5,
1093                 .n_val_shift = 16,
1094                 .m_val_shift = 16,
1095                 .width = 8,
1096         },
1097         .p = {
1098                 .pre_div_shift = 3,
1099                 .pre_div_width = 2,
1100         },
1101         .s = {
1102                 .src_sel_shift = 0,
1103                 .parent_map = gcc_pxo_pll8_map,
1104         },
1105         .freq_tbl = clk_tbl_gsbi_qup,
1106         .clkr = {
1107                 .enable_reg = 0x2aac,
1108                 .enable_mask = BIT(11),
1109                 .hw.init = &(struct clk_init_data){
1110                         .name = "gsbi8_qup_src",
1111                         .parent_data = gcc_pxo_pll8,
1112                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1113                         .ops = &clk_rcg_ops,
1114                         .flags = CLK_SET_PARENT_GATE,
1115                 },
1116         },
1117 };
1118
1119 static struct clk_branch gsbi8_qup_clk = {
1120         .halt_reg = 0x2fd0,
1121         .halt_bit = 8,
1122         .clkr = {
1123                 .enable_reg = 0x2aac,
1124                 .enable_mask = BIT(9),
1125                 .hw.init = &(struct clk_init_data){
1126                         .name = "gsbi8_qup_clk",
1127                         .parent_hws = (const struct clk_hw*[]){
1128                                 &gsbi8_qup_src.clkr.hw
1129                         },
1130                         .num_parents = 1,
1131                         .ops = &clk_branch_ops,
1132                         .flags = CLK_SET_RATE_PARENT,
1133                 },
1134         },
1135 };
1136
1137 static struct clk_rcg gsbi9_qup_src = {
1138         .ns_reg = 0x2acc,
1139         .md_reg = 0x2ac8,
1140         .mn = {
1141                 .mnctr_en_bit = 8,
1142                 .mnctr_reset_bit = 7,
1143                 .mnctr_mode_shift = 5,
1144                 .n_val_shift = 16,
1145                 .m_val_shift = 16,
1146                 .width = 8,
1147         },
1148         .p = {
1149                 .pre_div_shift = 3,
1150                 .pre_div_width = 2,
1151         },
1152         .s = {
1153                 .src_sel_shift = 0,
1154                 .parent_map = gcc_pxo_pll8_map,
1155         },
1156         .freq_tbl = clk_tbl_gsbi_qup,
1157         .clkr = {
1158                 .enable_reg = 0x2acc,
1159                 .enable_mask = BIT(11),
1160                 .hw.init = &(struct clk_init_data){
1161                         .name = "gsbi9_qup_src",
1162                         .parent_data = gcc_pxo_pll8,
1163                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1164                         .ops = &clk_rcg_ops,
1165                         .flags = CLK_SET_PARENT_GATE,
1166                 },
1167         },
1168 };
1169
1170 static struct clk_branch gsbi9_qup_clk = {
1171         .halt_reg = 0x2fd0,
1172         .halt_bit = 4,
1173         .clkr = {
1174                 .enable_reg = 0x2acc,
1175                 .enable_mask = BIT(9),
1176                 .hw.init = &(struct clk_init_data){
1177                         .name = "gsbi9_qup_clk",
1178                         .parent_hws = (const struct clk_hw*[]){
1179                                 &gsbi9_qup_src.clkr.hw
1180                         },
1181                         .num_parents = 1,
1182                         .ops = &clk_branch_ops,
1183                         .flags = CLK_SET_RATE_PARENT,
1184                 },
1185         },
1186 };
1187
1188 static struct clk_rcg gsbi10_qup_src = {
1189         .ns_reg = 0x2aec,
1190         .md_reg = 0x2ae8,
1191         .mn = {
1192                 .mnctr_en_bit = 8,
1193                 .mnctr_reset_bit = 7,
1194                 .mnctr_mode_shift = 5,
1195                 .n_val_shift = 16,
1196                 .m_val_shift = 16,
1197                 .width = 8,
1198         },
1199         .p = {
1200                 .pre_div_shift = 3,
1201                 .pre_div_width = 2,
1202         },
1203         .s = {
1204                 .src_sel_shift = 0,
1205                 .parent_map = gcc_pxo_pll8_map,
1206         },
1207         .freq_tbl = clk_tbl_gsbi_qup,
1208         .clkr = {
1209                 .enable_reg = 0x2aec,
1210                 .enable_mask = BIT(11),
1211                 .hw.init = &(struct clk_init_data){
1212                         .name = "gsbi10_qup_src",
1213                         .parent_data = gcc_pxo_pll8,
1214                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1215                         .ops = &clk_rcg_ops,
1216                         .flags = CLK_SET_PARENT_GATE,
1217                 },
1218         },
1219 };
1220
1221 static struct clk_branch gsbi10_qup_clk = {
1222         .halt_reg = 0x2fd0,
1223         .halt_bit = 0,
1224         .clkr = {
1225                 .enable_reg = 0x2aec,
1226                 .enable_mask = BIT(9),
1227                 .hw.init = &(struct clk_init_data){
1228                         .name = "gsbi10_qup_clk",
1229                         .parent_hws = (const struct clk_hw*[]){
1230                                 &gsbi10_qup_src.clkr.hw
1231                         },
1232                         .num_parents = 1,
1233                         .ops = &clk_branch_ops,
1234                         .flags = CLK_SET_RATE_PARENT,
1235                 },
1236         },
1237 };
1238
1239 static struct clk_rcg gsbi11_qup_src = {
1240         .ns_reg = 0x2b0c,
1241         .md_reg = 0x2b08,
1242         .mn = {
1243                 .mnctr_en_bit = 8,
1244                 .mnctr_reset_bit = 7,
1245                 .mnctr_mode_shift = 5,
1246                 .n_val_shift = 16,
1247                 .m_val_shift = 16,
1248                 .width = 8,
1249         },
1250         .p = {
1251                 .pre_div_shift = 3,
1252                 .pre_div_width = 2,
1253         },
1254         .s = {
1255                 .src_sel_shift = 0,
1256                 .parent_map = gcc_pxo_pll8_map,
1257         },
1258         .freq_tbl = clk_tbl_gsbi_qup,
1259         .clkr = {
1260                 .enable_reg = 0x2b0c,
1261                 .enable_mask = BIT(11),
1262                 .hw.init = &(struct clk_init_data){
1263                         .name = "gsbi11_qup_src",
1264                         .parent_data = gcc_pxo_pll8,
1265                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1266                         .ops = &clk_rcg_ops,
1267                         .flags = CLK_SET_PARENT_GATE,
1268                 },
1269         },
1270 };
1271
1272 static struct clk_branch gsbi11_qup_clk = {
1273         .halt_reg = 0x2fd4,
1274         .halt_bit = 15,
1275         .clkr = {
1276                 .enable_reg = 0x2b0c,
1277                 .enable_mask = BIT(9),
1278                 .hw.init = &(struct clk_init_data){
1279                         .name = "gsbi11_qup_clk",
1280                         .parent_hws = (const struct clk_hw*[]){
1281                                 &gsbi11_qup_src.clkr.hw
1282                         },
1283                         .num_parents = 1,
1284                         .ops = &clk_branch_ops,
1285                         .flags = CLK_SET_RATE_PARENT,
1286                 },
1287         },
1288 };
1289
1290 static struct clk_rcg gsbi12_qup_src = {
1291         .ns_reg = 0x2b2c,
1292         .md_reg = 0x2b28,
1293         .mn = {
1294                 .mnctr_en_bit = 8,
1295                 .mnctr_reset_bit = 7,
1296                 .mnctr_mode_shift = 5,
1297                 .n_val_shift = 16,
1298                 .m_val_shift = 16,
1299                 .width = 8,
1300         },
1301         .p = {
1302                 .pre_div_shift = 3,
1303                 .pre_div_width = 2,
1304         },
1305         .s = {
1306                 .src_sel_shift = 0,
1307                 .parent_map = gcc_pxo_pll8_map,
1308         },
1309         .freq_tbl = clk_tbl_gsbi_qup,
1310         .clkr = {
1311                 .enable_reg = 0x2b2c,
1312                 .enable_mask = BIT(11),
1313                 .hw.init = &(struct clk_init_data){
1314                         .name = "gsbi12_qup_src",
1315                         .parent_data = gcc_pxo_pll8,
1316                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1317                         .ops = &clk_rcg_ops,
1318                         .flags = CLK_SET_PARENT_GATE,
1319                 },
1320         },
1321 };
1322
1323 static struct clk_branch gsbi12_qup_clk = {
1324         .halt_reg = 0x2fd4,
1325         .halt_bit = 11,
1326         .clkr = {
1327                 .enable_reg = 0x2b2c,
1328                 .enable_mask = BIT(9),
1329                 .hw.init = &(struct clk_init_data){
1330                         .name = "gsbi12_qup_clk",
1331                         .parent_hws = (const struct clk_hw*[]){
1332                                 &gsbi12_qup_src.clkr.hw
1333                         },
1334                         .num_parents = 1,
1335                         .ops = &clk_branch_ops,
1336                         .flags = CLK_SET_RATE_PARENT,
1337                 },
1338         },
1339 };
1340
1341 static const struct freq_tbl clk_tbl_gp[] = {
1342         { 9600000, P_CXO,  2, 0, 0 },
1343         { 13500000, P_PXO,  2, 0, 0 },
1344         { 19200000, P_CXO,  1, 0, 0 },
1345         { 27000000, P_PXO,  1, 0, 0 },
1346         { 64000000, P_PLL8, 2, 1, 3 },
1347         { 76800000, P_PLL8, 1, 1, 5 },
1348         { 96000000, P_PLL8, 4, 0, 0 },
1349         { 128000000, P_PLL8, 3, 0, 0 },
1350         { 192000000, P_PLL8, 2, 0, 0 },
1351         { }
1352 };
1353
1354 static struct clk_rcg gp0_src = {
1355         .ns_reg = 0x2d24,
1356         .md_reg = 0x2d00,
1357         .mn = {
1358                 .mnctr_en_bit = 8,
1359                 .mnctr_reset_bit = 7,
1360                 .mnctr_mode_shift = 5,
1361                 .n_val_shift = 16,
1362                 .m_val_shift = 16,
1363                 .width = 8,
1364         },
1365         .p = {
1366                 .pre_div_shift = 3,
1367                 .pre_div_width = 2,
1368         },
1369         .s = {
1370                 .src_sel_shift = 0,
1371                 .parent_map = gcc_pxo_pll8_cxo_map,
1372         },
1373         .freq_tbl = clk_tbl_gp,
1374         .clkr = {
1375                 .enable_reg = 0x2d24,
1376                 .enable_mask = BIT(11),
1377                 .hw.init = &(struct clk_init_data){
1378                         .name = "gp0_src",
1379                         .parent_data = gcc_pxo_pll8_cxo,
1380                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
1381                         .ops = &clk_rcg_ops,
1382                         .flags = CLK_SET_PARENT_GATE,
1383                 },
1384         }
1385 };
1386
1387 static struct clk_branch gp0_clk = {
1388         .halt_reg = 0x2fd8,
1389         .halt_bit = 7,
1390         .clkr = {
1391                 .enable_reg = 0x2d24,
1392                 .enable_mask = BIT(9),
1393                 .hw.init = &(struct clk_init_data){
1394                         .name = "gp0_clk",
1395                         .parent_hws = (const struct clk_hw*[]){
1396                                 &gp0_src.clkr.hw
1397                         },
1398                         .num_parents = 1,
1399                         .ops = &clk_branch_ops,
1400                         .flags = CLK_SET_RATE_PARENT,
1401                 },
1402         },
1403 };
1404
1405 static struct clk_rcg gp1_src = {
1406         .ns_reg = 0x2d44,
1407         .md_reg = 0x2d40,
1408         .mn = {
1409                 .mnctr_en_bit = 8,
1410                 .mnctr_reset_bit = 7,
1411                 .mnctr_mode_shift = 5,
1412                 .n_val_shift = 16,
1413                 .m_val_shift = 16,
1414                 .width = 8,
1415         },
1416         .p = {
1417                 .pre_div_shift = 3,
1418                 .pre_div_width = 2,
1419         },
1420         .s = {
1421                 .src_sel_shift = 0,
1422                 .parent_map = gcc_pxo_pll8_cxo_map,
1423         },
1424         .freq_tbl = clk_tbl_gp,
1425         .clkr = {
1426                 .enable_reg = 0x2d44,
1427                 .enable_mask = BIT(11),
1428                 .hw.init = &(struct clk_init_data){
1429                         .name = "gp1_src",
1430                         .parent_data = gcc_pxo_pll8_cxo,
1431                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
1432                         .ops = &clk_rcg_ops,
1433                         .flags = CLK_SET_RATE_GATE,
1434                 },
1435         }
1436 };
1437
1438 static struct clk_branch gp1_clk = {
1439         .halt_reg = 0x2fd8,
1440         .halt_bit = 6,
1441         .clkr = {
1442                 .enable_reg = 0x2d44,
1443                 .enable_mask = BIT(9),
1444                 .hw.init = &(struct clk_init_data){
1445                         .name = "gp1_clk",
1446                         .parent_hws = (const struct clk_hw*[]){
1447                                 &gp1_src.clkr.hw
1448                         },
1449                         .num_parents = 1,
1450                         .ops = &clk_branch_ops,
1451                         .flags = CLK_SET_RATE_PARENT,
1452                 },
1453         },
1454 };
1455
1456 static struct clk_rcg gp2_src = {
1457         .ns_reg = 0x2d64,
1458         .md_reg = 0x2d60,
1459         .mn = {
1460                 .mnctr_en_bit = 8,
1461                 .mnctr_reset_bit = 7,
1462                 .mnctr_mode_shift = 5,
1463                 .n_val_shift = 16,
1464                 .m_val_shift = 16,
1465                 .width = 8,
1466         },
1467         .p = {
1468                 .pre_div_shift = 3,
1469                 .pre_div_width = 2,
1470         },
1471         .s = {
1472                 .src_sel_shift = 0,
1473                 .parent_map = gcc_pxo_pll8_cxo_map,
1474         },
1475         .freq_tbl = clk_tbl_gp,
1476         .clkr = {
1477                 .enable_reg = 0x2d64,
1478                 .enable_mask = BIT(11),
1479                 .hw.init = &(struct clk_init_data){
1480                         .name = "gp2_src",
1481                         .parent_data = gcc_pxo_pll8_cxo,
1482                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
1483                         .ops = &clk_rcg_ops,
1484                         .flags = CLK_SET_RATE_GATE,
1485                 },
1486         }
1487 };
1488
1489 static struct clk_branch gp2_clk = {
1490         .halt_reg = 0x2fd8,
1491         .halt_bit = 5,
1492         .clkr = {
1493                 .enable_reg = 0x2d64,
1494                 .enable_mask = BIT(9),
1495                 .hw.init = &(struct clk_init_data){
1496                         .name = "gp2_clk",
1497                         .parent_hws = (const struct clk_hw*[]){
1498                                 &gp2_src.clkr.hw
1499                         },
1500                         .num_parents = 1,
1501                         .ops = &clk_branch_ops,
1502                         .flags = CLK_SET_RATE_PARENT,
1503                 },
1504         },
1505 };
1506
1507 static struct clk_branch pmem_clk = {
1508         .hwcg_reg = 0x25a0,
1509         .hwcg_bit = 6,
1510         .halt_reg = 0x2fc8,
1511         .halt_bit = 20,
1512         .clkr = {
1513                 .enable_reg = 0x25a0,
1514                 .enable_mask = BIT(4),
1515                 .hw.init = &(struct clk_init_data){
1516                         .name = "pmem_clk",
1517                         .ops = &clk_branch_ops,
1518                 },
1519         },
1520 };
1521
1522 static struct clk_rcg prng_src = {
1523         .ns_reg = 0x2e80,
1524         .p = {
1525                 .pre_div_shift = 3,
1526                 .pre_div_width = 4,
1527         },
1528         .s = {
1529                 .src_sel_shift = 0,
1530                 .parent_map = gcc_pxo_pll8_map,
1531         },
1532         .clkr.hw = {
1533                 .init = &(struct clk_init_data){
1534                         .name = "prng_src",
1535                         .parent_data = gcc_pxo_pll8,
1536                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1537                         .ops = &clk_rcg_ops,
1538                 },
1539         },
1540 };
1541
1542 static struct clk_branch prng_clk = {
1543         .halt_reg = 0x2fd8,
1544         .halt_check = BRANCH_HALT_VOTED,
1545         .halt_bit = 10,
1546         .clkr = {
1547                 .enable_reg = 0x3080,
1548                 .enable_mask = BIT(10),
1549                 .hw.init = &(struct clk_init_data){
1550                         .name = "prng_clk",
1551                         .parent_hws = (const struct clk_hw*[]){
1552                                 &prng_src.clkr.hw
1553                         },
1554                         .num_parents = 1,
1555                         .ops = &clk_branch_ops,
1556                 },
1557         },
1558 };
1559
1560 static const struct freq_tbl clk_tbl_sdc[] = {
1561         {    144000, P_PXO,   3, 2, 125 },
1562         {    400000, P_PLL8,  4, 1, 240 },
1563         {  16000000, P_PLL8,  4, 1,   6 },
1564         {  17070000, P_PLL8,  1, 2,  45 },
1565         {  20210000, P_PLL8,  1, 1,  19 },
1566         {  24000000, P_PLL8,  4, 1,   4 },
1567         {  48000000, P_PLL8,  4, 1,   2 },
1568         { }
1569 };
1570
1571 static struct clk_rcg sdc1_src = {
1572         .ns_reg = 0x282c,
1573         .md_reg = 0x2828,
1574         .mn = {
1575                 .mnctr_en_bit = 8,
1576                 .mnctr_reset_bit = 7,
1577                 .mnctr_mode_shift = 5,
1578                 .n_val_shift = 16,
1579                 .m_val_shift = 16,
1580                 .width = 8,
1581         },
1582         .p = {
1583                 .pre_div_shift = 3,
1584                 .pre_div_width = 2,
1585         },
1586         .s = {
1587                 .src_sel_shift = 0,
1588                 .parent_map = gcc_pxo_pll8_map,
1589         },
1590         .freq_tbl = clk_tbl_sdc,
1591         .clkr = {
1592                 .enable_reg = 0x282c,
1593                 .enable_mask = BIT(11),
1594                 .hw.init = &(struct clk_init_data){
1595                         .name = "sdc1_src",
1596                         .parent_data = gcc_pxo_pll8,
1597                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1598                         .ops = &clk_rcg_ops,
1599                 },
1600         }
1601 };
1602
1603 static struct clk_branch sdc1_clk = {
1604         .halt_reg = 0x2fc8,
1605         .halt_bit = 6,
1606         .clkr = {
1607                 .enable_reg = 0x282c,
1608                 .enable_mask = BIT(9),
1609                 .hw.init = &(struct clk_init_data){
1610                         .name = "sdc1_clk",
1611                         .parent_hws = (const struct clk_hw*[]){
1612                                 &sdc1_src.clkr.hw
1613                         },
1614                         .num_parents = 1,
1615                         .ops = &clk_branch_ops,
1616                         .flags = CLK_SET_RATE_PARENT,
1617                 },
1618         },
1619 };
1620
1621 static struct clk_rcg sdc2_src = {
1622         .ns_reg = 0x284c,
1623         .md_reg = 0x2848,
1624         .mn = {
1625                 .mnctr_en_bit = 8,
1626                 .mnctr_reset_bit = 7,
1627                 .mnctr_mode_shift = 5,
1628                 .n_val_shift = 16,
1629                 .m_val_shift = 16,
1630                 .width = 8,
1631         },
1632         .p = {
1633                 .pre_div_shift = 3,
1634                 .pre_div_width = 2,
1635         },
1636         .s = {
1637                 .src_sel_shift = 0,
1638                 .parent_map = gcc_pxo_pll8_map,
1639         },
1640         .freq_tbl = clk_tbl_sdc,
1641         .clkr = {
1642                 .enable_reg = 0x284c,
1643                 .enable_mask = BIT(11),
1644                 .hw.init = &(struct clk_init_data){
1645                         .name = "sdc2_src",
1646                         .parent_data = gcc_pxo_pll8,
1647                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1648                         .ops = &clk_rcg_ops,
1649                 },
1650         }
1651 };
1652
1653 static struct clk_branch sdc2_clk = {
1654         .halt_reg = 0x2fc8,
1655         .halt_bit = 5,
1656         .clkr = {
1657                 .enable_reg = 0x284c,
1658                 .enable_mask = BIT(9),
1659                 .hw.init = &(struct clk_init_data){
1660                         .name = "sdc2_clk",
1661                         .parent_hws = (const struct clk_hw*[]){
1662                                 &sdc2_src.clkr.hw
1663                         },
1664                         .num_parents = 1,
1665                         .ops = &clk_branch_ops,
1666                         .flags = CLK_SET_RATE_PARENT,
1667                 },
1668         },
1669 };
1670
1671 static struct clk_rcg sdc3_src = {
1672         .ns_reg = 0x286c,
1673         .md_reg = 0x2868,
1674         .mn = {
1675                 .mnctr_en_bit = 8,
1676                 .mnctr_reset_bit = 7,
1677                 .mnctr_mode_shift = 5,
1678                 .n_val_shift = 16,
1679                 .m_val_shift = 16,
1680                 .width = 8,
1681         },
1682         .p = {
1683                 .pre_div_shift = 3,
1684                 .pre_div_width = 2,
1685         },
1686         .s = {
1687                 .src_sel_shift = 0,
1688                 .parent_map = gcc_pxo_pll8_map,
1689         },
1690         .freq_tbl = clk_tbl_sdc,
1691         .clkr = {
1692                 .enable_reg = 0x286c,
1693                 .enable_mask = BIT(11),
1694                 .hw.init = &(struct clk_init_data){
1695                         .name = "sdc3_src",
1696                         .parent_data = gcc_pxo_pll8,
1697                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1698                         .ops = &clk_rcg_ops,
1699                 },
1700         }
1701 };
1702
1703 static struct clk_branch sdc3_clk = {
1704         .halt_reg = 0x2fc8,
1705         .halt_bit = 4,
1706         .clkr = {
1707                 .enable_reg = 0x286c,
1708                 .enable_mask = BIT(9),
1709                 .hw.init = &(struct clk_init_data){
1710                         .name = "sdc3_clk",
1711                         .parent_hws = (const struct clk_hw*[]){
1712                                 &sdc3_src.clkr.hw
1713                         },
1714                         .num_parents = 1,
1715                         .ops = &clk_branch_ops,
1716                         .flags = CLK_SET_RATE_PARENT,
1717                 },
1718         },
1719 };
1720
1721 static struct clk_rcg sdc4_src = {
1722         .ns_reg = 0x288c,
1723         .md_reg = 0x2888,
1724         .mn = {
1725                 .mnctr_en_bit = 8,
1726                 .mnctr_reset_bit = 7,
1727                 .mnctr_mode_shift = 5,
1728                 .n_val_shift = 16,
1729                 .m_val_shift = 16,
1730                 .width = 8,
1731         },
1732         .p = {
1733                 .pre_div_shift = 3,
1734                 .pre_div_width = 2,
1735         },
1736         .s = {
1737                 .src_sel_shift = 0,
1738                 .parent_map = gcc_pxo_pll8_map,
1739         },
1740         .freq_tbl = clk_tbl_sdc,
1741         .clkr = {
1742                 .enable_reg = 0x288c,
1743                 .enable_mask = BIT(11),
1744                 .hw.init = &(struct clk_init_data){
1745                         .name = "sdc4_src",
1746                         .parent_data = gcc_pxo_pll8,
1747                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1748                         .ops = &clk_rcg_ops,
1749                 },
1750         }
1751 };
1752
1753 static struct clk_branch sdc4_clk = {
1754         .halt_reg = 0x2fc8,
1755         .halt_bit = 3,
1756         .clkr = {
1757                 .enable_reg = 0x288c,
1758                 .enable_mask = BIT(9),
1759                 .hw.init = &(struct clk_init_data){
1760                         .name = "sdc4_clk",
1761                         .parent_hws = (const struct clk_hw*[]){
1762                                 &sdc4_src.clkr.hw
1763                         },
1764                         .num_parents = 1,
1765                         .ops = &clk_branch_ops,
1766                         .flags = CLK_SET_RATE_PARENT,
1767                 },
1768         },
1769 };
1770
1771 static struct clk_rcg sdc5_src = {
1772         .ns_reg = 0x28ac,
1773         .md_reg = 0x28a8,
1774         .mn = {
1775                 .mnctr_en_bit = 8,
1776                 .mnctr_reset_bit = 7,
1777                 .mnctr_mode_shift = 5,
1778                 .n_val_shift = 16,
1779                 .m_val_shift = 16,
1780                 .width = 8,
1781         },
1782         .p = {
1783                 .pre_div_shift = 3,
1784                 .pre_div_width = 2,
1785         },
1786         .s = {
1787                 .src_sel_shift = 0,
1788                 .parent_map = gcc_pxo_pll8_map,
1789         },
1790         .freq_tbl = clk_tbl_sdc,
1791         .clkr = {
1792                 .enable_reg = 0x28ac,
1793                 .enable_mask = BIT(11),
1794                 .hw.init = &(struct clk_init_data){
1795                         .name = "sdc5_src",
1796                         .parent_data = gcc_pxo_pll8,
1797                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1798                         .ops = &clk_rcg_ops,
1799                 },
1800         }
1801 };
1802
1803 static struct clk_branch sdc5_clk = {
1804         .halt_reg = 0x2fc8,
1805         .halt_bit = 2,
1806         .clkr = {
1807                 .enable_reg = 0x28ac,
1808                 .enable_mask = BIT(9),
1809                 .hw.init = &(struct clk_init_data){
1810                         .name = "sdc5_clk",
1811                         .parent_hws = (const struct clk_hw*[]){
1812                                 &sdc5_src.clkr.hw
1813                         },
1814                         .num_parents = 1,
1815                         .ops = &clk_branch_ops,
1816                         .flags = CLK_SET_RATE_PARENT,
1817                 },
1818         },
1819 };
1820
1821 static const struct freq_tbl clk_tbl_tsif_ref[] = {
1822         { 105000, P_PXO,  1, 1, 256 },
1823         { }
1824 };
1825
1826 static struct clk_rcg tsif_ref_src = {
1827         .ns_reg = 0x2710,
1828         .md_reg = 0x270c,
1829         .mn = {
1830                 .mnctr_en_bit = 8,
1831                 .mnctr_reset_bit = 7,
1832                 .mnctr_mode_shift = 5,
1833                 .n_val_shift = 16,
1834                 .m_val_shift = 16,
1835                 .width = 16,
1836         },
1837         .p = {
1838                 .pre_div_shift = 3,
1839                 .pre_div_width = 2,
1840         },
1841         .s = {
1842                 .src_sel_shift = 0,
1843                 .parent_map = gcc_pxo_pll8_map,
1844         },
1845         .freq_tbl = clk_tbl_tsif_ref,
1846         .clkr = {
1847                 .enable_reg = 0x2710,
1848                 .enable_mask = BIT(11),
1849                 .hw.init = &(struct clk_init_data){
1850                         .name = "tsif_ref_src",
1851                         .parent_data = gcc_pxo_pll8,
1852                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1853                         .ops = &clk_rcg_ops,
1854                         .flags = CLK_SET_RATE_GATE,
1855                 },
1856         }
1857 };
1858
1859 static struct clk_branch tsif_ref_clk = {
1860         .halt_reg = 0x2fd4,
1861         .halt_bit = 5,
1862         .clkr = {
1863                 .enable_reg = 0x2710,
1864                 .enable_mask = BIT(9),
1865                 .hw.init = &(struct clk_init_data){
1866                         .name = "tsif_ref_clk",
1867                         .parent_hws = (const struct clk_hw*[]){
1868                                 &tsif_ref_src.clkr.hw
1869                         },
1870                         .num_parents = 1,
1871                         .ops = &clk_branch_ops,
1872                         .flags = CLK_SET_RATE_PARENT,
1873                 },
1874         },
1875 };
1876
1877 static const struct freq_tbl clk_tbl_usb[] = {
1878         { 60000000, P_PLL8, 1, 5, 32 },
1879         { }
1880 };
1881
1882 static struct clk_rcg usb_hs1_xcvr_src = {
1883         .ns_reg = 0x290c,
1884         .md_reg = 0x2908,
1885         .mn = {
1886                 .mnctr_en_bit = 8,
1887                 .mnctr_reset_bit = 7,
1888                 .mnctr_mode_shift = 5,
1889                 .n_val_shift = 16,
1890                 .m_val_shift = 16,
1891                 .width = 8,
1892         },
1893         .p = {
1894                 .pre_div_shift = 3,
1895                 .pre_div_width = 2,
1896         },
1897         .s = {
1898                 .src_sel_shift = 0,
1899                 .parent_map = gcc_pxo_pll8_map,
1900         },
1901         .freq_tbl = clk_tbl_usb,
1902         .clkr = {
1903                 .enable_reg = 0x290c,
1904                 .enable_mask = BIT(11),
1905                 .hw.init = &(struct clk_init_data){
1906                         .name = "usb_hs1_xcvr_src",
1907                         .parent_data = gcc_pxo_pll8,
1908                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1909                         .ops = &clk_rcg_ops,
1910                         .flags = CLK_SET_RATE_GATE,
1911                 },
1912         }
1913 };
1914
1915 static struct clk_branch usb_hs1_xcvr_clk = {
1916         .halt_reg = 0x2fc8,
1917         .halt_bit = 0,
1918         .clkr = {
1919                 .enable_reg = 0x290c,
1920                 .enable_mask = BIT(9),
1921                 .hw.init = &(struct clk_init_data){
1922                         .name = "usb_hs1_xcvr_clk",
1923                         .parent_hws = (const struct clk_hw*[]){
1924                                 &usb_hs1_xcvr_src.clkr.hw
1925                         },
1926                         .num_parents = 1,
1927                         .ops = &clk_branch_ops,
1928                         .flags = CLK_SET_RATE_PARENT,
1929                 },
1930         },
1931 };
1932
1933 static struct clk_rcg usb_fs1_xcvr_fs_src = {
1934         .ns_reg = 0x2968,
1935         .md_reg = 0x2964,
1936         .mn = {
1937                 .mnctr_en_bit = 8,
1938                 .mnctr_reset_bit = 7,
1939                 .mnctr_mode_shift = 5,
1940                 .n_val_shift = 16,
1941                 .m_val_shift = 16,
1942                 .width = 8,
1943         },
1944         .p = {
1945                 .pre_div_shift = 3,
1946                 .pre_div_width = 2,
1947         },
1948         .s = {
1949                 .src_sel_shift = 0,
1950                 .parent_map = gcc_pxo_pll8_map,
1951         },
1952         .freq_tbl = clk_tbl_usb,
1953         .clkr = {
1954                 .enable_reg = 0x2968,
1955                 .enable_mask = BIT(11),
1956                 .hw.init = &(struct clk_init_data){
1957                         .name = "usb_fs1_xcvr_fs_src",
1958                         .parent_data = gcc_pxo_pll8,
1959                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
1960                         .ops = &clk_rcg_ops,
1961                         .flags = CLK_SET_RATE_GATE,
1962                 },
1963         }
1964 };
1965
1966 static struct clk_branch usb_fs1_xcvr_fs_clk = {
1967         .halt_reg = 0x2fcc,
1968         .halt_bit = 15,
1969         .clkr = {
1970                 .enable_reg = 0x2968,
1971                 .enable_mask = BIT(9),
1972                 .hw.init = &(struct clk_init_data){
1973                         .name = "usb_fs1_xcvr_fs_clk",
1974                         .parent_hws = (const struct clk_hw*[]){
1975                                 &usb_fs1_xcvr_fs_src.clkr.hw,
1976                         },
1977                         .num_parents = 1,
1978                         .ops = &clk_branch_ops,
1979                         .flags = CLK_SET_RATE_PARENT,
1980                 },
1981         },
1982 };
1983
1984 static struct clk_branch usb_fs1_system_clk = {
1985         .halt_reg = 0x2fcc,
1986         .halt_bit = 16,
1987         .clkr = {
1988                 .enable_reg = 0x296c,
1989                 .enable_mask = BIT(4),
1990                 .hw.init = &(struct clk_init_data){
1991                         .parent_hws = (const struct clk_hw*[]){
1992                                 &usb_fs1_xcvr_fs_src.clkr.hw,
1993                         },
1994                         .num_parents = 1,
1995                         .name = "usb_fs1_system_clk",
1996                         .ops = &clk_branch_ops,
1997                         .flags = CLK_SET_RATE_PARENT,
1998                 },
1999         },
2000 };
2001
2002 static struct clk_rcg usb_fs2_xcvr_fs_src = {
2003         .ns_reg = 0x2988,
2004         .md_reg = 0x2984,
2005         .mn = {
2006                 .mnctr_en_bit = 8,
2007                 .mnctr_reset_bit = 7,
2008                 .mnctr_mode_shift = 5,
2009                 .n_val_shift = 16,
2010                 .m_val_shift = 16,
2011                 .width = 8,
2012         },
2013         .p = {
2014                 .pre_div_shift = 3,
2015                 .pre_div_width = 2,
2016         },
2017         .s = {
2018                 .src_sel_shift = 0,
2019                 .parent_map = gcc_pxo_pll8_map,
2020         },
2021         .freq_tbl = clk_tbl_usb,
2022         .clkr = {
2023                 .enable_reg = 0x2988,
2024                 .enable_mask = BIT(11),
2025                 .hw.init = &(struct clk_init_data){
2026                         .name = "usb_fs2_xcvr_fs_src",
2027                         .parent_data = gcc_pxo_pll8,
2028                         .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
2029                         .ops = &clk_rcg_ops,
2030                         .flags = CLK_SET_RATE_GATE,
2031                 },
2032         }
2033 };
2034
2035 static struct clk_branch usb_fs2_xcvr_fs_clk = {
2036         .halt_reg = 0x2fcc,
2037         .halt_bit = 12,
2038         .clkr = {
2039                 .enable_reg = 0x2988,
2040                 .enable_mask = BIT(9),
2041                 .hw.init = &(struct clk_init_data){
2042                         .name = "usb_fs2_xcvr_fs_clk",
2043                         .parent_hws = (const struct clk_hw*[]){
2044                                 &usb_fs2_xcvr_fs_src.clkr.hw,
2045                         },
2046                         .num_parents = 1,
2047                         .ops = &clk_branch_ops,
2048                         .flags = CLK_SET_RATE_PARENT,
2049                 },
2050         },
2051 };
2052
2053 static struct clk_branch usb_fs2_system_clk = {
2054         .halt_reg = 0x2fcc,
2055         .halt_bit = 13,
2056         .clkr = {
2057                 .enable_reg = 0x298c,
2058                 .enable_mask = BIT(4),
2059                 .hw.init = &(struct clk_init_data){
2060                         .name = "usb_fs2_system_clk",
2061                         .parent_hws = (const struct clk_hw*[]){
2062                                 &usb_fs2_xcvr_fs_src.clkr.hw,
2063                         },
2064                         .num_parents = 1,
2065                         .ops = &clk_branch_ops,
2066                         .flags = CLK_SET_RATE_PARENT,
2067                 },
2068         },
2069 };
2070
2071 static struct clk_branch gsbi1_h_clk = {
2072         .halt_reg = 0x2fcc,
2073         .halt_bit = 11,
2074         .clkr = {
2075                 .enable_reg = 0x29c0,
2076                 .enable_mask = BIT(4),
2077                 .hw.init = &(struct clk_init_data){
2078                         .name = "gsbi1_h_clk",
2079                         .ops = &clk_branch_ops,
2080                 },
2081         },
2082 };
2083
2084 static struct clk_branch gsbi2_h_clk = {
2085         .halt_reg = 0x2fcc,
2086         .halt_bit = 7,
2087         .clkr = {
2088                 .enable_reg = 0x29e0,
2089                 .enable_mask = BIT(4),
2090                 .hw.init = &(struct clk_init_data){
2091                         .name = "gsbi2_h_clk",
2092                         .ops = &clk_branch_ops,
2093                 },
2094         },
2095 };
2096
2097 static struct clk_branch gsbi3_h_clk = {
2098         .halt_reg = 0x2fcc,
2099         .halt_bit = 3,
2100         .clkr = {
2101                 .enable_reg = 0x2a00,
2102                 .enable_mask = BIT(4),
2103                 .hw.init = &(struct clk_init_data){
2104                         .name = "gsbi3_h_clk",
2105                         .ops = &clk_branch_ops,
2106                 },
2107         },
2108 };
2109
2110 static struct clk_branch gsbi4_h_clk = {
2111         .halt_reg = 0x2fd0,
2112         .halt_bit = 27,
2113         .clkr = {
2114                 .enable_reg = 0x2a20,
2115                 .enable_mask = BIT(4),
2116                 .hw.init = &(struct clk_init_data){
2117                         .name = "gsbi4_h_clk",
2118                         .ops = &clk_branch_ops,
2119                 },
2120         },
2121 };
2122
2123 static struct clk_branch gsbi5_h_clk = {
2124         .halt_reg = 0x2fd0,
2125         .halt_bit = 23,
2126         .clkr = {
2127                 .enable_reg = 0x2a40,
2128                 .enable_mask = BIT(4),
2129                 .hw.init = &(struct clk_init_data){
2130                         .name = "gsbi5_h_clk",
2131                         .ops = &clk_branch_ops,
2132                 },
2133         },
2134 };
2135
2136 static struct clk_branch gsbi6_h_clk = {
2137         .halt_reg = 0x2fd0,
2138         .halt_bit = 19,
2139         .clkr = {
2140                 .enable_reg = 0x2a60,
2141                 .enable_mask = BIT(4),
2142                 .hw.init = &(struct clk_init_data){
2143                         .name = "gsbi6_h_clk",
2144                         .ops = &clk_branch_ops,
2145                 },
2146         },
2147 };
2148
2149 static struct clk_branch gsbi7_h_clk = {
2150         .halt_reg = 0x2fd0,
2151         .halt_bit = 15,
2152         .clkr = {
2153                 .enable_reg = 0x2a80,
2154                 .enable_mask = BIT(4),
2155                 .hw.init = &(struct clk_init_data){
2156                         .name = "gsbi7_h_clk",
2157                         .ops = &clk_branch_ops,
2158                 },
2159         },
2160 };
2161
2162 static struct clk_branch gsbi8_h_clk = {
2163         .halt_reg = 0x2fd0,
2164         .halt_bit = 11,
2165         .clkr = {
2166                 .enable_reg = 0x2aa0,
2167                 .enable_mask = BIT(4),
2168                 .hw.init = &(struct clk_init_data){
2169                         .name = "gsbi8_h_clk",
2170                         .ops = &clk_branch_ops,
2171                 },
2172         },
2173 };
2174
2175 static struct clk_branch gsbi9_h_clk = {
2176         .halt_reg = 0x2fd0,
2177         .halt_bit = 7,
2178         .clkr = {
2179                 .enable_reg = 0x2ac0,
2180                 .enable_mask = BIT(4),
2181                 .hw.init = &(struct clk_init_data){
2182                         .name = "gsbi9_h_clk",
2183                         .ops = &clk_branch_ops,
2184                 },
2185         },
2186 };
2187
2188 static struct clk_branch gsbi10_h_clk = {
2189         .halt_reg = 0x2fd0,
2190         .halt_bit = 3,
2191         .clkr = {
2192                 .enable_reg = 0x2ae0,
2193                 .enable_mask = BIT(4),
2194                 .hw.init = &(struct clk_init_data){
2195                         .name = "gsbi10_h_clk",
2196                         .ops = &clk_branch_ops,
2197                 },
2198         },
2199 };
2200
2201 static struct clk_branch gsbi11_h_clk = {
2202         .halt_reg = 0x2fd4,
2203         .halt_bit = 18,
2204         .clkr = {
2205                 .enable_reg = 0x2b00,
2206                 .enable_mask = BIT(4),
2207                 .hw.init = &(struct clk_init_data){
2208                         .name = "gsbi11_h_clk",
2209                         .ops = &clk_branch_ops,
2210                 },
2211         },
2212 };
2213
2214 static struct clk_branch gsbi12_h_clk = {
2215         .halt_reg = 0x2fd4,
2216         .halt_bit = 14,
2217         .clkr = {
2218                 .enable_reg = 0x2b20,
2219                 .enable_mask = BIT(4),
2220                 .hw.init = &(struct clk_init_data){
2221                         .name = "gsbi12_h_clk",
2222                         .ops = &clk_branch_ops,
2223                 },
2224         },
2225 };
2226
2227 static struct clk_branch tsif_h_clk = {
2228         .halt_reg = 0x2fd4,
2229         .halt_bit = 7,
2230         .clkr = {
2231                 .enable_reg = 0x2700,
2232                 .enable_mask = BIT(4),
2233                 .hw.init = &(struct clk_init_data){
2234                         .name = "tsif_h_clk",
2235                         .ops = &clk_branch_ops,
2236                 },
2237         },
2238 };
2239
2240 static struct clk_branch usb_fs1_h_clk = {
2241         .halt_reg = 0x2fcc,
2242         .halt_bit = 17,
2243         .clkr = {
2244                 .enable_reg = 0x2960,
2245                 .enable_mask = BIT(4),
2246                 .hw.init = &(struct clk_init_data){
2247                         .name = "usb_fs1_h_clk",
2248                         .ops = &clk_branch_ops,
2249                 },
2250         },
2251 };
2252
2253 static struct clk_branch usb_fs2_h_clk = {
2254         .halt_reg = 0x2fcc,
2255         .halt_bit = 14,
2256         .clkr = {
2257                 .enable_reg = 0x2980,
2258                 .enable_mask = BIT(4),
2259                 .hw.init = &(struct clk_init_data){
2260                         .name = "usb_fs2_h_clk",
2261                         .ops = &clk_branch_ops,
2262                 },
2263         },
2264 };
2265
2266 static struct clk_branch usb_hs1_h_clk = {
2267         .halt_reg = 0x2fc8,
2268         .halt_bit = 1,
2269         .clkr = {
2270                 .enable_reg = 0x2900,
2271                 .enable_mask = BIT(4),
2272                 .hw.init = &(struct clk_init_data){
2273                         .name = "usb_hs1_h_clk",
2274                         .ops = &clk_branch_ops,
2275                 },
2276         },
2277 };
2278
2279 static struct clk_branch sdc1_h_clk = {
2280         .halt_reg = 0x2fc8,
2281         .halt_bit = 11,
2282         .clkr = {
2283                 .enable_reg = 0x2820,
2284                 .enable_mask = BIT(4),
2285                 .hw.init = &(struct clk_init_data){
2286                         .name = "sdc1_h_clk",
2287                         .ops = &clk_branch_ops,
2288                 },
2289         },
2290 };
2291
2292 static struct clk_branch sdc2_h_clk = {
2293         .halt_reg = 0x2fc8,
2294         .halt_bit = 10,
2295         .clkr = {
2296                 .enable_reg = 0x2840,
2297                 .enable_mask = BIT(4),
2298                 .hw.init = &(struct clk_init_data){
2299                         .name = "sdc2_h_clk",
2300                         .ops = &clk_branch_ops,
2301                 },
2302         },
2303 };
2304
2305 static struct clk_branch sdc3_h_clk = {
2306         .halt_reg = 0x2fc8,
2307         .halt_bit = 9,
2308         .clkr = {
2309                 .enable_reg = 0x2860,
2310                 .enable_mask = BIT(4),
2311                 .hw.init = &(struct clk_init_data){
2312                         .name = "sdc3_h_clk",
2313                         .ops = &clk_branch_ops,
2314                 },
2315         },
2316 };
2317
2318 static struct clk_branch sdc4_h_clk = {
2319         .halt_reg = 0x2fc8,
2320         .halt_bit = 8,
2321         .clkr = {
2322                 .enable_reg = 0x2880,
2323                 .enable_mask = BIT(4),
2324                 .hw.init = &(struct clk_init_data){
2325                         .name = "sdc4_h_clk",
2326                         .ops = &clk_branch_ops,
2327                 },
2328         },
2329 };
2330
2331 static struct clk_branch sdc5_h_clk = {
2332         .halt_reg = 0x2fc8,
2333         .halt_bit = 7,
2334         .clkr = {
2335                 .enable_reg = 0x28a0,
2336                 .enable_mask = BIT(4),
2337                 .hw.init = &(struct clk_init_data){
2338                         .name = "sdc5_h_clk",
2339                         .ops = &clk_branch_ops,
2340                 },
2341         },
2342 };
2343
2344 static struct clk_branch ebi2_2x_clk = {
2345         .halt_reg = 0x2fcc,
2346         .halt_bit = 18,
2347         .clkr = {
2348                 .enable_reg = 0x2660,
2349                 .enable_mask = BIT(4),
2350                 .hw.init = &(struct clk_init_data){
2351                         .name = "ebi2_2x_clk",
2352                         .ops = &clk_branch_ops,
2353                 },
2354         },
2355 };
2356
2357 static struct clk_branch ebi2_clk = {
2358         .halt_reg = 0x2fcc,
2359         .halt_bit = 19,
2360         .clkr = {
2361                 .enable_reg = 0x2664,
2362                 .enable_mask = BIT(4),
2363                 .hw.init = &(struct clk_init_data){
2364                         .name = "ebi2_clk",
2365                         .ops = &clk_branch_ops,
2366                 },
2367         },
2368 };
2369
2370 static struct clk_branch adm0_clk = {
2371         .halt_reg = 0x2fdc,
2372         .halt_check = BRANCH_HALT_VOTED,
2373         .halt_bit = 14,
2374         .clkr = {
2375                 .enable_reg = 0x3080,
2376                 .enable_mask = BIT(2),
2377                 .hw.init = &(struct clk_init_data){
2378                         .name = "adm0_clk",
2379                         .ops = &clk_branch_ops,
2380                 },
2381         },
2382 };
2383
2384 static struct clk_branch adm0_pbus_clk = {
2385         .halt_reg = 0x2fdc,
2386         .halt_check = BRANCH_HALT_VOTED,
2387         .halt_bit = 13,
2388         .clkr = {
2389                 .enable_reg = 0x3080,
2390                 .enable_mask = BIT(3),
2391                 .hw.init = &(struct clk_init_data){
2392                         .name = "adm0_pbus_clk",
2393                         .ops = &clk_branch_ops,
2394                 },
2395         },
2396 };
2397
2398 static struct clk_branch adm1_clk = {
2399         .halt_reg = 0x2fdc,
2400         .halt_bit = 12,
2401         .halt_check = BRANCH_HALT_VOTED,
2402         .clkr = {
2403                 .enable_reg = 0x3080,
2404                 .enable_mask = BIT(4),
2405                 .hw.init = &(struct clk_init_data){
2406                         .name = "adm1_clk",
2407                         .ops = &clk_branch_ops,
2408                 },
2409         },
2410 };
2411
2412 static struct clk_branch adm1_pbus_clk = {
2413         .halt_reg = 0x2fdc,
2414         .halt_bit = 11,
2415         .halt_check = BRANCH_HALT_VOTED,
2416         .clkr = {
2417                 .enable_reg = 0x3080,
2418                 .enable_mask = BIT(5),
2419                 .hw.init = &(struct clk_init_data){
2420                         .name = "adm1_pbus_clk",
2421                         .ops = &clk_branch_ops,
2422                 },
2423         },
2424 };
2425
2426 static struct clk_branch modem_ahb1_h_clk = {
2427         .halt_reg = 0x2fdc,
2428         .halt_bit = 8,
2429         .halt_check = BRANCH_HALT_VOTED,
2430         .clkr = {
2431                 .enable_reg = 0x3080,
2432                 .enable_mask = BIT(0),
2433                 .hw.init = &(struct clk_init_data){
2434                         .name = "modem_ahb1_h_clk",
2435                         .ops = &clk_branch_ops,
2436                 },
2437         },
2438 };
2439
2440 static struct clk_branch modem_ahb2_h_clk = {
2441         .halt_reg = 0x2fdc,
2442         .halt_bit = 7,
2443         .halt_check = BRANCH_HALT_VOTED,
2444         .clkr = {
2445                 .enable_reg = 0x3080,
2446                 .enable_mask = BIT(1),
2447                 .hw.init = &(struct clk_init_data){
2448                         .name = "modem_ahb2_h_clk",
2449                         .ops = &clk_branch_ops,
2450                 },
2451         },
2452 };
2453
2454 static struct clk_branch pmic_arb0_h_clk = {
2455         .halt_reg = 0x2fd8,
2456         .halt_check = BRANCH_HALT_VOTED,
2457         .halt_bit = 22,
2458         .clkr = {
2459                 .enable_reg = 0x3080,
2460                 .enable_mask = BIT(8),
2461                 .hw.init = &(struct clk_init_data){
2462                         .name = "pmic_arb0_h_clk",
2463                         .ops = &clk_branch_ops,
2464                 },
2465         },
2466 };
2467
2468 static struct clk_branch pmic_arb1_h_clk = {
2469         .halt_reg = 0x2fd8,
2470         .halt_check = BRANCH_HALT_VOTED,
2471         .halt_bit = 21,
2472         .clkr = {
2473                 .enable_reg = 0x3080,
2474                 .enable_mask = BIT(9),
2475                 .hw.init = &(struct clk_init_data){
2476                         .name = "pmic_arb1_h_clk",
2477                         .ops = &clk_branch_ops,
2478                 },
2479         },
2480 };
2481
2482 static struct clk_branch pmic_ssbi2_clk = {
2483         .halt_reg = 0x2fd8,
2484         .halt_check = BRANCH_HALT_VOTED,
2485         .halt_bit = 23,
2486         .clkr = {
2487                 .enable_reg = 0x3080,
2488                 .enable_mask = BIT(7),
2489                 .hw.init = &(struct clk_init_data){
2490                         .name = "pmic_ssbi2_clk",
2491                         .ops = &clk_branch_ops,
2492                 },
2493         },
2494 };
2495
2496 static struct clk_branch rpm_msg_ram_h_clk = {
2497         .hwcg_reg = 0x27e0,
2498         .hwcg_bit = 6,
2499         .halt_reg = 0x2fd8,
2500         .halt_check = BRANCH_HALT_VOTED,
2501         .halt_bit = 12,
2502         .clkr = {
2503                 .enable_reg = 0x3080,
2504                 .enable_mask = BIT(6),
2505                 .hw.init = &(struct clk_init_data){
2506                         .name = "rpm_msg_ram_h_clk",
2507                         .ops = &clk_branch_ops,
2508                 },
2509         },
2510 };
2511
2512 static struct clk_regmap *gcc_msm8660_clks[] = {
2513         [PLL8] = &pll8.clkr,
2514         [PLL8_VOTE] = &pll8_vote,
2515         [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
2516         [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
2517         [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
2518         [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
2519         [GSBI3_UART_SRC] = &gsbi3_uart_src.clkr,
2520         [GSBI3_UART_CLK] = &gsbi3_uart_clk.clkr,
2521         [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,
2522         [GSBI4_UART_CLK] = &gsbi4_uart_clk.clkr,
2523         [GSBI5_UART_SRC] = &gsbi5_uart_src.clkr,
2524         [GSBI5_UART_CLK] = &gsbi5_uart_clk.clkr,
2525         [GSBI6_UART_SRC] = &gsbi6_uart_src.clkr,
2526         [GSBI6_UART_CLK] = &gsbi6_uart_clk.clkr,
2527         [GSBI7_UART_SRC] = &gsbi7_uart_src.clkr,
2528         [GSBI7_UART_CLK] = &gsbi7_uart_clk.clkr,
2529         [GSBI8_UART_SRC] = &gsbi8_uart_src.clkr,
2530         [GSBI8_UART_CLK] = &gsbi8_uart_clk.clkr,
2531         [GSBI9_UART_SRC] = &gsbi9_uart_src.clkr,
2532         [GSBI9_UART_CLK] = &gsbi9_uart_clk.clkr,
2533         [GSBI10_UART_SRC] = &gsbi10_uart_src.clkr,
2534         [GSBI10_UART_CLK] = &gsbi10_uart_clk.clkr,
2535         [GSBI11_UART_SRC] = &gsbi11_uart_src.clkr,
2536         [GSBI11_UART_CLK] = &gsbi11_uart_clk.clkr,
2537         [GSBI12_UART_SRC] = &gsbi12_uart_src.clkr,
2538         [GSBI12_UART_CLK] = &gsbi12_uart_clk.clkr,
2539         [GSBI1_QUP_SRC] = &gsbi1_qup_src.clkr,
2540         [GSBI1_QUP_CLK] = &gsbi1_qup_clk.clkr,
2541         [GSBI2_QUP_SRC] = &gsbi2_qup_src.clkr,
2542         [GSBI2_QUP_CLK] = &gsbi2_qup_clk.clkr,
2543         [GSBI3_QUP_SRC] = &gsbi3_qup_src.clkr,
2544         [GSBI3_QUP_CLK] = &gsbi3_qup_clk.clkr,
2545         [GSBI4_QUP_SRC] = &gsbi4_qup_src.clkr,
2546         [GSBI4_QUP_CLK] = &gsbi4_qup_clk.clkr,
2547         [GSBI5_QUP_SRC] = &gsbi5_qup_src.clkr,
2548         [GSBI5_QUP_CLK] = &gsbi5_qup_clk.clkr,
2549         [GSBI6_QUP_SRC] = &gsbi6_qup_src.clkr,
2550         [GSBI6_QUP_CLK] = &gsbi6_qup_clk.clkr,
2551         [GSBI7_QUP_SRC] = &gsbi7_qup_src.clkr,
2552         [GSBI7_QUP_CLK] = &gsbi7_qup_clk.clkr,
2553         [GSBI8_QUP_SRC] = &gsbi8_qup_src.clkr,
2554         [GSBI8_QUP_CLK] = &gsbi8_qup_clk.clkr,
2555         [GSBI9_QUP_SRC] = &gsbi9_qup_src.clkr,
2556         [GSBI9_QUP_CLK] = &gsbi9_qup_clk.clkr,
2557         [GSBI10_QUP_SRC] = &gsbi10_qup_src.clkr,
2558         [GSBI10_QUP_CLK] = &gsbi10_qup_clk.clkr,
2559         [GSBI11_QUP_SRC] = &gsbi11_qup_src.clkr,
2560         [GSBI11_QUP_CLK] = &gsbi11_qup_clk.clkr,
2561         [GSBI12_QUP_SRC] = &gsbi12_qup_src.clkr,
2562         [GSBI12_QUP_CLK] = &gsbi12_qup_clk.clkr,
2563         [GP0_SRC] = &gp0_src.clkr,
2564         [GP0_CLK] = &gp0_clk.clkr,
2565         [GP1_SRC] = &gp1_src.clkr,
2566         [GP1_CLK] = &gp1_clk.clkr,
2567         [GP2_SRC] = &gp2_src.clkr,
2568         [GP2_CLK] = &gp2_clk.clkr,
2569         [PMEM_CLK] = &pmem_clk.clkr,
2570         [PRNG_SRC] = &prng_src.clkr,
2571         [PRNG_CLK] = &prng_clk.clkr,
2572         [SDC1_SRC] = &sdc1_src.clkr,
2573         [SDC1_CLK] = &sdc1_clk.clkr,
2574         [SDC2_SRC] = &sdc2_src.clkr,
2575         [SDC2_CLK] = &sdc2_clk.clkr,
2576         [SDC3_SRC] = &sdc3_src.clkr,
2577         [SDC3_CLK] = &sdc3_clk.clkr,
2578         [SDC4_SRC] = &sdc4_src.clkr,
2579         [SDC4_CLK] = &sdc4_clk.clkr,
2580         [SDC5_SRC] = &sdc5_src.clkr,
2581         [SDC5_CLK] = &sdc5_clk.clkr,
2582         [TSIF_REF_SRC] = &tsif_ref_src.clkr,
2583         [TSIF_REF_CLK] = &tsif_ref_clk.clkr,
2584         [USB_HS1_XCVR_SRC] = &usb_hs1_xcvr_src.clkr,
2585         [USB_HS1_XCVR_CLK] = &usb_hs1_xcvr_clk.clkr,
2586         [USB_FS1_XCVR_FS_SRC] = &usb_fs1_xcvr_fs_src.clkr,
2587         [USB_FS1_XCVR_FS_CLK] = &usb_fs1_xcvr_fs_clk.clkr,
2588         [USB_FS1_SYSTEM_CLK] = &usb_fs1_system_clk.clkr,
2589         [USB_FS2_XCVR_FS_SRC] = &usb_fs2_xcvr_fs_src.clkr,
2590         [USB_FS2_XCVR_FS_CLK] = &usb_fs2_xcvr_fs_clk.clkr,
2591         [USB_FS2_SYSTEM_CLK] = &usb_fs2_system_clk.clkr,
2592         [GSBI1_H_CLK] = &gsbi1_h_clk.clkr,
2593         [GSBI2_H_CLK] = &gsbi2_h_clk.clkr,
2594         [GSBI3_H_CLK] = &gsbi3_h_clk.clkr,
2595         [GSBI4_H_CLK] = &gsbi4_h_clk.clkr,
2596         [GSBI5_H_CLK] = &gsbi5_h_clk.clkr,
2597         [GSBI6_H_CLK] = &gsbi6_h_clk.clkr,
2598         [GSBI7_H_CLK] = &gsbi7_h_clk.clkr,
2599         [GSBI8_H_CLK] = &gsbi8_h_clk.clkr,
2600         [GSBI9_H_CLK] = &gsbi9_h_clk.clkr,
2601         [GSBI10_H_CLK] = &gsbi10_h_clk.clkr,
2602         [GSBI11_H_CLK] = &gsbi11_h_clk.clkr,
2603         [GSBI12_H_CLK] = &gsbi12_h_clk.clkr,
2604         [TSIF_H_CLK] = &tsif_h_clk.clkr,
2605         [USB_FS1_H_CLK] = &usb_fs1_h_clk.clkr,
2606         [USB_FS2_H_CLK] = &usb_fs2_h_clk.clkr,
2607         [USB_HS1_H_CLK] = &usb_hs1_h_clk.clkr,
2608         [SDC1_H_CLK] = &sdc1_h_clk.clkr,
2609         [SDC2_H_CLK] = &sdc2_h_clk.clkr,
2610         [SDC3_H_CLK] = &sdc3_h_clk.clkr,
2611         [SDC4_H_CLK] = &sdc4_h_clk.clkr,
2612         [SDC5_H_CLK] = &sdc5_h_clk.clkr,
2613         [EBI2_2X_CLK] = &ebi2_2x_clk.clkr,
2614         [EBI2_CLK] = &ebi2_clk.clkr,
2615         [ADM0_CLK] = &adm0_clk.clkr,
2616         [ADM0_PBUS_CLK] = &adm0_pbus_clk.clkr,
2617         [ADM1_CLK] = &adm1_clk.clkr,
2618         [ADM1_PBUS_CLK] = &adm1_pbus_clk.clkr,
2619         [MODEM_AHB1_H_CLK] = &modem_ahb1_h_clk.clkr,
2620         [MODEM_AHB2_H_CLK] = &modem_ahb2_h_clk.clkr,
2621         [PMIC_ARB0_H_CLK] = &pmic_arb0_h_clk.clkr,
2622         [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
2623         [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
2624         [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
2625 };
2626
2627 static const struct qcom_reset_map gcc_msm8660_resets[] = {
2628         [AFAB_CORE_RESET] = { 0x2080, 7 },
2629         [SCSS_SYS_RESET] = { 0x20b4, 1 },
2630         [SCSS_SYS_POR_RESET] = { 0x20b4 },
2631         [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
2632         [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
2633         [AFAB_SMPSS_M0_RESET] = { 0x20b8 },
2634         [AFAB_EBI1_S_RESET] = { 0x20c0, 7 },
2635         [SFAB_CORE_RESET] = { 0x2120, 7 },
2636         [SFAB_ADM0_M0_RESET] = { 0x21e0, 7 },
2637         [SFAB_ADM0_M1_RESET] = { 0x21e4, 7 },
2638         [SFAB_ADM0_M2_RESET] = { 0x21e4, 7 },
2639         [ADM0_C2_RESET] = { 0x220c, 4 },
2640         [ADM0_C1_RESET] = { 0x220c, 3 },
2641         [ADM0_C0_RESET] = { 0x220c, 2 },
2642         [ADM0_PBUS_RESET] = { 0x220c, 1 },
2643         [ADM0_RESET] = { 0x220c },
2644         [SFAB_ADM1_M0_RESET] = { 0x2220, 7 },
2645         [SFAB_ADM1_M1_RESET] = { 0x2224, 7 },
2646         [SFAB_ADM1_M2_RESET] = { 0x2228, 7 },
2647         [MMFAB_ADM1_M3_RESET] = { 0x2240, 7 },
2648         [ADM1_C3_RESET] = { 0x226c, 5 },
2649         [ADM1_C2_RESET] = { 0x226c, 4 },
2650         [ADM1_C1_RESET] = { 0x226c, 3 },
2651         [ADM1_C0_RESET] = { 0x226c, 2 },
2652         [ADM1_PBUS_RESET] = { 0x226c, 1 },
2653         [ADM1_RESET] = { 0x226c },
2654         [IMEM0_RESET] = { 0x2280, 7 },
2655         [SFAB_LPASS_Q6_RESET] = { 0x23a0, 7 },
2656         [SFAB_AFAB_M_RESET] = { 0x23e0, 7 },
2657         [AFAB_SFAB_M0_RESET] = { 0x2420, 7 },
2658         [AFAB_SFAB_M1_RESET] = { 0x2424, 7 },
2659         [DFAB_CORE_RESET] = { 0x24ac, 7 },
2660         [SFAB_DFAB_M_RESET] = { 0x2500, 7 },
2661         [DFAB_SFAB_M_RESET] = { 0x2520, 7 },
2662         [DFAB_SWAY0_RESET] = { 0x2540, 7 },
2663         [DFAB_SWAY1_RESET] = { 0x2544, 7 },
2664         [DFAB_ARB0_RESET] = { 0x2560, 7 },
2665         [DFAB_ARB1_RESET] = { 0x2564, 7 },
2666         [PPSS_PROC_RESET] = { 0x2594, 1 },
2667         [PPSS_RESET] = { 0x2594 },
2668         [PMEM_RESET] = { 0x25a0, 7 },
2669         [DMA_BAM_RESET] = { 0x25c0, 7 },
2670         [SIC_RESET] = { 0x25e0, 7 },
2671         [SPS_TIC_RESET] = { 0x2600, 7 },
2672         [CFBP0_RESET] = { 0x2650, 7 },
2673         [CFBP1_RESET] = { 0x2654, 7 },
2674         [CFBP2_RESET] = { 0x2658, 7 },
2675         [EBI2_RESET] = { 0x2664, 7 },
2676         [SFAB_CFPB_M_RESET] = { 0x2680, 7 },
2677         [CFPB_MASTER_RESET] = { 0x26a0, 7 },
2678         [SFAB_CFPB_S_RESET] = { 0x26c0, 7 },
2679         [CFPB_SPLITTER_RESET] = { 0x26e0, 7 },
2680         [TSIF_RESET] = { 0x2700, 7 },
2681         [CE1_RESET] = { 0x2720, 7 },
2682         [CE2_RESET] = { 0x2740, 7 },
2683         [SFAB_SFPB_M_RESET] = { 0x2780, 7 },
2684         [SFAB_SFPB_S_RESET] = { 0x27a0, 7 },
2685         [RPM_PROC_RESET] = { 0x27c0, 7 },
2686         [RPM_BUS_RESET] = { 0x27c4, 7 },
2687         [RPM_MSG_RAM_RESET] = { 0x27e0, 7 },
2688         [PMIC_ARB0_RESET] = { 0x2800, 7 },
2689         [PMIC_ARB1_RESET] = { 0x2804, 7 },
2690         [PMIC_SSBI2_RESET] = { 0x280c, 12 },
2691         [SDC1_RESET] = { 0x2830 },
2692         [SDC2_RESET] = { 0x2850 },
2693         [SDC3_RESET] = { 0x2870 },
2694         [SDC4_RESET] = { 0x2890 },
2695         [SDC5_RESET] = { 0x28b0 },
2696         [USB_HS1_RESET] = { 0x2910 },
2697         [USB_HS2_XCVR_RESET] = { 0x2934, 1 },
2698         [USB_HS2_RESET] = { 0x2934 },
2699         [USB_FS1_XCVR_RESET] = { 0x2974, 1 },
2700         [USB_FS1_RESET] = { 0x2974 },
2701         [USB_FS2_XCVR_RESET] = { 0x2994, 1 },
2702         [USB_FS2_RESET] = { 0x2994 },
2703         [GSBI1_RESET] = { 0x29dc },
2704         [GSBI2_RESET] = { 0x29fc },
2705         [GSBI3_RESET] = { 0x2a1c },
2706         [GSBI4_RESET] = { 0x2a3c },
2707         [GSBI5_RESET] = { 0x2a5c },
2708         [GSBI6_RESET] = { 0x2a7c },
2709         [GSBI7_RESET] = { 0x2a9c },
2710         [GSBI8_RESET] = { 0x2abc },
2711         [GSBI9_RESET] = { 0x2adc },
2712         [GSBI10_RESET] = { 0x2afc },
2713         [GSBI11_RESET] = { 0x2b1c },
2714         [GSBI12_RESET] = { 0x2b3c },
2715         [SPDM_RESET] = { 0x2b6c },
2716         [SEC_CTRL_RESET] = { 0x2b80, 7 },
2717         [TLMM_H_RESET] = { 0x2ba0, 7 },
2718         [TLMM_RESET] = { 0x2ba4, 7 },
2719         [MARRM_PWRON_RESET] = { 0x2bd4, 1 },
2720         [MARM_RESET] = { 0x2bd4 },
2721         [MAHB1_RESET] = { 0x2be4, 7 },
2722         [SFAB_MSS_S_RESET] = { 0x2c00, 7 },
2723         [MAHB2_RESET] = { 0x2c20, 7 },
2724         [MODEM_SW_AHB_RESET] = { 0x2c48, 1 },
2725         [MODEM_RESET] = { 0x2c48 },
2726         [SFAB_MSS_MDM1_RESET] = { 0x2c4c, 1 },
2727         [SFAB_MSS_MDM0_RESET] = { 0x2c4c },
2728         [MSS_SLP_RESET] = { 0x2c60, 7 },
2729         [MSS_MARM_SAW_RESET] = { 0x2c68, 1 },
2730         [MSS_WDOG_RESET] = { 0x2c68 },
2731         [TSSC_RESET] = { 0x2ca0, 7 },
2732         [PDM_RESET] = { 0x2cc0, 12 },
2733         [SCSS_CORE0_RESET] = { 0x2d60, 1 },
2734         [SCSS_CORE0_POR_RESET] = { 0x2d60 },
2735         [SCSS_CORE1_RESET] = { 0x2d80, 1 },
2736         [SCSS_CORE1_POR_RESET] = { 0x2d80 },
2737         [MPM_RESET] = { 0x2da4, 1 },
2738         [EBI1_1X_DIV_RESET] = { 0x2dec, 9 },
2739         [EBI1_RESET] = { 0x2dec, 7 },
2740         [SFAB_SMPSS_S_RESET] = { 0x2e00, 7 },
2741         [USB_PHY0_RESET] = { 0x2e20 },
2742         [USB_PHY1_RESET] = { 0x2e40 },
2743         [PRNG_RESET] = { 0x2e80, 12 },
2744 };
2745
2746 static const struct regmap_config gcc_msm8660_regmap_config = {
2747         .reg_bits       = 32,
2748         .reg_stride     = 4,
2749         .val_bits       = 32,
2750         .max_register   = 0x363c,
2751         .fast_io        = true,
2752 };
2753
2754 static const struct qcom_cc_desc gcc_msm8660_desc = {
2755         .config = &gcc_msm8660_regmap_config,
2756         .clks = gcc_msm8660_clks,
2757         .num_clks = ARRAY_SIZE(gcc_msm8660_clks),
2758         .resets = gcc_msm8660_resets,
2759         .num_resets = ARRAY_SIZE(gcc_msm8660_resets),
2760 };
2761
2762 static const struct of_device_id gcc_msm8660_match_table[] = {
2763         { .compatible = "qcom,gcc-msm8660" },
2764         { }
2765 };
2766 MODULE_DEVICE_TABLE(of, gcc_msm8660_match_table);
2767
2768 static int gcc_msm8660_probe(struct platform_device *pdev)
2769 {
2770         int ret;
2771         struct device *dev = &pdev->dev;
2772
2773         ret = qcom_cc_register_board_clk(dev, "cxo_board", "cxo", 19200000);
2774         if (ret)
2775                 return ret;
2776
2777         ret = qcom_cc_register_board_clk(dev, "pxo_board", "pxo", 27000000);
2778         if (ret)
2779                 return ret;
2780
2781         return qcom_cc_probe(pdev, &gcc_msm8660_desc);
2782 }
2783
2784 static struct platform_driver gcc_msm8660_driver = {
2785         .probe          = gcc_msm8660_probe,
2786         .driver         = {
2787                 .name   = "gcc-msm8660",
2788                 .of_match_table = gcc_msm8660_match_table,
2789         },
2790 };
2791
2792 static int __init gcc_msm8660_init(void)
2793 {
2794         return platform_driver_register(&gcc_msm8660_driver);
2795 }
2796 core_initcall(gcc_msm8660_init);
2797
2798 static void __exit gcc_msm8660_exit(void)
2799 {
2800         platform_driver_unregister(&gcc_msm8660_driver);
2801 }
2802 module_exit(gcc_msm8660_exit);
2803
2804 MODULE_DESCRIPTION("GCC MSM 8660 Driver");
2805 MODULE_LICENSE("GPL v2");
2806 MODULE_ALIAS("platform:gcc-msm8660");