drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <drm/ttm/ttm_bo_api.h>
  33 #include <drm/ttm/ttm_bo_driver.h>
  34 #include <drm/ttm/ttm_placement.h>
  35 #include <drm/ttm/ttm_module.h>
  36 #include <drm/ttm/ttm_page_alloc.h>
  37 #include <drm/drmP.h>
  38 #include <drm/amdgpu_drm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/swap.h>
  43 #include <linux/pagemap.h>
  44 #include <linux/debugfs.h>
  45 #include <linux/iommu.h>
  46 #include "amdgpu.h"
  47 #include "amdgpu_object.h"
  48 #include "amdgpu_trace.h"
  49 #include "amdgpu_amdkfd.h"
  50 #include "amdgpu_sdma.h"
  51 #include "bif/bif_4_1_d.h"
  52
  53 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  54
  55 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
  56                              struct ttm_mem_reg *mem, unsigned num_pages,
  57                              uint64_t offset, unsigned window,
  58                              struct amdgpu_ring *ring,
  59                              uint64_t *addr);
  60
  61 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  62 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  63
  64 /*
  65  * Global memory.
  66  */
  67
  68 /**
  69  * amdgpu_ttm_mem_global_init - Initialize and acquire reference to
  70  * memory object
  71  *
  72  * @ref: Object for initialization.
  73  *
  74  * This is called by drm_global_item_ref() when an object is being
  75  * initialized.
  76  */
  77 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
  78 {
  79         return ttm_mem_global_init(ref->object);
  80 }
  81
  82 /**
  83  * amdgpu_ttm_mem_global_release - Drop reference to a memory object
  84  *
  85  * @ref: Object being removed
  86  *
  87  * This is called by drm_global_item_unref() when an object is being
  88  * released.
  89  */
  90 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
  91 {
  92         ttm_mem_global_release(ref->object);
  93 }
  94
  95 /**
  96  * amdgpu_ttm_global_init - Initialize global TTM memory reference structures.
  97  *
  98  * @adev: AMDGPU device for which the global structures need to be registered.
  99  *
 100  * This is called as part of the AMDGPU ttm init from amdgpu_ttm_init()
 101  * during bring up.
 102  */
 103 static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
 104 {
 105         struct drm_global_reference *global_ref;
 106         int r;
 107
 108         /* ensure reference is false in case init fails */
 109         adev->mman.mem_global_referenced = false;
 110
 111         global_ref = &adev->mman.mem_global_ref;
 112         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
 113         global_ref->size = sizeof(struct ttm_mem_global);
 114         global_ref->init = &amdgpu_ttm_mem_global_init;
 115         global_ref->release = &amdgpu_ttm_mem_global_release;
 116         r = drm_global_item_ref(global_ref);
 117         if (r) {
 118                 DRM_ERROR("Failed setting up TTM memory accounting "
 119                           "subsystem.\n");
 120                 goto error_mem;
 121         }
 122
 123         adev->mman.bo_global_ref.mem_glob =
 124                 adev->mman.mem_global_ref.object;
 125         global_ref = &adev->mman.bo_global_ref.ref;
 126         global_ref->global_type = DRM_GLOBAL_TTM_BO;
 127         global_ref->size = sizeof(struct ttm_bo_global);
 128         global_ref->init = &ttm_bo_global_init;
 129         global_ref->release = &ttm_bo_global_release;
 130         r = drm_global_item_ref(global_ref);
 131         if (r) {
 132                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 133                 goto error_bo;
 134         }
 135
 136         mutex_init(&adev->mman.gtt_window_lock);
 137
 138         adev->mman.mem_global_referenced = true;
 139
 140         return 0;
 141
 142 error_bo:
 143         drm_global_item_unref(&adev->mman.mem_global_ref);
 144 error_mem:
 145         return r;
 146 }
 147
 148 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
 149 {
 150         if (adev->mman.mem_global_referenced) {
 151                 mutex_destroy(&adev->mman.gtt_window_lock);
 152                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 153                 drm_global_item_unref(&adev->mman.mem_global_ref);
 154                 adev->mman.mem_global_referenced = false;
 155         }
 156 }
 157
 158 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 159 {
 160         return 0;
 161 }
 162
 163 /**
 164  * amdgpu_init_mem_type - Initialize a memory manager for a specific type of
 165  * memory request.
 166  *
 167  * @bdev: The TTM BO device object (contains a reference to amdgpu_device)
 168  * @type: The type of memory requested
 169  * @man: The memory type manager for each domain
 170  *
 171  * This is called by ttm_bo_init_mm() when a buffer object is being
 172  * initialized.
 173  */
 174 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 175                                 struct ttm_mem_type_manager *man)
 176 {
 177         struct amdgpu_device *adev;
 178
 179         adev = amdgpu_ttm_adev(bdev);
 180
 181         switch (type) {
 182         case TTM_PL_SYSTEM:
 183                 /* System memory */
 184                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 185                 man->available_caching = TTM_PL_MASK_CACHING;
 186                 man->default_caching = TTM_PL_FLAG_CACHED;
 187                 break;
 188         case TTM_PL_TT:
 189                 /* GTT memory  */
 190                 man->func = &amdgpu_gtt_mgr_func;
 191                 man->gpu_offset = adev->gmc.gart_start;
 192                 man->available_caching = TTM_PL_MASK_CACHING;
 193                 man->default_caching = TTM_PL_FLAG_CACHED;
 194                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 195                 break;
 196         case TTM_PL_VRAM:
 197                 /* "On-card" video ram */
 198                 man->func = &amdgpu_vram_mgr_func;
 199                 man->gpu_offset = adev->gmc.vram_start;
 200                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 201                              TTM_MEMTYPE_FLAG_MAPPABLE;
 202                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 203                 man->default_caching = TTM_PL_FLAG_WC;
 204                 break;
 205         case AMDGPU_PL_GDS:
 206         case AMDGPU_PL_GWS:
 207         case AMDGPU_PL_OA:
 208                 /* On-chip GDS memory*/
 209                 man->func = &ttm_bo_manager_func;
 210                 man->gpu_offset = 0;
 211                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 212                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 213                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 214                 break;
 215         default:
 216                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 217                 return -EINVAL;
 218         }
 219         return 0;
 220 }
 221
 222 /**
 223  * amdgpu_evict_flags - Compute placement flags
 224  *
 225  * @bo: The buffer object to evict
 226  * @placement: Possible destination(s) for evicted BO
 227  *
 228  * Fill in placement data when ttm_bo_evict() is called
 229  */
 230 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 231                                 struct ttm_placement *placement)
 232 {
 233         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 234         struct amdgpu_bo *abo;
 235         static const struct ttm_place placements = {
 236                 .fpfn = 0,
 237                 .lpfn = 0,
 238                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 239         };
 240
 241         /* Don't handle scatter gather BOs */
 242         if (bo->type == ttm_bo_type_sg) {
 243                 placement->num_placement = 0;
 244                 placement->num_busy_placement = 0;
 245                 return;
 246         }
 247
 248         /* Object isn't an AMDGPU object so ignore */
 249         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 250                 placement->placement = &placements;
 251                 placement->busy_placement = &placements;
 252                 placement->num_placement = 1;
 253                 placement->num_busy_placement = 1;
 254                 return;
 255         }
 256
 257         abo = ttm_to_amdgpu_bo(bo);
 258         switch (bo->mem.mem_type) {
 259         case AMDGPU_PL_GDS:
 260         case AMDGPU_PL_GWS:
 261         case AMDGPU_PL_OA:
 262                 placement->num_placement = 0;
 263                 placement->num_busy_placement = 0;
 264                 return;
 265
 266         case TTM_PL_VRAM:
 267                 if (!adev->mman.buffer_funcs_enabled) {
 268                         /* Move to system memory */
 269                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 270                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 271                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 272                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 273
 274                         /* Try evicting to the CPU inaccessible part of VRAM
 275                          * first, but only set GTT as busy placement, so this
 276                          * BO will be evicted to GTT rather than causing other
 277                          * BOs to be evicted from VRAM
 278                          */
 279                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 280                                                          AMDGPU_GEM_DOMAIN_GTT);
 281                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 282                         abo->placements[0].lpfn = 0;
 283                         abo->placement.busy_placement = &abo->placements[1];
 284                         abo->placement.num_busy_placement = 1;
 285                 } else {
 286                         /* Move to GTT memory */
 287                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 288                 }
 289                 break;
 290         case TTM_PL_TT:
 291         default:
 292                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 293                 break;
 294         }
 295         *placement = abo->placement;
 296 }
 297
 298 /**
 299  * amdgpu_verify_access - Verify access for a mmap call
 300  *
 301  * @bo: The buffer object to map
 302  * @filp: The file pointer from the process performing the mmap
 303  *
 304  * This is called by ttm_bo_mmap() to verify whether a process
 305  * has the right to mmap a BO to their process space.
 306  */
 307 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 308 {
 309         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 310
 311         /*
 312          * Don't verify access for KFD BOs. They don't have a GEM
 313          * object associated with them.
 314          */
 315         if (abo->kfd_bo)
 316                 return 0;
 317
 318         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 319                 return -EPERM;
 320         return drm_vma_node_verify_access(&abo->gem_base.vma_node,
 321                                           filp->private_data);
 322 }
 323
 324 /**
 325  * amdgpu_move_null - Register memory for a buffer object
 326  *
 327  * @bo: The bo to assign the memory to
 328  * @new_mem: The memory to be assigned.
 329  *
 330  * Assign the memory from new_mem to the memory of the buffer object bo.
 331  */
 332 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 333                              struct ttm_mem_reg *new_mem)
 334 {
 335         struct ttm_mem_reg *old_mem = &bo->mem;
 336
 337         BUG_ON(old_mem->mm_node != NULL);
 338         *old_mem = *new_mem;
 339         new_mem->mm_node = NULL;
 340 }
 341
 342 /**
 343  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 344  *
 345  * @bo: The bo to assign the memory to.
 346  * @mm_node: Memory manager node for drm allocator.
 347  * @mem: The region where the bo resides.
 348  *
 349  */
 350 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 351                                     struct drm_mm_node *mm_node,
 352                                     struct ttm_mem_reg *mem)
 353 {
 354         uint64_t addr = 0;
 355
 356         if (mm_node->start != AMDGPU_BO_INVALID_OFFSET) {
 357                 addr = mm_node->start << PAGE_SHIFT;
 358                 addr += bo->bdev->man[mem->mem_type].gpu_offset;
 359         }
 360         return addr;
 361 }
 362
 363 /**
 364  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 365  * @offset. It also modifies the offset to be within the drm_mm_node returned
 366  *
 367  * @mem: The region where the bo resides.
 368  * @offset: The offset that drm_mm_node is used for finding.
 369  *
 370  */
 371 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
 372                                                unsigned long *offset)
 373 {
 374         struct drm_mm_node *mm_node = mem->mm_node;
 375
 376         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 377                 *offset -= (mm_node->size << PAGE_SHIFT);
 378                 ++mm_node;
 379         }
 380         return mm_node;
 381 }
 382
 383 /**
 384  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 385  *
 386  * The function copies @size bytes from {src->mem + src->offset} to
 387  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 388  * move and different for a BO to BO copy.
 389  *
 390  * @f: Returns the last fence if multiple jobs are submitted.
 391  */
 392 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 393                                struct amdgpu_copy_mem *src,
 394                                struct amdgpu_copy_mem *dst,
 395                                uint64_t size,
 396                                struct reservation_object *resv,
 397                                struct dma_fence **f)
 398 {
 399         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 400         struct drm_mm_node *src_mm, *dst_mm;
 401         uint64_t src_node_start, dst_node_start, src_node_size,
 402                  dst_node_size, src_page_offset, dst_page_offset;
 403         struct dma_fence *fence = NULL;
 404         int r = 0;
 405         const uint64_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 406                                         AMDGPU_GPU_PAGE_SIZE);
 407
 408         if (!adev->mman.buffer_funcs_enabled) {
 409                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 410                 return -EINVAL;
 411         }
 412
 413         src_mm = amdgpu_find_mm_node(src->mem, &src->offset);
 414         src_node_start = amdgpu_mm_node_addr(src->bo, src_mm, src->mem) +
 415                                              src->offset;
 416         src_node_size = (src_mm->size << PAGE_SHIFT) - src->offset;
 417         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 418
 419         dst_mm = amdgpu_find_mm_node(dst->mem, &dst->offset);
 420         dst_node_start = amdgpu_mm_node_addr(dst->bo, dst_mm, dst->mem) +
 421                                              dst->offset;
 422         dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst->offset;
 423         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 424
 425         mutex_lock(&adev->mman.gtt_window_lock);
 426
 427         while (size) {
 428                 unsigned long cur_size;
 429                 uint64_t from = src_node_start, to = dst_node_start;
 430                 struct dma_fence *next;
 431
 432                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 433                  * begins at an offset, then adjust the size accordingly
 434                  */
 435                 cur_size = min3(min(src_node_size, dst_node_size), size,
 436                                 GTT_MAX_BYTES);
 437                 if (cur_size + src_page_offset > GTT_MAX_BYTES ||
 438                     cur_size + dst_page_offset > GTT_MAX_BYTES)
 439                         cur_size -= max(src_page_offset, dst_page_offset);
 440
 441                 /* Map only what needs to be accessed. Map src to window 0 and
 442                  * dst to window 1
 443                  */
 444                 if (src->mem->start == AMDGPU_BO_INVALID_OFFSET) {
 445                         r = amdgpu_map_buffer(src->bo, src->mem,
 446                                         PFN_UP(cur_size + src_page_offset),
 447                                         src_node_start, 0, ring,
 448                                         &from);
 449                         if (r)
 450                                 goto error;
 451                         /* Adjust the offset because amdgpu_map_buffer returns
 452                          * start of mapped page
 453                          */
 454                         from += src_page_offset;
 455                 }
 456
 457                 if (dst->mem->start == AMDGPU_BO_INVALID_OFFSET) {
 458                         r = amdgpu_map_buffer(dst->bo, dst->mem,
 459                                         PFN_UP(cur_size + dst_page_offset),
 460                                         dst_node_start, 1, ring,
 461                                         &to);
 462                         if (r)
 463                                 goto error;
 464                         to += dst_page_offset;
 465                 }
 466
 467                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 468                                        resv, &next, false, true);
 469                 if (r)
 470                         goto error;
 471
 472                 dma_fence_put(fence);
 473                 fence = next;
 474
 475                 size -= cur_size;
 476                 if (!size)
 477                         break;
 478
 479                 src_node_size -= cur_size;
 480                 if (!src_node_size) {
 481                         src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm,
 482                                                              src->mem);
 483                         src_node_size = (src_mm->size << PAGE_SHIFT);
 484                 } else {
 485                         src_node_start += cur_size;
 486                         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 487                 }
 488                 dst_node_size -= cur_size;
 489                 if (!dst_node_size) {
 490                         dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm,
 491                                                              dst->mem);
 492                         dst_node_size = (dst_mm->size << PAGE_SHIFT);
 493                 } else {
 494                         dst_node_start += cur_size;
 495                         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 496                 }
 497         }
 498 error:
 499         mutex_unlock(&adev->mman.gtt_window_lock);
 500         if (f)
 501                 *f = dma_fence_get(fence);
 502         dma_fence_put(fence);
 503         return r;
 504 }
 505
 506 /**
 507  * amdgpu_move_blit - Copy an entire buffer to another buffer
 508  *
 509  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 510  * help move buffers to and from VRAM.
 511  */
 512 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 513                             bool evict, bool no_wait_gpu,
 514                             struct ttm_mem_reg *new_mem,
 515                             struct ttm_mem_reg *old_mem)
 516 {
 517         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 518         struct amdgpu_copy_mem src, dst;
 519         struct dma_fence *fence = NULL;
 520         int r;
 521
 522         src.bo = bo;
 523         dst.bo = bo;
 524         src.mem = old_mem;
 525         dst.mem = new_mem;
 526         src.offset = 0;
 527         dst.offset = 0;
 528
 529         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 530                                        new_mem->num_pages << PAGE_SHIFT,
 531                                        bo->resv, &fence);
 532         if (r)
 533                 goto error;
 534
 535         /* Always block for VM page tables before committing the new location */
 536         if (bo->type == ttm_bo_type_kernel)
 537                 r = ttm_bo_move_accel_cleanup(bo, fence, true, new_mem);
 538         else
 539                 r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 540         dma_fence_put(fence);
 541         return r;
 542
 543 error:
 544         if (fence)
 545                 dma_fence_wait(fence, false);
 546         dma_fence_put(fence);
 547         return r;
 548 }
 549
 550 /**
 551  * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
 552  *
 553  * Called by amdgpu_bo_move().
 554  */
 555 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 556                                 struct ttm_operation_ctx *ctx,
 557                                 struct ttm_mem_reg *new_mem)
 558 {
 559         struct amdgpu_device *adev;
 560         struct ttm_mem_reg *old_mem = &bo->mem;
 561         struct ttm_mem_reg tmp_mem;
 562         struct ttm_place placements;
 563         struct ttm_placement placement;
 564         int r;
 565
 566         adev = amdgpu_ttm_adev(bo->bdev);
 567
 568         /* create space/pages for new_mem in GTT space */
 569         tmp_mem = *new_mem;
 570         tmp_mem.mm_node = NULL;
 571         placement.num_placement = 1;
 572         placement.placement = &placements;
 573         placement.num_busy_placement = 1;
 574         placement.busy_placement = &placements;
 575         placements.fpfn = 0;
 576         placements.lpfn = 0;
 577         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 578         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 579         if (unlikely(r)) {
 580                 return r;
 581         }
 582
 583         /* set caching flags */
 584         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 585         if (unlikely(r)) {
 586                 goto out_cleanup;
 587         }
 588
 589         /* Bind the memory to the GTT space */
 590         r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
 591         if (unlikely(r)) {
 592                 goto out_cleanup;
 593         }
 594
 595         /* blit VRAM to GTT */
 596         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, &tmp_mem, old_mem);
 597         if (unlikely(r)) {
 598                 goto out_cleanup;
 599         }
 600
 601         /* move BO (in tmp_mem) to new_mem */
 602         r = ttm_bo_move_ttm(bo, ctx, new_mem);
 603 out_cleanup:
 604         ttm_bo_mem_put(bo, &tmp_mem);
 605         return r;
 606 }
 607
 608 /**
 609  * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
 610  *
 611  * Called by amdgpu_bo_move().
 612  */
 613 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 614                                 struct ttm_operation_ctx *ctx,
 615                                 struct ttm_mem_reg *new_mem)
 616 {
 617         struct amdgpu_device *adev;
 618         struct ttm_mem_reg *old_mem = &bo->mem;
 619         struct ttm_mem_reg tmp_mem;
 620         struct ttm_placement placement;
 621         struct ttm_place placements;
 622         int r;
 623
 624         adev = amdgpu_ttm_adev(bo->bdev);
 625
 626         /* make space in GTT for old_mem buffer */
 627         tmp_mem = *new_mem;
 628         tmp_mem.mm_node = NULL;
 629         placement.num_placement = 1;
 630         placement.placement = &placements;
 631         placement.num_busy_placement = 1;
 632         placement.busy_placement = &placements;
 633         placements.fpfn = 0;
 634         placements.lpfn = 0;
 635         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 636         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 637         if (unlikely(r)) {
 638                 return r;
 639         }
 640
 641         /* move/bind old memory to GTT space */
 642         r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
 643         if (unlikely(r)) {
 644                 goto out_cleanup;
 645         }
 646
 647         /* copy to VRAM */
 648         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem);
 649         if (unlikely(r)) {
 650                 goto out_cleanup;
 651         }
 652 out_cleanup:
 653         ttm_bo_mem_put(bo, &tmp_mem);
 654         return r;
 655 }
 656
 657 /**
 658  * amdgpu_bo_move - Move a buffer object to a new memory location
 659  *
 660  * Called by ttm_bo_handle_move_mem()
 661  */
 662 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 663                           struct ttm_operation_ctx *ctx,
 664                           struct ttm_mem_reg *new_mem)
 665 {
 666         struct amdgpu_device *adev;
 667         struct amdgpu_bo *abo;
 668         struct ttm_mem_reg *old_mem = &bo->mem;
 669         int r;
 670
 671         /* Can't move a pinned BO */
 672         abo = ttm_to_amdgpu_bo(bo);
 673         if (WARN_ON_ONCE(abo->pin_count > 0))
 674                 return -EINVAL;
 675
 676         adev = amdgpu_ttm_adev(bo->bdev);
 677
 678         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 679                 amdgpu_move_null(bo, new_mem);
 680                 return 0;
 681         }
 682         if ((old_mem->mem_type == TTM_PL_TT &&
 683              new_mem->mem_type == TTM_PL_SYSTEM) ||
 684             (old_mem->mem_type == TTM_PL_SYSTEM &&
 685              new_mem->mem_type == TTM_PL_TT)) {
 686                 /* bind is enough */
 687                 amdgpu_move_null(bo, new_mem);
 688                 return 0;
 689         }
 690         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 691             old_mem->mem_type == AMDGPU_PL_GWS ||
 692             old_mem->mem_type == AMDGPU_PL_OA ||
 693             new_mem->mem_type == AMDGPU_PL_GDS ||
 694             new_mem->mem_type == AMDGPU_PL_GWS ||
 695             new_mem->mem_type == AMDGPU_PL_OA) {
 696                 /* Nothing to save here */
 697                 amdgpu_move_null(bo, new_mem);
 698                 return 0;
 699         }
 700
 701         if (!adev->mman.buffer_funcs_enabled)
 702                 goto memcpy;
 703
 704         if (old_mem->mem_type == TTM_PL_VRAM &&
 705             new_mem->mem_type == TTM_PL_SYSTEM) {
 706                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 707         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 708                    new_mem->mem_type == TTM_PL_VRAM) {
 709                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 710         } else {
 711                 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
 712                                      new_mem, old_mem);
 713         }
 714
 715         if (r) {
 716 memcpy:
 717                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 718                 if (r) {
 719                         return r;
 720                 }
 721         }
 722
 723         if (bo->type == ttm_bo_type_device &&
 724             new_mem->mem_type == TTM_PL_VRAM &&
 725             old_mem->mem_type != TTM_PL_VRAM) {
 726                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 727                  * accesses the BO after it's moved.
 728                  */
 729                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 730         }
 731
 732         /* update statistics */
 733         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 734         return 0;
 735 }
 736
 737 /**
 738  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 739  *
 740  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 741  */
 742 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 743 {
 744         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 745         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 746         struct drm_mm_node *mm_node = mem->mm_node;
 747
 748         mem->bus.addr = NULL;
 749         mem->bus.offset = 0;
 750         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 751         mem->bus.base = 0;
 752         mem->bus.is_iomem = false;
 753         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 754                 return -EINVAL;
 755         switch (mem->mem_type) {
 756         case TTM_PL_SYSTEM:
 757                 /* system memory */
 758                 return 0;
 759         case TTM_PL_TT:
 760                 break;
 761         case TTM_PL_VRAM:
 762                 mem->bus.offset = mem->start << PAGE_SHIFT;
 763                 /* check if it's visible */
 764                 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size)
 765                         return -EINVAL;
 766                 /* Only physically contiguous buffers apply. In a contiguous
 767                  * buffer, size of the first mm_node would match the number of
 768                  * pages in ttm_mem_reg.
 769                  */
 770                 if (adev->mman.aper_base_kaddr &&
 771                     (mm_node->size == mem->num_pages))
 772                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 773                                         mem->bus.offset;
 774
 775                 mem->bus.base = adev->gmc.aper_base;
 776                 mem->bus.is_iomem = true;
 777                 break;
 778         default:
 779                 return -EINVAL;
 780         }
 781         return 0;
 782 }
 783
 784 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 785 {
 786 }
 787
 788 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 789                                            unsigned long page_offset)
 790 {
 791         struct drm_mm_node *mm;
 792         unsigned long offset = (page_offset << PAGE_SHIFT);
 793
 794         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 795         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
 796                 (offset >> PAGE_SHIFT);
 797 }
 798
 799 /*
 800  * TTM backend functions.
 801  */
 802 struct amdgpu_ttm_gup_task_list {
 803         struct list_head        list;
 804         struct task_struct      *task;
 805 };
 806
 807 struct amdgpu_ttm_tt {
 808         struct ttm_dma_tt       ttm;
 809         u64                     offset;
 810         uint64_t                userptr;
 811         struct task_struct      *usertask;
 812         uint32_t                userflags;
 813         spinlock_t              guptasklock;
 814         struct list_head        guptasks;
 815         atomic_t                mmu_invalidations;
 816         uint32_t                last_set_pages;
 817 };
 818
 819 /**
 820  * amdgpu_ttm_tt_get_user_pages - Pin pages of memory pointed to by a USERPTR
 821  * pointer to memory
 822  *
 823  * Called by amdgpu_gem_userptr_ioctl() and amdgpu_cs_parser_bos().
 824  * This provides a wrapper around the get_user_pages() call to provide
 825  * device accessible pages that back user memory.
 826  */
 827 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 828 {
 829         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 830         struct mm_struct *mm = gtt->usertask->mm;
 831         unsigned int flags = 0;
 832         unsigned pinned = 0;
 833         int r;
 834
 835         if (!mm) /* Happens during process shutdown */
 836                 return -ESRCH;
 837
 838         if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 839                 flags |= FOLL_WRITE;
 840
 841         down_read(&mm->mmap_sem);
 842
 843         if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
 844                 /*
 845                  * check that we only use anonymous memory to prevent problems
 846                  * with writeback
 847                  */
 848                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 849                 struct vm_area_struct *vma;
 850
 851                 vma = find_vma(mm, gtt->userptr);
 852                 if (!vma || vma->vm_file || vma->vm_end < end) {
 853                         up_read(&mm->mmap_sem);
 854                         return -EPERM;
 855                 }
 856         }
 857
 858         /* loop enough times using contiguous pages of memory */
 859         do {
 860                 unsigned num_pages = ttm->num_pages - pinned;
 861                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 862                 struct page **p = pages + pinned;
 863                 struct amdgpu_ttm_gup_task_list guptask;
 864
 865                 guptask.task = current;
 866                 spin_lock(&gtt->guptasklock);
 867                 list_add(&guptask.list, &gtt->guptasks);
 868                 spin_unlock(&gtt->guptasklock);
 869
 870                 if (mm == current->mm)
 871                         r = get_user_pages(userptr, num_pages, flags, p, NULL);
 872                 else
 873                         r = get_user_pages_remote(gtt->usertask,
 874                                         mm, userptr, num_pages,
 875                                         flags, p, NULL, NULL);
 876
 877                 spin_lock(&gtt->guptasklock);
 878                 list_del(&guptask.list);
 879                 spin_unlock(&gtt->guptasklock);
 880
 881                 if (r < 0)
 882                         goto release_pages;
 883
 884                 pinned += r;
 885
 886         } while (pinned < ttm->num_pages);
 887
 888         up_read(&mm->mmap_sem);
 889         return 0;
 890
 891 release_pages:
 892         release_pages(pages, pinned);
 893         up_read(&mm->mmap_sem);
 894         return r;
 895 }
 896
 897 /**
 898  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 899  *
 900  * Called by amdgpu_cs_list_validate(). This creates the page list
 901  * that backs user memory and will ultimately be mapped into the device
 902  * address space.
 903  */
 904 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 905 {
 906         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 907         unsigned i;
 908
 909         gtt->last_set_pages = atomic_read(&gtt->mmu_invalidations);
 910         for (i = 0; i < ttm->num_pages; ++i) {
 911                 if (ttm->pages[i])
 912                         put_page(ttm->pages[i]);
 913
 914                 ttm->pages[i] = pages ? pages[i] : NULL;
 915         }
 916 }
 917
 918 /**
 919  * amdgpu_ttm_tt_mark_user_page - Mark pages as dirty
 920  *
 921  * Called while unpinning userptr pages
 922  */
 923 void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm)
 924 {
 925         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 926         unsigned i;
 927
 928         for (i = 0; i < ttm->num_pages; ++i) {
 929                 struct page *page = ttm->pages[i];
 930
 931                 if (!page)
 932                         continue;
 933
 934                 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 935                         set_page_dirty(page);
 936
 937                 mark_page_accessed(page);
 938         }
 939 }
 940
 941 /**
 942  * amdgpu_ttm_tt_pin_userptr -  prepare the sg table with the user pages
 943  *
 944  * Called by amdgpu_ttm_backend_bind()
 945  **/
 946 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 947 {
 948         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 949         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 950         unsigned nents;
 951         int r;
 952
 953         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 954         enum dma_data_direction direction = write ?
 955                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 956
 957         /* Allocate an SG array and squash pages into it */
 958         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 959                                       ttm->num_pages << PAGE_SHIFT,
 960                                       GFP_KERNEL);
 961         if (r)
 962                 goto release_sg;
 963
 964         /* Map SG to device */
 965         r = -ENOMEM;
 966         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 967         if (nents != ttm->sg->nents)
 968                 goto release_sg;
 969
 970         /* convert SG to linear array of pages and dma addresses */
 971         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 972                                          gtt->ttm.dma_address, ttm->num_pages);
 973
 974         return 0;
 975
 976 release_sg:
 977         kfree(ttm->sg);
 978         return r;
 979 }
 980
 981 /**
 982  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 983  */
 984 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 985 {
 986         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 987         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 988
 989         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 990         enum dma_data_direction direction = write ?
 991                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 992
 993         /* double check that we don't free the table twice */
 994         if (!ttm->sg->sgl)
 995                 return;
 996
 997         /* unmap the pages mapped to the device */
 998         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 999
1000         /* mark the pages as dirty */
1001         amdgpu_ttm_tt_mark_user_pages(ttm);
1002
1003         sg_free_table(ttm->sg);
1004 }
1005
1006 int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
1007                                 struct ttm_buffer_object *tbo,
1008                                 uint64_t flags)
1009 {
1010         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
1011         struct ttm_tt *ttm = tbo->ttm;
1012         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1013         int r;
1014
1015         if (abo->flags & AMDGPU_GEM_CREATE_MQD_GFX9) {
1016                 uint64_t page_idx = 1;
1017
1018                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
1019                                 ttm->pages, gtt->ttm.dma_address, flags);
1020                 if (r)
1021                         goto gart_bind_fail;
1022
1023                 /* Patch mtype of the second part BO */
1024                 flags &=  ~AMDGPU_PTE_MTYPE_MASK;
1025                 flags |= AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_NC);
1026
1027                 r = amdgpu_gart_bind(adev,
1028                                 gtt->offset + (page_idx << PAGE_SHIFT),
1029                                 ttm->num_pages - page_idx,
1030                                 &ttm->pages[page_idx],
1031                                 &(gtt->ttm.dma_address[page_idx]), flags);
1032         } else {
1033                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1034                                      ttm->pages, gtt->ttm.dma_address, flags);
1035         }
1036
1037 gart_bind_fail:
1038         if (r)
1039                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1040                           ttm->num_pages, gtt->offset);
1041
1042         return r;
1043 }
1044
1045 /**
1046  * amdgpu_ttm_backend_bind - Bind GTT memory
1047  *
1048  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1049  * This handles binding GTT memory to the device address space.
1050  */
1051 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
1052                                    struct ttm_mem_reg *bo_mem)
1053 {
1054         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1055         struct amdgpu_ttm_tt *gtt = (void*)ttm;
1056         uint64_t flags;
1057         int r = 0;
1058
1059         if (gtt->userptr) {
1060                 r = amdgpu_ttm_tt_pin_userptr(ttm);
1061                 if (r) {
1062                         DRM_ERROR("failed to pin userptr\n");
1063                         return r;
1064                 }
1065         }
1066         if (!ttm->num_pages) {
1067                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1068                      ttm->num_pages, bo_mem, ttm);
1069         }
1070
1071         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1072             bo_mem->mem_type == AMDGPU_PL_GWS ||
1073             bo_mem->mem_type == AMDGPU_PL_OA)
1074                 return -EINVAL;
1075
1076         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1077                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1078                 return 0;
1079         }
1080
1081         /* compute PTE flags relevant to this BO memory */
1082         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1083
1084         /* bind pages into GART page tables */
1085         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1086         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1087                 ttm->pages, gtt->ttm.dma_address, flags);
1088
1089         if (r)
1090                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1091                           ttm->num_pages, gtt->offset);
1092         return r;
1093 }
1094
1095 /**
1096  * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1097  */
1098 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1099 {
1100         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1101         struct ttm_operation_ctx ctx = { false, false };
1102         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1103         struct ttm_mem_reg tmp;
1104         struct ttm_placement placement;
1105         struct ttm_place placements;
1106         uint64_t addr, flags;
1107         int r;
1108
1109         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
1110                 return 0;
1111
1112         addr = amdgpu_gmc_agp_addr(bo);
1113         if (addr != AMDGPU_BO_INVALID_OFFSET) {
1114                 bo->mem.start = addr >> PAGE_SHIFT;
1115         } else {
1116
1117                 /* allocate GART space */
1118                 tmp = bo->mem;
1119                 tmp.mm_node = NULL;
1120                 placement.num_placement = 1;
1121                 placement.placement = &placements;
1122                 placement.num_busy_placement = 1;
1123                 placement.busy_placement = &placements;
1124                 placements.fpfn = 0;
1125                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1126                 placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
1127                         TTM_PL_FLAG_TT;
1128
1129                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1130                 if (unlikely(r))
1131                         return r;
1132
1133                 /* compute PTE flags for this buffer object */
1134                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1135
1136                 /* Bind pages */
1137                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1138                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
1139                 if (unlikely(r)) {
1140                         ttm_bo_mem_put(bo, &tmp);
1141                         return r;
1142                 }
1143
1144                 ttm_bo_mem_put(bo, &bo->mem);
1145                 bo->mem = tmp;
1146         }
1147
1148         bo->offset = (bo->mem.start << PAGE_SHIFT) +
1149                 bo->bdev->man[bo->mem.mem_type].gpu_offset;
1150
1151         return 0;
1152 }
1153
1154 /**
1155  * amdgpu_ttm_recover_gart - Rebind GTT pages
1156  *
1157  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1158  * rebind GTT pages during a GPU reset.
1159  */
1160 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1161 {
1162         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1163         uint64_t flags;
1164         int r;
1165
1166         if (!tbo->ttm)
1167                 return 0;
1168
1169         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1170         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1171
1172         return r;
1173 }
1174
1175 /**
1176  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1177  *
1178  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1179  * ttm_tt_destroy().
1180  */
1181 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
1182 {
1183         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1184         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1185         int r;
1186
1187         /* if the pages have userptr pinning then clear that first */
1188         if (gtt->userptr)
1189                 amdgpu_ttm_tt_unpin_userptr(ttm);
1190
1191         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1192                 return 0;
1193
1194         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1195         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1196         if (r)
1197                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1198                           gtt->ttm.ttm.num_pages, gtt->offset);
1199         return r;
1200 }
1201
1202 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
1203 {
1204         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1205
1206         if (gtt->usertask)
1207                 put_task_struct(gtt->usertask);
1208
1209         ttm_dma_tt_fini(&gtt->ttm);
1210         kfree(gtt);
1211 }
1212
1213 static struct ttm_backend_func amdgpu_backend_func = {
1214         .bind = &amdgpu_ttm_backend_bind,
1215         .unbind = &amdgpu_ttm_backend_unbind,
1216         .destroy = &amdgpu_ttm_backend_destroy,
1217 };
1218
1219 /**
1220  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1221  *
1222  * @bo: The buffer object to create a GTT ttm_tt object around
1223  *
1224  * Called by ttm_tt_create().
1225  */
1226 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1227                                            uint32_t page_flags)
1228 {
1229         struct amdgpu_device *adev;
1230         struct amdgpu_ttm_tt *gtt;
1231
1232         adev = amdgpu_ttm_adev(bo->bdev);
1233
1234         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1235         if (gtt == NULL) {
1236                 return NULL;
1237         }
1238         gtt->ttm.ttm.func = &amdgpu_backend_func;
1239
1240         /* allocate space for the uninitialized page entries */
1241         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {
1242                 kfree(gtt);
1243                 return NULL;
1244         }
1245         return &gtt->ttm.ttm;
1246 }
1247
1248 /**
1249  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1250  *
1251  * Map the pages of a ttm_tt object to an address space visible
1252  * to the underlying device.
1253  */
1254 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
1255                         struct ttm_operation_ctx *ctx)
1256 {
1257         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1258         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1259         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1260
1261         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1262         if (gtt && gtt->userptr) {
1263                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1264                 if (!ttm->sg)
1265                         return -ENOMEM;
1266
1267                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1268                 ttm->state = tt_unbound;
1269                 return 0;
1270         }
1271
1272         if (slave && ttm->sg) {
1273                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1274                                                  gtt->ttm.dma_address,
1275                                                  ttm->num_pages);
1276                 ttm->state = tt_unbound;
1277                 return 0;
1278         }
1279
1280 #ifdef CONFIG_SWIOTLB
1281         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1282                 return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
1283         }
1284 #endif
1285
1286         /* fall back to generic helper to populate the page array
1287          * and map them to the device */
1288         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1289 }
1290
1291 /**
1292  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1293  *
1294  * Unmaps pages of a ttm_tt object from the device address space and
1295  * unpopulates the page array backing it.
1296  */
1297 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1298 {
1299         struct amdgpu_device *adev;
1300         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1301         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1302
1303         if (gtt && gtt->userptr) {
1304                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1305                 kfree(ttm->sg);
1306                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1307                 return;
1308         }
1309
1310         if (slave)
1311                 return;
1312
1313         adev = amdgpu_ttm_adev(ttm->bdev);
1314
1315 #ifdef CONFIG_SWIOTLB
1316         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1317                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1318                 return;
1319         }
1320 #endif
1321
1322         /* fall back to generic helper to unmap and unpopulate array */
1323         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1324 }
1325
1326 /**
1327  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1328  * task
1329  *
1330  * @ttm: The ttm_tt object to bind this userptr object to
1331  * @addr:  The address in the current tasks VM space to use
1332  * @flags: Requirements of userptr object.
1333  *
1334  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1335  * to current task
1336  */
1337 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1338                               uint32_t flags)
1339 {
1340         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1341
1342         if (gtt == NULL)
1343                 return -EINVAL;
1344
1345         gtt->userptr = addr;
1346         gtt->userflags = flags;
1347
1348         if (gtt->usertask)
1349                 put_task_struct(gtt->usertask);
1350         gtt->usertask = current->group_leader;
1351         get_task_struct(gtt->usertask);
1352
1353         spin_lock_init(&gtt->guptasklock);
1354         INIT_LIST_HEAD(&gtt->guptasks);
1355         atomic_set(&gtt->mmu_invalidations, 0);
1356         gtt->last_set_pages = 0;
1357
1358         return 0;
1359 }
1360
1361 /**
1362  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1363  */
1364 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1365 {
1366         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1367
1368         if (gtt == NULL)
1369                 return NULL;
1370
1371         if (gtt->usertask == NULL)
1372                 return NULL;
1373
1374         return gtt->usertask->mm;
1375 }
1376
1377 /**
1378  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1379  * address range for the current task.
1380  *
1381  */
1382 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1383                                   unsigned long end)
1384 {
1385         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1386         struct amdgpu_ttm_gup_task_list *entry;
1387         unsigned long size;
1388
1389         if (gtt == NULL || !gtt->userptr)
1390                 return false;
1391
1392         /* Return false if no part of the ttm_tt object lies within
1393          * the range
1394          */
1395         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1396         if (gtt->userptr > end || gtt->userptr + size <= start)
1397                 return false;
1398
1399         /* Search the lists of tasks that hold this mapping and see
1400          * if current is one of them.  If it is return false.
1401          */
1402         spin_lock(&gtt->guptasklock);
1403         list_for_each_entry(entry, &gtt->guptasks, list) {
1404                 if (entry->task == current) {
1405                         spin_unlock(&gtt->guptasklock);
1406                         return false;
1407                 }
1408         }
1409         spin_unlock(&gtt->guptasklock);
1410
1411         atomic_inc(&gtt->mmu_invalidations);
1412
1413         return true;
1414 }
1415
1416 /**
1417  * amdgpu_ttm_tt_userptr_invalidated - Has the ttm_tt object been invalidated?
1418  */
1419 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1420                                        int *last_invalidated)
1421 {
1422         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1423         int prev_invalidated = *last_invalidated;
1424
1425         *last_invalidated = atomic_read(&gtt->mmu_invalidations);
1426         return prev_invalidated != *last_invalidated;
1427 }
1428
1429 /**
1430  * amdgpu_ttm_tt_userptr_needs_pages - Have the pages backing this ttm_tt object
1431  * been invalidated since the last time they've been set?
1432  */
1433 bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm)
1434 {
1435         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1436
1437         if (gtt == NULL || !gtt->userptr)
1438                 return false;
1439
1440         return atomic_read(&gtt->mmu_invalidations) != gtt->last_set_pages;
1441 }
1442
1443 /**
1444  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1445  */
1446 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1447 {
1448         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1449
1450         if (gtt == NULL)
1451                 return false;
1452
1453         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1454 }
1455
1456 /**
1457  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1458  *
1459  * @ttm: The ttm_tt object to compute the flags for
1460  * @mem: The memory registry backing this ttm_tt object
1461  *
1462  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1463  */
1464 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
1465 {
1466         uint64_t flags = 0;
1467
1468         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1469                 flags |= AMDGPU_PTE_VALID;
1470
1471         if (mem && mem->mem_type == TTM_PL_TT) {
1472                 flags |= AMDGPU_PTE_SYSTEM;
1473
1474                 if (ttm->caching_state == tt_cached)
1475                         flags |= AMDGPU_PTE_SNOOPED;
1476         }
1477
1478         return flags;
1479 }
1480
1481 /**
1482  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1483  *
1484  * @ttm: The ttm_tt object to compute the flags for
1485  * @mem: The memory registry backing this ttm_tt object
1486
1487  * Figure out the flags to use for a VM PTE (Page Table Entry).
1488  */
1489 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1490                                  struct ttm_mem_reg *mem)
1491 {
1492         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1493
1494         flags |= adev->gart.gart_pte_flags;
1495         flags |= AMDGPU_PTE_READABLE;
1496
1497         if (!amdgpu_ttm_tt_is_readonly(ttm))
1498                 flags |= AMDGPU_PTE_WRITEABLE;
1499
1500         return flags;
1501 }
1502
1503 /**
1504  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1505  * object.
1506  *
1507  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1508  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1509  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1510  * used to clean out a memory space.
1511  */
1512 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1513                                             const struct ttm_place *place)
1514 {
1515         unsigned long num_pages = bo->mem.num_pages;
1516         struct drm_mm_node *node = bo->mem.mm_node;
1517         struct reservation_object_list *flist;
1518         struct dma_fence *f;
1519         int i;
1520
1521         /* If bo is a KFD BO, check if the bo belongs to the current process.
1522          * If true, then return false as any KFD process needs all its BOs to
1523          * be resident to run successfully
1524          */
1525         flist = reservation_object_get_list(bo->resv);
1526         if (flist) {
1527                 for (i = 0; i < flist->shared_count; ++i) {
1528                         f = rcu_dereference_protected(flist->shared[i],
1529                                 reservation_object_held(bo->resv));
1530                         if (amdkfd_fence_check_mm(f, current->mm))
1531                                 return false;
1532                 }
1533         }
1534
1535         switch (bo->mem.mem_type) {
1536         case TTM_PL_TT:
1537                 return true;
1538
1539         case TTM_PL_VRAM:
1540                 /* Check each drm MM node individually */
1541                 while (num_pages) {
1542                         if (place->fpfn < (node->start + node->size) &&
1543                             !(place->lpfn && place->lpfn <= node->start))
1544                                 return true;
1545
1546                         num_pages -= node->size;
1547                         ++node;
1548                 }
1549                 return false;
1550
1551         default:
1552                 break;
1553         }
1554
1555         return ttm_bo_eviction_valuable(bo, place);
1556 }
1557
1558 /**
1559  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1560  *
1561  * @bo:  The buffer object to read/write
1562  * @offset:  Offset into buffer object
1563  * @buf:  Secondary buffer to write/read from
1564  * @len: Length in bytes of access
1565  * @write:  true if writing
1566  *
1567  * This is used to access VRAM that backs a buffer object via MMIO
1568  * access for debugging purposes.
1569  */
1570 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1571                                     unsigned long offset,
1572                                     void *buf, int len, int write)
1573 {
1574         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1575         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1576         struct drm_mm_node *nodes;
1577         uint32_t value = 0;
1578         int ret = 0;
1579         uint64_t pos;
1580         unsigned long flags;
1581
1582         if (bo->mem.mem_type != TTM_PL_VRAM)
1583                 return -EIO;
1584
1585         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset);
1586         pos = (nodes->start << PAGE_SHIFT) + offset;
1587
1588         while (len && pos < adev->gmc.mc_vram_size) {
1589                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1590                 uint32_t bytes = 4 - (pos & 3);
1591                 uint32_t shift = (pos & 3) * 8;
1592                 uint32_t mask = 0xffffffff << shift;
1593
1594                 if (len < bytes) {
1595                         mask &= 0xffffffff >> (bytes - len) * 8;
1596                         bytes = len;
1597                 }
1598
1599                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1600                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1601                 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1602                 if (!write || mask != 0xffffffff)
1603                         value = RREG32_NO_KIQ(mmMM_DATA);
1604                 if (write) {
1605                         value &= ~mask;
1606                         value |= (*(uint32_t *)buf << shift) & mask;
1607                         WREG32_NO_KIQ(mmMM_DATA, value);
1608                 }
1609                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1610                 if (!write) {
1611                         value = (value & mask) >> shift;
1612                         memcpy(buf, &value, bytes);
1613                 }
1614
1615                 ret += bytes;
1616                 buf = (uint8_t *)buf + bytes;
1617                 pos += bytes;
1618                 len -= bytes;
1619                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1620                         ++nodes;
1621                         pos = (nodes->start << PAGE_SHIFT);
1622                 }
1623         }
1624
1625         return ret;
1626 }
1627
1628 static struct ttm_bo_driver amdgpu_bo_driver = {
1629         .ttm_tt_create = &amdgpu_ttm_tt_create,
1630         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1631         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1632         .invalidate_caches = &amdgpu_invalidate_caches,
1633         .init_mem_type = &amdgpu_init_mem_type,
1634         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1635         .evict_flags = &amdgpu_evict_flags,
1636         .move = &amdgpu_bo_move,
1637         .verify_access = &amdgpu_verify_access,
1638         .move_notify = &amdgpu_bo_move_notify,
1639         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1640         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1641         .io_mem_free = &amdgpu_ttm_io_mem_free,
1642         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1643         .access_memory = &amdgpu_ttm_access_memory
1644 };
1645
1646 /*
1647  * Firmware Reservation functions
1648  */
1649 /**
1650  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1651  *
1652  * @adev: amdgpu_device pointer
1653  *
1654  * free fw reserved vram if it has been reserved.
1655  */
1656 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1657 {
1658         amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
1659                 NULL, &adev->fw_vram_usage.va);
1660 }
1661
1662 /**
1663  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1664  *
1665  * @adev: amdgpu_device pointer
1666  *
1667  * create bo vram reservation from fw.
1668  */
1669 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1670 {
1671         struct ttm_operation_ctx ctx = { false, false };
1672         struct amdgpu_bo_param bp;
1673         int r = 0;
1674         int i;
1675         u64 vram_size = adev->gmc.visible_vram_size;
1676         u64 offset = adev->fw_vram_usage.start_offset;
1677         u64 size = adev->fw_vram_usage.size;
1678         struct amdgpu_bo *bo;
1679
1680         memset(&bp, 0, sizeof(bp));
1681         bp.size = adev->fw_vram_usage.size;
1682         bp.byte_align = PAGE_SIZE;
1683         bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
1684         bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1685                 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1686         bp.type = ttm_bo_type_kernel;
1687         bp.resv = NULL;
1688         adev->fw_vram_usage.va = NULL;
1689         adev->fw_vram_usage.reserved_bo = NULL;
1690
1691         if (adev->fw_vram_usage.size > 0 &&
1692                 adev->fw_vram_usage.size <= vram_size) {
1693
1694                 r = amdgpu_bo_create(adev, &bp,
1695                                      &adev->fw_vram_usage.reserved_bo);
1696                 if (r)
1697                         goto error_create;
1698
1699                 r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false);
1700                 if (r)
1701                         goto error_reserve;
1702
1703                 /* remove the original mem node and create a new one at the
1704                  * request position
1705                  */
1706                 bo = adev->fw_vram_usage.reserved_bo;
1707                 offset = ALIGN(offset, PAGE_SIZE);
1708                 for (i = 0; i < bo->placement.num_placement; ++i) {
1709                         bo->placements[i].fpfn = offset >> PAGE_SHIFT;
1710                         bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
1711                 }
1712
1713                 ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
1714                 r = ttm_bo_mem_space(&bo->tbo, &bo->placement,
1715                                      &bo->tbo.mem, &ctx);
1716                 if (r)
1717                         goto error_pin;
1718
1719                 r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo,
1720                         AMDGPU_GEM_DOMAIN_VRAM,
1721                         adev->fw_vram_usage.start_offset,
1722                         (adev->fw_vram_usage.start_offset +
1723                         adev->fw_vram_usage.size));
1724                 if (r)
1725                         goto error_pin;
1726                 r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo,
1727                         &adev->fw_vram_usage.va);
1728                 if (r)
1729                         goto error_kmap;
1730
1731                 amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
1732         }
1733         return r;
1734
1735 error_kmap:
1736         amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
1737 error_pin:
1738         amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
1739 error_reserve:
1740         amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo);
1741 error_create:
1742         adev->fw_vram_usage.va = NULL;
1743         adev->fw_vram_usage.reserved_bo = NULL;
1744         return r;
1745 }
1746 /**
1747  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1748  * gtt/vram related fields.
1749  *
1750  * This initializes all of the memory space pools that the TTM layer
1751  * will need such as the GTT space (system memory mapped to the device),
1752  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1753  * can be mapped per VMID.
1754  */
1755 int amdgpu_ttm_init(struct amdgpu_device *adev)
1756 {
1757         uint64_t gtt_size;
1758         int r;
1759         u64 vis_vram_limit;
1760
1761         /* initialize global references for vram/gtt */
1762         r = amdgpu_ttm_global_init(adev);
1763         if (r) {
1764                 return r;
1765         }
1766         /* No others user of address space so set it to 0 */
1767         r = ttm_bo_device_init(&adev->mman.bdev,
1768                                adev->mman.bo_global_ref.ref.object,
1769                                &amdgpu_bo_driver,
1770                                adev->ddev->anon_inode->i_mapping,
1771                                DRM_FILE_PAGE_OFFSET,
1772                                adev->need_dma32);
1773         if (r) {
1774                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1775                 return r;
1776         }
1777         adev->mman.initialized = true;
1778
1779         /* We opt to avoid OOM on system pages allocations */
1780         adev->mman.bdev.no_retry = true;
1781
1782         /* Initialize VRAM pool with all of VRAM divided into pages */
1783         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1784                                 adev->gmc.real_vram_size >> PAGE_SHIFT);
1785         if (r) {
1786                 DRM_ERROR("Failed initializing VRAM heap.\n");
1787                 return r;
1788         }
1789
1790         /* Reduce size of CPU-visible VRAM if requested */
1791         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1792         if (amdgpu_vis_vram_limit > 0 &&
1793             vis_vram_limit <= adev->gmc.visible_vram_size)
1794                 adev->gmc.visible_vram_size = vis_vram_limit;
1795
1796         /* Change the size here instead of the init above so only lpfn is affected */
1797         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1798 #ifdef CONFIG_64BIT
1799         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1800                                                 adev->gmc.visible_vram_size);
1801 #endif
1802
1803         /*
1804          *The reserved vram for firmware must be pinned to the specified
1805          *place on the VRAM, so reserve it early.
1806          */
1807         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1808         if (r) {
1809                 return r;
1810         }
1811
1812         /* allocate memory as required for VGA
1813          * This is used for VGA emulation and pre-OS scanout buffers to
1814          * avoid display artifacts while transitioning between pre-OS
1815          * and driver.  */
1816         r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1817                                     AMDGPU_GEM_DOMAIN_VRAM,
1818                                     &adev->stolen_vga_memory,
1819                                     NULL, NULL);
1820         if (r)
1821                 return r;
1822         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1823                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1824
1825         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1826          * or whatever the user passed on module init */
1827         if (amdgpu_gtt_size == -1) {
1828                 struct sysinfo si;
1829
1830                 si_meminfo(&si);
1831                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1832                                adev->gmc.mc_vram_size),
1833                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1834         }
1835         else
1836                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1837
1838         /* Initialize GTT memory pool */
1839         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1840         if (r) {
1841                 DRM_ERROR("Failed initializing GTT heap.\n");
1842                 return r;
1843         }
1844         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1845                  (unsigned)(gtt_size / (1024 * 1024)));
1846
1847         /* Initialize various on-chip memory pools */
1848         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1849                            adev->gds.mem.total_size);
1850         if (r) {
1851                 DRM_ERROR("Failed initializing GDS heap.\n");
1852                 return r;
1853         }
1854
1855         r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size,
1856                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS,
1857                                     &adev->gds.gds_gfx_bo, NULL, NULL);
1858         if (r)
1859                 return r;
1860
1861         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1862                            adev->gds.gws.total_size);
1863         if (r) {
1864                 DRM_ERROR("Failed initializing gws heap.\n");
1865                 return r;
1866         }
1867
1868         r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size,
1869                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS,
1870                                     &adev->gds.gws_gfx_bo, NULL, NULL);
1871         if (r)
1872                 return r;
1873
1874         r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1875                            adev->gds.oa.total_size);
1876         if (r) {
1877                 DRM_ERROR("Failed initializing oa heap.\n");
1878                 return r;
1879         }
1880
1881         r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size,
1882                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA,
1883                                     &adev->gds.oa_gfx_bo, NULL, NULL);
1884         if (r)
1885                 return r;
1886
1887         /* Register debugfs entries for amdgpu_ttm */
1888         r = amdgpu_ttm_debugfs_init(adev);
1889         if (r) {
1890                 DRM_ERROR("Failed to init debugfs\n");
1891                 return r;
1892         }
1893         return 0;
1894 }
1895
1896 /**
1897  * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
1898  */
1899 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
1900 {
1901         /* return the VGA stolen memory (if any) back to VRAM */
1902         amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
1903 }
1904
1905 /**
1906  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1907  */
1908 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1909 {
1910         if (!adev->mman.initialized)
1911                 return;
1912
1913         amdgpu_ttm_debugfs_fini(adev);
1914         amdgpu_ttm_fw_reserve_vram_fini(adev);
1915         if (adev->mman.aper_base_kaddr)
1916                 iounmap(adev->mman.aper_base_kaddr);
1917         adev->mman.aper_base_kaddr = NULL;
1918
1919         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1920         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1921         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1922         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1923         ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1924         ttm_bo_device_release(&adev->mman.bdev);
1925         amdgpu_ttm_global_fini(adev);
1926         adev->mman.initialized = false;
1927         DRM_INFO("amdgpu: ttm finalized\n");
1928 }
1929
1930 /**
1931  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1932  *
1933  * @adev: amdgpu_device pointer
1934  * @enable: true when we can use buffer functions.
1935  *
1936  * Enable/disable use of buffer functions during suspend/resume. This should
1937  * only be called at bootup or when userspace isn't running.
1938  */
1939 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1940 {
1941         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM];
1942         uint64_t size;
1943         int r;
1944
1945         if (!adev->mman.initialized || adev->in_gpu_reset ||
1946             adev->mman.buffer_funcs_enabled == enable)
1947                 return;
1948
1949         if (enable) {
1950                 struct amdgpu_ring *ring;
1951                 struct drm_sched_rq *rq;
1952
1953                 ring = adev->mman.buffer_funcs_ring;
1954                 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
1955                 r = drm_sched_entity_init(&adev->mman.entity, &rq, 1, NULL);
1956                 if (r) {
1957                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1958                                   r);
1959                         return;
1960                 }
1961         } else {
1962                 drm_sched_entity_destroy(&adev->mman.entity);
1963                 dma_fence_put(man->move);
1964                 man->move = NULL;
1965         }
1966
1967         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1968         if (enable)
1969                 size = adev->gmc.real_vram_size;
1970         else
1971                 size = adev->gmc.visible_vram_size;
1972         man->size = size >> PAGE_SHIFT;
1973         adev->mman.buffer_funcs_enabled = enable;
1974 }
1975
1976 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1977 {
1978         struct drm_file *file_priv;
1979         struct amdgpu_device *adev;
1980
1981         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1982                 return -EINVAL;
1983
1984         file_priv = filp->private_data;
1985         adev = file_priv->minor->dev->dev_private;
1986         if (adev == NULL)
1987                 return -EINVAL;
1988
1989         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1990 }
1991
1992 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
1993                              struct ttm_mem_reg *mem, unsigned num_pages,
1994                              uint64_t offset, unsigned window,
1995                              struct amdgpu_ring *ring,
1996                              uint64_t *addr)
1997 {
1998         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
1999         struct amdgpu_device *adev = ring->adev;
2000         struct ttm_tt *ttm = bo->ttm;
2001         struct amdgpu_job *job;
2002         unsigned num_dw, num_bytes;
2003         dma_addr_t *dma_address;
2004         struct dma_fence *fence;
2005         uint64_t src_addr, dst_addr;
2006         uint64_t flags;
2007         int r;
2008
2009         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
2010                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
2011
2012         *addr = adev->gmc.gart_start;
2013         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
2014                 AMDGPU_GPU_PAGE_SIZE;
2015
2016         num_dw = adev->mman.buffer_funcs->copy_num_dw;
2017         while (num_dw & 0x7)
2018                 num_dw++;
2019
2020         num_bytes = num_pages * 8;
2021
2022         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
2023         if (r)
2024                 return r;
2025
2026         src_addr = num_dw * 4;
2027         src_addr += job->ibs[0].gpu_addr;
2028
2029         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
2030         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
2031         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
2032                                 dst_addr, num_bytes);
2033
2034         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2035         WARN_ON(job->ibs[0].length_dw > num_dw);
2036
2037         dma_address = &gtt->ttm.dma_address[offset >> PAGE_SHIFT];
2038         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
2039         r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
2040                             &job->ibs[0].ptr[num_dw]);
2041         if (r)
2042                 goto error_free;
2043
2044         r = amdgpu_job_submit(job, &adev->mman.entity,
2045                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
2046         if (r)
2047                 goto error_free;
2048
2049         dma_fence_put(fence);
2050
2051         return r;
2052
2053 error_free:
2054         amdgpu_job_free(job);
2055         return r;
2056 }
2057
2058 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2059                        uint64_t dst_offset, uint32_t byte_count,
2060                        struct reservation_object *resv,
2061                        struct dma_fence **fence, bool direct_submit,
2062                        bool vm_needs_flush)
2063 {
2064         struct amdgpu_device *adev = ring->adev;
2065         struct amdgpu_job *job;
2066
2067         uint32_t max_bytes;
2068         unsigned num_loops, num_dw;
2069         unsigned i;
2070         int r;
2071
2072         if (direct_submit && !ring->ready) {
2073                 DRM_ERROR("Trying to move memory with ring turned off.\n");
2074                 return -EINVAL;
2075         }
2076
2077         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2078         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2079         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
2080
2081         /* for IB padding */
2082         while (num_dw & 0x7)
2083                 num_dw++;
2084
2085         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
2086         if (r)
2087                 return r;
2088
2089         if (vm_needs_flush) {
2090                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
2091                 job->vm_needs_flush = true;
2092         }
2093         if (resv) {
2094                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2095                                      AMDGPU_FENCE_OWNER_UNDEFINED,
2096                                      false);
2097                 if (r) {
2098                         DRM_ERROR("sync failed (%d).\n", r);
2099                         goto error_free;
2100                 }
2101         }
2102
2103         for (i = 0; i < num_loops; i++) {
2104                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2105
2106                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2107                                         dst_offset, cur_size_in_bytes);
2108
2109                 src_offset += cur_size_in_bytes;
2110                 dst_offset += cur_size_in_bytes;
2111                 byte_count -= cur_size_in_bytes;
2112         }
2113
2114         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2115         WARN_ON(job->ibs[0].length_dw > num_dw);
2116         if (direct_submit)
2117                 r = amdgpu_job_submit_direct(job, ring, fence);
2118         else
2119                 r = amdgpu_job_submit(job, &adev->mman.entity,
2120                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2121         if (r)
2122                 goto error_free;
2123
2124         return r;
2125
2126 error_free:
2127         amdgpu_job_free(job);
2128         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2129         return r;
2130 }
2131
2132 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2133                        uint32_t src_data,
2134                        struct reservation_object *resv,
2135                        struct dma_fence **fence)
2136 {
2137         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2138         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2139         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2140
2141         struct drm_mm_node *mm_node;
2142         unsigned long num_pages;
2143         unsigned int num_loops, num_dw;
2144
2145         struct amdgpu_job *job;
2146         int r;
2147
2148         if (!adev->mman.buffer_funcs_enabled) {
2149                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2150                 return -EINVAL;
2151         }
2152
2153         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2154                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2155                 if (r)
2156                         return r;
2157         }
2158
2159         num_pages = bo->tbo.num_pages;
2160         mm_node = bo->tbo.mem.mm_node;
2161         num_loops = 0;
2162         while (num_pages) {
2163                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
2164
2165                 num_loops += DIV_ROUND_UP(byte_count, max_bytes);
2166                 num_pages -= mm_node->size;
2167                 ++mm_node;
2168         }
2169         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2170
2171         /* for IB padding */
2172         num_dw += 64;
2173
2174         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
2175         if (r)
2176                 return r;
2177
2178         if (resv) {
2179                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2180                                      AMDGPU_FENCE_OWNER_UNDEFINED, false);
2181                 if (r) {
2182                         DRM_ERROR("sync failed (%d).\n", r);
2183                         goto error_free;
2184                 }
2185         }
2186
2187         num_pages = bo->tbo.num_pages;
2188         mm_node = bo->tbo.mem.mm_node;
2189
2190         while (num_pages) {
2191                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
2192                 uint64_t dst_addr;
2193
2194                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2195                 while (byte_count) {
2196                         uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2197
2198                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2199                                                 dst_addr, cur_size_in_bytes);
2200
2201                         dst_addr += cur_size_in_bytes;
2202                         byte_count -= cur_size_in_bytes;
2203                 }
2204
2205                 num_pages -= mm_node->size;
2206                 ++mm_node;
2207         }
2208
2209         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2210         WARN_ON(job->ibs[0].length_dw > num_dw);
2211         r = amdgpu_job_submit(job, &adev->mman.entity,
2212                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2213         if (r)
2214                 goto error_free;
2215
2216         return 0;
2217
2218 error_free:
2219         amdgpu_job_free(job);
2220         return r;
2221 }
2222
2223 #if defined(CONFIG_DEBUG_FS)
2224
2225 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2226 {
2227         struct drm_info_node *node = (struct drm_info_node *)m->private;
2228         unsigned ttm_pl = (uintptr_t)node->info_ent->data;
2229         struct drm_device *dev = node->minor->dev;
2230         struct amdgpu_device *adev = dev->dev_private;
2231         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
2232         struct drm_printer p = drm_seq_file_printer(m);
2233
2234         man->func->debug(man, &p);
2235         return 0;
2236 }
2237
2238 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2239         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_VRAM},
2240         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, (void *)TTM_PL_TT},
2241         {"amdgpu_gds_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GDS},
2242         {"amdgpu_gws_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_GWS},
2243         {"amdgpu_oa_mm", amdgpu_mm_dump_table, 0, (void *)AMDGPU_PL_OA},
2244         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2245 #ifdef CONFIG_SWIOTLB
2246         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2247 #endif
2248 };
2249
2250 /**
2251  * amdgpu_ttm_vram_read - Linear read access to VRAM
2252  *
2253  * Accesses VRAM via MMIO for debugging purposes.
2254  */
2255 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2256                                     size_t size, loff_t *pos)
2257 {
2258         struct amdgpu_device *adev = file_inode(f)->i_private;
2259         ssize_t result = 0;
2260         int r;
2261
2262         if (size & 0x3 || *pos & 0x3)
2263                 return -EINVAL;
2264
2265         if (*pos >= adev->gmc.mc_vram_size)
2266                 return -ENXIO;
2267
2268         while (size) {
2269                 unsigned long flags;
2270                 uint32_t value;
2271
2272                 if (*pos >= adev->gmc.mc_vram_size)
2273                         return result;
2274
2275                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2276                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2277                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2278                 value = RREG32_NO_KIQ(mmMM_DATA);
2279                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2280
2281                 r = put_user(value, (uint32_t *)buf);
2282                 if (r)
2283                         return r;
2284
2285                 result += 4;
2286                 buf += 4;
2287                 *pos += 4;
2288                 size -= 4;
2289         }
2290
2291         return result;
2292 }
2293
2294 /**
2295  * amdgpu_ttm_vram_write - Linear write access to VRAM
2296  *
2297  * Accesses VRAM via MMIO for debugging purposes.
2298  */
2299 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2300                                     size_t size, loff_t *pos)
2301 {
2302         struct amdgpu_device *adev = file_inode(f)->i_private;
2303         ssize_t result = 0;
2304         int r;
2305
2306         if (size & 0x3 || *pos & 0x3)
2307                 return -EINVAL;
2308
2309         if (*pos >= adev->gmc.mc_vram_size)
2310                 return -ENXIO;
2311
2312         while (size) {
2313                 unsigned long flags;
2314                 uint32_t value;
2315
2316                 if (*pos >= adev->gmc.mc_vram_size)
2317                         return result;
2318
2319                 r = get_user(value, (uint32_t *)buf);
2320                 if (r)
2321                         return r;
2322
2323                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2324                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2325                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2326                 WREG32_NO_KIQ(mmMM_DATA, value);
2327                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2328
2329                 result += 4;
2330                 buf += 4;
2331                 *pos += 4;
2332                 size -= 4;
2333         }
2334
2335         return result;
2336 }
2337
2338 static const struct file_operations amdgpu_ttm_vram_fops = {
2339         .owner = THIS_MODULE,
2340         .read = amdgpu_ttm_vram_read,
2341         .write = amdgpu_ttm_vram_write,
2342         .llseek = default_llseek,
2343 };
2344
2345 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2346
2347 /**
2348  * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2349  */
2350 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2351                                    size_t size, loff_t *pos)
2352 {
2353         struct amdgpu_device *adev = file_inode(f)->i_private;
2354         ssize_t result = 0;
2355         int r;
2356
2357         while (size) {
2358                 loff_t p = *pos / PAGE_SIZE;
2359                 unsigned off = *pos & ~PAGE_MASK;
2360                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2361                 struct page *page;
2362                 void *ptr;
2363
2364                 if (p >= adev->gart.num_cpu_pages)
2365                         return result;
2366
2367                 page = adev->gart.pages[p];
2368                 if (page) {
2369                         ptr = kmap(page);
2370                         ptr += off;
2371
2372                         r = copy_to_user(buf, ptr, cur_size);
2373                         kunmap(adev->gart.pages[p]);
2374                 } else
2375                         r = clear_user(buf, cur_size);
2376
2377                 if (r)
2378                         return -EFAULT;
2379
2380                 result += cur_size;
2381                 buf += cur_size;
2382                 *pos += cur_size;
2383                 size -= cur_size;
2384         }
2385
2386         return result;
2387 }
2388
2389 static const struct file_operations amdgpu_ttm_gtt_fops = {
2390         .owner = THIS_MODULE,
2391         .read = amdgpu_ttm_gtt_read,
2392         .llseek = default_llseek
2393 };
2394
2395 #endif
2396
2397 /**
2398  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2399  *
2400  * This function is used to read memory that has been mapped to the
2401  * GPU and the known addresses are not physical addresses but instead
2402  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2403  */
2404 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2405                                  size_t size, loff_t *pos)
2406 {
2407         struct amdgpu_device *adev = file_inode(f)->i_private;
2408         struct iommu_domain *dom;
2409         ssize_t result = 0;
2410         int r;
2411
2412         /* retrieve the IOMMU domain if any for this device */
2413         dom = iommu_get_domain_for_dev(adev->dev);
2414
2415         while (size) {
2416                 phys_addr_t addr = *pos & PAGE_MASK;
2417                 loff_t off = *pos & ~PAGE_MASK;
2418                 size_t bytes = PAGE_SIZE - off;
2419                 unsigned long pfn;
2420                 struct page *p;
2421                 void *ptr;
2422
2423                 bytes = bytes < size ? bytes : size;
2424
2425                 /* Translate the bus address to a physical address.  If
2426                  * the domain is NULL it means there is no IOMMU active
2427                  * and the address translation is the identity
2428                  */
2429                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2430
2431                 pfn = addr >> PAGE_SHIFT;
2432                 if (!pfn_valid(pfn))
2433                         return -EPERM;
2434
2435                 p = pfn_to_page(pfn);
2436                 if (p->mapping != adev->mman.bdev.dev_mapping)
2437                         return -EPERM;
2438
2439                 ptr = kmap(p);
2440                 r = copy_to_user(buf, ptr + off, bytes);
2441                 kunmap(p);
2442                 if (r)
2443                         return -EFAULT;
2444
2445                 size -= bytes;
2446                 *pos += bytes;
2447                 result += bytes;
2448         }
2449
2450         return result;
2451 }
2452
2453 /**
2454  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2455  *
2456  * This function is used to write memory that has been mapped to the
2457  * GPU and the known addresses are not physical addresses but instead
2458  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2459  */
2460 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2461                                  size_t size, loff_t *pos)
2462 {
2463         struct amdgpu_device *adev = file_inode(f)->i_private;
2464         struct iommu_domain *dom;
2465         ssize_t result = 0;
2466         int r;
2467
2468         dom = iommu_get_domain_for_dev(adev->dev);
2469
2470         while (size) {
2471                 phys_addr_t addr = *pos & PAGE_MASK;
2472                 loff_t off = *pos & ~PAGE_MASK;
2473                 size_t bytes = PAGE_SIZE - off;
2474                 unsigned long pfn;
2475                 struct page *p;
2476                 void *ptr;
2477
2478                 bytes = bytes < size ? bytes : size;
2479
2480                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2481
2482                 pfn = addr >> PAGE_SHIFT;
2483                 if (!pfn_valid(pfn))
2484                         return -EPERM;
2485
2486                 p = pfn_to_page(pfn);
2487                 if (p->mapping != adev->mman.bdev.dev_mapping)
2488                         return -EPERM;
2489
2490                 ptr = kmap(p);
2491                 r = copy_from_user(ptr + off, buf, bytes);
2492                 kunmap(p);
2493                 if (r)
2494                         return -EFAULT;
2495
2496                 size -= bytes;
2497                 *pos += bytes;
2498                 result += bytes;
2499         }
2500
2501         return result;
2502 }
2503
2504 static const struct file_operations amdgpu_ttm_iomem_fops = {
2505         .owner = THIS_MODULE,
2506         .read = amdgpu_iomem_read,
2507         .write = amdgpu_iomem_write,
2508         .llseek = default_llseek
2509 };
2510
2511 static const struct {
2512         char *name;
2513         const struct file_operations *fops;
2514         int domain;
2515 } ttm_debugfs_entries[] = {
2516         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2517 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2518         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2519 #endif
2520         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2521 };
2522
2523 #endif
2524
2525 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2526 {
2527 #if defined(CONFIG_DEBUG_FS)
2528         unsigned count;
2529
2530         struct drm_minor *minor = adev->ddev->primary;
2531         struct dentry *ent, *root = minor->debugfs_root;
2532
2533         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2534                 ent = debugfs_create_file(
2535                                 ttm_debugfs_entries[count].name,
2536                                 S_IFREG | S_IRUGO, root,
2537                                 adev,
2538                                 ttm_debugfs_entries[count].fops);
2539                 if (IS_ERR(ent))
2540                         return PTR_ERR(ent);
2541                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2542                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2543                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2544                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2545                 adev->mman.debugfs_entries[count] = ent;
2546         }
2547
2548         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2549
2550 #ifdef CONFIG_SWIOTLB
2551         if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2552                 --count;
2553 #endif
2554
2555         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2556 #else
2557         return 0;
2558 #endif
2559 }
2560
2561 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
2562 {
2563 #if defined(CONFIG_DEBUG_FS)
2564         unsigned i;
2565
2566         for (i = 0; i < ARRAY_SIZE(ttm_debugfs_entries); i++)
2567                 debugfs_remove(adev->mman.debugfs_entries[i]);
2568 #endif
2569 }