drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <[email protected]>
  21  *          Alex Deucher <[email protected]>
  22  */
  23 #include <drm/drmP.h>
  24 #include "amdgpu.h"
  25 #include "amdgpu_drv.h"
  26 #include "amdgpu_pm.h"
  27 #include "amdgpu_dpm.h"
  28 #include "atom.h"
  29 #include <linux/power_supply.h>
  30 #include <linux/hwmon.h>
  31 #include <linux/hwmon-sysfs.h>
  32
  33 #include "amd_powerplay.h"
  34
  35 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev);
  36
  37 static const struct cg_flag_name clocks[] = {
  38         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  39         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  40         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  41         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  42         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  43         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  44         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  45         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  46         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  47         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  48         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  49         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  50         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  51         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  52         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  53         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  54         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  55         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  56         {0, NULL},
  57 };
  58
  59 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev)
  60 {
  61         if (adev->pp_enabled)
  62                 /* TODO */
  63                 return;
  64
  65         if (adev->pm.dpm_enabled) {
  66                 mutex_lock(&adev->pm.mutex);
  67                 if (power_supply_is_system_supplied() > 0)
  68                         adev->pm.dpm.ac_power = true;
  69                 else
  70                         adev->pm.dpm.ac_power = false;
  71                 if (adev->pm.funcs->enable_bapm)
  72                         amdgpu_dpm_enable_bapm(adev, adev->pm.dpm.ac_power);
  73                 mutex_unlock(&adev->pm.mutex);
  74         }
  75 }
  76
  77 static ssize_t amdgpu_get_dpm_state(struct device *dev,
  78                                     struct device_attribute *attr,
  79                                     char *buf)
  80 {
  81         struct drm_device *ddev = dev_get_drvdata(dev);
  82         struct amdgpu_device *adev = ddev->dev_private;
  83         enum amd_pm_state_type pm;
  84
  85         if (adev->pp_enabled) {
  86                 pm = amdgpu_dpm_get_current_power_state(adev);
  87         } else
  88                 pm = adev->pm.dpm.user_state;
  89
  90         return snprintf(buf, PAGE_SIZE, "%s\n",
  91                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
  92                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
  93 }
  94
  95 static ssize_t amdgpu_set_dpm_state(struct device *dev,
  96                                     struct device_attribute *attr,
  97                                     const char *buf,
  98                                     size_t count)
  99 {
 100         struct drm_device *ddev = dev_get_drvdata(dev);
 101         struct amdgpu_device *adev = ddev->dev_private;
 102         enum amd_pm_state_type  state;
 103
 104         if (strncmp("battery", buf, strlen("battery")) == 0)
 105                 state = POWER_STATE_TYPE_BATTERY;
 106         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 107                 state = POWER_STATE_TYPE_BALANCED;
 108         else if (strncmp("performance", buf, strlen("performance")) == 0)
 109                 state = POWER_STATE_TYPE_PERFORMANCE;
 110         else {
 111                 count = -EINVAL;
 112                 goto fail;
 113         }
 114
 115         if (adev->pp_enabled) {
 116                 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
 117         } else {
 118                 mutex_lock(&adev->pm.mutex);
 119                 adev->pm.dpm.user_state = state;
 120                 mutex_unlock(&adev->pm.mutex);
 121
 122                 /* Can't set dpm state when the card is off */
 123                 if (!(adev->flags & AMD_IS_PX) ||
 124                     (ddev->switch_power_state == DRM_SWITCH_POWER_ON))
 125                         amdgpu_pm_compute_clocks(adev);
 126         }
 127 fail:
 128         return count;
 129 }
 130
 131 static ssize_t amdgpu_get_dpm_forced_performance_level(struct device *dev,
 132                                                 struct device_attribute *attr,
 133                                                                 char *buf)
 134 {
 135         struct drm_device *ddev = dev_get_drvdata(dev);
 136         struct amdgpu_device *adev = ddev->dev_private;
 137         enum amd_dpm_forced_level level;
 138
 139         if  ((adev->flags & AMD_IS_PX) &&
 140              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 141                 return snprintf(buf, PAGE_SIZE, "off\n");
 142
 143         level = amdgpu_dpm_get_performance_level(adev);
 144         return snprintf(buf, PAGE_SIZE, "%s\n",
 145                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 146                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 147                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 148                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 149                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 150                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 151                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 152                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 153                         "unknown");
 154 }
 155
 156 static ssize_t amdgpu_set_dpm_forced_performance_level(struct device *dev,
 157                                                        struct device_attribute *attr,
 158                                                        const char *buf,
 159                                                        size_t count)
 160 {
 161         struct drm_device *ddev = dev_get_drvdata(dev);
 162         struct amdgpu_device *adev = ddev->dev_private;
 163         enum amd_dpm_forced_level level;
 164         enum amd_dpm_forced_level current_level;
 165         int ret = 0;
 166
 167         /* Can't force performance level when the card is off */
 168         if  ((adev->flags & AMD_IS_PX) &&
 169              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 170                 return -EINVAL;
 171
 172         current_level = amdgpu_dpm_get_performance_level(adev);
 173
 174         if (strncmp("low", buf, strlen("low")) == 0) {
 175                 level = AMD_DPM_FORCED_LEVEL_LOW;
 176         } else if (strncmp("high", buf, strlen("high")) == 0) {
 177                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 178         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 179                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 180         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 181                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 182         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 183                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 184         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 185                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 186         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 187                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 188         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 189                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 190         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 191                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 192         }  else {
 193                 count = -EINVAL;
 194                 goto fail;
 195         }
 196
 197         if (current_level == level)
 198                 return count;
 199
 200         if (adev->pp_enabled)
 201                 amdgpu_dpm_force_performance_level(adev, level);
 202         else {
 203                 mutex_lock(&adev->pm.mutex);
 204                 if (adev->pm.dpm.thermal_active) {
 205                         count = -EINVAL;
 206                         mutex_unlock(&adev->pm.mutex);
 207                         goto fail;
 208                 }
 209                 ret = amdgpu_dpm_force_performance_level(adev, level);
 210                 if (ret)
 211                         count = -EINVAL;
 212                 else
 213                         adev->pm.dpm.forced_level = level;
 214                 mutex_unlock(&adev->pm.mutex);
 215         }
 216
 217 fail:
 218         return count;
 219 }
 220
 221 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 222                 struct device_attribute *attr,
 223                 char *buf)
 224 {
 225         struct drm_device *ddev = dev_get_drvdata(dev);
 226         struct amdgpu_device *adev = ddev->dev_private;
 227         struct pp_states_info data;
 228         int i, buf_len;
 229
 230         if (adev->pp_enabled)
 231                 amdgpu_dpm_get_pp_num_states(adev, &data);
 232
 233         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 234         for (i = 0; i < data.nums; i++)
 235                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 236                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 237                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 238                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 239                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 240
 241         return buf_len;
 242 }
 243
 244 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 245                 struct device_attribute *attr,
 246                 char *buf)
 247 {
 248         struct drm_device *ddev = dev_get_drvdata(dev);
 249         struct amdgpu_device *adev = ddev->dev_private;
 250         struct pp_states_info data;
 251         enum amd_pm_state_type pm = 0;
 252         int i = 0;
 253
 254         if (adev->pp_enabled) {
 255
 256                 pm = amdgpu_dpm_get_current_power_state(adev);
 257                 amdgpu_dpm_get_pp_num_states(adev, &data);
 258
 259                 for (i = 0; i < data.nums; i++) {
 260                         if (pm == data.states[i])
 261                                 break;
 262                 }
 263
 264                 if (i == data.nums)
 265                         i = -EINVAL;
 266         }
 267
 268         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 269 }
 270
 271 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 272                 struct device_attribute *attr,
 273                 char *buf)
 274 {
 275         struct drm_device *ddev = dev_get_drvdata(dev);
 276         struct amdgpu_device *adev = ddev->dev_private;
 277         struct pp_states_info data;
 278         enum amd_pm_state_type pm = 0;
 279         int i;
 280
 281         if (adev->pp_force_state_enabled && adev->pp_enabled) {
 282                 pm = amdgpu_dpm_get_current_power_state(adev);
 283                 amdgpu_dpm_get_pp_num_states(adev, &data);
 284
 285                 for (i = 0; i < data.nums; i++) {
 286                         if (pm == data.states[i])
 287                                 break;
 288                 }
 289
 290                 if (i == data.nums)
 291                         i = -EINVAL;
 292
 293                 return snprintf(buf, PAGE_SIZE, "%d\n", i);
 294
 295         } else
 296                 return snprintf(buf, PAGE_SIZE, "\n");
 297 }
 298
 299 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 300                 struct device_attribute *attr,
 301                 const char *buf,
 302                 size_t count)
 303 {
 304         struct drm_device *ddev = dev_get_drvdata(dev);
 305         struct amdgpu_device *adev = ddev->dev_private;
 306         enum amd_pm_state_type state = 0;
 307         unsigned long idx;
 308         int ret;
 309
 310         if (strlen(buf) == 1)
 311                 adev->pp_force_state_enabled = false;
 312         else if (adev->pp_enabled) {
 313                 struct pp_states_info data;
 314
 315                 ret = kstrtoul(buf, 0, &idx);
 316                 if (ret || idx >= ARRAY_SIZE(data.states)) {
 317                         count = -EINVAL;
 318                         goto fail;
 319                 }
 320
 321                 amdgpu_dpm_get_pp_num_states(adev, &data);
 322                 state = data.states[idx];
 323                 /* only set user selected power states */
 324                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 325                     state != POWER_STATE_TYPE_DEFAULT) {
 326                         amdgpu_dpm_dispatch_task(adev,
 327                                         AMD_PP_EVENT_ENABLE_USER_STATE, &state, NULL);
 328                         adev->pp_force_state_enabled = true;
 329                 }
 330         }
 331 fail:
 332         return count;
 333 }
 334
 335 static ssize_t amdgpu_get_pp_table(struct device *dev,
 336                 struct device_attribute *attr,
 337                 char *buf)
 338 {
 339         struct drm_device *ddev = dev_get_drvdata(dev);
 340         struct amdgpu_device *adev = ddev->dev_private;
 341         char *table = NULL;
 342         int size;
 343
 344         if (adev->pp_enabled)
 345                 size = amdgpu_dpm_get_pp_table(adev, &table);
 346         else
 347                 return 0;
 348
 349         if (size >= PAGE_SIZE)
 350                 size = PAGE_SIZE - 1;
 351
 352         memcpy(buf, table, size);
 353
 354         return size;
 355 }
 356
 357 static ssize_t amdgpu_set_pp_table(struct device *dev,
 358                 struct device_attribute *attr,
 359                 const char *buf,
 360                 size_t count)
 361 {
 362         struct drm_device *ddev = dev_get_drvdata(dev);
 363         struct amdgpu_device *adev = ddev->dev_private;
 364
 365         if (adev->pp_enabled)
 366                 amdgpu_dpm_set_pp_table(adev, buf, count);
 367
 368         return count;
 369 }
 370
 371 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
 372                 struct device_attribute *attr,
 373                 char *buf)
 374 {
 375         struct drm_device *ddev = dev_get_drvdata(dev);
 376         struct amdgpu_device *adev = ddev->dev_private;
 377         ssize_t size = 0;
 378
 379         if (adev->pp_enabled)
 380                 size = amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
 381         else if (adev->pm.funcs->print_clock_levels)
 382                 size = adev->pm.funcs->print_clock_levels(adev, PP_SCLK, buf);
 383
 384         return size;
 385 }
 386
 387 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
 388                 struct device_attribute *attr,
 389                 const char *buf,
 390                 size_t count)
 391 {
 392         struct drm_device *ddev = dev_get_drvdata(dev);
 393         struct amdgpu_device *adev = ddev->dev_private;
 394         int ret;
 395         long level;
 396         uint32_t i, mask = 0;
 397         char sub_str[2];
 398
 399         for (i = 0; i < strlen(buf); i++) {
 400                 if (*(buf + i) == '\n')
 401                         continue;
 402                 sub_str[0] = *(buf + i);
 403                 sub_str[1] = '\0';
 404                 ret = kstrtol(sub_str, 0, &level);
 405
 406                 if (ret) {
 407                         count = -EINVAL;
 408                         goto fail;
 409                 }
 410                 mask |= 1 << level;
 411         }
 412
 413         if (adev->pp_enabled)
 414                 amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
 415         else if (adev->pm.funcs->force_clock_level)
 416                 adev->pm.funcs->force_clock_level(adev, PP_SCLK, mask);
 417 fail:
 418         return count;
 419 }
 420
 421 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
 422                 struct device_attribute *attr,
 423                 char *buf)
 424 {
 425         struct drm_device *ddev = dev_get_drvdata(dev);
 426         struct amdgpu_device *adev = ddev->dev_private;
 427         ssize_t size = 0;
 428
 429         if (adev->pp_enabled)
 430                 size = amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
 431         else if (adev->pm.funcs->print_clock_levels)
 432                 size = adev->pm.funcs->print_clock_levels(adev, PP_MCLK, buf);
 433
 434         return size;
 435 }
 436
 437 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
 438                 struct device_attribute *attr,
 439                 const char *buf,
 440                 size_t count)
 441 {
 442         struct drm_device *ddev = dev_get_drvdata(dev);
 443         struct amdgpu_device *adev = ddev->dev_private;
 444         int ret;
 445         long level;
 446         uint32_t i, mask = 0;
 447         char sub_str[2];
 448
 449         for (i = 0; i < strlen(buf); i++) {
 450                 if (*(buf + i) == '\n')
 451                         continue;
 452                 sub_str[0] = *(buf + i);
 453                 sub_str[1] = '\0';
 454                 ret = kstrtol(sub_str, 0, &level);
 455
 456                 if (ret) {
 457                         count = -EINVAL;
 458                         goto fail;
 459                 }
 460                 mask |= 1 << level;
 461         }
 462
 463         if (adev->pp_enabled)
 464                 amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
 465         else if (adev->pm.funcs->force_clock_level)
 466                 adev->pm.funcs->force_clock_level(adev, PP_MCLK, mask);
 467 fail:
 468         return count;
 469 }
 470
 471 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
 472                 struct device_attribute *attr,
 473                 char *buf)
 474 {
 475         struct drm_device *ddev = dev_get_drvdata(dev);
 476         struct amdgpu_device *adev = ddev->dev_private;
 477         ssize_t size = 0;
 478
 479         if (adev->pp_enabled)
 480                 size = amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
 481         else if (adev->pm.funcs->print_clock_levels)
 482                 size = adev->pm.funcs->print_clock_levels(adev, PP_PCIE, buf);
 483
 484         return size;
 485 }
 486
 487 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
 488                 struct device_attribute *attr,
 489                 const char *buf,
 490                 size_t count)
 491 {
 492         struct drm_device *ddev = dev_get_drvdata(dev);
 493         struct amdgpu_device *adev = ddev->dev_private;
 494         int ret;
 495         long level;
 496         uint32_t i, mask = 0;
 497         char sub_str[2];
 498
 499         for (i = 0; i < strlen(buf); i++) {
 500                 if (*(buf + i) == '\n')
 501                         continue;
 502                 sub_str[0] = *(buf + i);
 503                 sub_str[1] = '\0';
 504                 ret = kstrtol(sub_str, 0, &level);
 505
 506                 if (ret) {
 507                         count = -EINVAL;
 508                         goto fail;
 509                 }
 510                 mask |= 1 << level;
 511         }
 512
 513         if (adev->pp_enabled)
 514                 amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
 515         else if (adev->pm.funcs->force_clock_level)
 516                 adev->pm.funcs->force_clock_level(adev, PP_PCIE, mask);
 517 fail:
 518         return count;
 519 }
 520
 521 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
 522                 struct device_attribute *attr,
 523                 char *buf)
 524 {
 525         struct drm_device *ddev = dev_get_drvdata(dev);
 526         struct amdgpu_device *adev = ddev->dev_private;
 527         uint32_t value = 0;
 528
 529         if (adev->pp_enabled)
 530                 value = amdgpu_dpm_get_sclk_od(adev);
 531         else if (adev->pm.funcs->get_sclk_od)
 532                 value = adev->pm.funcs->get_sclk_od(adev);
 533
 534         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 535 }
 536
 537 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
 538                 struct device_attribute *attr,
 539                 const char *buf,
 540                 size_t count)
 541 {
 542         struct drm_device *ddev = dev_get_drvdata(dev);
 543         struct amdgpu_device *adev = ddev->dev_private;
 544         int ret;
 545         long int value;
 546
 547         ret = kstrtol(buf, 0, &value);
 548
 549         if (ret) {
 550                 count = -EINVAL;
 551                 goto fail;
 552         }
 553
 554         if (adev->pp_enabled) {
 555                 amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
 556                 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_READJUST_POWER_STATE, NULL, NULL);
 557         } else if (adev->pm.funcs->set_sclk_od) {
 558                 adev->pm.funcs->set_sclk_od(adev, (uint32_t)value);
 559                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 560                 amdgpu_pm_compute_clocks(adev);
 561         }
 562
 563 fail:
 564         return count;
 565 }
 566
 567 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
 568                 struct device_attribute *attr,
 569                 char *buf)
 570 {
 571         struct drm_device *ddev = dev_get_drvdata(dev);
 572         struct amdgpu_device *adev = ddev->dev_private;
 573         uint32_t value = 0;
 574
 575         if (adev->pp_enabled)
 576                 value = amdgpu_dpm_get_mclk_od(adev);
 577         else if (adev->pm.funcs->get_mclk_od)
 578                 value = adev->pm.funcs->get_mclk_od(adev);
 579
 580         return snprintf(buf, PAGE_SIZE, "%d\n", value);
 581 }
 582
 583 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
 584                 struct device_attribute *attr,
 585                 const char *buf,
 586                 size_t count)
 587 {
 588         struct drm_device *ddev = dev_get_drvdata(dev);
 589         struct amdgpu_device *adev = ddev->dev_private;
 590         int ret;
 591         long int value;
 592
 593         ret = kstrtol(buf, 0, &value);
 594
 595         if (ret) {
 596                 count = -EINVAL;
 597                 goto fail;
 598         }
 599
 600         if (adev->pp_enabled) {
 601                 amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
 602                 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_READJUST_POWER_STATE, NULL, NULL);
 603         } else if (adev->pm.funcs->set_mclk_od) {
 604                 adev->pm.funcs->set_mclk_od(adev, (uint32_t)value);
 605                 adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
 606                 amdgpu_pm_compute_clocks(adev);
 607         }
 608
 609 fail:
 610         return count;
 611 }
 612
 613 static ssize_t amdgpu_get_pp_power_profile(struct device *dev,
 614                 char *buf, struct amd_pp_profile *query)
 615 {
 616         struct drm_device *ddev = dev_get_drvdata(dev);
 617         struct amdgpu_device *adev = ddev->dev_private;
 618         int ret = 0;
 619
 620         if (adev->pp_enabled)
 621                 ret = amdgpu_dpm_get_power_profile_state(
 622                                 adev, query);
 623         else if (adev->pm.funcs->get_power_profile_state)
 624                 ret = adev->pm.funcs->get_power_profile_state(
 625                                 adev, query);
 626
 627         if (ret)
 628                 return ret;
 629
 630         return snprintf(buf, PAGE_SIZE,
 631                         "%d %d %d %d %d\n",
 632                         query->min_sclk / 100,
 633                         query->min_mclk / 100,
 634                         query->activity_threshold,
 635                         query->up_hyst,
 636                         query->down_hyst);
 637 }
 638
 639 static ssize_t amdgpu_get_pp_gfx_power_profile(struct device *dev,
 640                 struct device_attribute *attr,
 641                 char *buf)
 642 {
 643         struct amd_pp_profile query = {0};
 644
 645         query.type = AMD_PP_GFX_PROFILE;
 646
 647         return amdgpu_get_pp_power_profile(dev, buf, &query);
 648 }
 649
 650 static ssize_t amdgpu_get_pp_compute_power_profile(struct device *dev,
 651                 struct device_attribute *attr,
 652                 char *buf)
 653 {
 654         struct amd_pp_profile query = {0};
 655
 656         query.type = AMD_PP_COMPUTE_PROFILE;
 657
 658         return amdgpu_get_pp_power_profile(dev, buf, &query);
 659 }
 660
 661 static ssize_t amdgpu_set_pp_power_profile(struct device *dev,
 662                 const char *buf,
 663                 size_t count,
 664                 struct amd_pp_profile *request)
 665 {
 666         struct drm_device *ddev = dev_get_drvdata(dev);
 667         struct amdgpu_device *adev = ddev->dev_private;
 668         uint32_t loop = 0;
 669         char *sub_str, buf_cpy[128], *tmp_str;
 670         const char delimiter[3] = {' ', '\n', '\0'};
 671         long int value;
 672         int ret = 0;
 673
 674         if (strncmp("reset", buf, strlen("reset")) == 0) {
 675                 if (adev->pp_enabled)
 676                         ret = amdgpu_dpm_reset_power_profile_state(
 677                                         adev, request);
 678                 else if (adev->pm.funcs->reset_power_profile_state)
 679                         ret = adev->pm.funcs->reset_power_profile_state(
 680                                         adev, request);
 681                 if (ret) {
 682                         count = -EINVAL;
 683                         goto fail;
 684                 }
 685                 return count;
 686         }
 687
 688         if (strncmp("set", buf, strlen("set")) == 0) {
 689                 if (adev->pp_enabled)
 690                         ret = amdgpu_dpm_set_power_profile_state(
 691                                         adev, request);
 692                 else if (adev->pm.funcs->set_power_profile_state)
 693                         ret = adev->pm.funcs->set_power_profile_state(
 694                                         adev, request);
 695                 if (ret) {
 696                         count = -EINVAL;
 697                         goto fail;
 698                 }
 699                 return count;
 700         }
 701
 702         if (count + 1 >= 128) {
 703                 count = -EINVAL;
 704                 goto fail;
 705         }
 706
 707         memcpy(buf_cpy, buf, count + 1);
 708         tmp_str = buf_cpy;
 709
 710         while (tmp_str[0]) {
 711                 sub_str = strsep(&tmp_str, delimiter);
 712                 ret = kstrtol(sub_str, 0, &value);
 713                 if (ret) {
 714                         count = -EINVAL;
 715                         goto fail;
 716                 }
 717
 718                 switch (loop) {
 719                 case 0:
 720                         /* input unit MHz convert to dpm table unit 10KHz*/
 721                         request->min_sclk = (uint32_t)value * 100;
 722                         break;
 723                 case 1:
 724                         /* input unit MHz convert to dpm table unit 10KHz*/
 725                         request->min_mclk = (uint32_t)value * 100;
 726                         break;
 727                 case 2:
 728                         request->activity_threshold = (uint16_t)value;
 729                         break;
 730                 case 3:
 731                         request->up_hyst = (uint8_t)value;
 732                         break;
 733                 case 4:
 734                         request->down_hyst = (uint8_t)value;
 735                         break;
 736                 default:
 737                         break;
 738                 }
 739
 740                 loop++;
 741         }
 742
 743         if (adev->pp_enabled)
 744                 ret = amdgpu_dpm_set_power_profile_state(
 745                                 adev, request);
 746         else if (adev->pm.funcs->set_power_profile_state)
 747                 ret = adev->pm.funcs->set_power_profile_state(
 748                                 adev, request);
 749
 750         if (ret)
 751                 count = -EINVAL;
 752
 753 fail:
 754         return count;
 755 }
 756
 757 static ssize_t amdgpu_set_pp_gfx_power_profile(struct device *dev,
 758                 struct device_attribute *attr,
 759                 const char *buf,
 760                 size_t count)
 761 {
 762         struct amd_pp_profile request = {0};
 763
 764         request.type = AMD_PP_GFX_PROFILE;
 765
 766         return amdgpu_set_pp_power_profile(dev, buf, count, &request);
 767 }
 768
 769 static ssize_t amdgpu_set_pp_compute_power_profile(struct device *dev,
 770                 struct device_attribute *attr,
 771                 const char *buf,
 772                 size_t count)
 773 {
 774         struct amd_pp_profile request = {0};
 775
 776         request.type = AMD_PP_COMPUTE_PROFILE;
 777
 778         return amdgpu_set_pp_power_profile(dev, buf, count, &request);
 779 }
 780
 781 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);
 782 static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,
 783                    amdgpu_get_dpm_forced_performance_level,
 784                    amdgpu_set_dpm_forced_performance_level);
 785 static DEVICE_ATTR(pp_num_states, S_IRUGO, amdgpu_get_pp_num_states, NULL);
 786 static DEVICE_ATTR(pp_cur_state, S_IRUGO, amdgpu_get_pp_cur_state, NULL);
 787 static DEVICE_ATTR(pp_force_state, S_IRUGO | S_IWUSR,
 788                 amdgpu_get_pp_force_state,
 789                 amdgpu_set_pp_force_state);
 790 static DEVICE_ATTR(pp_table, S_IRUGO | S_IWUSR,
 791                 amdgpu_get_pp_table,
 792                 amdgpu_set_pp_table);
 793 static DEVICE_ATTR(pp_dpm_sclk, S_IRUGO | S_IWUSR,
 794                 amdgpu_get_pp_dpm_sclk,
 795                 amdgpu_set_pp_dpm_sclk);
 796 static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,
 797                 amdgpu_get_pp_dpm_mclk,
 798                 amdgpu_set_pp_dpm_mclk);
 799 static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,
 800                 amdgpu_get_pp_dpm_pcie,
 801                 amdgpu_set_pp_dpm_pcie);
 802 static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,
 803                 amdgpu_get_pp_sclk_od,
 804                 amdgpu_set_pp_sclk_od);
 805 static DEVICE_ATTR(pp_mclk_od, S_IRUGO | S_IWUSR,
 806                 amdgpu_get_pp_mclk_od,
 807                 amdgpu_set_pp_mclk_od);
 808 static DEVICE_ATTR(pp_gfx_power_profile, S_IRUGO | S_IWUSR,
 809                 amdgpu_get_pp_gfx_power_profile,
 810                 amdgpu_set_pp_gfx_power_profile);
 811 static DEVICE_ATTR(pp_compute_power_profile, S_IRUGO | S_IWUSR,
 812                 amdgpu_get_pp_compute_power_profile,
 813                 amdgpu_set_pp_compute_power_profile);
 814
 815 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
 816                                       struct device_attribute *attr,
 817                                       char *buf)
 818 {
 819         struct amdgpu_device *adev = dev_get_drvdata(dev);
 820         struct drm_device *ddev = adev->ddev;
 821         int temp;
 822
 823         /* Can't get temperature when the card is off */
 824         if  ((adev->flags & AMD_IS_PX) &&
 825              (ddev->switch_power_state != DRM_SWITCH_POWER_ON))
 826                 return -EINVAL;
 827
 828         if (!adev->pp_enabled && !adev->pm.funcs->get_temperature)
 829                 temp = 0;
 830         else
 831                 temp = amdgpu_dpm_get_temperature(adev);
 832
 833         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 834 }
 835
 836 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
 837                                              struct device_attribute *attr,
 838                                              char *buf)
 839 {
 840         struct amdgpu_device *adev = dev_get_drvdata(dev);
 841         int hyst = to_sensor_dev_attr(attr)->index;
 842         int temp;
 843
 844         if (hyst)
 845                 temp = adev->pm.dpm.thermal.min_temp;
 846         else
 847                 temp = adev->pm.dpm.thermal.max_temp;
 848
 849         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 850 }
 851
 852 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
 853                                             struct device_attribute *attr,
 854                                             char *buf)
 855 {
 856         struct amdgpu_device *adev = dev_get_drvdata(dev);
 857         u32 pwm_mode = 0;
 858
 859         if (!adev->pp_enabled && !adev->pm.funcs->get_fan_control_mode)
 860                 return -EINVAL;
 861
 862         pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
 863
 864         /* never 0 (full-speed), fuse or smc-controlled always */
 865         return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2);
 866 }
 867
 868 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
 869                                             struct device_attribute *attr,
 870                                             const char *buf,
 871                                             size_t count)
 872 {
 873         struct amdgpu_device *adev = dev_get_drvdata(dev);
 874         int err;
 875         int value;
 876
 877         if (!adev->pp_enabled && !adev->pm.funcs->set_fan_control_mode)
 878                 return -EINVAL;
 879
 880         err = kstrtoint(buf, 10, &value);
 881         if (err)
 882                 return err;
 883
 884         switch (value) {
 885         case 1: /* manual, percent-based */
 886                 amdgpu_dpm_set_fan_control_mode(adev, FDO_PWM_MODE_STATIC);
 887                 break;
 888         default: /* disable */
 889                 amdgpu_dpm_set_fan_control_mode(adev, 0);
 890                 break;
 891         }
 892
 893         return count;
 894 }
 895
 896 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
 897                                          struct device_attribute *attr,
 898                                          char *buf)
 899 {
 900         return sprintf(buf, "%i\n", 0);
 901 }
 902
 903 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
 904                                          struct device_attribute *attr,
 905                                          char *buf)
 906 {
 907         return sprintf(buf, "%i\n", 255);
 908 }
 909
 910 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
 911                                      struct device_attribute *attr,
 912                                      const char *buf, size_t count)
 913 {
 914         struct amdgpu_device *adev = dev_get_drvdata(dev);
 915         int err;
 916         u32 value;
 917
 918         err = kstrtou32(buf, 10, &value);
 919         if (err)
 920                 return err;
 921
 922         value = (value * 100) / 255;
 923
 924         err = amdgpu_dpm_set_fan_speed_percent(adev, value);
 925         if (err)
 926                 return err;
 927
 928         return count;
 929 }
 930
 931 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
 932                                      struct device_attribute *attr,
 933                                      char *buf)
 934 {
 935         struct amdgpu_device *adev = dev_get_drvdata(dev);
 936         int err;
 937         u32 speed;
 938
 939         err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
 940         if (err)
 941                 return err;
 942
 943         speed = (speed * 255) / 100;
 944
 945         return sprintf(buf, "%i\n", speed);
 946 }
 947
 948 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
 949                                            struct device_attribute *attr,
 950                                            char *buf)
 951 {
 952         struct amdgpu_device *adev = dev_get_drvdata(dev);
 953         int err;
 954         u32 speed;
 955
 956         err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
 957         if (err)
 958                 return err;
 959
 960         return sprintf(buf, "%i\n", speed);
 961 }
 962
 963 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, 0);
 964 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
 965 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
 966 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
 967 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
 968 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
 969 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
 970 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
 971
 972 static struct attribute *hwmon_attributes[] = {
 973         &sensor_dev_attr_temp1_input.dev_attr.attr,
 974         &sensor_dev_attr_temp1_crit.dev_attr.attr,
 975         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
 976         &sensor_dev_attr_pwm1.dev_attr.attr,
 977         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
 978         &sensor_dev_attr_pwm1_min.dev_attr.attr,
 979         &sensor_dev_attr_pwm1_max.dev_attr.attr,
 980         &sensor_dev_attr_fan1_input.dev_attr.attr,
 981         NULL
 982 };
 983
 984 static umode_t hwmon_attributes_visible(struct kobject *kobj,
 985                                         struct attribute *attr, int index)
 986 {
 987         struct device *dev = kobj_to_dev(kobj);
 988         struct amdgpu_device *adev = dev_get_drvdata(dev);
 989         umode_t effective_mode = attr->mode;
 990
 991         /* Skip limit attributes if DPM is not enabled */
 992         if (!adev->pm.dpm_enabled &&
 993             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
 994              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
 995              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
 996              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
 997              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
 998              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
 999                 return 0;
1000
1001         if (adev->pp_enabled)
1002                 return effective_mode;
1003
1004         /* Skip fan attributes if fan is not present */
1005         if (adev->pm.no_fan &&
1006             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
1007              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
1008              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1009              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1010                 return 0;
1011
1012         /* mask fan attributes if we have no bindings for this asic to expose */
1013         if ((!adev->pm.funcs->get_fan_speed_percent &&
1014              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
1015             (!adev->pm.funcs->get_fan_control_mode &&
1016              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
1017                 effective_mode &= ~S_IRUGO;
1018
1019         if ((!adev->pm.funcs->set_fan_speed_percent &&
1020              attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
1021             (!adev->pm.funcs->set_fan_control_mode &&
1022              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
1023                 effective_mode &= ~S_IWUSR;
1024
1025         /* hide max/min values if we can't both query and manage the fan */
1026         if ((!adev->pm.funcs->set_fan_speed_percent &&
1027              !adev->pm.funcs->get_fan_speed_percent) &&
1028             (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
1029              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
1030                 return 0;
1031
1032         /* requires powerplay */
1033         if (attr == &sensor_dev_attr_fan1_input.dev_attr.attr)
1034                 return 0;
1035
1036         return effective_mode;
1037 }
1038
1039 static const struct attribute_group hwmon_attrgroup = {
1040         .attrs = hwmon_attributes,
1041         .is_visible = hwmon_attributes_visible,
1042 };
1043
1044 static const struct attribute_group *hwmon_groups[] = {
1045         &hwmon_attrgroup,
1046         NULL
1047 };
1048
1049 void amdgpu_dpm_thermal_work_handler(struct work_struct *work)
1050 {
1051         struct amdgpu_device *adev =
1052                 container_of(work, struct amdgpu_device,
1053                              pm.dpm.thermal.work);
1054         /* switch to the thermal state */
1055         enum amd_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
1056
1057         if (!adev->pm.dpm_enabled)
1058                 return;
1059
1060         if (adev->pm.funcs->get_temperature) {
1061                 int temp = amdgpu_dpm_get_temperature(adev);
1062
1063                 if (temp < adev->pm.dpm.thermal.min_temp)
1064                         /* switch back the user state */
1065                         dpm_state = adev->pm.dpm.user_state;
1066         } else {
1067                 if (adev->pm.dpm.thermal.high_to_low)
1068                         /* switch back the user state */
1069                         dpm_state = adev->pm.dpm.user_state;
1070         }
1071         mutex_lock(&adev->pm.mutex);
1072         if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL)
1073                 adev->pm.dpm.thermal_active = true;
1074         else
1075                 adev->pm.dpm.thermal_active = false;
1076         adev->pm.dpm.state = dpm_state;
1077         mutex_unlock(&adev->pm.mutex);
1078
1079         amdgpu_pm_compute_clocks(adev);
1080 }
1081
1082 static struct amdgpu_ps *amdgpu_dpm_pick_power_state(struct amdgpu_device *adev,
1083                                                      enum amd_pm_state_type dpm_state)
1084 {
1085         int i;
1086         struct amdgpu_ps *ps;
1087         u32 ui_class;
1088         bool single_display = (adev->pm.dpm.new_active_crtc_count < 2) ?
1089                 true : false;
1090
1091         /* check if the vblank period is too short to adjust the mclk */
1092         if (single_display && adev->pm.funcs->vblank_too_short) {
1093                 if (amdgpu_dpm_vblank_too_short(adev))
1094                         single_display = false;
1095         }
1096
1097         /* certain older asics have a separare 3D performance state,
1098          * so try that first if the user selected performance
1099          */
1100         if (dpm_state == POWER_STATE_TYPE_PERFORMANCE)
1101                 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF;
1102         /* balanced states don't exist at the moment */
1103         if (dpm_state == POWER_STATE_TYPE_BALANCED)
1104                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1105
1106 restart_search:
1107         /* Pick the best power state based on current conditions */
1108         for (i = 0; i < adev->pm.dpm.num_ps; i++) {
1109                 ps = &adev->pm.dpm.ps[i];
1110                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
1111                 switch (dpm_state) {
1112                 /* user states */
1113                 case POWER_STATE_TYPE_BATTERY:
1114                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
1115                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1116                                         if (single_display)
1117                                                 return ps;
1118                                 } else
1119                                         return ps;
1120                         }
1121                         break;
1122                 case POWER_STATE_TYPE_BALANCED:
1123                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
1124                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1125                                         if (single_display)
1126                                                 return ps;
1127                                 } else
1128                                         return ps;
1129                         }
1130                         break;
1131                 case POWER_STATE_TYPE_PERFORMANCE:
1132                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
1133                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
1134                                         if (single_display)
1135                                                 return ps;
1136                                 } else
1137                                         return ps;
1138                         }
1139                         break;
1140                 /* internal states */
1141                 case POWER_STATE_TYPE_INTERNAL_UVD:
1142                         if (adev->pm.dpm.uvd_ps)
1143                                 return adev->pm.dpm.uvd_ps;
1144                         else
1145                                 break;
1146                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1147                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
1148                                 return ps;
1149                         break;
1150                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1151                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
1152                                 return ps;
1153                         break;
1154                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1155                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
1156                                 return ps;
1157                         break;
1158                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1159                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
1160                                 return ps;
1161                         break;
1162                 case POWER_STATE_TYPE_INTERNAL_BOOT:
1163                         return adev->pm.dpm.boot_ps;
1164                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
1165                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1166                                 return ps;
1167                         break;
1168                 case POWER_STATE_TYPE_INTERNAL_ACPI:
1169                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
1170                                 return ps;
1171                         break;
1172                 case POWER_STATE_TYPE_INTERNAL_ULV:
1173                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
1174                                 return ps;
1175                         break;
1176                 case POWER_STATE_TYPE_INTERNAL_3DPERF:
1177                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
1178                                 return ps;
1179                         break;
1180                 default:
1181                         break;
1182                 }
1183         }
1184         /* use a fallback state if we didn't match */
1185         switch (dpm_state) {
1186         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
1187                 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD;
1188                 goto restart_search;
1189         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
1190         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
1191         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
1192                 if (adev->pm.dpm.uvd_ps) {
1193                         return adev->pm.dpm.uvd_ps;
1194                 } else {
1195                         dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1196                         goto restart_search;
1197                 }
1198         case POWER_STATE_TYPE_INTERNAL_THERMAL:
1199                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
1200                 goto restart_search;
1201         case POWER_STATE_TYPE_INTERNAL_ACPI:
1202                 dpm_state = POWER_STATE_TYPE_BATTERY;
1203                 goto restart_search;
1204         case POWER_STATE_TYPE_BATTERY:
1205         case POWER_STATE_TYPE_BALANCED:
1206         case POWER_STATE_TYPE_INTERNAL_3DPERF:
1207                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
1208                 goto restart_search;
1209         default:
1210                 break;
1211         }
1212
1213         return NULL;
1214 }
1215
1216 static void amdgpu_dpm_change_power_state_locked(struct amdgpu_device *adev)
1217 {
1218         struct amdgpu_ps *ps;
1219         enum amd_pm_state_type dpm_state;
1220         int ret;
1221         bool equal;
1222
1223         /* if dpm init failed */
1224         if (!adev->pm.dpm_enabled)
1225                 return;
1226
1227         if (adev->pm.dpm.user_state != adev->pm.dpm.state) {
1228                 /* add other state override checks here */
1229                 if ((!adev->pm.dpm.thermal_active) &&
1230                     (!adev->pm.dpm.uvd_active))
1231                         adev->pm.dpm.state = adev->pm.dpm.user_state;
1232         }
1233         dpm_state = adev->pm.dpm.state;
1234
1235         ps = amdgpu_dpm_pick_power_state(adev, dpm_state);
1236         if (ps)
1237                 adev->pm.dpm.requested_ps = ps;
1238         else
1239                 return;
1240
1241         if (amdgpu_dpm == 1) {
1242                 printk("switching from power state:\n");
1243                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.current_ps);
1244                 printk("switching to power state:\n");
1245                 amdgpu_dpm_print_power_state(adev, adev->pm.dpm.requested_ps);
1246         }
1247
1248         /* update whether vce is active */
1249         ps->vce_active = adev->pm.dpm.vce_active;
1250
1251         amdgpu_dpm_display_configuration_changed(adev);
1252
1253         ret = amdgpu_dpm_pre_set_power_state(adev);
1254         if (ret)
1255                 return;
1256
1257         if ((0 != amgdpu_dpm_check_state_equal(adev, adev->pm.dpm.current_ps, adev->pm.dpm.requested_ps, &equal)))
1258                 equal = false;
1259
1260         if (equal)
1261                 return;
1262
1263         amdgpu_dpm_set_power_state(adev);
1264         amdgpu_dpm_post_set_power_state(adev);
1265
1266         adev->pm.dpm.current_active_crtcs = adev->pm.dpm.new_active_crtcs;
1267         adev->pm.dpm.current_active_crtc_count = adev->pm.dpm.new_active_crtc_count;
1268
1269         if (adev->pm.funcs->force_performance_level) {
1270                 if (adev->pm.dpm.thermal_active) {
1271                         enum amd_dpm_forced_level level = adev->pm.dpm.forced_level;
1272                         /* force low perf level for thermal */
1273                         amdgpu_dpm_force_performance_level(adev, AMD_DPM_FORCED_LEVEL_LOW);
1274                         /* save the user's level */
1275                         adev->pm.dpm.forced_level = level;
1276                 } else {
1277                         /* otherwise, user selected level */
1278                         amdgpu_dpm_force_performance_level(adev, adev->pm.dpm.forced_level);
1279                 }
1280         }
1281 }
1282
1283 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
1284 {
1285         if (adev->pp_enabled || adev->pm.funcs->powergate_uvd) {
1286                 /* enable/disable UVD */
1287                 mutex_lock(&adev->pm.mutex);
1288                 amdgpu_dpm_powergate_uvd(adev, !enable);
1289                 mutex_unlock(&adev->pm.mutex);
1290         } else {
1291                 if (enable) {
1292                         mutex_lock(&adev->pm.mutex);
1293                         adev->pm.dpm.uvd_active = true;
1294                         adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
1295                         mutex_unlock(&adev->pm.mutex);
1296                 } else {
1297                         mutex_lock(&adev->pm.mutex);
1298                         adev->pm.dpm.uvd_active = false;
1299                         mutex_unlock(&adev->pm.mutex);
1300                 }
1301                 amdgpu_pm_compute_clocks(adev);
1302         }
1303 }
1304
1305 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
1306 {
1307         if (adev->pp_enabled || adev->pm.funcs->powergate_vce) {
1308                 /* enable/disable VCE */
1309                 mutex_lock(&adev->pm.mutex);
1310                 amdgpu_dpm_powergate_vce(adev, !enable);
1311                 mutex_unlock(&adev->pm.mutex);
1312         } else {
1313                 if (enable) {
1314                         mutex_lock(&adev->pm.mutex);
1315                         adev->pm.dpm.vce_active = true;
1316                         /* XXX select vce level based on ring/task */
1317                         adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
1318                         mutex_unlock(&adev->pm.mutex);
1319                         amdgpu_pm_compute_clocks(adev);
1320                         amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1321                                                         AMD_PG_STATE_UNGATE);
1322                         amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1323                                                         AMD_CG_STATE_UNGATE);
1324                 } else {
1325                         amdgpu_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1326                                                         AMD_PG_STATE_GATE);
1327                         amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1328                                                         AMD_CG_STATE_GATE);
1329                         mutex_lock(&adev->pm.mutex);
1330                         adev->pm.dpm.vce_active = false;
1331                         mutex_unlock(&adev->pm.mutex);
1332                         amdgpu_pm_compute_clocks(adev);
1333                 }
1334
1335         }
1336 }
1337
1338 void amdgpu_pm_print_power_states(struct amdgpu_device *adev)
1339 {
1340         int i;
1341
1342         if (adev->pp_enabled)
1343                 /* TO DO */
1344                 return;
1345
1346         for (i = 0; i < adev->pm.dpm.num_ps; i++)
1347                 amdgpu_dpm_print_power_state(adev, &adev->pm.dpm.ps[i]);
1348
1349 }
1350
1351 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
1352 {
1353         int ret;
1354
1355         if (adev->pm.sysfs_initialized)
1356                 return 0;
1357
1358         if (!adev->pp_enabled) {
1359                 if (adev->pm.funcs->get_temperature == NULL)
1360                         return 0;
1361         }
1362
1363         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
1364                                                                    DRIVER_NAME, adev,
1365                                                                    hwmon_groups);
1366         if (IS_ERR(adev->pm.int_hwmon_dev)) {
1367                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
1368                 dev_err(adev->dev,
1369                         "Unable to register hwmon device: %d\n", ret);
1370                 return ret;
1371         }
1372
1373         ret = device_create_file(adev->dev, &dev_attr_power_dpm_state);
1374         if (ret) {
1375                 DRM_ERROR("failed to create device file for dpm state\n");
1376                 return ret;
1377         }
1378         ret = device_create_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1379         if (ret) {
1380                 DRM_ERROR("failed to create device file for dpm state\n");
1381                 return ret;
1382         }
1383
1384         if (adev->pp_enabled) {
1385                 ret = device_create_file(adev->dev, &dev_attr_pp_num_states);
1386                 if (ret) {
1387                         DRM_ERROR("failed to create device file pp_num_states\n");
1388                         return ret;
1389                 }
1390                 ret = device_create_file(adev->dev, &dev_attr_pp_cur_state);
1391                 if (ret) {
1392                         DRM_ERROR("failed to create device file pp_cur_state\n");
1393                         return ret;
1394                 }
1395                 ret = device_create_file(adev->dev, &dev_attr_pp_force_state);
1396                 if (ret) {
1397                         DRM_ERROR("failed to create device file pp_force_state\n");
1398                         return ret;
1399                 }
1400                 ret = device_create_file(adev->dev, &dev_attr_pp_table);
1401                 if (ret) {
1402                         DRM_ERROR("failed to create device file pp_table\n");
1403                         return ret;
1404                 }
1405         }
1406
1407         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_sclk);
1408         if (ret) {
1409                 DRM_ERROR("failed to create device file pp_dpm_sclk\n");
1410                 return ret;
1411         }
1412         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_mclk);
1413         if (ret) {
1414                 DRM_ERROR("failed to create device file pp_dpm_mclk\n");
1415                 return ret;
1416         }
1417         ret = device_create_file(adev->dev, &dev_attr_pp_dpm_pcie);
1418         if (ret) {
1419                 DRM_ERROR("failed to create device file pp_dpm_pcie\n");
1420                 return ret;
1421         }
1422         ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);
1423         if (ret) {
1424                 DRM_ERROR("failed to create device file pp_sclk_od\n");
1425                 return ret;
1426         }
1427         ret = device_create_file(adev->dev, &dev_attr_pp_mclk_od);
1428         if (ret) {
1429                 DRM_ERROR("failed to create device file pp_mclk_od\n");
1430                 return ret;
1431         }
1432         ret = device_create_file(adev->dev,
1433                         &dev_attr_pp_gfx_power_profile);
1434         if (ret) {
1435                 DRM_ERROR("failed to create device file "
1436                                 "pp_gfx_power_profile\n");
1437                 return ret;
1438         }
1439         ret = device_create_file(adev->dev,
1440                         &dev_attr_pp_compute_power_profile);
1441         if (ret) {
1442                 DRM_ERROR("failed to create device file "
1443                                 "pp_compute_power_profile\n");
1444                 return ret;
1445         }
1446
1447         ret = amdgpu_debugfs_pm_init(adev);
1448         if (ret) {
1449                 DRM_ERROR("Failed to register debugfs file for dpm!\n");
1450                 return ret;
1451         }
1452
1453         adev->pm.sysfs_initialized = true;
1454
1455         return 0;
1456 }
1457
1458 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
1459 {
1460         if (adev->pm.int_hwmon_dev)
1461                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
1462         device_remove_file(adev->dev, &dev_attr_power_dpm_state);
1463         device_remove_file(adev->dev, &dev_attr_power_dpm_force_performance_level);
1464         if (adev->pp_enabled) {
1465                 device_remove_file(adev->dev, &dev_attr_pp_num_states);
1466                 device_remove_file(adev->dev, &dev_attr_pp_cur_state);
1467                 device_remove_file(adev->dev, &dev_attr_pp_force_state);
1468                 device_remove_file(adev->dev, &dev_attr_pp_table);
1469         }
1470         device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);
1471         device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);
1472         device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);
1473         device_remove_file(adev->dev, &dev_attr_pp_sclk_od);
1474         device_remove_file(adev->dev, &dev_attr_pp_mclk_od);
1475         device_remove_file(adev->dev,
1476                         &dev_attr_pp_gfx_power_profile);
1477         device_remove_file(adev->dev,
1478                         &dev_attr_pp_compute_power_profile);
1479 }
1480
1481 void amdgpu_pm_compute_clocks(struct amdgpu_device *adev)
1482 {
1483         struct drm_device *ddev = adev->ddev;
1484         struct drm_crtc *crtc;
1485         struct amdgpu_crtc *amdgpu_crtc;
1486         int i = 0;
1487
1488         if (!adev->pm.dpm_enabled)
1489                 return;
1490
1491         if (adev->mode_info.num_crtc)
1492                 amdgpu_display_bandwidth_update(adev);
1493
1494         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1495                 struct amdgpu_ring *ring = adev->rings[i];
1496                 if (ring && ring->ready)
1497                         amdgpu_fence_wait_empty(ring);
1498         }
1499
1500         if (adev->pp_enabled) {
1501                 amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE, NULL, NULL);
1502         } else {
1503                 mutex_lock(&adev->pm.mutex);
1504                 adev->pm.dpm.new_active_crtcs = 0;
1505                 adev->pm.dpm.new_active_crtc_count = 0;
1506                 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
1507                         list_for_each_entry(crtc,
1508                                             &ddev->mode_config.crtc_list, head) {
1509                                 amdgpu_crtc = to_amdgpu_crtc(crtc);
1510                                 if (crtc->enabled) {
1511                                         adev->pm.dpm.new_active_crtcs |= (1 << amdgpu_crtc->crtc_id);
1512                                         adev->pm.dpm.new_active_crtc_count++;
1513                                 }
1514                         }
1515                 }
1516                 /* update battery/ac status */
1517                 if (power_supply_is_system_supplied() > 0)
1518                         adev->pm.dpm.ac_power = true;
1519                 else
1520                         adev->pm.dpm.ac_power = false;
1521
1522                 amdgpu_dpm_change_power_state_locked(adev);
1523
1524                 mutex_unlock(&adev->pm.mutex);
1525         }
1526 }
1527
1528 /*
1529  * Debugfs info
1530  */
1531 #if defined(CONFIG_DEBUG_FS)
1532
1533 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
1534 {
1535         uint32_t value;
1536         struct pp_gpu_power query = {0};
1537         int size;
1538
1539         /* sanity check PP is enabled */
1540         if (!(adev->powerplay.pp_funcs &&
1541               adev->powerplay.pp_funcs->read_sensor))
1542               return -EINVAL;
1543
1544         /* GPU Clocks */
1545         size = sizeof(value);
1546         seq_printf(m, "GFX Clocks and Power:\n");
1547         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
1548                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
1549         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
1550                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
1551         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
1552                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
1553         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
1554                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
1555         size = sizeof(query);
1556         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size)) {
1557                 seq_printf(m, "\t%u.%u W (VDDC)\n", query.vddc_power >> 8,
1558                                 query.vddc_power & 0xff);
1559                 seq_printf(m, "\t%u.%u W (VDDCI)\n", query.vddci_power >> 8,
1560                                 query.vddci_power & 0xff);
1561                 seq_printf(m, "\t%u.%u W (max GPU)\n", query.max_gpu_power >> 8,
1562                                 query.max_gpu_power & 0xff);
1563                 seq_printf(m, "\t%u.%u W (average GPU)\n", query.average_gpu_power >> 8,
1564                                 query.average_gpu_power & 0xff);
1565         }
1566         size = sizeof(value);
1567         seq_printf(m, "\n");
1568
1569         /* GPU Temp */
1570         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
1571                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
1572
1573         /* GPU Load */
1574         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
1575                 seq_printf(m, "GPU Load: %u %%\n", value);
1576         seq_printf(m, "\n");
1577
1578         /* UVD clocks */
1579         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
1580                 if (!value) {
1581                         seq_printf(m, "UVD: Disabled\n");
1582                 } else {
1583                         seq_printf(m, "UVD: Enabled\n");
1584                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
1585                                 seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
1586                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
1587                                 seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
1588                 }
1589         }
1590         seq_printf(m, "\n");
1591
1592         /* VCE clocks */
1593         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
1594                 if (!value) {
1595                         seq_printf(m, "VCE: Disabled\n");
1596                 } else {
1597                         seq_printf(m, "VCE: Enabled\n");
1598                         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
1599                                 seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
1600                 }
1601         }
1602
1603         return 0;
1604 }
1605
1606 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
1607 {
1608         int i;
1609
1610         for (i = 0; clocks[i].flag; i++)
1611                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
1612                            (flags & clocks[i].flag) ? "On" : "Off");
1613 }
1614
1615 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
1616 {
1617         struct drm_info_node *node = (struct drm_info_node *) m->private;
1618         struct drm_device *dev = node->minor->dev;
1619         struct amdgpu_device *adev = dev->dev_private;
1620         struct drm_device *ddev = adev->ddev;
1621         u32 flags = 0;
1622
1623         amdgpu_get_clockgating_state(adev, &flags);
1624         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
1625         amdgpu_parse_cg_state(m, flags);
1626         seq_printf(m, "\n");
1627
1628         if (!adev->pm.dpm_enabled) {
1629                 seq_printf(m, "dpm not enabled\n");
1630                 return 0;
1631         }
1632         if  ((adev->flags & AMD_IS_PX) &&
1633              (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) {
1634                 seq_printf(m, "PX asic powered off\n");
1635         } else if (adev->pp_enabled) {
1636                 return amdgpu_debugfs_pm_info_pp(m, adev);
1637         } else {
1638                 mutex_lock(&adev->pm.mutex);
1639                 if (adev->pm.funcs->debugfs_print_current_performance_level)
1640                         adev->pm.funcs->debugfs_print_current_performance_level(adev, m);
1641                 else
1642                         seq_printf(m, "Debugfs support not implemented for this asic\n");
1643                 mutex_unlock(&adev->pm.mutex);
1644         }
1645
1646         return 0;
1647 }
1648
1649 static const struct drm_info_list amdgpu_pm_info_list[] = {
1650         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
1651 };
1652 #endif
1653
1654 static int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
1655 {
1656 #if defined(CONFIG_DEBUG_FS)
1657         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
1658 #else
1659         return 0;
1660 #endif
1661 }