2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/interval_tree.h>
36 #include <linux/hashtable.h>
37 #include <linux/dma-fence.h>
39 #include <ttm/ttm_bo_api.h>
40 #include <ttm/ttm_bo_driver.h>
41 #include <ttm/ttm_placement.h>
42 #include <ttm/ttm_module.h>
43 #include <ttm/ttm_execbuf_util.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
49 #include "amd_shared.h"
50 #include "amdgpu_mode.h"
51 #include "amdgpu_ih.h"
52 #include "amdgpu_irq.h"
53 #include "amdgpu_ucode.h"
54 #include "amdgpu_ttm.h"
55 #include "amdgpu_gds.h"
56 #include "amdgpu_sync.h"
57 #include "amdgpu_ring.h"
58 #include "amdgpu_vm.h"
59 #include "amd_powerplay.h"
60 #include "amdgpu_dpm.h"
61 #include "amdgpu_acp.h"
63 #include "gpu_scheduler.h"
64 #include "amdgpu_virt.h"
69 extern int amdgpu_modeset;
70 extern int amdgpu_vram_limit;
71 extern int amdgpu_gart_size;
72 extern int amdgpu_moverate;
73 extern int amdgpu_benchmarking;
74 extern int amdgpu_testing;
75 extern int amdgpu_audio;
76 extern int amdgpu_disp_priority;
77 extern int amdgpu_hw_i2c;
78 extern int amdgpu_pcie_gen2;
79 extern int amdgpu_msi;
80 extern int amdgpu_lockup_timeout;
81 extern int amdgpu_dpm;
82 extern int amdgpu_smc_load_fw;
83 extern int amdgpu_aspm;
84 extern int amdgpu_runtime_pm;
85 extern unsigned amdgpu_ip_block_mask;
86 extern int amdgpu_bapm;
87 extern int amdgpu_deep_color;
88 extern int amdgpu_vm_size;
89 extern int amdgpu_vm_block_size;
90 extern int amdgpu_vm_fault_stop;
91 extern int amdgpu_vm_debug;
92 extern int amdgpu_sched_jobs;
93 extern int amdgpu_sched_hw_submission;
94 extern int amdgpu_no_evict;
95 extern int amdgpu_direct_gma_size;
96 extern unsigned amdgpu_pcie_gen_cap;
97 extern unsigned amdgpu_pcie_lane_cap;
98 extern unsigned amdgpu_cg_mask;
99 extern unsigned amdgpu_pg_mask;
100 extern char *amdgpu_disable_cu;
101 extern char *amdgpu_virtual_display;
102 extern unsigned amdgpu_pp_feature_mask;
103 extern int amdgpu_vram_page_split;
105 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
106 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
107 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
108 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
109 #define AMDGPU_IB_POOL_SIZE 16
110 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
111 #define AMDGPUFB_CONN_LIMIT 4
112 #define AMDGPU_BIOS_NUM_SCRATCH 8
114 /* max number of IP instances */
115 #define AMDGPU_MAX_SDMA_INSTANCES 2
117 /* hardcode that limit for now */
118 #define AMDGPU_VA_RESERVED_SIZE (8 << 20)
120 /* hard reset data */
121 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
124 #define AMDGPU_RESET_GFX (1 << 0)
125 #define AMDGPU_RESET_COMPUTE (1 << 1)
126 #define AMDGPU_RESET_DMA (1 << 2)
127 #define AMDGPU_RESET_CP (1 << 3)
128 #define AMDGPU_RESET_GRBM (1 << 4)
129 #define AMDGPU_RESET_DMA1 (1 << 5)
130 #define AMDGPU_RESET_RLC (1 << 6)
131 #define AMDGPU_RESET_SEM (1 << 7)
132 #define AMDGPU_RESET_IH (1 << 8)
133 #define AMDGPU_RESET_VMC (1 << 9)
134 #define AMDGPU_RESET_MC (1 << 10)
135 #define AMDGPU_RESET_DISPLAY (1 << 11)
136 #define AMDGPU_RESET_UVD (1 << 12)
137 #define AMDGPU_RESET_VCE (1 << 13)
138 #define AMDGPU_RESET_VCE1 (1 << 14)
140 /* GFX current status */
141 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
142 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
143 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
144 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
145 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
147 /* max cursor sizes (in pixels) */
148 #define CIK_CURSOR_WIDTH 128
149 #define CIK_CURSOR_HEIGHT 128
151 struct amdgpu_device;
153 struct amdgpu_cs_parser;
155 struct amdgpu_irq_src;
159 AMDGPU_CP_IRQ_GFX_EOP = 0,
160 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
161 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
162 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
163 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
164 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
165 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
166 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
167 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
172 enum amdgpu_sdma_irq {
173 AMDGPU_SDMA_IRQ_TRAP0 = 0,
174 AMDGPU_SDMA_IRQ_TRAP1,
179 enum amdgpu_thermal_irq {
180 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
181 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
183 AMDGPU_THERMAL_IRQ_LAST
186 enum amdgpu_kiq_irq {
187 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
188 AMDGPU_CP_KIQ_IRQ_LAST
191 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
192 enum amd_ip_block_type block_type,
193 enum amd_clockgating_state state);
194 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
195 enum amd_ip_block_type block_type,
196 enum amd_powergating_state state);
197 void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);
198 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
199 enum amd_ip_block_type block_type);
200 bool amdgpu_is_idle(struct amdgpu_device *adev,
201 enum amd_ip_block_type block_type);
203 #define AMDGPU_MAX_IP_NUM 16
205 struct amdgpu_ip_block_status {
209 bool late_initialized;
213 struct amdgpu_ip_block_version {
214 const enum amd_ip_block_type type;
218 const struct amd_ip_funcs *funcs;
221 struct amdgpu_ip_block {
222 struct amdgpu_ip_block_status status;
223 const struct amdgpu_ip_block_version *version;
226 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
227 enum amd_ip_block_type type,
228 u32 major, u32 minor);
230 struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
231 enum amd_ip_block_type type);
233 int amdgpu_ip_block_add(struct amdgpu_device *adev,
234 const struct amdgpu_ip_block_version *ip_block_version);
236 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
237 struct amdgpu_buffer_funcs {
238 /* maximum bytes in a single operation */
239 uint32_t copy_max_bytes;
241 /* number of dw to reserve per operation */
242 unsigned copy_num_dw;
244 /* used for buffer migration */
245 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
246 /* src addr in bytes */
248 /* dst addr in bytes */
250 /* number of byte to transfer */
251 uint32_t byte_count);
253 /* maximum bytes in a single operation */
254 uint32_t fill_max_bytes;
256 /* number of dw to reserve per operation */
257 unsigned fill_num_dw;
259 /* used for buffer clearing */
260 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
261 /* value to write to memory */
263 /* dst addr in bytes */
265 /* number of byte to fill */
266 uint32_t byte_count);
269 /* provided by hw blocks that can write ptes, e.g., sdma */
270 struct amdgpu_vm_pte_funcs {
271 /* copy pte entries from GART */
272 void (*copy_pte)(struct amdgpu_ib *ib,
273 uint64_t pe, uint64_t src,
275 /* write pte one entry at a time with addr mapping */
276 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
277 uint64_t value, unsigned count,
279 /* for linear pte/pde updates without addr mapping */
280 void (*set_pte_pde)(struct amdgpu_ib *ib,
282 uint64_t addr, unsigned count,
283 uint32_t incr, uint32_t flags);
286 /* provided by the gmc block */
287 struct amdgpu_gart_funcs {
288 /* flush the vm tlb via mmio */
289 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
291 /* write pte/pde updates using the cpu */
292 int (*set_pte_pde)(struct amdgpu_device *adev,
293 void *cpu_pt_addr, /* cpu addr of page table */
294 uint32_t gpu_page_idx, /* pte/pde to update */
295 uint64_t addr, /* addr to write into pte/pde */
296 uint32_t flags); /* access flags */
297 /* enable/disable PRT support */
298 void (*set_prt)(struct amdgpu_device *adev, bool enable);
301 /* provided by the ih block */
302 struct amdgpu_ih_funcs {
303 /* ring read/write ptr handling, called from interrupt context */
304 u32 (*get_wptr)(struct amdgpu_device *adev);
305 void (*decode_iv)(struct amdgpu_device *adev,
306 struct amdgpu_iv_entry *entry);
307 void (*set_rptr)(struct amdgpu_device *adev);
313 bool amdgpu_get_bios(struct amdgpu_device *adev);
314 bool amdgpu_read_bios(struct amdgpu_device *adev);
319 struct amdgpu_dummy_page {
323 int amdgpu_dummy_page_init(struct amdgpu_device *adev);
324 void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
331 #define AMDGPU_MAX_PPLL 3
333 struct amdgpu_clock {
334 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
335 struct amdgpu_pll spll;
336 struct amdgpu_pll mpll;
338 uint32_t default_mclk;
339 uint32_t default_sclk;
340 uint32_t default_dispclk;
341 uint32_t current_dispclk;
343 uint32_t max_pixel_clock;
349 struct amdgpu_bo_list_entry {
350 struct amdgpu_bo *robj;
351 struct ttm_validate_buffer tv;
352 struct amdgpu_bo_va *bo_va;
354 struct page **user_pages;
355 int user_invalidated;
358 struct amdgpu_bo_va_mapping {
359 struct list_head list;
360 struct interval_tree_node it;
365 /* bo virtual addresses in a specific vm */
366 struct amdgpu_bo_va {
367 /* protected by bo being reserved */
368 struct list_head bo_list;
369 struct dma_fence *last_pt_update;
372 /* protected by vm mutex and spinlock */
373 struct list_head vm_status;
375 /* mappings for this bo_va */
376 struct list_head invalids;
377 struct list_head valids;
379 /* constant after initialization */
380 struct amdgpu_vm *vm;
381 struct amdgpu_bo *bo;
384 #define AMDGPU_GEM_DOMAIN_MAX 0x3
387 /* Protected by tbo.reserved */
388 u32 prefered_domains;
390 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
391 struct ttm_placement placement;
392 struct ttm_buffer_object tbo;
393 struct ttm_bo_kmap_obj kmap;
401 unsigned prime_shared_count;
402 /* list of all virtual address to which this bo
406 /* Constant after initialization */
407 struct drm_gem_object gem_base;
408 struct amdgpu_bo *parent;
409 struct amdgpu_bo *shadow;
411 struct ttm_bo_kmap_obj dma_buf_vmap;
412 struct amdgpu_mn *mn;
413 struct list_head mn_list;
414 struct list_head shadow_list;
416 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
418 void amdgpu_gem_object_free(struct drm_gem_object *obj);
419 int amdgpu_gem_object_open(struct drm_gem_object *obj,
420 struct drm_file *file_priv);
421 void amdgpu_gem_object_close(struct drm_gem_object *obj,
422 struct drm_file *file_priv);
423 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
424 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
425 struct drm_gem_object *
426 amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
427 struct dma_buf_attachment *attach,
428 struct sg_table *sg);
429 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
430 struct drm_gem_object *gobj,
432 int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
433 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
434 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
435 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
436 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
437 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
439 /* sub-allocation manager, it has to be protected by another lock.
440 * By conception this is an helper for other part of the driver
441 * like the indirect buffer or semaphore, which both have their
444 * Principe is simple, we keep a list of sub allocation in offset
445 * order (first entry has offset == 0, last entry has the highest
448 * When allocating new object we first check if there is room at
449 * the end total_size - (last_object_offset + last_object_size) >=
450 * alloc_size. If so we allocate new object there.
452 * When there is not enough room at the end, we start waiting for
453 * each sub object until we reach object_offset+object_size >=
454 * alloc_size, this object then become the sub object we return.
456 * Alignment can't be bigger than page size.
458 * Hole are not considered for allocation to keep things simple.
459 * Assumption is that there won't be hole (all object on same
463 #define AMDGPU_SA_NUM_FENCE_LISTS 32
465 struct amdgpu_sa_manager {
466 wait_queue_head_t wq;
467 struct amdgpu_bo *bo;
468 struct list_head *hole;
469 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
470 struct list_head olist;
478 /* sub-allocation buffer */
479 struct amdgpu_sa_bo {
480 struct list_head olist;
481 struct list_head flist;
482 struct amdgpu_sa_manager *manager;
485 struct dma_fence *fence;
491 void amdgpu_gem_force_release(struct amdgpu_device *adev);
492 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
493 int alignment, u32 initial_domain,
494 u64 flags, bool kernel,
495 struct drm_gem_object **obj);
497 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
498 struct drm_device *dev,
499 struct drm_mode_create_dumb *args);
500 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
501 struct drm_device *dev,
502 uint32_t handle, uint64_t *offset_p);
503 int amdgpu_fence_slab_init(void);
504 void amdgpu_fence_slab_fini(void);
507 * GART structures, functions & helpers
511 #define AMDGPU_GPU_PAGE_SIZE 4096
512 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
513 #define AMDGPU_GPU_PAGE_SHIFT 12
514 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
517 dma_addr_t table_addr;
518 struct amdgpu_bo *robj;
520 unsigned num_gpu_pages;
521 unsigned num_cpu_pages;
523 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
527 const struct amdgpu_gart_funcs *gart_funcs;
530 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev);
531 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev);
532 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
533 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
534 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
535 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
536 int amdgpu_gart_init(struct amdgpu_device *adev);
537 void amdgpu_gart_fini(struct amdgpu_device *adev);
538 void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
540 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
541 int pages, struct page **pagelist,
542 dma_addr_t *dma_addr, uint32_t flags);
543 int amdgpu_ttm_recover_gart(struct amdgpu_device *adev);
546 * GPU MC structures, functions & helpers
549 resource_size_t aper_size;
550 resource_size_t aper_base;
551 resource_size_t agp_base;
552 /* for some chips with <= 32MB we need to lie
553 * about vram size near mc fb location */
555 u64 visible_vram_size;
566 const struct firmware *fw; /* MC firmware */
568 struct amdgpu_irq_src vm_fault;
570 uint32_t srbm_soft_reset;
571 struct amdgpu_mode_mc_save save;
574 u64 shared_aperture_start;
575 u64 shared_aperture_end;
576 u64 private_aperture_start;
577 u64 private_aperture_end;
581 * GPU doorbell structures, functions & helpers
583 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
585 AMDGPU_DOORBELL_KIQ = 0x000,
586 AMDGPU_DOORBELL_HIQ = 0x001,
587 AMDGPU_DOORBELL_DIQ = 0x002,
588 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
589 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
590 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
591 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
592 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
593 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
594 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
595 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
596 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
597 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
598 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
599 AMDGPU_DOORBELL_IH = 0x1E8,
600 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
601 AMDGPU_DOORBELL_INVALID = 0xFFFF
602 } AMDGPU_DOORBELL_ASSIGNMENT;
604 struct amdgpu_doorbell {
606 resource_size_t base;
607 resource_size_t size;
609 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
612 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
613 phys_addr_t *aperture_base,
614 size_t *aperture_size,
615 size_t *start_offset);
621 struct amdgpu_flip_work {
622 struct delayed_work flip_work;
623 struct work_struct unpin_work;
624 struct amdgpu_device *adev;
628 struct drm_pending_vblank_event *event;
629 struct amdgpu_bo *old_abo;
630 struct dma_fence *excl;
631 unsigned shared_count;
632 struct dma_fence **shared;
633 struct dma_fence_cb cb;
643 struct amdgpu_sa_bo *sa_bo;
650 extern const struct amd_sched_backend_ops amdgpu_sched_ops;
652 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
653 struct amdgpu_job **job, struct amdgpu_vm *vm);
654 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
655 struct amdgpu_job **job);
657 void amdgpu_job_free_resources(struct amdgpu_job *job);
658 void amdgpu_job_free(struct amdgpu_job *job);
659 int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
660 struct amd_sched_entity *entity, void *owner,
661 struct dma_fence **f);
664 * context related structures
667 struct amdgpu_ctx_ring {
669 struct dma_fence **fences;
670 struct amd_sched_entity entity;
674 struct kref refcount;
675 struct amdgpu_device *adev;
676 unsigned reset_counter;
677 spinlock_t ring_lock;
678 struct dma_fence **fences;
679 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
680 bool preamble_presented;
683 struct amdgpu_ctx_mgr {
684 struct amdgpu_device *adev;
686 /* protected by lock */
687 struct idr ctx_handles;
690 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
691 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
693 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
694 struct dma_fence *fence);
695 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
696 struct amdgpu_ring *ring, uint64_t seq);
698 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
699 struct drm_file *filp);
701 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
702 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
705 * file private structure
708 struct amdgpu_fpriv {
710 struct amdgpu_bo_va *prt_va;
711 struct mutex bo_list_lock;
712 struct idr bo_list_handles;
713 struct amdgpu_ctx_mgr ctx_mgr;
720 struct amdgpu_bo_list {
722 struct amdgpu_bo *gds_obj;
723 struct amdgpu_bo *gws_obj;
724 struct amdgpu_bo *oa_obj;
725 unsigned first_userptr;
726 unsigned num_entries;
727 struct amdgpu_bo_list_entry *array;
730 struct amdgpu_bo_list *
731 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
732 void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
733 struct list_head *validated);
734 void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
735 void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
740 #include "clearstate_defs.h"
742 struct amdgpu_rlc_funcs {
743 void (*enter_safe_mode)(struct amdgpu_device *adev);
744 void (*exit_safe_mode)(struct amdgpu_device *adev);
748 /* for power gating */
749 struct amdgpu_bo *save_restore_obj;
750 uint64_t save_restore_gpu_addr;
751 volatile uint32_t *sr_ptr;
754 /* for clear state */
755 struct amdgpu_bo *clear_state_obj;
756 uint64_t clear_state_gpu_addr;
757 volatile uint32_t *cs_ptr;
758 const struct cs_section_def *cs_data;
759 u32 clear_state_size;
761 struct amdgpu_bo *cp_table_obj;
762 uint64_t cp_table_gpu_addr;
763 volatile uint32_t *cp_table_ptr;
766 /* safe mode for updating CG/PG state */
768 const struct amdgpu_rlc_funcs *funcs;
770 /* for firmware data */
771 u32 save_and_restore_offset;
772 u32 clear_state_descriptor_offset;
773 u32 avail_scratch_ram_locations;
774 u32 reg_restore_list_size;
775 u32 reg_list_format_start;
776 u32 reg_list_format_separate_start;
777 u32 starting_offsets_start;
778 u32 reg_list_format_size_bytes;
779 u32 reg_list_size_bytes;
781 u32 *register_list_format;
782 u32 *register_restore;
786 struct amdgpu_bo *hpd_eop_obj;
787 u64 hpd_eop_gpu_addr;
791 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
796 struct amdgpu_bo *eop_obj;
797 struct amdgpu_ring ring;
798 struct amdgpu_irq_src irq;
802 * GPU scratch registers structures, functions & helpers
804 struct amdgpu_scratch {
813 #define AMDGPU_GFX_MAX_SE 4
814 #define AMDGPU_GFX_MAX_SH_PER_SE 2
816 struct amdgpu_rb_config {
817 uint32_t rb_backend_disable;
818 uint32_t user_rb_backend_disable;
819 uint32_t raster_config;
820 uint32_t raster_config_1;
823 struct amdgpu_gfx_config {
824 unsigned max_shader_engines;
825 unsigned max_tile_pipes;
826 unsigned max_cu_per_sh;
827 unsigned max_sh_per_se;
828 unsigned max_backends_per_se;
829 unsigned max_texture_channel_caches;
831 unsigned max_gs_threads;
832 unsigned max_hw_contexts;
833 unsigned sc_prim_fifo_size_frontend;
834 unsigned sc_prim_fifo_size_backend;
835 unsigned sc_hiz_tile_fifo_size;
836 unsigned sc_earlyz_tile_fifo_size;
838 unsigned num_tile_pipes;
839 unsigned backend_enable_mask;
840 unsigned mem_max_burst_length_bytes;
841 unsigned mem_row_size_in_kb;
842 unsigned shader_engine_tile_size;
844 unsigned multi_gpu_tile_size;
845 unsigned mc_arb_ramcfg;
846 unsigned gb_addr_config;
849 uint32_t tile_mode_array[32];
850 uint32_t macrotile_mode_array[16];
852 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
854 /* gfx configure feature */
855 uint32_t double_offchip_lds_buf;
858 struct amdgpu_cu_info {
859 uint32_t number; /* total active CU number */
861 uint32_t bitmap[4][4];
864 struct amdgpu_gfx_funcs {
865 /* get the gpu clock counter */
866 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
867 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
868 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
869 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
870 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
874 struct mutex gpu_clock_mutex;
875 struct amdgpu_gfx_config config;
876 struct amdgpu_rlc rlc;
877 struct amdgpu_mec mec;
878 struct amdgpu_kiq kiq;
879 struct amdgpu_scratch scratch;
880 const struct firmware *me_fw; /* ME firmware */
881 uint32_t me_fw_version;
882 const struct firmware *pfp_fw; /* PFP firmware */
883 uint32_t pfp_fw_version;
884 const struct firmware *ce_fw; /* CE firmware */
885 uint32_t ce_fw_version;
886 const struct firmware *rlc_fw; /* RLC firmware */
887 uint32_t rlc_fw_version;
888 const struct firmware *mec_fw; /* MEC firmware */
889 uint32_t mec_fw_version;
890 const struct firmware *mec2_fw; /* MEC2 firmware */
891 uint32_t mec2_fw_version;
892 uint32_t me_feature_version;
893 uint32_t ce_feature_version;
894 uint32_t pfp_feature_version;
895 uint32_t rlc_feature_version;
896 uint32_t mec_feature_version;
897 uint32_t mec2_feature_version;
898 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
899 unsigned num_gfx_rings;
900 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
901 unsigned num_compute_rings;
902 struct amdgpu_irq_src eop_irq;
903 struct amdgpu_irq_src priv_reg_irq;
904 struct amdgpu_irq_src priv_inst_irq;
906 uint32_t gfx_current_status;
908 unsigned ce_ram_size;
909 struct amdgpu_cu_info cu_info;
910 const struct amdgpu_gfx_funcs *funcs;
913 uint32_t grbm_soft_reset;
914 uint32_t srbm_soft_reset;
918 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
919 unsigned size, struct amdgpu_ib *ib);
920 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
921 struct dma_fence *f);
922 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
923 struct amdgpu_ib *ibs, struct amdgpu_job *job,
924 struct dma_fence **f);
925 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
926 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
927 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
932 struct amdgpu_cs_chunk {
938 struct amdgpu_cs_parser {
939 struct amdgpu_device *adev;
940 struct drm_file *filp;
941 struct amdgpu_ctx *ctx;
945 struct amdgpu_cs_chunk *chunks;
947 /* scheduler job object */
948 struct amdgpu_job *job;
951 struct ww_acquire_ctx ticket;
952 struct amdgpu_bo_list *bo_list;
953 struct amdgpu_bo_list_entry vm_pd;
954 struct list_head validated;
955 struct dma_fence *fence;
956 uint64_t bytes_moved_threshold;
957 uint64_t bytes_moved;
958 struct amdgpu_bo_list_entry *evictable;
961 struct amdgpu_bo_list_entry uf_entry;
964 #define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */
965 #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */
966 #define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */
967 #define AMDGPU_VM_DOMAIN (1 << 3) /* bit set means in virtual memory context */
970 struct amd_sched_job base;
971 struct amdgpu_device *adev;
972 struct amdgpu_vm *vm;
973 struct amdgpu_ring *ring;
974 struct amdgpu_sync sync;
975 struct amdgpu_ib *ibs;
976 struct dma_fence *fence; /* the hw fence */
977 uint32_t preamble_status;
980 uint64_t fence_ctx; /* the fence_context this job uses */
984 uint32_t gds_base, gds_size;
985 uint32_t gws_base, gws_size;
986 uint32_t oa_base, oa_size;
988 /* user fence handling */
990 uint64_t uf_sequence;
993 #define to_amdgpu_job(sched_job) \
994 container_of((sched_job), struct amdgpu_job, base)
996 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
997 uint32_t ib_idx, int idx)
999 return p->job->ibs[ib_idx].ptr[idx];
1002 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1003 uint32_t ib_idx, int idx,
1006 p->job->ibs[ib_idx].ptr[idx] = value;
1012 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1015 struct amdgpu_bo *wb_obj;
1016 volatile uint32_t *wb;
1018 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1019 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1022 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1023 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1024 int amdgpu_wb_get_64bit(struct amdgpu_device *adev, u32 *wb);
1025 void amdgpu_wb_free_64bit(struct amdgpu_device *adev, u32 wb);
1027 void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1032 #define AMDGPU_DEFAULT_UVD_HANDLES 10
1033 #define AMDGPU_MAX_UVD_HANDLES 40
1034 #define AMDGPU_UVD_STACK_SIZE (200*1024)
1035 #define AMDGPU_UVD_HEAP_SIZE (256*1024)
1036 #define AMDGPU_UVD_SESSION_SIZE (50*1024)
1037 #define AMDGPU_UVD_FIRMWARE_OFFSET 256
1040 struct amdgpu_bo *vcpu_bo;
1043 unsigned fw_version;
1045 unsigned max_handles;
1046 atomic_t handles[AMDGPU_MAX_UVD_HANDLES];
1047 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES];
1048 struct delayed_work idle_work;
1049 const struct firmware *fw; /* UVD firmware */
1050 struct amdgpu_ring ring;
1051 struct amdgpu_irq_src irq;
1052 bool address_64_bit;
1054 struct amd_sched_entity entity;
1055 uint32_t srbm_soft_reset;
1061 #define AMDGPU_MAX_VCE_HANDLES 16
1062 #define AMDGPU_VCE_FIRMWARE_OFFSET 256
1064 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0)
1065 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1)
1068 struct amdgpu_bo *vcpu_bo;
1070 unsigned fw_version;
1071 unsigned fb_version;
1072 atomic_t handles[AMDGPU_MAX_VCE_HANDLES];
1073 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES];
1074 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES];
1075 struct delayed_work idle_work;
1076 struct mutex idle_mutex;
1077 const struct firmware *fw; /* VCE firmware */
1078 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS];
1079 struct amdgpu_irq_src irq;
1080 unsigned harvest_config;
1081 struct amd_sched_entity entity;
1082 uint32_t srbm_soft_reset;
1089 struct amdgpu_sdma_instance {
1091 const struct firmware *fw;
1092 uint32_t fw_version;
1093 uint32_t feature_version;
1095 struct amdgpu_ring ring;
1099 struct amdgpu_sdma {
1100 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1101 #ifdef CONFIG_DRM_AMDGPU_SI
1102 //SI DMA has a difference trap irq number for the second engine
1103 struct amdgpu_irq_src trap_irq_1;
1105 struct amdgpu_irq_src trap_irq;
1106 struct amdgpu_irq_src illegal_inst_irq;
1108 uint32_t srbm_soft_reset;
1114 struct amdgpu_firmware {
1115 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1117 struct amdgpu_bo *fw_buf;
1118 unsigned int fw_size;
1124 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1130 void amdgpu_test_moves(struct amdgpu_device *adev);
1135 #if defined(CONFIG_MMU_NOTIFIER)
1136 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1137 void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1139 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
1143 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
1149 struct amdgpu_debugfs {
1150 const struct drm_info_list *files;
1154 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1155 const struct drm_info_list *files,
1157 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1159 #if defined(CONFIG_DEBUG_FS)
1160 int amdgpu_debugfs_init(struct drm_minor *minor);
1163 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
1166 * amdgpu smumgr functions
1168 struct amdgpu_smumgr_funcs {
1169 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1170 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1171 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1177 struct amdgpu_smumgr {
1178 struct amdgpu_bo *toc_buf;
1179 struct amdgpu_bo *smu_buf;
1180 /* asic priv smu data */
1182 spinlock_t smu_lock;
1183 /* smumgr functions */
1184 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1185 /* ucode loading complete flag */
1190 * ASIC specific register table accessible by UMD
1192 struct amdgpu_allowed_register_entry {
1193 uint32_t reg_offset;
1199 * ASIC specific functions.
1201 struct amdgpu_asic_funcs {
1202 bool (*read_disabled_bios)(struct amdgpu_device *adev);
1203 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1204 u8 *bios, u32 length_bytes);
1205 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1206 u32 sh_num, u32 reg_offset, u32 *value);
1207 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1208 int (*reset)(struct amdgpu_device *adev);
1209 /* get the reference clock */
1210 u32 (*get_xclk)(struct amdgpu_device *adev);
1211 /* MM block clocks */
1212 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1213 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1214 /* static power management */
1215 int (*get_pcie_lanes)(struct amdgpu_device *adev);
1216 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
1222 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1223 struct drm_file *filp);
1224 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1225 struct drm_file *filp);
1227 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1228 struct drm_file *filp);
1229 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1230 struct drm_file *filp);
1231 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1232 struct drm_file *filp);
1233 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1234 struct drm_file *filp);
1235 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1236 struct drm_file *filp);
1237 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1238 struct drm_file *filp);
1239 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1240 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1241 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1242 struct drm_file *filp);
1244 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1245 struct drm_file *filp);
1247 /* VRAM scratch page for HDP bug, default vram page */
1248 struct amdgpu_vram_scratch {
1249 struct amdgpu_bo *robj;
1250 volatile uint32_t *ptr;
1257 struct amdgpu_atif_notification_cfg {
1262 struct amdgpu_atif_notifications {
1263 bool display_switch;
1264 bool expansion_mode_change;
1266 bool forced_power_state;
1267 bool system_power_state;
1268 bool display_conf_change;
1270 bool brightness_change;
1271 bool dgpu_display_event;
1274 struct amdgpu_atif_functions {
1276 bool sbios_requests;
1277 bool select_active_disp;
1279 bool get_tv_standard;
1280 bool set_tv_standard;
1281 bool get_panel_expansion_mode;
1282 bool set_panel_expansion_mode;
1283 bool temperature_change;
1284 bool graphics_device_types;
1287 struct amdgpu_atif {
1288 struct amdgpu_atif_notifications notifications;
1289 struct amdgpu_atif_functions functions;
1290 struct amdgpu_atif_notification_cfg notification_cfg;
1291 struct amdgpu_encoder *encoder_for_bl;
1294 struct amdgpu_atcs_functions {
1298 bool pcie_bus_width;
1301 struct amdgpu_atcs {
1302 struct amdgpu_atcs_functions functions;
1308 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1309 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
1312 * Core structure, functions and helpers.
1314 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1315 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1317 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1318 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1320 struct amdgpu_device {
1322 struct drm_device *ddev;
1323 struct pci_dev *pdev;
1325 #ifdef CONFIG_DRM_AMD_ACP
1326 struct amdgpu_acp acp;
1330 enum amd_asic_type asic_type;
1333 uint32_t external_rev_id;
1334 unsigned long flags;
1336 const struct amdgpu_asic_funcs *asic_funcs;
1340 struct work_struct reset_work;
1341 struct notifier_block acpi_nb;
1342 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1343 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1344 unsigned debugfs_count;
1345 #if defined(CONFIG_DEBUG_FS)
1346 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1348 struct amdgpu_atif atif;
1349 struct amdgpu_atcs atcs;
1350 struct mutex srbm_mutex;
1351 /* GRBM index mutex. Protects concurrent access to GRBM index */
1352 struct mutex grbm_idx_mutex;
1353 struct dev_pm_domain vga_pm_domain;
1354 bool have_disp_power_ref;
1359 struct amdgpu_bo *stollen_vga_memory;
1360 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1362 /* Register/doorbell mmio */
1363 resource_size_t rmmio_base;
1364 resource_size_t rmmio_size;
1365 void __iomem *rmmio;
1366 /* protects concurrent MM_INDEX/DATA based register access */
1367 spinlock_t mmio_idx_lock;
1368 /* protects concurrent SMC based register access */
1369 spinlock_t smc_idx_lock;
1370 amdgpu_rreg_t smc_rreg;
1371 amdgpu_wreg_t smc_wreg;
1372 /* protects concurrent PCIE register access */
1373 spinlock_t pcie_idx_lock;
1374 amdgpu_rreg_t pcie_rreg;
1375 amdgpu_wreg_t pcie_wreg;
1376 amdgpu_rreg_t pciep_rreg;
1377 amdgpu_wreg_t pciep_wreg;
1378 /* protects concurrent UVD register access */
1379 spinlock_t uvd_ctx_idx_lock;
1380 amdgpu_rreg_t uvd_ctx_rreg;
1381 amdgpu_wreg_t uvd_ctx_wreg;
1382 /* protects concurrent DIDT register access */
1383 spinlock_t didt_idx_lock;
1384 amdgpu_rreg_t didt_rreg;
1385 amdgpu_wreg_t didt_wreg;
1386 /* protects concurrent gc_cac register access */
1387 spinlock_t gc_cac_idx_lock;
1388 amdgpu_rreg_t gc_cac_rreg;
1389 amdgpu_wreg_t gc_cac_wreg;
1390 /* protects concurrent ENDPOINT (audio) register access */
1391 spinlock_t audio_endpt_idx_lock;
1392 amdgpu_block_rreg_t audio_endpt_rreg;
1393 amdgpu_block_wreg_t audio_endpt_wreg;
1394 void __iomem *rio_mem;
1395 resource_size_t rio_mem_size;
1396 struct amdgpu_doorbell doorbell;
1398 /* clock/pll info */
1399 struct amdgpu_clock clock;
1402 struct amdgpu_mc mc;
1403 struct amdgpu_gart gart;
1404 struct amdgpu_dummy_page dummy_page;
1405 struct amdgpu_vm_manager vm_manager;
1407 /* memory management */
1408 struct amdgpu_mman mman;
1409 struct amdgpu_vram_scratch vram_scratch;
1410 struct amdgpu_wb wb;
1411 atomic64_t vram_usage;
1412 atomic64_t vram_vis_usage;
1413 atomic64_t gtt_usage;
1414 atomic64_t num_bytes_moved;
1415 atomic64_t num_evictions;
1416 atomic_t gpu_reset_counter;
1418 /* data for buffer migration throttling */
1422 s64 accum_us; /* accumulated microseconds */
1427 bool enable_virtual_display;
1428 struct amdgpu_mode_info mode_info;
1429 struct work_struct hotplug_work;
1430 struct amdgpu_irq_src crtc_irq;
1431 struct amdgpu_irq_src pageflip_irq;
1432 struct amdgpu_irq_src hpd_irq;
1437 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
1439 struct amdgpu_sa_manager ring_tmp_bo;
1442 struct amdgpu_irq irq;
1445 struct amd_powerplay powerplay;
1447 bool pp_force_state_enabled;
1450 struct amdgpu_pm pm;
1455 struct amdgpu_smumgr smu;
1458 struct amdgpu_gfx gfx;
1461 struct amdgpu_sdma sdma;
1464 struct amdgpu_uvd uvd;
1467 struct amdgpu_vce vce;
1470 struct amdgpu_firmware firmware;
1473 struct amdgpu_gds gds;
1475 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
1477 struct mutex mn_lock;
1478 DECLARE_HASHTABLE(mn_hash, 7);
1480 /* tracking pinned memory */
1482 u64 invisible_pin_size;
1485 /* amdkfd interface */
1486 struct kfd_dev *kfd;
1488 struct amdgpu_virt virt;
1490 /* link all shadow bo */
1491 struct list_head shadow_list;
1492 struct mutex shadow_list_lock;
1494 spinlock_t gtt_list_lock;
1495 struct list_head gtt_list;
1497 /* record hw reset is performed */
1502 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1504 return container_of(bdev, struct amdgpu_device, mman.bdev);
1507 bool amdgpu_device_is_px(struct drm_device *dev);
1508 int amdgpu_device_init(struct amdgpu_device *adev,
1509 struct drm_device *ddev,
1510 struct pci_dev *pdev,
1512 void amdgpu_device_fini(struct amdgpu_device *adev);
1513 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1515 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
1516 uint32_t acc_flags);
1517 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
1518 uint32_t acc_flags);
1519 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1520 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1522 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
1523 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
1524 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
1525 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
1528 * Registers read & write functions.
1531 #define AMDGPU_REGS_IDX (1<<0)
1532 #define AMDGPU_REGS_NO_KIQ (1<<1)
1534 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1535 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1537 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1538 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1539 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1540 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1541 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
1542 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1543 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1544 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1545 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1546 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1547 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1548 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1549 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1550 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1551 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1552 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1553 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1554 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1555 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1556 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1557 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1558 #define WREG32_P(reg, val, mask) \
1560 uint32_t tmp_ = RREG32(reg); \
1562 tmp_ |= ((val) & ~(mask)); \
1563 WREG32(reg, tmp_); \
1565 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1566 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1567 #define WREG32_PLL_P(reg, val, mask) \
1569 uint32_t tmp_ = RREG32_PLL(reg); \
1571 tmp_ |= ((val) & ~(mask)); \
1572 WREG32_PLL(reg, tmp_); \
1574 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1575 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1576 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1578 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
1579 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
1580 #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
1581 #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
1583 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1584 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1586 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
1587 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1588 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1590 #define REG_GET_FIELD(value, reg, field) \
1591 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1593 #define WREG32_FIELD(reg, field, val) \
1594 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1599 #define RBIOS8(i) (adev->bios[i])
1600 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1601 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1606 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v)
1608 if (ring->count_dw <= 0)
1609 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
1610 ring->ring[ring->wptr++ & ring->buf_mask] = v;
1611 ring->wptr &= ring->ptr_mask;
1615 static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, void *src, int count_dw)
1617 unsigned occupied, chunk1, chunk2;
1620 if (ring->count_dw < count_dw) {
1621 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n");
1623 occupied = ring->wptr & ring->ptr_mask;
1624 dst = (void *)&ring->ring[occupied];
1625 chunk1 = ring->ptr_mask + 1 - occupied;
1626 chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1;
1627 chunk2 = count_dw - chunk1;
1632 memcpy(dst, src, chunk1);
1636 dst = (void *)ring->ring;
1637 memcpy(dst, src, chunk2);
1640 ring->wptr += count_dw;
1641 ring->wptr &= ring->ptr_mask;
1642 ring->count_dw -= count_dw;
1646 static inline struct amdgpu_sdma_instance *
1647 amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
1649 struct amdgpu_device *adev = ring->adev;
1652 for (i = 0; i < adev->sdma.num_instances; i++)
1653 if (&adev->sdma.instance[i].ring == ring)
1656 if (i < AMDGPU_MAX_SDMA_INSTANCES)
1657 return &adev->sdma.instance[i];
1665 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1666 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1667 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1668 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1669 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1670 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1671 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1672 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1673 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1674 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1675 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1676 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
1677 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
1678 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
1679 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
1680 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
1681 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
1682 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
1683 #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
1684 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
1685 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
1686 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
1687 #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
1688 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
1689 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
1690 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
1691 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
1692 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
1693 #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
1694 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
1695 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
1696 #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
1697 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
1698 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
1699 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
1700 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
1701 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
1702 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
1703 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
1704 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r))
1705 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
1706 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
1707 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
1708 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
1709 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
1710 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
1711 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
1712 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
1713 #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
1714 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
1715 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
1716 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
1717 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s))
1718 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s))
1719 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
1720 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
1721 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
1722 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
1723 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
1725 /* Common functions */
1726 int amdgpu_gpu_reset(struct amdgpu_device *adev);
1727 bool amdgpu_need_backup(struct amdgpu_device *adev);
1728 void amdgpu_pci_config_reset(struct amdgpu_device *adev);
1729 bool amdgpu_need_post(struct amdgpu_device *adev);
1730 void amdgpu_update_display_priority(struct amdgpu_device *adev);
1732 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data);
1733 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
1734 u32 ip_instance, u32 ring,
1735 struct amdgpu_ring **out_ring);
1736 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes);
1737 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
1738 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
1739 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
1740 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1742 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
1743 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
1744 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1746 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1747 int *last_invalidated);
1748 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
1749 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1750 struct ttm_mem_reg *mem);
1751 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
1752 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
1753 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
1754 int amdgpu_ttm_init(struct amdgpu_device *adev);
1755 void amdgpu_ttm_fini(struct amdgpu_device *adev);
1756 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
1757 const u32 *registers,
1758 const u32 array_size);
1760 bool amdgpu_device_is_px(struct drm_device *dev);
1762 #if defined(CONFIG_VGA_SWITCHEROO)
1763 void amdgpu_register_atpx_handler(void);
1764 void amdgpu_unregister_atpx_handler(void);
1765 bool amdgpu_has_atpx_dgpu_power_cntl(void);
1766 bool amdgpu_is_atpx_hybrid(void);
1767 bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1769 static inline void amdgpu_register_atpx_handler(void) {}
1770 static inline void amdgpu_unregister_atpx_handler(void) {}
1771 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
1772 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
1773 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
1779 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1780 extern const int amdgpu_max_kms_ioctl;
1782 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
1783 void amdgpu_driver_unload_kms(struct drm_device *dev);
1784 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1785 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1786 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1787 struct drm_file *file_priv);
1788 int amdgpu_suspend(struct amdgpu_device *adev);
1789 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1790 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
1791 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1792 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1793 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1794 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
1796 struct timeval *vblank_time,
1798 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1802 * functions used by amdgpu_encoder.c
1804 struct amdgpu_afmt_acr {
1818 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1821 #if defined(CONFIG_ACPI)
1822 int amdgpu_acpi_init(struct amdgpu_device *adev);
1823 void amdgpu_acpi_fini(struct amdgpu_device *adev);
1824 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1825 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1826 u8 perf_req, bool advertise);
1827 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1829 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
1830 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1833 struct amdgpu_bo_va_mapping *
1834 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1835 uint64_t addr, struct amdgpu_bo **bo);
1836 int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser);
1838 #include "amdgpu_object.h"