drivers/gpu/drm/i915/display/intel_dp_mst.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *             2014 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <drm/drm_atomic.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_edid.h>
  29 #include <drm/drm_fixed.h>
  30 #include <drm/drm_probe_helper.h>
  31
  32 #include "i915_drv.h"
  33 #include "i915_reg.h"
  34 #include "intel_atomic.h"
  35 #include "intel_audio.h"
  36 #include "intel_connector.h"
  37 #include "intel_crtc.h"
  38 #include "intel_ddi.h"
  39 #include "intel_de.h"
  40 #include "intel_display_driver.h"
  41 #include "intel_display_types.h"
  42 #include "intel_dp.h"
  43 #include "intel_dp_hdcp.h"
  44 #include "intel_dp_mst.h"
  45 #include "intel_dp_tunnel.h"
  46 #include "intel_dpio_phy.h"
  47 #include "intel_hdcp.h"
  48 #include "intel_hotplug.h"
  49 #include "intel_link_bw.h"
  50 #include "intel_psr.h"
  51 #include "intel_vdsc.h"
  52 #include "skl_scaler.h"
  53
  54 static int intel_dp_mst_max_dpt_bpp(const struct intel_crtc_state *crtc_state,
  55                                     bool dsc)
  56 {
  57         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
  58         const struct drm_display_mode *adjusted_mode =
  59                 &crtc_state->hw.adjusted_mode;
  60
  61         if (!intel_dp_is_uhbr(crtc_state) || DISPLAY_VER(i915) >= 20 || !dsc)
  62                 return INT_MAX;
  63
  64         /*
  65          * DSC->DPT interface width:
  66          *   ICL-MTL: 72 bits (each branch has 72 bits, only left branch is used)
  67          *   LNL+:    144 bits (not a bottleneck in any config)
  68          *
  69          * Bspec/49259 suggests that the FEC overhead needs to be
  70          * applied here, though HW people claim that neither this FEC
  71          * or any other overhead is applicable here (that is the actual
  72          * available_bw is just symbol_clock * 72). However based on
  73          * testing on MTL-P the
  74          * - DELL U3224KBA display
  75          * - Unigraf UCD-500 CTS test sink
  76          * devices the
  77          * - 5120x2880/995.59Mhz
  78          * - 6016x3384/1357.23Mhz
  79          * - 6144x3456/1413.39Mhz
  80          * modes (all the ones having a DPT limit on the above devices),
  81          * both the channel coding efficiency and an additional 3%
  82          * overhead needs to be accounted for.
  83          */
  84         return div64_u64(mul_u32_u32(intel_dp_link_symbol_clock(crtc_state->port_clock) * 72,
  85                                      drm_dp_bw_channel_coding_efficiency(true)),
  86                          mul_u32_u32(adjusted_mode->crtc_clock, 1030000));
  87 }
  88
  89 static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
  90                                     const struct intel_connector *connector,
  91                                     bool ssc, bool dsc, int bpp_x16)
  92 {
  93         const struct drm_display_mode *adjusted_mode =
  94                 &crtc_state->hw.adjusted_mode;
  95         unsigned long flags = DRM_DP_BW_OVERHEAD_MST;
  96         int dsc_slice_count = 0;
  97         int overhead;
  98
  99         flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR : 0;
 100         flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0;
 101         flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;
 102
 103         if (dsc) {
 104                 flags |= DRM_DP_BW_OVERHEAD_DSC;
 105                 dsc_slice_count = intel_dp_dsc_get_slice_count(connector,
 106                                                                adjusted_mode->clock,
 107                                                                adjusted_mode->hdisplay,
 108                                                                crtc_state->joiner_pipes);
 109         }
 110
 111         overhead = drm_dp_bw_overhead(crtc_state->lane_count,
 112                                       adjusted_mode->hdisplay,
 113                                       dsc_slice_count,
 114                                       bpp_x16,
 115                                       flags);
 116
 117         /*
 118          * TODO: clarify whether a minimum required by the fixed FEC overhead
 119          * in the bspec audio programming sequence is required here.
 120          */
 121         return max(overhead, intel_dp_bw_fec_overhead(crtc_state->fec_enable));
 122 }
 123
 124 static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state,
 125                                      const struct intel_connector *connector,
 126                                      int overhead,
 127                                      int bpp_x16,
 128                                      struct intel_link_m_n *m_n)
 129 {
 130         const struct drm_display_mode *adjusted_mode =
 131                 &crtc_state->hw.adjusted_mode;
 132
 133         /* TODO: Check WA 14013163432 to set data M/N for full BW utilization. */
 134         intel_link_compute_m_n(bpp_x16, crtc_state->lane_count,
 135                                adjusted_mode->crtc_clock,
 136                                crtc_state->port_clock,
 137                                overhead,
 138                                m_n);
 139
 140         m_n->tu = DIV_ROUND_UP_ULL(mul_u32_u32(m_n->data_m, 64), m_n->data_n);
 141 }
 142
 143 static int intel_dp_mst_calc_pbn(int pixel_clock, int bpp_x16, int bw_overhead)
 144 {
 145         int effective_data_rate =
 146                 intel_dp_effective_data_rate(pixel_clock, bpp_x16, bw_overhead);
 147
 148         /*
 149          * TODO: Use drm_dp_calc_pbn_mode() instead, once it's converted
 150          * to calculate PBN with the BW overhead passed to it.
 151          */
 152         return DIV_ROUND_UP(effective_data_rate * 64, 54 * 1000);
 153 }
 154
 155 static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
 156                                                 struct intel_crtc_state *crtc_state,
 157                                                 int max_bpp,
 158                                                 int min_bpp,
 159                                                 struct link_config_limits *limits,
 160                                                 struct drm_connector_state *conn_state,
 161                                                 int step,
 162                                                 bool dsc)
 163 {
 164         struct drm_atomic_state *state = crtc_state->uapi.state;
 165         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 166         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 167         struct drm_dp_mst_topology_state *mst_state;
 168         struct intel_connector *connector =
 169                 to_intel_connector(conn_state->connector);
 170         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 171         const struct drm_display_mode *adjusted_mode =
 172                 &crtc_state->hw.adjusted_mode;
 173         int bpp, slots = -EINVAL;
 174         int max_dpt_bpp;
 175         int ret = 0;
 176
 177         mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst_mgr);
 178         if (IS_ERR(mst_state))
 179                 return PTR_ERR(mst_state);
 180
 181         crtc_state->lane_count = limits->max_lane_count;
 182         crtc_state->port_clock = limits->max_rate;
 183
 184         if (dsc) {
 185                 if (!intel_dp_supports_fec(intel_dp, connector, crtc_state))
 186                         return -EINVAL;
 187
 188                 crtc_state->fec_enable = !intel_dp_is_uhbr(crtc_state);
 189         }
 190
 191         mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr,
 192                                                       crtc_state->port_clock,
 193                                                       crtc_state->lane_count);
 194
 195         max_dpt_bpp = intel_dp_mst_max_dpt_bpp(crtc_state, dsc);
 196         if (max_bpp > max_dpt_bpp) {
 197                 drm_dbg_kms(&i915->drm, "Limiting bpp to max DPT bpp (%d -> %d)\n",
 198                             max_bpp, max_dpt_bpp);
 199                 max_bpp = max_dpt_bpp;
 200         }
 201
 202         drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d max bpp %d\n",
 203                     min_bpp, max_bpp);
 204
 205         for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
 206                 int local_bw_overhead;
 207                 int remote_bw_overhead;
 208                 int link_bpp_x16;
 209                 int remote_tu;
 210                 fixed20_12 pbn;
 211
 212                 drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
 213
 214                 link_bpp_x16 = to_bpp_x16(dsc ? bpp :
 215                                           intel_dp_output_bpp(crtc_state->output_format, bpp));
 216
 217                 local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector,
 218                                                              false, dsc, link_bpp_x16);
 219                 remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector,
 220                                                               true, dsc, link_bpp_x16);
 221
 222                 intel_dp_mst_compute_m_n(crtc_state, connector,
 223                                          local_bw_overhead,
 224                                          link_bpp_x16,
 225                                          &crtc_state->dp_m_n);
 226
 227                 /*
 228                  * The TU size programmed to the HW determines which slots in
 229                  * an MTP frame are used for this stream, which needs to match
 230                  * the payload size programmed to the first downstream branch
 231                  * device's payload table.
 232                  *
 233                  * Note that atm the payload's PBN value DRM core sends via
 234                  * the ALLOCATE_PAYLOAD side-band message matches the payload
 235                  * size (which it calculates from the PBN value) it programs
 236                  * to the first branch device's payload table. The allocation
 237                  * in the payload table could be reduced though (to
 238                  * crtc_state->dp_m_n.tu), provided that the driver doesn't
 239                  * enable SSC on the corresponding link.
 240                  */
 241                 pbn.full = dfixed_const(intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock,
 242                                                               link_bpp_x16,
 243                                                               remote_bw_overhead));
 244                 remote_tu = DIV_ROUND_UP(pbn.full, mst_state->pbn_div.full);
 245
 246                 /*
 247                  * Aligning the TUs ensures that symbols consisting of multiple
 248                  * (4) symbol cycles don't get split between two consecutive
 249                  * MTPs, as required by Bspec.
 250                  * TODO: remove the alignment restriction for 128b/132b links
 251                  * on some platforms, where Bspec allows this.
 252                  */
 253                 remote_tu = ALIGN(remote_tu, 4 / crtc_state->lane_count);
 254
 255                 /*
 256                  * Also align PBNs accordingly, since MST core will derive its
 257                  * own copy of TU from the PBN in drm_dp_atomic_find_time_slots().
 258                  * The above comment about the difference between the PBN
 259                  * allocated for the whole path and the TUs allocated for the
 260                  * first branch device's link also applies here.
 261                  */
 262                 pbn.full = remote_tu * mst_state->pbn_div.full;
 263                 crtc_state->pbn = dfixed_trunc(pbn);
 264
 265                 drm_WARN_ON(&i915->drm, remote_tu < crtc_state->dp_m_n.tu);
 266                 crtc_state->dp_m_n.tu = remote_tu;
 267
 268                 slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
 269                                                       connector->port,
 270                                                       crtc_state->pbn);
 271                 if (slots == -EDEADLK)
 272                         return slots;
 273
 274                 if (slots >= 0) {
 275                         drm_WARN_ON(&i915->drm, slots != crtc_state->dp_m_n.tu);
 276
 277                         break;
 278                 }
 279         }
 280
 281         /* We failed to find a proper bpp/timeslots, return error */
 282         if (ret)
 283                 slots = ret;
 284
 285         if (slots < 0) {
 286                 drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n",
 287                             slots);
 288         } else {
 289                 if (!dsc)
 290                         crtc_state->pipe_bpp = bpp;
 291                 else
 292                         crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(bpp);
 293                 drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc);
 294         }
 295
 296         return slots;
 297 }
 298
 299 static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
 300                                             struct intel_crtc_state *crtc_state,
 301                                             struct drm_connector_state *conn_state,
 302                                             struct link_config_limits *limits)
 303 {
 304         int slots = -EINVAL;
 305
 306         /*
 307          * FIXME: allocate the BW according to link_bpp, which in the case of
 308          * YUV420 is only half of the pipe bpp value.
 309          */
 310         slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
 311                                                      to_bpp_int(limits->link.max_bpp_x16),
 312                                                      to_bpp_int(limits->link.min_bpp_x16),
 313                                                      limits,
 314                                                      conn_state, 2 * 3, false);
 315
 316         if (slots < 0)
 317                 return slots;
 318
 319         return 0;
 320 }
 321
 322 static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
 323                                                 struct intel_crtc_state *crtc_state,
 324                                                 struct drm_connector_state *conn_state,
 325                                                 struct link_config_limits *limits)
 326 {
 327         struct intel_connector *connector =
 328                 to_intel_connector(conn_state->connector);
 329         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 330         int slots = -EINVAL;
 331         int i, num_bpc;
 332         u8 dsc_bpc[3] = {};
 333         int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp;
 334         u8 dsc_max_bpc;
 335         int min_compressed_bpp, max_compressed_bpp;
 336
 337         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
 338         if (DISPLAY_VER(i915) >= 12)
 339                 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
 340         else
 341                 dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc);
 342
 343         max_bpp = min_t(u8, dsc_max_bpc * 3, limits->pipe.max_bpp);
 344         min_bpp = limits->pipe.min_bpp;
 345
 346         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,
 347                                                        dsc_bpc);
 348
 349         drm_dbg_kms(&i915->drm, "DSC Source supported min bpp %d max bpp %d\n",
 350                     min_bpp, max_bpp);
 351
 352         sink_max_bpp = dsc_bpc[0] * 3;
 353         sink_min_bpp = sink_max_bpp;
 354
 355         for (i = 1; i < num_bpc; i++) {
 356                 if (sink_min_bpp > dsc_bpc[i] * 3)
 357                         sink_min_bpp = dsc_bpc[i] * 3;
 358                 if (sink_max_bpp < dsc_bpc[i] * 3)
 359                         sink_max_bpp = dsc_bpc[i] * 3;
 360         }
 361
 362         drm_dbg_kms(&i915->drm, "DSC Sink supported min bpp %d max bpp %d\n",
 363                     sink_min_bpp, sink_max_bpp);
 364
 365         if (min_bpp < sink_min_bpp)
 366                 min_bpp = sink_min_bpp;
 367
 368         if (max_bpp > sink_max_bpp)
 369                 max_bpp = sink_max_bpp;
 370
 371         crtc_state->pipe_bpp = max_bpp;
 372
 373         max_compressed_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
 374                                                                   crtc_state,
 375                                                                   max_bpp / 3);
 376         max_compressed_bpp = min(max_compressed_bpp,
 377                                  to_bpp_int(limits->link.max_bpp_x16));
 378
 379         min_compressed_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state);
 380         min_compressed_bpp = max(min_compressed_bpp,
 381                                  to_bpp_int_roundup(limits->link.min_bpp_x16));
 382
 383         drm_dbg_kms(&i915->drm, "DSC Sink supported compressed min bpp %d compressed max bpp %d\n",
 384                     min_compressed_bpp, max_compressed_bpp);
 385
 386         /* Align compressed bpps according to our own constraints */
 387         max_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, max_compressed_bpp,
 388                                                             crtc_state->pipe_bpp);
 389         min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, min_compressed_bpp,
 390                                                             crtc_state->pipe_bpp);
 391
 392         slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_compressed_bpp,
 393                                                      min_compressed_bpp, limits,
 394                                                      conn_state, 1, true);
 395
 396         if (slots < 0)
 397                 return slots;
 398
 399         return 0;
 400 }
 401 static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
 402                                      struct intel_crtc_state *crtc_state,
 403                                      struct drm_connector_state *conn_state)
 404 {
 405         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 406         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 407         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 408         struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
 409         struct drm_dp_mst_topology_state *topology_state;
 410         u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ?
 411                 DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B;
 412
 413         topology_state = drm_atomic_get_mst_topology_state(conn_state->state, mgr);
 414         if (IS_ERR(topology_state)) {
 415                 drm_dbg_kms(&i915->drm, "slot update failed\n");
 416                 return PTR_ERR(topology_state);
 417         }
 418
 419         drm_dp_mst_update_slots(topology_state, link_coding_cap);
 420
 421         return 0;
 422 }
 423
 424 static int mode_hblank_period_ns(const struct drm_display_mode *mode)
 425 {
 426         return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(mode->htotal - mode->hdisplay,
 427                                                  NSEC_PER_SEC / 1000),
 428                                      mode->crtc_clock);
 429 }
 430
 431 static bool
 432 hblank_expansion_quirk_needs_dsc(const struct intel_connector *connector,
 433                                  const struct intel_crtc_state *crtc_state,
 434                                  const struct link_config_limits *limits)
 435 {
 436         const struct drm_display_mode *adjusted_mode =
 437                 &crtc_state->hw.adjusted_mode;
 438         bool is_uhbr_sink = connector->mst_port &&
 439                             drm_dp_128b132b_supported(connector->mst_port->dpcd);
 440         int hblank_limit = is_uhbr_sink ? 500 : 300;
 441
 442         if (!connector->dp.dsc_hblank_expansion_quirk)
 443                 return false;
 444
 445         if (is_uhbr_sink && !drm_dp_is_uhbr_rate(limits->max_rate))
 446                 return false;
 447
 448         if (mode_hblank_period_ns(adjusted_mode) > hblank_limit)
 449                 return false;
 450
 451         return true;
 452 }
 453
 454 static bool
 455 adjust_limits_for_dsc_hblank_expansion_quirk(const struct intel_connector *connector,
 456                                              const struct intel_crtc_state *crtc_state,
 457                                              struct link_config_limits *limits,
 458                                              bool dsc)
 459 {
 460         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 461         const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 462         int min_bpp_x16 = limits->link.min_bpp_x16;
 463
 464         if (!hblank_expansion_quirk_needs_dsc(connector, crtc_state, limits))
 465                 return true;
 466
 467         if (!dsc) {
 468                 if (intel_dp_supports_dsc(connector, crtc_state)) {
 469                         drm_dbg_kms(&i915->drm,
 470                                     "[CRTC:%d:%s][CONNECTOR:%d:%s] DSC needed by hblank expansion quirk\n",
 471                                     crtc->base.base.id, crtc->base.name,
 472                                     connector->base.base.id, connector->base.name);
 473                         return false;
 474                 }
 475
 476                 drm_dbg_kms(&i915->drm,
 477                             "[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to 24 due to hblank expansion quirk\n",
 478                             crtc->base.base.id, crtc->base.name,
 479                             connector->base.base.id, connector->base.name);
 480
 481                 if (limits->link.max_bpp_x16 < to_bpp_x16(24))
 482                         return false;
 483
 484                 limits->link.min_bpp_x16 = to_bpp_x16(24);
 485
 486                 return true;
 487         }
 488
 489         drm_WARN_ON(&i915->drm, limits->min_rate != limits->max_rate);
 490
 491         if (limits->max_rate < 540000)
 492                 min_bpp_x16 = to_bpp_x16(13);
 493         else if (limits->max_rate < 810000)
 494                 min_bpp_x16 = to_bpp_x16(10);
 495
 496         if (limits->link.min_bpp_x16 >= min_bpp_x16)
 497                 return true;
 498
 499         drm_dbg_kms(&i915->drm,
 500                     "[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to " BPP_X16_FMT " in DSC mode due to hblank expansion quirk\n",
 501                     crtc->base.base.id, crtc->base.name,
 502                     connector->base.base.id, connector->base.name,
 503                     BPP_X16_ARGS(min_bpp_x16));
 504
 505         if (limits->link.max_bpp_x16 < min_bpp_x16)
 506                 return false;
 507
 508         limits->link.min_bpp_x16 = min_bpp_x16;
 509
 510         return true;
 511 }
 512
 513 static bool
 514 intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
 515                                    const struct intel_connector *connector,
 516                                    struct intel_crtc_state *crtc_state,
 517                                    bool dsc,
 518                                    struct link_config_limits *limits)
 519 {
 520         /*
 521          * for MST we always configure max link bw - the spec doesn't
 522          * seem to suggest we should do otherwise.
 523          */
 524         limits->min_rate = limits->max_rate =
 525                 intel_dp_max_link_rate(intel_dp);
 526
 527         limits->min_lane_count = limits->max_lane_count =
 528                 intel_dp_max_lane_count(intel_dp);
 529
 530         limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
 531         /*
 532          * FIXME: If all the streams can't fit into the link with
 533          * their current pipe_bpp we should reduce pipe_bpp across
 534          * the board until things start to fit. Until then we
 535          * limit to <= 8bpc since that's what was hardcoded for all
 536          * MST streams previously. This hack should be removed once
 537          * we have the proper retry logic in place.
 538          */
 539         limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24);
 540
 541         intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
 542
 543         if (!intel_dp_compute_config_link_bpp_limits(intel_dp,
 544                                                      crtc_state,
 545                                                      dsc,
 546                                                      limits))
 547                 return false;
 548
 549         return adjust_limits_for_dsc_hblank_expansion_quirk(connector,
 550                                                             crtc_state,
 551                                                             limits,
 552                                                             dsc);
 553 }
 554
 555 static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
 556                                        struct intel_crtc_state *pipe_config,
 557                                        struct drm_connector_state *conn_state)
 558 {
 559         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 560         struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
 561         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 562         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 563         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 564         struct intel_connector *connector =
 565                 to_intel_connector(conn_state->connector);
 566         const struct drm_display_mode *adjusted_mode =
 567                 &pipe_config->hw.adjusted_mode;
 568         struct link_config_limits limits;
 569         bool dsc_needed, joiner_needs_dsc;
 570         int ret = 0;
 571
 572         if (pipe_config->fec_enable &&
 573             !intel_dp_supports_fec(intel_dp, connector, pipe_config))
 574                 return -EINVAL;
 575
 576         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 577                 return -EINVAL;
 578
 579         if (intel_dp_need_joiner(intel_dp, connector,
 580                                  adjusted_mode->crtc_hdisplay,
 581                                  adjusted_mode->crtc_clock))
 582                 pipe_config->joiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
 583
 584         pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
 585         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 586         pipe_config->has_pch_encoder = false;
 587
 588         joiner_needs_dsc = intel_dp_joiner_needs_dsc(dev_priv, pipe_config->joiner_pipes);
 589
 590         dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
 591                      !intel_dp_mst_compute_config_limits(intel_dp,
 592                                                          connector,
 593                                                          pipe_config,
 594                                                          false,
 595                                                          &limits);
 596
 597         if (!dsc_needed) {
 598                 ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
 599                                                        conn_state, &limits);
 600
 601                 if (ret == -EDEADLK)
 602                         return ret;
 603
 604                 if (ret)
 605                         dsc_needed = true;
 606         }
 607
 608         /* enable compression if the mode doesn't fit available BW */
 609         if (dsc_needed) {
 610                 drm_dbg_kms(&dev_priv->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
 611                             str_yes_no(ret), str_yes_no(joiner_needs_dsc),
 612                             str_yes_no(intel_dp->force_dsc_en));
 613
 614                 if (!intel_dp_supports_dsc(connector, pipe_config))
 615                         return -EINVAL;
 616
 617                 if (!intel_dp_mst_compute_config_limits(intel_dp,
 618                                                         connector,
 619                                                         pipe_config,
 620                                                         true,
 621                                                         &limits))
 622                         return -EINVAL;
 623
 624                 /*
 625                  * FIXME: As bpc is hardcoded to 8, as mentioned above,
 626                  * WARN and ignore the debug flag force_dsc_bpc for now.
 627                  */
 628                 drm_WARN(&dev_priv->drm, intel_dp->force_dsc_bpc, "Cannot Force BPC for MST\n");
 629                 /*
 630                  * Try to get at least some timeslots and then see, if
 631                  * we can fit there with DSC.
 632                  */
 633                 drm_dbg_kms(&dev_priv->drm, "Trying to find VCPI slots in DSC mode\n");
 634
 635                 ret = intel_dp_dsc_mst_compute_link_config(encoder, pipe_config,
 636                                                            conn_state, &limits);
 637                 if (ret < 0)
 638                         return ret;
 639
 640                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
 641                                                   conn_state, &limits,
 642                                                   pipe_config->dp_m_n.tu, false);
 643         }
 644
 645         if (ret)
 646                 return ret;
 647
 648         ret = intel_dp_mst_update_slots(encoder, pipe_config, conn_state);
 649         if (ret)
 650                 return ret;
 651
 652         pipe_config->limited_color_range =
 653                 intel_dp_limited_color_range(pipe_config, conn_state);
 654
 655         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
 656                 pipe_config->lane_lat_optim_mask =
 657                         bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
 658
 659         intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
 660
 661         intel_ddi_compute_min_voltage_level(pipe_config);
 662
 663         intel_psr_compute_config(intel_dp, pipe_config, conn_state);
 664
 665         return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector,
 666                                                         pipe_config);
 667 }
 668
 669 /*
 670  * Iterate over all connectors and return a mask of
 671  * all CPU transcoders streaming over the same DP link.
 672  */
 673 static unsigned int
 674 intel_dp_mst_transcoder_mask(struct intel_atomic_state *state,
 675                              struct intel_dp *mst_port)
 676 {
 677         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 678         const struct intel_digital_connector_state *conn_state;
 679         struct intel_connector *connector;
 680         u8 transcoders = 0;
 681         int i;
 682
 683         if (DISPLAY_VER(dev_priv) < 12)
 684                 return 0;
 685
 686         for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
 687                 const struct intel_crtc_state *crtc_state;
 688                 struct intel_crtc *crtc;
 689
 690                 if (connector->mst_port != mst_port || !conn_state->base.crtc)
 691                         continue;
 692
 693                 crtc = to_intel_crtc(conn_state->base.crtc);
 694                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
 695
 696                 if (!crtc_state->hw.active)
 697                         continue;
 698
 699                 transcoders |= BIT(crtc_state->cpu_transcoder);
 700         }
 701
 702         return transcoders;
 703 }
 704
 705 static u8 get_pipes_downstream_of_mst_port(struct intel_atomic_state *state,
 706                                            struct drm_dp_mst_topology_mgr *mst_mgr,
 707                                            struct drm_dp_mst_port *parent_port)
 708 {
 709         const struct intel_digital_connector_state *conn_state;
 710         struct intel_connector *connector;
 711         u8 mask = 0;
 712         int i;
 713
 714         for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
 715                 if (!conn_state->base.crtc)
 716                         continue;
 717
 718                 if (&connector->mst_port->mst_mgr != mst_mgr)
 719                         continue;
 720
 721                 if (connector->port != parent_port &&
 722                     !drm_dp_mst_port_downstream_of_parent(mst_mgr,
 723                                                           connector->port,
 724                                                           parent_port))
 725                         continue;
 726
 727                 mask |= BIT(to_intel_crtc(conn_state->base.crtc)->pipe);
 728         }
 729
 730         return mask;
 731 }
 732
 733 static int intel_dp_mst_check_fec_change(struct intel_atomic_state *state,
 734                                          struct drm_dp_mst_topology_mgr *mst_mgr,
 735                                          struct intel_link_bw_limits *limits)
 736 {
 737         struct drm_i915_private *i915 = to_i915(state->base.dev);
 738         struct intel_crtc *crtc;
 739         u8 mst_pipe_mask;
 740         u8 fec_pipe_mask = 0;
 741         int ret;
 742
 743         mst_pipe_mask = get_pipes_downstream_of_mst_port(state, mst_mgr, NULL);
 744
 745         for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, mst_pipe_mask) {
 746                 struct intel_crtc_state *crtc_state =
 747                         intel_atomic_get_new_crtc_state(state, crtc);
 748
 749                 /* Atomic connector check should've added all the MST CRTCs. */
 750                 if (drm_WARN_ON(&i915->drm, !crtc_state))
 751                         return -EINVAL;
 752
 753                 if (crtc_state->fec_enable)
 754                         fec_pipe_mask |= BIT(crtc->pipe);
 755         }
 756
 757         if (!fec_pipe_mask || mst_pipe_mask == fec_pipe_mask)
 758                 return 0;
 759
 760         limits->force_fec_pipes |= mst_pipe_mask;
 761
 762         ret = intel_modeset_pipes_in_mask_early(state, "MST FEC",
 763                                                 mst_pipe_mask);
 764
 765         return ret ? : -EAGAIN;
 766 }
 767
 768 static int intel_dp_mst_check_bw(struct intel_atomic_state *state,
 769                                  struct drm_dp_mst_topology_mgr *mst_mgr,
 770                                  struct drm_dp_mst_topology_state *mst_state,
 771                                  struct intel_link_bw_limits *limits)
 772 {
 773         struct drm_dp_mst_port *mst_port;
 774         u8 mst_port_pipes;
 775         int ret;
 776
 777         ret = drm_dp_mst_atomic_check_mgr(&state->base, mst_mgr, mst_state, &mst_port);
 778         if (ret != -ENOSPC)
 779                 return ret;
 780
 781         mst_port_pipes = get_pipes_downstream_of_mst_port(state, mst_mgr, mst_port);
 782
 783         ret = intel_link_bw_reduce_bpp(state, limits,
 784                                        mst_port_pipes, "MST link BW");
 785
 786         return ret ? : -EAGAIN;
 787 }
 788
 789 /**
 790  * intel_dp_mst_atomic_check_link - check all modeset MST link configuration
 791  * @state: intel atomic state
 792  * @limits: link BW limits
 793  *
 794  * Check the link configuration for all modeset MST outputs. If the
 795  * configuration is invalid @limits will be updated if possible to
 796  * reduce the total BW, after which the configuration for all CRTCs in
 797  * @state must be recomputed with the updated @limits.
 798  *
 799  * Returns:
 800  *   - 0 if the confugration is valid
 801  *   - %-EAGAIN, if the configuration is invalid and @limits got updated
 802  *     with fallback values with which the configuration of all CRTCs in
 803  *     @state must be recomputed
 804  *   - Other negative error, if the configuration is invalid without a
 805  *     fallback possibility, or the check failed for another reason
 806  */
 807 int intel_dp_mst_atomic_check_link(struct intel_atomic_state *state,
 808                                    struct intel_link_bw_limits *limits)
 809 {
 810         struct drm_dp_mst_topology_mgr *mgr;
 811         struct drm_dp_mst_topology_state *mst_state;
 812         int ret;
 813         int i;
 814
 815         for_each_new_mst_mgr_in_state(&state->base, mgr, mst_state, i) {
 816                 ret = intel_dp_mst_check_fec_change(state, mgr, limits);
 817                 if (ret)
 818                         return ret;
 819
 820                 ret = intel_dp_mst_check_bw(state, mgr, mst_state,
 821                                             limits);
 822                 if (ret)
 823                         return ret;
 824         }
 825
 826         return 0;
 827 }
 828
 829 static int intel_dp_mst_compute_config_late(struct intel_encoder *encoder,
 830                                             struct intel_crtc_state *crtc_state,
 831                                             struct drm_connector_state *conn_state)
 832 {
 833         struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
 834         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 835         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 836
 837         /* lowest numbered transcoder will be designated master */
 838         crtc_state->mst_master_transcoder =
 839                 ffs(intel_dp_mst_transcoder_mask(state, intel_dp)) - 1;
 840
 841         return 0;
 842 }
 843
 844 /*
 845  * If one of the connectors in a MST stream needs a modeset, mark all CRTCs
 846  * that shares the same MST stream as mode changed,
 847  * intel_modeset_pipe_config()+intel_crtc_check_fastset() will take care to do
 848  * a fastset when possible.
 849  *
 850  * On TGL+ this is required since each stream go through a master transcoder,
 851  * so if the master transcoder needs modeset, all other streams in the
 852  * topology need a modeset. All platforms need to add the atomic state
 853  * for all streams in the topology, since a modeset on one may require
 854  * changing the MST link BW usage of the others, which in turn needs a
 855  * recomputation of the corresponding CRTC states.
 856  */
 857 static int
 858 intel_dp_mst_atomic_topology_check(struct intel_connector *connector,
 859                                    struct intel_atomic_state *state)
 860 {
 861         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 862         struct drm_connector_list_iter connector_list_iter;
 863         struct intel_connector *connector_iter;
 864         int ret = 0;
 865
 866         if (!intel_connector_needs_modeset(state, &connector->base))
 867                 return 0;
 868
 869         drm_connector_list_iter_begin(&dev_priv->drm, &connector_list_iter);
 870         for_each_intel_connector_iter(connector_iter, &connector_list_iter) {
 871                 struct intel_digital_connector_state *conn_iter_state;
 872                 struct intel_crtc_state *crtc_state;
 873                 struct intel_crtc *crtc;
 874
 875                 if (connector_iter->mst_port != connector->mst_port ||
 876                     connector_iter == connector)
 877                         continue;
 878
 879                 conn_iter_state = intel_atomic_get_digital_connector_state(state,
 880                                                                            connector_iter);
 881                 if (IS_ERR(conn_iter_state)) {
 882                         ret = PTR_ERR(conn_iter_state);
 883                         break;
 884                 }
 885
 886                 if (!conn_iter_state->base.crtc)
 887                         continue;
 888
 889                 crtc = to_intel_crtc(conn_iter_state->base.crtc);
 890                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
 891                 if (IS_ERR(crtc_state)) {
 892                         ret = PTR_ERR(crtc_state);
 893                         break;
 894                 }
 895
 896                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
 897                 if (ret)
 898                         break;
 899                 crtc_state->uapi.mode_changed = true;
 900         }
 901         drm_connector_list_iter_end(&connector_list_iter);
 902
 903         return ret;
 904 }
 905
 906 static int
 907 intel_dp_mst_atomic_check(struct drm_connector *connector,
 908                           struct drm_atomic_state *_state)
 909 {
 910         struct intel_atomic_state *state = to_intel_atomic_state(_state);
 911         struct intel_connector *intel_connector =
 912                 to_intel_connector(connector);
 913         int ret;
 914
 915         ret = intel_digital_connector_atomic_check(connector, &state->base);
 916         if (ret)
 917                 return ret;
 918
 919         ret = intel_dp_mst_atomic_topology_check(intel_connector, state);
 920         if (ret)
 921                 return ret;
 922
 923         if (intel_connector_needs_modeset(state, connector)) {
 924                 ret = intel_dp_tunnel_atomic_check_state(state,
 925                                                          intel_connector->mst_port,
 926                                                          intel_connector);
 927                 if (ret)
 928                         return ret;
 929         }
 930
 931         return drm_dp_atomic_release_time_slots(&state->base,
 932                                                 &intel_connector->mst_port->mst_mgr,
 933                                                 intel_connector->port);
 934 }
 935
 936 static void clear_act_sent(struct intel_encoder *encoder,
 937                            const struct intel_crtc_state *crtc_state)
 938 {
 939         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 940
 941         intel_de_write(i915, dp_tp_status_reg(encoder, crtc_state),
 942                        DP_TP_STATUS_ACT_SENT);
 943 }
 944
 945 static void wait_for_act_sent(struct intel_encoder *encoder,
 946                               const struct intel_crtc_state *crtc_state)
 947 {
 948         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 949         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 950         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 951
 952         if (intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state),
 953                                   DP_TP_STATUS_ACT_SENT, 1))
 954                 drm_err(&i915->drm, "Timed out waiting for ACT sent\n");
 955
 956         drm_dp_check_act_status(&intel_dp->mst_mgr);
 957 }
 958
 959 static void intel_mst_disable_dp(struct intel_atomic_state *state,
 960                                  struct intel_encoder *encoder,
 961                                  const struct intel_crtc_state *old_crtc_state,
 962                                  const struct drm_connector_state *old_conn_state)
 963 {
 964         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 965         struct intel_digital_port *dig_port = intel_mst->primary;
 966         struct intel_dp *intel_dp = &dig_port->dp;
 967         struct intel_connector *connector =
 968                 to_intel_connector(old_conn_state->connector);
 969         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 970
 971         drm_dbg_kms(&i915->drm, "active links %d\n",
 972                     intel_dp->active_mst_links);
 973
 974         if (intel_dp->active_mst_links == 1)
 975                 intel_dp->link_trained = false;
 976
 977         intel_hdcp_disable(intel_mst->connector);
 978
 979         intel_dp_sink_disable_decompression(state, connector, old_crtc_state);
 980 }
 981
 982 static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
 983                                       struct intel_encoder *encoder,
 984                                       const struct intel_crtc_state *old_crtc_state,
 985                                       const struct drm_connector_state *old_conn_state)
 986 {
 987         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 988         struct intel_digital_port *dig_port = intel_mst->primary;
 989         struct intel_dp *intel_dp = &dig_port->dp;
 990         struct intel_connector *connector =
 991                 to_intel_connector(old_conn_state->connector);
 992         struct drm_dp_mst_topology_state *old_mst_state =
 993                 drm_atomic_get_old_mst_topology_state(&state->base, &intel_dp->mst_mgr);
 994         struct drm_dp_mst_topology_state *new_mst_state =
 995                 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
 996         const struct drm_dp_mst_atomic_payload *old_payload =
 997                 drm_atomic_get_mst_payload_state(old_mst_state, connector->port);
 998         struct drm_dp_mst_atomic_payload *new_payload =
 999                 drm_atomic_get_mst_payload_state(new_mst_state, connector->port);
1000         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1001         struct intel_crtc *pipe_crtc;
1002         bool last_mst_stream;
1003
1004         intel_dp->active_mst_links--;
1005         last_mst_stream = intel_dp->active_mst_links == 0;
1006         drm_WARN_ON(&dev_priv->drm,
1007                     DISPLAY_VER(dev_priv) >= 12 && last_mst_stream &&
1008                     !intel_dp_mst_is_master_trans(old_crtc_state));
1009
1010         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc,
1011                                          intel_crtc_joined_pipe_mask(old_crtc_state)) {
1012                 const struct intel_crtc_state *old_pipe_crtc_state =
1013                         intel_atomic_get_old_crtc_state(state, pipe_crtc);
1014
1015                 intel_crtc_vblank_off(old_pipe_crtc_state);
1016         }
1017
1018         intel_disable_transcoder(old_crtc_state);
1019
1020         drm_dp_remove_payload_part1(&intel_dp->mst_mgr, new_mst_state, new_payload);
1021
1022         clear_act_sent(encoder, old_crtc_state);
1023
1024         intel_de_rmw(dev_priv,
1025                      TRANS_DDI_FUNC_CTL(dev_priv, old_crtc_state->cpu_transcoder),
1026                      TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0);
1027
1028         wait_for_act_sent(encoder, old_crtc_state);
1029
1030         drm_dp_remove_payload_part2(&intel_dp->mst_mgr, new_mst_state,
1031                                     old_payload, new_payload);
1032
1033         intel_ddi_disable_transcoder_func(old_crtc_state);
1034
1035         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc,
1036                                          intel_crtc_joined_pipe_mask(old_crtc_state)) {
1037                 const struct intel_crtc_state *old_pipe_crtc_state =
1038                         intel_atomic_get_old_crtc_state(state, pipe_crtc);
1039
1040                 intel_dsc_disable(old_pipe_crtc_state);
1041
1042                 if (DISPLAY_VER(dev_priv) >= 9)
1043                         skl_scaler_disable(old_pipe_crtc_state);
1044                 else
1045                         ilk_pfit_disable(old_pipe_crtc_state);
1046         }
1047
1048         /*
1049          * Power down mst path before disabling the port, otherwise we end
1050          * up getting interrupts from the sink upon detecting link loss.
1051          */
1052         drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port,
1053                                      false);
1054
1055         /*
1056          * BSpec 4287: disable DIP after the transcoder is disabled and before
1057          * the transcoder clock select is set to none.
1058          */
1059         intel_dp_set_infoframes(&dig_port->base, false,
1060                                 old_crtc_state, NULL);
1061         /*
1062          * From TGL spec: "If multi-stream slave transcoder: Configure
1063          * Transcoder Clock Select to direct no clock to the transcoder"
1064          *
1065          * From older GENs spec: "Configure Transcoder Clock Select to direct
1066          * no clock to the transcoder"
1067          */
1068         if (DISPLAY_VER(dev_priv) < 12 || !last_mst_stream)
1069                 intel_ddi_disable_transcoder_clock(old_crtc_state);
1070
1071
1072         intel_mst->connector = NULL;
1073         if (last_mst_stream)
1074                 dig_port->base.post_disable(state, &dig_port->base,
1075                                                   old_crtc_state, NULL);
1076
1077         drm_dbg_kms(&dev_priv->drm, "active links %d\n",
1078                     intel_dp->active_mst_links);
1079 }
1080
1081 static void intel_mst_post_pll_disable_dp(struct intel_atomic_state *state,
1082                                           struct intel_encoder *encoder,
1083                                           const struct intel_crtc_state *old_crtc_state,
1084                                           const struct drm_connector_state *old_conn_state)
1085 {
1086         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1087         struct intel_digital_port *dig_port = intel_mst->primary;
1088         struct intel_dp *intel_dp = &dig_port->dp;
1089
1090         if (intel_dp->active_mst_links == 0 &&
1091             dig_port->base.post_pll_disable)
1092                 dig_port->base.post_pll_disable(state, encoder, old_crtc_state, old_conn_state);
1093 }
1094
1095 static void intel_mst_pre_pll_enable_dp(struct intel_atomic_state *state,
1096                                         struct intel_encoder *encoder,
1097                                         const struct intel_crtc_state *pipe_config,
1098                                         const struct drm_connector_state *conn_state)
1099 {
1100         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1101         struct intel_digital_port *dig_port = intel_mst->primary;
1102         struct intel_dp *intel_dp = &dig_port->dp;
1103
1104         if (intel_dp->active_mst_links == 0)
1105                 dig_port->base.pre_pll_enable(state, &dig_port->base,
1106                                                     pipe_config, NULL);
1107         else
1108                 /*
1109                  * The port PLL state needs to get updated for secondary
1110                  * streams as for the primary stream.
1111                  */
1112                 intel_ddi_update_active_dpll(state, &dig_port->base,
1113                                              to_intel_crtc(pipe_config->uapi.crtc));
1114 }
1115
1116 static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
1117                                     struct intel_encoder *encoder,
1118                                     const struct intel_crtc_state *pipe_config,
1119                                     const struct drm_connector_state *conn_state)
1120 {
1121         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1122         struct intel_digital_port *dig_port = intel_mst->primary;
1123         struct intel_dp *intel_dp = &dig_port->dp;
1124         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1125         struct intel_connector *connector =
1126                 to_intel_connector(conn_state->connector);
1127         struct drm_dp_mst_topology_state *mst_state =
1128                 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
1129         int ret;
1130         bool first_mst_stream;
1131
1132         /* MST encoders are bound to a crtc, not to a connector,
1133          * force the mapping here for get_hw_state.
1134          */
1135         connector->encoder = encoder;
1136         intel_mst->connector = connector;
1137         first_mst_stream = intel_dp->active_mst_links == 0;
1138         drm_WARN_ON(&dev_priv->drm,
1139                     DISPLAY_VER(dev_priv) >= 12 && first_mst_stream &&
1140                     !intel_dp_mst_is_master_trans(pipe_config));
1141
1142         drm_dbg_kms(&dev_priv->drm, "active links %d\n",
1143                     intel_dp->active_mst_links);
1144
1145         if (first_mst_stream)
1146                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
1147
1148         drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
1149
1150         intel_dp_sink_enable_decompression(state, connector, pipe_config);
1151
1152         if (first_mst_stream)
1153                 dig_port->base.pre_enable(state, &dig_port->base,
1154                                                 pipe_config, NULL);
1155
1156         intel_dp->active_mst_links++;
1157
1158         ret = drm_dp_add_payload_part1(&intel_dp->mst_mgr, mst_state,
1159                                        drm_atomic_get_mst_payload_state(mst_state, connector->port));
1160         if (ret < 0)
1161                 drm_dbg_kms(&dev_priv->drm, "Failed to create MST payload for %s: %d\n",
1162                             connector->base.name, ret);
1163
1164         /*
1165          * Before Gen 12 this is not done as part of
1166          * dig_port->base.pre_enable() and should be done here. For
1167          * Gen 12+ the step in which this should be done is different for the
1168          * first MST stream, so it's done on the DDI for the first stream and
1169          * here for the following ones.
1170          */
1171         if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream)
1172                 intel_ddi_enable_transcoder_clock(encoder, pipe_config);
1173
1174         intel_dsc_dp_pps_write(&dig_port->base, pipe_config);
1175         intel_ddi_set_dp_msa(pipe_config, conn_state);
1176 }
1177
1178 static void enable_bs_jitter_was(const struct intel_crtc_state *crtc_state)
1179 {
1180         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1181         u32 clear = 0;
1182         u32 set = 0;
1183
1184         if (!IS_ALDERLAKE_P(i915))
1185                 return;
1186
1187         if (!IS_DISPLAY_STEP(i915, STEP_D0, STEP_FOREVER))
1188                 return;
1189
1190         /* Wa_14013163432:adlp */
1191         if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state))
1192                 set |= DP_MST_FEC_BS_JITTER_WA(crtc_state->cpu_transcoder);
1193
1194         /* Wa_14014143976:adlp */
1195         if (IS_DISPLAY_STEP(i915, STEP_E0, STEP_FOREVER)) {
1196                 if (intel_dp_is_uhbr(crtc_state))
1197                         set |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);
1198                 else if (crtc_state->fec_enable)
1199                         clear |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);
1200
1201                 if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state))
1202                         set |= DP_MST_DPT_DPTP_ALIGN_WA(crtc_state->cpu_transcoder);
1203         }
1204
1205         if (!clear && !set)
1206                 return;
1207
1208         intel_de_rmw(i915, CHICKEN_MISC_3, clear, set);
1209 }
1210
1211 static void intel_mst_enable_dp(struct intel_atomic_state *state,
1212                                 struct intel_encoder *encoder,
1213                                 const struct intel_crtc_state *pipe_config,
1214                                 const struct drm_connector_state *conn_state)
1215 {
1216         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1217         struct intel_digital_port *dig_port = intel_mst->primary;
1218         struct intel_dp *intel_dp = &dig_port->dp;
1219         struct intel_connector *connector = to_intel_connector(conn_state->connector);
1220         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1221         struct drm_dp_mst_topology_state *mst_state =
1222                 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
1223         enum transcoder trans = pipe_config->cpu_transcoder;
1224         bool first_mst_stream = intel_dp->active_mst_links == 1;
1225         struct intel_crtc *pipe_crtc;
1226
1227         drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
1228
1229         if (intel_dp_is_uhbr(pipe_config)) {
1230                 const struct drm_display_mode *adjusted_mode =
1231                         &pipe_config->hw.adjusted_mode;
1232                 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
1233
1234                 intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder),
1235                                TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));
1236                 intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder),
1237                                TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
1238         }
1239
1240         enable_bs_jitter_was(pipe_config);
1241
1242         intel_ddi_enable_transcoder_func(encoder, pipe_config);
1243
1244         clear_act_sent(encoder, pipe_config);
1245
1246         intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, trans), 0,
1247                      TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1248
1249         drm_dbg_kms(&dev_priv->drm, "active links %d\n",
1250                     intel_dp->active_mst_links);
1251
1252         wait_for_act_sent(encoder, pipe_config);
1253
1254         if (first_mst_stream)
1255                 intel_ddi_wait_for_fec_status(encoder, pipe_config, true);
1256
1257         drm_dp_add_payload_part2(&intel_dp->mst_mgr,
1258                                  drm_atomic_get_mst_payload_state(mst_state, connector->port));
1259
1260         if (DISPLAY_VER(dev_priv) >= 12)
1261                 intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, trans),
1262                              FECSTALL_DIS_DPTSTREAM_DPTTG,
1263                              pipe_config->fec_enable ? FECSTALL_DIS_DPTSTREAM_DPTTG : 0);
1264
1265         intel_audio_sdp_split_update(pipe_config);
1266
1267         intel_enable_transcoder(pipe_config);
1268
1269         for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
1270                                                  intel_crtc_joined_pipe_mask(pipe_config)) {
1271                 const struct intel_crtc_state *pipe_crtc_state =
1272                         intel_atomic_get_new_crtc_state(state, pipe_crtc);
1273
1274                 intel_crtc_vblank_on(pipe_crtc_state);
1275         }
1276
1277         intel_hdcp_enable(state, encoder, pipe_config, conn_state);
1278 }
1279
1280 static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder,
1281                                       enum pipe *pipe)
1282 {
1283         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1284         *pipe = intel_mst->pipe;
1285         if (intel_mst->connector)
1286                 return true;
1287         return false;
1288 }
1289
1290 static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
1291                                         struct intel_crtc_state *pipe_config)
1292 {
1293         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1294         struct intel_digital_port *dig_port = intel_mst->primary;
1295
1296         dig_port->base.get_config(&dig_port->base, pipe_config);
1297 }
1298
1299 static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,
1300                                                struct intel_crtc_state *crtc_state)
1301 {
1302         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1303         struct intel_digital_port *dig_port = intel_mst->primary;
1304
1305         return intel_dp_initial_fastset_check(&dig_port->base, crtc_state);
1306 }
1307
1308 static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector)
1309 {
1310         struct intel_connector *intel_connector = to_intel_connector(connector);
1311         struct drm_i915_private *i915 = to_i915(intel_connector->base.dev);
1312         struct intel_dp *intel_dp = intel_connector->mst_port;
1313         const struct drm_edid *drm_edid;
1314         int ret;
1315
1316         if (drm_connector_is_unregistered(connector))
1317                 return intel_connector_update_modes(connector, NULL);
1318
1319         if (!intel_display_driver_check_access(i915))
1320                 return drm_edid_connector_add_modes(connector);
1321
1322         drm_edid = drm_dp_mst_edid_read(connector, &intel_dp->mst_mgr, intel_connector->port);
1323
1324         ret = intel_connector_update_modes(connector, drm_edid);
1325
1326         drm_edid_free(drm_edid);
1327
1328         return ret;
1329 }
1330
1331 static int
1332 intel_dp_mst_connector_late_register(struct drm_connector *connector)
1333 {
1334         struct intel_connector *intel_connector = to_intel_connector(connector);
1335         int ret;
1336
1337         ret = drm_dp_mst_connector_late_register(connector,
1338                                                  intel_connector->port);
1339         if (ret < 0)
1340                 return ret;
1341
1342         ret = intel_connector_register(connector);
1343         if (ret < 0)
1344                 drm_dp_mst_connector_early_unregister(connector,
1345                                                       intel_connector->port);
1346
1347         return ret;
1348 }
1349
1350 static void
1351 intel_dp_mst_connector_early_unregister(struct drm_connector *connector)
1352 {
1353         struct intel_connector *intel_connector = to_intel_connector(connector);
1354
1355         intel_connector_unregister(connector);
1356         drm_dp_mst_connector_early_unregister(connector,
1357                                               intel_connector->port);
1358 }
1359
1360 static const struct drm_connector_funcs intel_dp_mst_connector_funcs = {
1361         .fill_modes = drm_helper_probe_single_connector_modes,
1362         .atomic_get_property = intel_digital_connector_atomic_get_property,
1363         .atomic_set_property = intel_digital_connector_atomic_set_property,
1364         .late_register = intel_dp_mst_connector_late_register,
1365         .early_unregister = intel_dp_mst_connector_early_unregister,
1366         .destroy = intel_connector_destroy,
1367         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1368         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1369 };
1370
1371 static int intel_dp_mst_get_modes(struct drm_connector *connector)
1372 {
1373         return intel_dp_mst_get_ddc_modes(connector);
1374 }
1375
1376 static int
1377 intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
1378                             struct drm_display_mode *mode,
1379                             struct drm_modeset_acquire_ctx *ctx,
1380                             enum drm_mode_status *status)
1381 {
1382         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1383         struct intel_connector *intel_connector = to_intel_connector(connector);
1384         struct intel_dp *intel_dp = intel_connector->mst_port;
1385         struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
1386         struct drm_dp_mst_port *port = intel_connector->port;
1387         const int min_bpp = 18;
1388         int max_dotclk = to_i915(connector->dev)->display.cdclk.max_dotclk_freq;
1389         int max_rate, mode_rate, max_lanes, max_link_clock;
1390         int ret;
1391         bool dsc = false, joiner = false;
1392         u16 dsc_max_compressed_bpp = 0;
1393         u8 dsc_slice_count = 0;
1394         int target_clock = mode->clock;
1395
1396         if (drm_connector_is_unregistered(connector)) {
1397                 *status = MODE_ERROR;
1398                 return 0;
1399         }
1400
1401         *status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
1402         if (*status != MODE_OK)
1403                 return 0;
1404
1405         if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1406                 *status = MODE_H_ILLEGAL;
1407                 return 0;
1408         }
1409
1410         if (mode->clock < 10000) {
1411                 *status = MODE_CLOCK_LOW;
1412                 return 0;
1413         }
1414
1415         max_link_clock = intel_dp_max_link_rate(intel_dp);
1416         max_lanes = intel_dp_max_lane_count(intel_dp);
1417
1418         max_rate = intel_dp_max_link_data_rate(intel_dp,
1419                                                max_link_clock, max_lanes);
1420         mode_rate = intel_dp_link_required(mode->clock, min_bpp);
1421
1422         /*
1423          * TODO:
1424          * - Also check if compression would allow for the mode
1425          * - Calculate the overhead using drm_dp_bw_overhead() /
1426          *   drm_dp_bw_channel_coding_efficiency(), similarly to the
1427          *   compute config code, as drm_dp_calc_pbn_mode() doesn't
1428          *   account with all the overheads.
1429          * - Check here and during compute config the BW reported by
1430          *   DFP_Link_Available_Payload_Bandwidth_Number (or the
1431          *   corresponding link capabilities of the sink) in case the
1432          *   stream is uncompressed for it by the last branch device.
1433          */
1434         if (intel_dp_need_joiner(intel_dp, intel_connector,
1435                                  mode->hdisplay, target_clock)) {
1436                 joiner = true;
1437                 max_dotclk *= 2;
1438         }
1439
1440         ret = drm_modeset_lock(&mgr->base.lock, ctx);
1441         if (ret)
1442                 return ret;
1443
1444         if (mode_rate > max_rate || mode->clock > max_dotclk ||
1445             drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) {
1446                 *status = MODE_CLOCK_HIGH;
1447                 return 0;
1448         }
1449
1450         if (intel_dp_has_dsc(intel_connector)) {
1451                 /*
1452                  * TBD pass the connector BPC,
1453                  * for now U8_MAX so that max BPC on that platform would be picked
1454                  */
1455                 int pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_connector, U8_MAX);
1456
1457                 if (drm_dp_sink_supports_fec(intel_connector->dp.fec_capability)) {
1458                         dsc_max_compressed_bpp =
1459                                 intel_dp_dsc_get_max_compressed_bpp(dev_priv,
1460                                                                     max_link_clock,
1461                                                                     max_lanes,
1462                                                                     target_clock,
1463                                                                     mode->hdisplay,
1464                                                                     joiner,
1465                                                                     INTEL_OUTPUT_FORMAT_RGB,
1466                                                                     pipe_bpp, 64);
1467                         dsc_slice_count =
1468                                 intel_dp_dsc_get_slice_count(intel_connector,
1469                                                              target_clock,
1470                                                              mode->hdisplay,
1471                                                              joiner);
1472                 }
1473
1474                 dsc = dsc_max_compressed_bpp && dsc_slice_count;
1475         }
1476
1477         if (intel_dp_joiner_needs_dsc(dev_priv, joiner) && !dsc) {
1478                 *status = MODE_CLOCK_HIGH;
1479                 return 0;
1480         }
1481
1482         if (mode_rate > max_rate && !dsc) {
1483                 *status = MODE_CLOCK_HIGH;
1484                 return 0;
1485         }
1486
1487         *status = intel_mode_valid_max_plane_size(dev_priv, mode, joiner);
1488         return 0;
1489 }
1490
1491 static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *connector,
1492                                                          struct drm_atomic_state *state)
1493 {
1494         struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
1495                                                                                          connector);
1496         struct intel_connector *intel_connector = to_intel_connector(connector);
1497         struct intel_dp *intel_dp = intel_connector->mst_port;
1498         struct intel_crtc *crtc = to_intel_crtc(connector_state->crtc);
1499
1500         return &intel_dp->mst_encoders[crtc->pipe]->base.base;
1501 }
1502
1503 static int
1504 intel_dp_mst_detect(struct drm_connector *connector,
1505                     struct drm_modeset_acquire_ctx *ctx, bool force)
1506 {
1507         struct drm_i915_private *i915 = to_i915(connector->dev);
1508         struct intel_connector *intel_connector = to_intel_connector(connector);
1509         struct intel_dp *intel_dp = intel_connector->mst_port;
1510
1511         if (!intel_display_device_enabled(i915))
1512                 return connector_status_disconnected;
1513
1514         if (drm_connector_is_unregistered(connector))
1515                 return connector_status_disconnected;
1516
1517         if (!intel_display_driver_check_access(i915))
1518                 return connector->status;
1519
1520         return drm_dp_mst_detect_port(connector, ctx, &intel_dp->mst_mgr,
1521                                       intel_connector->port);
1522 }
1523
1524 static const struct drm_connector_helper_funcs intel_dp_mst_connector_helper_funcs = {
1525         .get_modes = intel_dp_mst_get_modes,
1526         .mode_valid_ctx = intel_dp_mst_mode_valid_ctx,
1527         .atomic_best_encoder = intel_mst_atomic_best_encoder,
1528         .atomic_check = intel_dp_mst_atomic_check,
1529         .detect_ctx = intel_dp_mst_detect,
1530 };
1531
1532 static void intel_dp_mst_encoder_destroy(struct drm_encoder *encoder)
1533 {
1534         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(to_intel_encoder(encoder));
1535
1536         drm_encoder_cleanup(encoder);
1537         kfree(intel_mst);
1538 }
1539
1540 static const struct drm_encoder_funcs intel_dp_mst_enc_funcs = {
1541         .destroy = intel_dp_mst_encoder_destroy,
1542 };
1543
1544 static bool intel_dp_mst_get_hw_state(struct intel_connector *connector)
1545 {
1546         if (intel_attached_encoder(connector) && connector->base.state->crtc) {
1547                 enum pipe pipe;
1548                 if (!intel_attached_encoder(connector)->get_hw_state(intel_attached_encoder(connector), &pipe))
1549                         return false;
1550                 return true;
1551         }
1552         return false;
1553 }
1554
1555 static int intel_dp_mst_add_properties(struct intel_dp *intel_dp,
1556                                        struct drm_connector *connector,
1557                                        const char *pathprop)
1558 {
1559         struct drm_i915_private *i915 = to_i915(connector->dev);
1560
1561         drm_object_attach_property(&connector->base,
1562                                    i915->drm.mode_config.path_property, 0);
1563         drm_object_attach_property(&connector->base,
1564                                    i915->drm.mode_config.tile_property, 0);
1565
1566         intel_attach_force_audio_property(connector);
1567         intel_attach_broadcast_rgb_property(connector);
1568
1569         /*
1570          * Reuse the prop from the SST connector because we're
1571          * not allowed to create new props after device registration.
1572          */
1573         connector->max_bpc_property =
1574                 intel_dp->attached_connector->base.max_bpc_property;
1575         if (connector->max_bpc_property)
1576                 drm_connector_attach_max_bpc_property(connector, 6, 12);
1577
1578         return drm_connector_set_path_property(connector, pathprop);
1579 }
1580
1581 static void
1582 intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,
1583                                               struct intel_connector *connector)
1584 {
1585         u8 dpcd_caps[DP_RECEIVER_CAP_SIZE];
1586
1587         if (!connector->dp.dsc_decompression_aux)
1588                 return;
1589
1590         if (drm_dp_read_dpcd_caps(connector->dp.dsc_decompression_aux, dpcd_caps) < 0)
1591                 return;
1592
1593         intel_dp_get_dsc_sink_cap(dpcd_caps[DP_DPCD_REV], connector);
1594 }
1595
1596 static bool detect_dsc_hblank_expansion_quirk(const struct intel_connector *connector)
1597 {
1598         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1599         struct drm_dp_aux *aux = connector->dp.dsc_decompression_aux;
1600         struct drm_dp_desc desc;
1601         u8 dpcd[DP_RECEIVER_CAP_SIZE];
1602
1603         if (!aux)
1604                 return false;
1605
1606         /*
1607          * A logical port's OUI (at least for affected sinks) is all 0, so
1608          * instead of that the parent port's OUI is used for identification.
1609          */
1610         if (drm_dp_mst_port_is_logical(connector->port)) {
1611                 aux = drm_dp_mst_aux_for_parent(connector->port);
1612                 if (!aux)
1613                         aux = &connector->mst_port->aux;
1614         }
1615
1616         if (drm_dp_read_dpcd_caps(aux, dpcd) < 0)
1617                 return false;
1618
1619         if (drm_dp_read_desc(aux, &desc, drm_dp_is_branch(dpcd)) < 0)
1620                 return false;
1621
1622         if (!drm_dp_has_quirk(&desc,
1623                               DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC))
1624                 return false;
1625
1626         /*
1627          * UHBR (MST sink) devices requiring this quirk don't advertise the
1628          * HBLANK expansion support. Presuming that they perform HBLANK
1629          * expansion internally, or are affected by this issue on modes with a
1630          * short HBLANK for other reasons.
1631          */
1632         if (!drm_dp_128b132b_supported(dpcd) &&
1633             !(dpcd[DP_RECEIVE_PORT_0_CAP_0] & DP_HBLANK_EXPANSION_CAPABLE))
1634                 return false;
1635
1636         drm_dbg_kms(&i915->drm,
1637                     "[CONNECTOR:%d:%s] DSC HBLANK expansion quirk detected\n",
1638                     connector->base.base.id, connector->base.name);
1639
1640         return true;
1641 }
1642
1643 static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
1644                                                         struct drm_dp_mst_port *port,
1645                                                         const char *pathprop)
1646 {
1647         struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr);
1648         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1649         struct drm_device *dev = dig_port->base.base.dev;
1650         struct drm_i915_private *dev_priv = to_i915(dev);
1651         struct intel_connector *intel_connector;
1652         struct drm_connector *connector;
1653         enum pipe pipe;
1654         int ret;
1655
1656         intel_connector = intel_connector_alloc();
1657         if (!intel_connector)
1658                 return NULL;
1659
1660         intel_connector->get_hw_state = intel_dp_mst_get_hw_state;
1661         intel_connector->sync_state = intel_dp_connector_sync_state;
1662         intel_connector->mst_port = intel_dp;
1663         intel_connector->port = port;
1664         drm_dp_mst_get_port_malloc(port);
1665
1666         intel_dp_init_modeset_retry_work(intel_connector);
1667
1668         intel_connector->dp.dsc_decompression_aux = drm_dp_mst_dsc_aux_for_port(port);
1669         intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, intel_connector);
1670         intel_connector->dp.dsc_hblank_expansion_quirk =
1671                 detect_dsc_hblank_expansion_quirk(intel_connector);
1672
1673         connector = &intel_connector->base;
1674         ret = drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs,
1675                                  DRM_MODE_CONNECTOR_DisplayPort);
1676         if (ret) {
1677                 drm_dp_mst_put_port_malloc(port);
1678                 intel_connector_free(intel_connector);
1679                 return NULL;
1680         }
1681
1682         drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs);
1683
1684         for_each_pipe(dev_priv, pipe) {
1685                 struct drm_encoder *enc =
1686                         &intel_dp->mst_encoders[pipe]->base.base;
1687
1688                 ret = drm_connector_attach_encoder(&intel_connector->base, enc);
1689                 if (ret)
1690                         goto err;
1691         }
1692
1693         ret = intel_dp_mst_add_properties(intel_dp, connector, pathprop);
1694         if (ret)
1695                 goto err;
1696
1697         ret = intel_dp_hdcp_init(dig_port, intel_connector);
1698         if (ret)
1699                 drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP MST init failed, skipping.\n",
1700                             connector->name, connector->base.id);
1701
1702         return connector;
1703
1704 err:
1705         drm_connector_cleanup(connector);
1706         return NULL;
1707 }
1708
1709 static void
1710 intel_dp_mst_poll_hpd_irq(struct drm_dp_mst_topology_mgr *mgr)
1711 {
1712         struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr);
1713
1714         intel_hpd_trigger_irq(dp_to_dig_port(intel_dp));
1715 }
1716
1717 static const struct drm_dp_mst_topology_cbs mst_cbs = {
1718         .add_connector = intel_dp_add_mst_connector,
1719         .poll_hpd_irq = intel_dp_mst_poll_hpd_irq,
1720 };
1721
1722 static struct intel_dp_mst_encoder *
1723 intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe pipe)
1724 {
1725         struct intel_dp_mst_encoder *intel_mst;
1726         struct intel_encoder *intel_encoder;
1727         struct drm_device *dev = dig_port->base.base.dev;
1728
1729         intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL);
1730
1731         if (!intel_mst)
1732                 return NULL;
1733
1734         intel_mst->pipe = pipe;
1735         intel_encoder = &intel_mst->base;
1736         intel_mst->primary = dig_port;
1737
1738         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs,
1739                          DRM_MODE_ENCODER_DPMST, "DP-MST %c", pipe_name(pipe));
1740
1741         intel_encoder->type = INTEL_OUTPUT_DP_MST;
1742         intel_encoder->power_domain = dig_port->base.power_domain;
1743         intel_encoder->port = dig_port->base.port;
1744         intel_encoder->cloneable = 0;
1745         /*
1746          * This is wrong, but broken userspace uses the intersection
1747          * of possible_crtcs of all the encoders of a given connector
1748          * to figure out which crtcs can drive said connector. What
1749          * should be used instead is the union of possible_crtcs.
1750          * To keep such userspace functioning we must misconfigure
1751          * this to make sure the intersection is not empty :(
1752          */
1753         intel_encoder->pipe_mask = ~0;
1754
1755         intel_encoder->compute_config = intel_dp_mst_compute_config;
1756         intel_encoder->compute_config_late = intel_dp_mst_compute_config_late;
1757         intel_encoder->disable = intel_mst_disable_dp;
1758         intel_encoder->post_disable = intel_mst_post_disable_dp;
1759         intel_encoder->post_pll_disable = intel_mst_post_pll_disable_dp;
1760         intel_encoder->update_pipe = intel_ddi_update_pipe;
1761         intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp;
1762         intel_encoder->pre_enable = intel_mst_pre_enable_dp;
1763         intel_encoder->enable = intel_mst_enable_dp;
1764         intel_encoder->audio_enable = intel_audio_codec_enable;
1765         intel_encoder->audio_disable = intel_audio_codec_disable;
1766         intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
1767         intel_encoder->get_config = intel_dp_mst_enc_get_config;
1768         intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;
1769
1770         return intel_mst;
1771
1772 }
1773
1774 static bool
1775 intel_dp_create_fake_mst_encoders(struct intel_digital_port *dig_port)
1776 {
1777         struct intel_dp *intel_dp = &dig_port->dp;
1778         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1779         enum pipe pipe;
1780
1781         for_each_pipe(dev_priv, pipe)
1782                 intel_dp->mst_encoders[pipe] = intel_dp_create_fake_mst_encoder(dig_port, pipe);
1783         return true;
1784 }
1785
1786 int
1787 intel_dp_mst_encoder_active_links(struct intel_digital_port *dig_port)
1788 {
1789         return dig_port->dp.active_mst_links;
1790 }
1791
1792 int
1793 intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id)
1794 {
1795         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1796         struct intel_dp *intel_dp = &dig_port->dp;
1797         enum port port = dig_port->base.port;
1798         int ret;
1799
1800         if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp))
1801                 return 0;
1802
1803         if (DISPLAY_VER(i915) < 12 && port == PORT_A)
1804                 return 0;
1805
1806         if (DISPLAY_VER(i915) < 11 && port == PORT_E)
1807                 return 0;
1808
1809         intel_dp->mst_mgr.cbs = &mst_cbs;
1810
1811         /* create encoders */
1812         intel_dp_create_fake_mst_encoders(dig_port);
1813         ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm,
1814                                            &intel_dp->aux, 16, 3, conn_base_id);
1815         if (ret) {
1816                 intel_dp->mst_mgr.cbs = NULL;
1817                 return ret;
1818         }
1819
1820         return 0;
1821 }
1822
1823 bool intel_dp_mst_source_support(struct intel_dp *intel_dp)
1824 {
1825         return intel_dp->mst_mgr.cbs;
1826 }
1827
1828 void
1829 intel_dp_mst_encoder_cleanup(struct intel_digital_port *dig_port)
1830 {
1831         struct intel_dp *intel_dp = &dig_port->dp;
1832
1833         if (!intel_dp_mst_source_support(intel_dp))
1834                 return;
1835
1836         drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr);
1837         /* encoders will get killed by normal cleanup */
1838
1839         intel_dp->mst_mgr.cbs = NULL;
1840 }
1841
1842 bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state)
1843 {
1844         return crtc_state->mst_master_transcoder == crtc_state->cpu_transcoder;
1845 }
1846
1847 bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state)
1848 {
1849         return crtc_state->mst_master_transcoder != INVALID_TRANSCODER &&
1850                crtc_state->mst_master_transcoder != crtc_state->cpu_transcoder;
1851 }
1852
1853 /**
1854  * intel_dp_mst_add_topology_state_for_connector - add MST topology state for a connector
1855  * @state: atomic state
1856  * @connector: connector to add the state for
1857  * @crtc: the CRTC @connector is attached to
1858  *
1859  * Add the MST topology state for @connector to @state.
1860  *
1861  * Returns 0 on success, negative error code on failure.
1862  */
1863 static int
1864 intel_dp_mst_add_topology_state_for_connector(struct intel_atomic_state *state,
1865                                               struct intel_connector *connector,
1866                                               struct intel_crtc *crtc)
1867 {
1868         struct drm_dp_mst_topology_state *mst_state;
1869
1870         if (!connector->mst_port)
1871                 return 0;
1872
1873         mst_state = drm_atomic_get_mst_topology_state(&state->base,
1874                                                       &connector->mst_port->mst_mgr);
1875         if (IS_ERR(mst_state))
1876                 return PTR_ERR(mst_state);
1877
1878         mst_state->pending_crtc_mask |= drm_crtc_mask(&crtc->base);
1879
1880         return 0;
1881 }
1882
1883 /**
1884  * intel_dp_mst_add_topology_state_for_crtc - add MST topology state for a CRTC
1885  * @state: atomic state
1886  * @crtc: CRTC to add the state for
1887  *
1888  * Add the MST topology state for @crtc to @state.
1889  *
1890  * Returns 0 on success, negative error code on failure.
1891  */
1892 int intel_dp_mst_add_topology_state_for_crtc(struct intel_atomic_state *state,
1893                                              struct intel_crtc *crtc)
1894 {
1895         struct drm_connector *_connector;
1896         struct drm_connector_state *conn_state;
1897         int i;
1898
1899         for_each_new_connector_in_state(&state->base, _connector, conn_state, i) {
1900                 struct intel_connector *connector = to_intel_connector(_connector);
1901                 int ret;
1902
1903                 if (conn_state->crtc != &crtc->base)
1904                         continue;
1905
1906                 ret = intel_dp_mst_add_topology_state_for_connector(state, connector, crtc);
1907                 if (ret)
1908                         return ret;
1909         }
1910
1911         return 0;
1912 }
1913
1914 static struct intel_connector *
1915 get_connector_in_state_for_crtc(struct intel_atomic_state *state,
1916                                 const struct intel_crtc *crtc)
1917 {
1918         struct drm_connector_state *old_conn_state;
1919         struct drm_connector_state *new_conn_state;
1920         struct drm_connector *_connector;
1921         int i;
1922
1923         for_each_oldnew_connector_in_state(&state->base, _connector,
1924                                            old_conn_state, new_conn_state, i) {
1925                 struct intel_connector *connector =
1926                         to_intel_connector(_connector);
1927
1928                 if (old_conn_state->crtc == &crtc->base ||
1929                     new_conn_state->crtc == &crtc->base)
1930                         return connector;
1931         }
1932
1933         return NULL;
1934 }
1935
1936 /**
1937  * intel_dp_mst_crtc_needs_modeset - check if changes in topology need to modeset the given CRTC
1938  * @state: atomic state
1939  * @crtc: CRTC for which to check the modeset requirement
1940  *
1941  * Check if any change in a MST topology requires a forced modeset on @crtc in
1942  * this topology. One such change is enabling/disabling the DSC decompression
1943  * state in the first branch device's UFP DPCD as required by one CRTC, while
1944  * the other @crtc in the same topology is still active, requiring a full modeset
1945  * on @crtc.
1946  */
1947 bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state,
1948                                      struct intel_crtc *crtc)
1949 {
1950         const struct intel_connector *crtc_connector;
1951         const struct drm_connector_state *conn_state;
1952         const struct drm_connector *_connector;
1953         int i;
1954
1955         if (!intel_crtc_has_type(intel_atomic_get_new_crtc_state(state, crtc),
1956                                  INTEL_OUTPUT_DP_MST))
1957                 return false;
1958
1959         crtc_connector = get_connector_in_state_for_crtc(state, crtc);
1960
1961         if (!crtc_connector)
1962                 /* None of the connectors in the topology needs modeset */
1963                 return false;
1964
1965         for_each_new_connector_in_state(&state->base, _connector, conn_state, i) {
1966                 const struct intel_connector *connector =
1967                         to_intel_connector(_connector);
1968                 const struct intel_crtc_state *new_crtc_state;
1969                 const struct intel_crtc_state *old_crtc_state;
1970                 struct intel_crtc *crtc_iter;
1971
1972                 if (connector->mst_port != crtc_connector->mst_port ||
1973                     !conn_state->crtc)
1974                         continue;
1975
1976                 crtc_iter = to_intel_crtc(conn_state->crtc);
1977
1978                 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc_iter);
1979                 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc_iter);
1980
1981                 if (!intel_crtc_needs_modeset(new_crtc_state))
1982                         continue;
1983
1984                 if (old_crtc_state->dsc.compression_enable ==
1985                     new_crtc_state->dsc.compression_enable)
1986                         continue;
1987                 /*
1988                  * Toggling the decompression flag because of this stream in
1989                  * the first downstream branch device's UFP DPCD may reset the
1990                  * whole branch device. To avoid the reset while other streams
1991                  * are also active modeset the whole MST topology in this
1992                  * case.
1993                  */
1994                 if (connector->dp.dsc_decompression_aux ==
1995                     &connector->mst_port->aux)
1996                         return true;
1997         }
1998
1999         return false;
2000 }