Documentation/devicetree/bindings/iio/adc/atmel,sama5d2-adc.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/iio/adc/atmel,sama5d2-adc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: AT91 SAMA5D2 Analog to Digital Converter (ADC)
   8
   9 maintainers:
  10   - Ludovic Desroches <[email protected]>
  11   - Eugen Hristev <[email protected]>
  12
  13 properties:
  14   compatible:
  15     enum:
  16       - atmel,sama5d2-adc
  17       - microchip,sam9x60-adc
  18       - microchip,sama7g5-adc
  19
  20   reg:
  21     maxItems: 1
  22
  23   interrupts:
  24     maxItems: 1
  25
  26   clocks:
  27     maxItems: 1
  28
  29   clock-names:
  30     const: adc_clk
  31
  32   vref-supply: true
  33   vddana-supply: true
  34
  35   atmel,min-sample-rate-hz:
  36     description: Minimum sampling rate, it depends on SoC.
  37
  38   atmel,max-sample-rate-hz:
  39     description: Maximum sampling rate, it depends on SoC.
  40
  41   atmel,startup-time-ms:
  42     description: Startup time expressed in ms, it depends on SoC.
  43
  44   atmel,trigger-edge-type:
  45     $ref: '/schemas/types.yaml#/definitions/uint32'
  46     description:
  47       One of possible edge types for the ADTRG hardware trigger pin.
  48       When the specific edge type is detected, the conversion will
  49       start. Should be one of IRQ_TYPE_EDGE_RISING, IRQ_TYPE_EDGE_FALLING
  50       or IRQ_TYPE_EDGE_BOTH.
  51     enum: [1, 2, 3]
  52
  53   dmas:
  54     maxItems: 1
  55
  56   dma-names:
  57     const: rx
  58
  59   "#io-channel-cells":
  60     const: 1
  61
  62 additionalProperties: false
  63
  64 required:
  65   - compatible
  66   - reg
  67   - interrupts
  68   - clocks
  69   - clock-names
  70   - vref-supply
  71   - vddana-supply
  72   - atmel,min-sample-rate-hz
  73   - atmel,max-sample-rate-hz
  74   - atmel,startup-time-ms
  75   - atmel,trigger-edge-type
  76
  77 examples:
  78   - |
  79     #include <dt-bindings/dma/at91.h>
  80     #include <dt-bindings/interrupt-controller/irq.h>
  81     soc {
  82         #address-cells = <1>;
  83         #size-cells = <1>;
  84
  85         adc@fc030000 {
  86             compatible = "atmel,sama5d2-adc";
  87             reg = <0xfc030000 0x100>;
  88             interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
  89             clocks = <&adc_clk>;
  90             clock-names = "adc_clk";
  91             atmel,min-sample-rate-hz = <200000>;
  92             atmel,max-sample-rate-hz = <20000000>;
  93             atmel,startup-time-ms = <4>;
  94             vddana-supply = <&vdd_3v3_lp_reg>;
  95             vref-supply = <&vdd_3v3_lp_reg>;
  96             atmel,trigger-edge-type = <IRQ_TYPE_EDGE_BOTH>;
  97             dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
  98             dma-names = "rx";
  99             #io-channel-cells = <1>;
 100         };
 101     };
 102 ...