arch/mips/kernel/smp-bmips.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2011 by Kevin Cernekee ([email protected])
   7  *
   8  * SMP support for BMIPS
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/sched.h>
  13 #include <linux/sched/hotplug.h>
  14 #include <linux/sched/task_stack.h>
  15 #include <linux/mm.h>
  16 #include <linux/delay.h>
  17 #include <linux/smp.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/cpu.h>
  21 #include <linux/cpumask.h>
  22 #include <linux/reboot.h>
  23 #include <linux/io.h>
  24 #include <linux/compiler.h>
  25 #include <linux/linkage.h>
  26 #include <linux/bug.h>
  27 #include <linux/kernel.h>
  28 #include <linux/kexec.h>
  29
  30 #include <asm/time.h>
  31 #include <asm/processor.h>
  32 #include <asm/bootinfo.h>
  33 #include <asm/cacheflush.h>
  34 #include <asm/tlbflush.h>
  35 #include <asm/mipsregs.h>
  36 #include <asm/bmips.h>
  37 #include <asm/traps.h>
  38 #include <asm/barrier.h>
  39 #include <asm/cpu-features.h>
  40
  41 static int __maybe_unused max_cpus = 1;
  42
  43 /* these may be configured by the platform code */
  44 int bmips_smp_enabled = 1;
  45 int bmips_cpu_offset;
  46 cpumask_t bmips_booted_mask;
  47 unsigned long bmips_tp1_irqs = IE_IRQ1;
  48
  49 #define RESET_FROM_KSEG0                0x80080800
  50 #define RESET_FROM_KSEG1                0xa0080800
  51
  52 static void bmips_set_reset_vec(int cpu, u32 val);
  53
  54 #ifdef CONFIG_SMP
  55
  56 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
  57 unsigned long bmips_smp_boot_sp;
  58 unsigned long bmips_smp_boot_gp;
  59
  60 static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
  61 static void bmips5000_send_ipi_single(int cpu, unsigned int action);
  62 static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id);
  63 static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id);
  64
  65 /* SW interrupts 0,1 are used for interprocessor signaling */
  66 #define IPI0_IRQ                        (MIPS_CPU_IRQ_BASE + 0)
  67 #define IPI1_IRQ                        (MIPS_CPU_IRQ_BASE + 1)
  68
  69 #define CPUNUM(cpu, shift)              (((cpu) + bmips_cpu_offset) << (shift))
  70 #define ACTION_CLR_IPI(cpu, ipi)        (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
  71 #define ACTION_SET_IPI(cpu, ipi)        (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
  72 #define ACTION_BOOT_THREAD(cpu)         (0x08 | CPUNUM(cpu, 0))
  73
  74 static void __init bmips_smp_setup(void)
  75 {
  76         int i, cpu = 1, boot_cpu = 0;
  77         int cpu_hw_intr;
  78
  79         switch (current_cpu_type()) {
  80         case CPU_BMIPS4350:
  81         case CPU_BMIPS4380:
  82                 /* arbitration priority */
  83                 clear_c0_brcm_cmt_ctrl(0x30);
  84
  85                 /* NBK and weak order flags */
  86                 set_c0_brcm_config_0(0x30000);
  87
  88                 /* Find out if we are running on TP0 or TP1 */
  89                 boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
  90
  91                 /*
  92                  * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other
  93                  * thread
  94                  * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
  95                  * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
  96                  */
  97                 if (boot_cpu == 0)
  98                         cpu_hw_intr = 0x02;
  99                 else
 100                         cpu_hw_intr = 0x1d;
 101
 102                 change_c0_brcm_cmt_intr(0xf8018000,
 103                                         (cpu_hw_intr << 27) | (0x03 << 15));
 104
 105                 /* single core, 2 threads (2 pipelines) */
 106                 max_cpus = 2;
 107
 108                 break;
 109         case CPU_BMIPS5000:
 110                 /* enable raceless SW interrupts */
 111                 set_c0_brcm_config(0x03 << 22);
 112
 113                 /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
 114                 change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
 115
 116                 /* N cores, 2 threads per core */
 117                 max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
 118
 119                 /* clear any pending SW interrupts */
 120                 for (i = 0; i < max_cpus; i++) {
 121                         write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
 122                         write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
 123                 }
 124
 125                 break;
 126         default:
 127                 max_cpus = 1;
 128         }
 129
 130         if (!bmips_smp_enabled)
 131                 max_cpus = 1;
 132
 133         /* this can be overridden by the BSP */
 134         if (!board_ebase_setup)
 135                 board_ebase_setup = &bmips_ebase_setup;
 136
 137         __cpu_number_map[boot_cpu] = 0;
 138         __cpu_logical_map[0] = boot_cpu;
 139
 140         for (i = 0; i < max_cpus; i++) {
 141                 if (i != boot_cpu) {
 142                         __cpu_number_map[i] = cpu;
 143                         __cpu_logical_map[cpu] = i;
 144                         cpu++;
 145                 }
 146                 set_cpu_possible(i, 1);
 147                 set_cpu_present(i, 1);
 148         }
 149 }
 150
 151 /*
 152  * IPI IRQ setup - runs on CPU0
 153  */
 154 static void bmips_prepare_cpus(unsigned int max_cpus)
 155 {
 156         irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id);
 157
 158         switch (current_cpu_type()) {
 159         case CPU_BMIPS4350:
 160         case CPU_BMIPS4380:
 161                 bmips_ipi_interrupt = bmips43xx_ipi_interrupt;
 162                 break;
 163         case CPU_BMIPS5000:
 164                 bmips_ipi_interrupt = bmips5000_ipi_interrupt;
 165                 break;
 166         default:
 167                 return;
 168         }
 169
 170         if (request_irq(IPI0_IRQ, bmips_ipi_interrupt,
 171                         IRQF_PERCPU | IRQF_NO_SUSPEND, "smp_ipi0", NULL))
 172                 panic("Can't request IPI0 interrupt");
 173         if (request_irq(IPI1_IRQ, bmips_ipi_interrupt,
 174                         IRQF_PERCPU | IRQF_NO_SUSPEND, "smp_ipi1", NULL))
 175                 panic("Can't request IPI1 interrupt");
 176 }
 177
 178 /*
 179  * Tell the hardware to boot CPUx - runs on CPU0
 180  */
 181 static int bmips_boot_secondary(int cpu, struct task_struct *idle)
 182 {
 183         bmips_smp_boot_sp = __KSTK_TOS(idle);
 184         bmips_smp_boot_gp = (unsigned long)task_thread_info(idle);
 185         mb();
 186
 187         /*
 188          * Initial boot sequence for secondary CPU:
 189          *   bmips_reset_nmi_vec @ a000_0000 ->
 190          *   bmips_smp_entry ->
 191          *   plat_wired_tlb_setup (cached function call; optional) ->
 192          *   start_secondary (cached jump)
 193          *
 194          * Warm restart sequence:
 195          *   play_dead WAIT loop ->
 196          *   bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->
 197          *   eret to play_dead ->
 198          *   bmips_secondary_reentry ->
 199          *   start_secondary
 200          */
 201
 202         pr_info("SMP: Booting CPU%d...\n", cpu);
 203
 204         if (cpumask_test_cpu(cpu, &bmips_booted_mask)) {
 205                 /* kseg1 might not exist if this CPU enabled XKS01 */
 206                 bmips_set_reset_vec(cpu, RESET_FROM_KSEG0);
 207
 208                 switch (current_cpu_type()) {
 209                 case CPU_BMIPS4350:
 210                 case CPU_BMIPS4380:
 211                         bmips43xx_send_ipi_single(cpu, 0);
 212                         break;
 213                 case CPU_BMIPS5000:
 214                         bmips5000_send_ipi_single(cpu, 0);
 215                         break;
 216                 }
 217         } else {
 218                 bmips_set_reset_vec(cpu, RESET_FROM_KSEG1);
 219
 220                 switch (current_cpu_type()) {
 221                 case CPU_BMIPS4350:
 222                 case CPU_BMIPS4380:
 223                         /* Reset slave TP1 if booting from TP0 */
 224                         if (cpu_logical_map(cpu) == 1)
 225                                 set_c0_brcm_cmt_ctrl(0x01);
 226                         break;
 227                 case CPU_BMIPS5000:
 228                         write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
 229                         break;
 230                 }
 231                 cpumask_set_cpu(cpu, &bmips_booted_mask);
 232         }
 233
 234         return 0;
 235 }
 236
 237 /*
 238  * Early setup - runs on secondary CPU after cache probe
 239  */
 240 static void bmips_init_secondary(void)
 241 {
 242         switch (current_cpu_type()) {
 243         case CPU_BMIPS4350:
 244         case CPU_BMIPS4380:
 245                 clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
 246                 break;
 247         case CPU_BMIPS5000:
 248                 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
 249                 cpu_set_core(&current_cpu_data, (read_c0_brcm_config() >> 25) & 3);
 250                 break;
 251         }
 252 }
 253
 254 /*
 255  * Late setup - runs on secondary CPU before entering the idle loop
 256  */
 257 static void bmips_smp_finish(void)
 258 {
 259         pr_info("SMP: CPU%d is running\n", smp_processor_id());
 260
 261         /* make sure there won't be a timer interrupt for a little while */
 262         write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
 263
 264         irq_enable_hazard();
 265         set_c0_status(IE_SW0 | IE_SW1 | bmips_tp1_irqs | IE_IRQ5 | ST0_IE);
 266         irq_enable_hazard();
 267 }
 268
 269 /*
 270  * BMIPS5000 raceless IPIs
 271  *
 272  * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
 273  * IPI0 is used for SMP_RESCHEDULE_YOURSELF
 274  * IPI1 is used for SMP_CALL_FUNCTION
 275  */
 276
 277 static void bmips5000_send_ipi_single(int cpu, unsigned int action)
 278 {
 279         write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
 280 }
 281
 282 static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id)
 283 {
 284         int action = irq - IPI0_IRQ;
 285
 286         write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action));
 287
 288         if (action == 0)
 289                 scheduler_ipi();
 290         else
 291                 generic_smp_call_function_interrupt();
 292
 293         return IRQ_HANDLED;
 294 }
 295
 296 static void bmips5000_send_ipi_mask(const struct cpumask *mask,
 297         unsigned int action)
 298 {
 299         unsigned int i;
 300
 301         for_each_cpu(i, mask)
 302                 bmips5000_send_ipi_single(i, action);
 303 }
 304
 305 /*
 306  * BMIPS43xx racey IPIs
 307  *
 308  * We use one inbound SW IRQ for each CPU.
 309  *
 310  * A spinlock must be held in order to keep CPUx from accidentally clearing
 311  * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy.  The
 312  * same spinlock is used to protect the action masks.
 313  */
 314
 315 static DEFINE_SPINLOCK(ipi_lock);
 316 static DEFINE_PER_CPU(int, ipi_action_mask);
 317
 318 static void bmips43xx_send_ipi_single(int cpu, unsigned int action)
 319 {
 320         unsigned long flags;
 321
 322         spin_lock_irqsave(&ipi_lock, flags);
 323         set_c0_cause(cpu ? C_SW1 : C_SW0);
 324         per_cpu(ipi_action_mask, cpu) |= action;
 325         irq_enable_hazard();
 326         spin_unlock_irqrestore(&ipi_lock, flags);
 327 }
 328
 329 static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id)
 330 {
 331         unsigned long flags;
 332         int action, cpu = irq - IPI0_IRQ;
 333
 334         spin_lock_irqsave(&ipi_lock, flags);
 335         action = __this_cpu_read(ipi_action_mask);
 336         per_cpu(ipi_action_mask, cpu) = 0;
 337         clear_c0_cause(cpu ? C_SW1 : C_SW0);
 338         spin_unlock_irqrestore(&ipi_lock, flags);
 339
 340         if (action & SMP_RESCHEDULE_YOURSELF)
 341                 scheduler_ipi();
 342         if (action & SMP_CALL_FUNCTION)
 343                 generic_smp_call_function_interrupt();
 344
 345         return IRQ_HANDLED;
 346 }
 347
 348 static void bmips43xx_send_ipi_mask(const struct cpumask *mask,
 349         unsigned int action)
 350 {
 351         unsigned int i;
 352
 353         for_each_cpu(i, mask)
 354                 bmips43xx_send_ipi_single(i, action);
 355 }
 356
 357 #ifdef CONFIG_HOTPLUG_CPU
 358
 359 static int bmips_cpu_disable(void)
 360 {
 361         unsigned int cpu = smp_processor_id();
 362
 363         if (cpu == 0)
 364                 return -EBUSY;
 365
 366         pr_info("SMP: CPU%d is offline\n", cpu);
 367
 368         set_cpu_online(cpu, false);
 369         calculate_cpu_foreign_map();
 370         irq_cpu_offline();
 371         clear_c0_status(IE_IRQ5);
 372
 373         local_flush_tlb_all();
 374         local_flush_icache_range(0, ~0);
 375
 376         return 0;
 377 }
 378
 379 static void bmips_cpu_die(unsigned int cpu)
 380 {
 381 }
 382
 383 void __ref play_dead(void)
 384 {
 385         idle_task_exit();
 386
 387         /* flush data cache */
 388         _dma_cache_wback_inv(0, ~0);
 389
 390         /*
 391          * Wakeup is on SW0 or SW1; disable everything else
 392          * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux
 393          * IRQ handlers; this clears ST0_IE and returns immediately.
 394          */
 395         clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1);
 396         change_c0_status(
 397                 IE_IRQ5 | bmips_tp1_irqs | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
 398                 IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV);
 399         irq_disable_hazard();
 400
 401         /*
 402          * wait for SW interrupt from bmips_boot_secondary(), then jump
 403          * back to start_secondary()
 404          */
 405         __asm__ __volatile__(
 406         "       wait\n"
 407         "       j       bmips_secondary_reentry\n"
 408         : : : "memory");
 409 }
 410
 411 #endif /* CONFIG_HOTPLUG_CPU */
 412
 413 const struct plat_smp_ops bmips43xx_smp_ops = {
 414         .smp_setup              = bmips_smp_setup,
 415         .prepare_cpus           = bmips_prepare_cpus,
 416         .boot_secondary         = bmips_boot_secondary,
 417         .smp_finish             = bmips_smp_finish,
 418         .init_secondary         = bmips_init_secondary,
 419         .send_ipi_single        = bmips43xx_send_ipi_single,
 420         .send_ipi_mask          = bmips43xx_send_ipi_mask,
 421 #ifdef CONFIG_HOTPLUG_CPU
 422         .cpu_disable            = bmips_cpu_disable,
 423         .cpu_die                = bmips_cpu_die,
 424 #endif
 425 #ifdef CONFIG_KEXEC
 426         .kexec_nonboot_cpu      = kexec_nonboot_cpu_jump,
 427 #endif
 428 };
 429
 430 const struct plat_smp_ops bmips5000_smp_ops = {
 431         .smp_setup              = bmips_smp_setup,
 432         .prepare_cpus           = bmips_prepare_cpus,
 433         .boot_secondary         = bmips_boot_secondary,
 434         .smp_finish             = bmips_smp_finish,
 435         .init_secondary         = bmips_init_secondary,
 436         .send_ipi_single        = bmips5000_send_ipi_single,
 437         .send_ipi_mask          = bmips5000_send_ipi_mask,
 438 #ifdef CONFIG_HOTPLUG_CPU
 439         .cpu_disable            = bmips_cpu_disable,
 440         .cpu_die                = bmips_cpu_die,
 441 #endif
 442 #ifdef CONFIG_KEXEC
 443         .kexec_nonboot_cpu      = kexec_nonboot_cpu_jump,
 444 #endif
 445 };
 446
 447 #endif /* CONFIG_SMP */
 448
 449 /***********************************************************************
 450  * BMIPS vector relocation
 451  * This is primarily used for SMP boot, but it is applicable to some
 452  * UP BMIPS systems as well.
 453  ***********************************************************************/
 454
 455 static void bmips_wr_vec(unsigned long dst, char *start, char *end)
 456 {
 457         memcpy((void *)dst, start, end - start);
 458         dma_cache_wback(dst, end - start);
 459         local_flush_icache_range(dst, dst + (end - start));
 460         instruction_hazard();
 461 }
 462
 463 static inline void bmips_nmi_handler_setup(void)
 464 {
 465         bmips_wr_vec(BMIPS_NMI_RESET_VEC, bmips_reset_nmi_vec,
 466                 bmips_reset_nmi_vec_end);
 467         bmips_wr_vec(BMIPS_WARM_RESTART_VEC, bmips_smp_int_vec,
 468                 bmips_smp_int_vec_end);
 469 }
 470
 471 struct reset_vec_info {
 472         int cpu;
 473         u32 val;
 474 };
 475
 476 static void bmips_set_reset_vec_remote(void *vinfo)
 477 {
 478         struct reset_vec_info *info = vinfo;
 479         int shift = info->cpu & 0x01 ? 16 : 0;
 480         u32 mask = ~(0xffff << shift), val = info->val >> 16;
 481
 482         preempt_disable();
 483         if (smp_processor_id() > 0) {
 484                 smp_call_function_single(0, &bmips_set_reset_vec_remote,
 485                                          info, 1);
 486         } else {
 487                 if (info->cpu & 0x02) {
 488                         /* BMIPS5200 "should" use mask/shift, but it's buggy */
 489                         bmips_write_zscm_reg(0xa0, (val << 16) | val);
 490                         bmips_read_zscm_reg(0xa0);
 491                 } else {
 492                         write_c0_brcm_bootvec((read_c0_brcm_bootvec() & mask) |
 493                                               (val << shift));
 494                 }
 495         }
 496         preempt_enable();
 497 }
 498
 499 static void bmips_set_reset_vec(int cpu, u32 val)
 500 {
 501         struct reset_vec_info info;
 502
 503         if (current_cpu_type() == CPU_BMIPS5000) {
 504                 /* this needs to run from CPU0 (which is always online) */
 505                 info.cpu = cpu;
 506                 info.val = val;
 507                 bmips_set_reset_vec_remote(&info);
 508         } else {
 509                 void __iomem *cbr = BMIPS_GET_CBR();
 510
 511                 if (cpu == 0)
 512                         __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
 513                 else {
 514                         if (current_cpu_type() != CPU_BMIPS4380)
 515                                 return;
 516                         __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
 517                 }
 518         }
 519         __sync();
 520         back_to_back_c0_hazard();
 521 }
 522
 523 void bmips_ebase_setup(void)
 524 {
 525         unsigned long new_ebase = ebase;
 526
 527         BUG_ON(ebase != CKSEG0);
 528
 529         switch (current_cpu_type()) {
 530         case CPU_BMIPS4350:
 531                 /*
 532                  * BMIPS4350 cannot relocate the normal vectors, but it
 533                  * can relocate the BEV=1 vectors.  So CPU1 starts up at
 534                  * the relocated BEV=1, IV=0 general exception vector @
 535                  * 0xa000_0380.
 536                  *
 537                  * set_uncached_handler() is used here because:
 538                  *  - CPU1 will run this from uncached space
 539                  *  - None of the cacheflush functions are set up yet
 540                  */
 541                 set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
 542                         &bmips_smp_int_vec, 0x80);
 543                 __sync();
 544                 return;
 545         case CPU_BMIPS3300:
 546         case CPU_BMIPS4380:
 547                 /*
 548                  * 0x8000_0000: reset/NMI (initially in kseg1)
 549                  * 0x8000_0400: normal vectors
 550                  */
 551                 new_ebase = 0x80000400;
 552                 bmips_set_reset_vec(0, RESET_FROM_KSEG0);
 553                 break;
 554         case CPU_BMIPS5000:
 555                 /*
 556                  * 0x8000_0000: reset/NMI (initially in kseg1)
 557                  * 0x8000_1000: normal vectors
 558                  */
 559                 new_ebase = 0x80001000;
 560                 bmips_set_reset_vec(0, RESET_FROM_KSEG0);
 561                 write_c0_ebase(new_ebase);
 562                 break;
 563         default:
 564                 return;
 565         }
 566
 567         board_nmi_handler_setup = &bmips_nmi_handler_setup;
 568         ebase = new_ebase;
 569 }
 570
 571 asmlinkage void __weak plat_wired_tlb_setup(void)
 572 {
 573         /*
 574          * Called when starting/restarting a secondary CPU.
 575          * Kernel stacks and other important data might only be accessible
 576          * once the wired entries are present.
 577          */
 578 }
 579
 580 void bmips_cpu_setup(void)
 581 {
 582         void __iomem __maybe_unused *cbr = BMIPS_GET_CBR();
 583         u32 __maybe_unused cfg;
 584
 585         switch (current_cpu_type()) {
 586         case CPU_BMIPS3300:
 587                 /* Set BIU to async mode */
 588                 set_c0_brcm_bus_pll(BIT(22));
 589                 __sync();
 590
 591                 /* put the BIU back in sync mode */
 592                 clear_c0_brcm_bus_pll(BIT(22));
 593
 594                 /* clear BHTD to enable branch history table */
 595                 clear_c0_brcm_reset(BIT(16));
 596
 597                 /* Flush and enable RAC */
 598                 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
 599                 __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
 600                 __raw_readl(cbr + BMIPS_RAC_CONFIG);
 601
 602                 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
 603                 __raw_writel(cfg | 0xf, cbr + BMIPS_RAC_CONFIG);
 604                 __raw_readl(cbr + BMIPS_RAC_CONFIG);
 605
 606                 cfg = __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
 607                 __raw_writel(cfg | 0x0fff0000, cbr + BMIPS_RAC_ADDRESS_RANGE);
 608                 __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
 609                 break;
 610
 611         case CPU_BMIPS4380:
 612                 /* CBG workaround for early BMIPS4380 CPUs */
 613                 switch (read_c0_prid()) {
 614                 case 0x2a040:
 615                 case 0x2a042:
 616                 case 0x2a044:
 617                 case 0x2a060:
 618                         cfg = __raw_readl(cbr + BMIPS_L2_CONFIG);
 619                         __raw_writel(cfg & ~0x07000000, cbr + BMIPS_L2_CONFIG);
 620                         __raw_readl(cbr + BMIPS_L2_CONFIG);
 621                 }
 622
 623                 /* clear BHTD to enable branch history table */
 624                 clear_c0_brcm_config_0(BIT(21));
 625
 626                 /* XI/ROTR enable */
 627                 set_c0_brcm_config_0(BIT(23));
 628                 set_c0_brcm_cmt_ctrl(BIT(15));
 629                 break;
 630
 631         case CPU_BMIPS5000:
 632                 /* enable RDHWR, BRDHWR */
 633                 set_c0_brcm_config(BIT(17) | BIT(21));
 634
 635                 /* Disable JTB */
 636                 __asm__ __volatile__(
 637                 "       .set    noreorder\n"
 638                 "       li      $8, 0x5a455048\n"
 639                 "       .word   0x4088b00f\n"   /* mtc0 t0, $22, 15 */
 640                 "       .word   0x4008b008\n"   /* mfc0 t0, $22, 8 */
 641                 "       li      $9, 0x00008000\n"
 642                 "       or      $8, $8, $9\n"
 643                 "       .word   0x4088b008\n"   /* mtc0 t0, $22, 8 */
 644                 "       sync\n"
 645                 "       li      $8, 0x0\n"
 646                 "       .word   0x4088b00f\n"   /* mtc0 t0, $22, 15 */
 647                 "       .set    reorder\n"
 648                 : : : "$8", "$9");
 649
 650                 /* XI enable */
 651                 set_c0_brcm_config(BIT(27));
 652
 653                 /* enable MIPS32R2 ROR instruction for XI TLB handlers */
 654                 __asm__ __volatile__(
 655                 "       li      $8, 0x5a455048\n"
 656                 "       .word   0x4088b00f\n"   /* mtc0 $8, $22, 15 */
 657                 "       nop; nop; nop\n"
 658                 "       .word   0x4008b008\n"   /* mfc0 $8, $22, 8 */
 659                 "       lui     $9, 0x0100\n"
 660                 "       or      $8, $9\n"
 661                 "       .word   0x4088b008\n"   /* mtc0 $8, $22, 8 */
 662                 : : : "$8", "$9");
 663                 break;
 664         }
 665 }