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1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/kthread.h>
29 #include <linux/console.h>
30 #include <linux/slab.h>
31 #include <linux/debugfs.h>
32 #include <drm/drmP.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/amdgpu_drm.h>
36 #include <linux/vgaarb.h>
37 #include <linux/vga_switcheroo.h>
38 #include <linux/efi.h>
39 #include "amdgpu.h"
40 #include "amdgpu_trace.h"
41 #include "amdgpu_i2c.h"
42 #include "atom.h"
43 #include "amdgpu_atombios.h"
44 #include "amdgpu_atomfirmware.h"
45 #include "amd_pcie.h"
46 #ifdef CONFIG_DRM_AMDGPU_SI
47 #include "si.h"
48 #endif
49 #ifdef CONFIG_DRM_AMDGPU_CIK
50 #include "cik.h"
51 #endif
52 #include "vi.h"
53 #include "soc15.h"
54 #include "bif/bif_4_1_d.h"
55 #include <linux/pci.h>
56 #include <linux/firmware.h>
57 #include "amdgpu_vf_error.h"
58
59 #include "amdgpu_amdkfd.h"
60 #include "amdgpu_pm.h"
61
62 MODULE_FIRMWARE("amdgpu/vega10_gpu_info.bin");
63 MODULE_FIRMWARE("amdgpu/raven_gpu_info.bin");
64
65 #define AMDGPU_RESUME_MS                2000
66
67 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev);
68 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev);
69 static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev);
70 static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev);
71
72 static const char *amdgpu_asic_name[] = {
73         "TAHITI",
74         "PITCAIRN",
75         "VERDE",
76         "OLAND",
77         "HAINAN",
78         "BONAIRE",
79         "KAVERI",
80         "KABINI",
81         "HAWAII",
82         "MULLINS",
83         "TOPAZ",
84         "TONGA",
85         "FIJI",
86         "CARRIZO",
87         "STONEY",
88         "POLARIS10",
89         "POLARIS11",
90         "POLARIS12",
91         "VEGA10",
92         "RAVEN",
93         "LAST",
94 };
95
96 bool amdgpu_device_is_px(struct drm_device *dev)
97 {
98         struct amdgpu_device *adev = dev->dev_private;
99
100         if (adev->flags & AMD_IS_PX)
101                 return true;
102         return false;
103 }
104
105 /*
106  * MMIO register access helper functions.
107  */
108 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
109                         uint32_t acc_flags)
110 {
111         uint32_t ret;
112
113         if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
114                 return amdgpu_virt_kiq_rreg(adev, reg);
115
116         if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
117                 ret = readl(((void __iomem *)adev->rmmio) + (reg * 4));
118         else {
119                 unsigned long flags;
120
121                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
122                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
123                 ret = readl(((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
124                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
125         }
126         trace_amdgpu_mm_rreg(adev->pdev->device, reg, ret);
127         return ret;
128 }
129
130 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
131                     uint32_t acc_flags)
132 {
133         trace_amdgpu_mm_wreg(adev->pdev->device, reg, v);
134
135         if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
136                 adev->last_mm_index = v;
137         }
138
139         if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
140                 return amdgpu_virt_kiq_wreg(adev, reg, v);
141
142         if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
143                 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
144         else {
145                 unsigned long flags;
146
147                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
148                 writel((reg * 4), ((void __iomem *)adev->rmmio) + (mmMM_INDEX * 4));
149                 writel(v, ((void __iomem *)adev->rmmio) + (mmMM_DATA * 4));
150                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
151         }
152
153         if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
154                 udelay(500);
155         }
156 }
157
158 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg)
159 {
160         if ((reg * 4) < adev->rio_mem_size)
161                 return ioread32(adev->rio_mem + (reg * 4));
162         else {
163                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
164                 return ioread32(adev->rio_mem + (mmMM_DATA * 4));
165         }
166 }
167
168 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
169 {
170         if (adev->asic_type >= CHIP_VEGA10 && reg == 0) {
171                 adev->last_mm_index = v;
172         }
173
174         if ((reg * 4) < adev->rio_mem_size)
175                 iowrite32(v, adev->rio_mem + (reg * 4));
176         else {
177                 iowrite32((reg * 4), adev->rio_mem + (mmMM_INDEX * 4));
178                 iowrite32(v, adev->rio_mem + (mmMM_DATA * 4));
179         }
180
181         if (adev->asic_type >= CHIP_VEGA10 && reg == 1 && adev->last_mm_index == 0x5702C) {
182                 udelay(500);
183         }
184 }
185
186 /**
187  * amdgpu_mm_rdoorbell - read a doorbell dword
188  *
189  * @adev: amdgpu_device pointer
190  * @index: doorbell index
191  *
192  * Returns the value in the doorbell aperture at the
193  * requested doorbell index (CIK).
194  */
195 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index)
196 {
197         if (index < adev->doorbell.num_doorbells) {
198                 return readl(adev->doorbell.ptr + index);
199         } else {
200                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
201                 return 0;
202         }
203 }
204
205 /**
206  * amdgpu_mm_wdoorbell - write a doorbell dword
207  *
208  * @adev: amdgpu_device pointer
209  * @index: doorbell index
210  * @v: value to write
211  *
212  * Writes @v to the doorbell aperture at the
213  * requested doorbell index (CIK).
214  */
215 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v)
216 {
217         if (index < adev->doorbell.num_doorbells) {
218                 writel(v, adev->doorbell.ptr + index);
219         } else {
220                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
221         }
222 }
223
224 /**
225  * amdgpu_mm_rdoorbell64 - read a doorbell Qword
226  *
227  * @adev: amdgpu_device pointer
228  * @index: doorbell index
229  *
230  * Returns the value in the doorbell aperture at the
231  * requested doorbell index (VEGA10+).
232  */
233 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index)
234 {
235         if (index < adev->doorbell.num_doorbells) {
236                 return atomic64_read((atomic64_t *)(adev->doorbell.ptr + index));
237         } else {
238                 DRM_ERROR("reading beyond doorbell aperture: 0x%08x!\n", index);
239                 return 0;
240         }
241 }
242
243 /**
244  * amdgpu_mm_wdoorbell64 - write a doorbell Qword
245  *
246  * @adev: amdgpu_device pointer
247  * @index: doorbell index
248  * @v: value to write
249  *
250  * Writes @v to the doorbell aperture at the
251  * requested doorbell index (VEGA10+).
252  */
253 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v)
254 {
255         if (index < adev->doorbell.num_doorbells) {
256                 atomic64_set((atomic64_t *)(adev->doorbell.ptr + index), v);
257         } else {
258                 DRM_ERROR("writing beyond doorbell aperture: 0x%08x!\n", index);
259         }
260 }
261
262 /**
263  * amdgpu_invalid_rreg - dummy reg read function
264  *
265  * @adev: amdgpu device pointer
266  * @reg: offset of register
267  *
268  * Dummy register read function.  Used for register blocks
269  * that certain asics don't have (all asics).
270  * Returns the value in the register.
271  */
272 static uint32_t amdgpu_invalid_rreg(struct amdgpu_device *adev, uint32_t reg)
273 {
274         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
275         BUG();
276         return 0;
277 }
278
279 /**
280  * amdgpu_invalid_wreg - dummy reg write function
281  *
282  * @adev: amdgpu device pointer
283  * @reg: offset of register
284  * @v: value to write to the register
285  *
286  * Dummy register read function.  Used for register blocks
287  * that certain asics don't have (all asics).
288  */
289 static void amdgpu_invalid_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
290 {
291         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
292                   reg, v);
293         BUG();
294 }
295
296 /**
297  * amdgpu_block_invalid_rreg - dummy reg read function
298  *
299  * @adev: amdgpu device pointer
300  * @block: offset of instance
301  * @reg: offset of register
302  *
303  * Dummy register read function.  Used for register blocks
304  * that certain asics don't have (all asics).
305  * Returns the value in the register.
306  */
307 static uint32_t amdgpu_block_invalid_rreg(struct amdgpu_device *adev,
308                                           uint32_t block, uint32_t reg)
309 {
310         DRM_ERROR("Invalid callback to read register 0x%04X in block 0x%04X\n",
311                   reg, block);
312         BUG();
313         return 0;
314 }
315
316 /**
317  * amdgpu_block_invalid_wreg - dummy reg write function
318  *
319  * @adev: amdgpu device pointer
320  * @block: offset of instance
321  * @reg: offset of register
322  * @v: value to write to the register
323  *
324  * Dummy register read function.  Used for register blocks
325  * that certain asics don't have (all asics).
326  */
327 static void amdgpu_block_invalid_wreg(struct amdgpu_device *adev,
328                                       uint32_t block,
329                                       uint32_t reg, uint32_t v)
330 {
331         DRM_ERROR("Invalid block callback to write register 0x%04X in block 0x%04X with 0x%08X\n",
332                   reg, block, v);
333         BUG();
334 }
335
336 static int amdgpu_vram_scratch_init(struct amdgpu_device *adev)
337 {
338         return amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_SIZE,
339                                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
340                                        &adev->vram_scratch.robj,
341                                        &adev->vram_scratch.gpu_addr,
342                                        (void **)&adev->vram_scratch.ptr);
343 }
344
345 static void amdgpu_vram_scratch_fini(struct amdgpu_device *adev)
346 {
347         amdgpu_bo_free_kernel(&adev->vram_scratch.robj, NULL, NULL);
348 }
349
350 /**
351  * amdgpu_program_register_sequence - program an array of registers.
352  *
353  * @adev: amdgpu_device pointer
354  * @registers: pointer to the register array
355  * @array_size: size of the register array
356  *
357  * Programs an array or registers with and and or masks.
358  * This is a helper for setting golden registers.
359  */
360 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
361                                       const u32 *registers,
362                                       const u32 array_size)
363 {
364         u32 tmp, reg, and_mask, or_mask;
365         int i;
366
367         if (array_size % 3)
368                 return;
369
370         for (i = 0; i < array_size; i +=3) {
371                 reg = registers[i + 0];
372                 and_mask = registers[i + 1];
373                 or_mask = registers[i + 2];
374
375                 if (and_mask == 0xffffffff) {
376                         tmp = or_mask;
377                 } else {
378                         tmp = RREG32(reg);
379                         tmp &= ~and_mask;
380                         tmp |= or_mask;
381                 }
382                 WREG32(reg, tmp);
383         }
384 }
385
386 void amdgpu_pci_config_reset(struct amdgpu_device *adev)
387 {
388         pci_write_config_dword(adev->pdev, 0x7c, AMDGPU_ASIC_RESET_DATA);
389 }
390
391 /*
392  * GPU doorbell aperture helpers function.
393  */
394 /**
395  * amdgpu_doorbell_init - Init doorbell driver information.
396  *
397  * @adev: amdgpu_device pointer
398  *
399  * Init doorbell driver information (CIK)
400  * Returns 0 on success, error on failure.
401  */
402 static int amdgpu_doorbell_init(struct amdgpu_device *adev)
403 {
404         /* No doorbell on SI hardware generation */
405         if (adev->asic_type < CHIP_BONAIRE) {
406                 adev->doorbell.base = 0;
407                 adev->doorbell.size = 0;
408                 adev->doorbell.num_doorbells = 0;
409                 adev->doorbell.ptr = NULL;
410                 return 0;
411         }
412
413         if (pci_resource_flags(adev->pdev, 2) & IORESOURCE_UNSET)
414                 return -EINVAL;
415
416         /* doorbell bar mapping */
417         adev->doorbell.base = pci_resource_start(adev->pdev, 2);
418         adev->doorbell.size = pci_resource_len(adev->pdev, 2);
419
420         adev->doorbell.num_doorbells = min_t(u32, adev->doorbell.size / sizeof(u32),
421                                              AMDGPU_DOORBELL_MAX_ASSIGNMENT+1);
422         if (adev->doorbell.num_doorbells == 0)
423                 return -EINVAL;
424
425         adev->doorbell.ptr = ioremap(adev->doorbell.base,
426                                      adev->doorbell.num_doorbells *
427                                      sizeof(u32));
428         if (adev->doorbell.ptr == NULL)
429                 return -ENOMEM;
430
431         return 0;
432 }
433
434 /**
435  * amdgpu_doorbell_fini - Tear down doorbell driver information.
436  *
437  * @adev: amdgpu_device pointer
438  *
439  * Tear down doorbell driver information (CIK)
440  */
441 static void amdgpu_doorbell_fini(struct amdgpu_device *adev)
442 {
443         iounmap(adev->doorbell.ptr);
444         adev->doorbell.ptr = NULL;
445 }
446
447 /**
448  * amdgpu_doorbell_get_kfd_info - Report doorbell configuration required to
449  *                                setup amdkfd
450  *
451  * @adev: amdgpu_device pointer
452  * @aperture_base: output returning doorbell aperture base physical address
453  * @aperture_size: output returning doorbell aperture size in bytes
454  * @start_offset: output returning # of doorbell bytes reserved for amdgpu.
455  *
456  * amdgpu and amdkfd share the doorbell aperture. amdgpu sets it up,
457  * takes doorbells required for its own rings and reports the setup to amdkfd.
458  * amdgpu reserved doorbells are at the start of the doorbell aperture.
459  */
460 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
461                                 phys_addr_t *aperture_base,
462                                 size_t *aperture_size,
463                                 size_t *start_offset)
464 {
465         /*
466          * The first num_doorbells are used by amdgpu.
467          * amdkfd takes whatever's left in the aperture.
468          */
469         if (adev->doorbell.size > adev->doorbell.num_doorbells * sizeof(u32)) {
470                 *aperture_base = adev->doorbell.base;
471                 *aperture_size = adev->doorbell.size;
472                 *start_offset = adev->doorbell.num_doorbells * sizeof(u32);
473         } else {
474                 *aperture_base = 0;
475                 *aperture_size = 0;
476                 *start_offset = 0;
477         }
478 }
479
480 /*
481  * amdgpu_wb_*()
482  * Writeback is the method by which the GPU updates special pages in memory
483  * with the status of certain GPU events (fences, ring pointers,etc.).
484  */
485
486 /**
487  * amdgpu_wb_fini - Disable Writeback and free memory
488  *
489  * @adev: amdgpu_device pointer
490  *
491  * Disables Writeback and frees the Writeback memory (all asics).
492  * Used at driver shutdown.
493  */
494 static void amdgpu_wb_fini(struct amdgpu_device *adev)
495 {
496         if (adev->wb.wb_obj) {
497                 amdgpu_bo_free_kernel(&adev->wb.wb_obj,
498                                       &adev->wb.gpu_addr,
499                                       (void **)&adev->wb.wb);
500                 adev->wb.wb_obj = NULL;
501         }
502 }
503
504 /**
505  * amdgpu_wb_init- Init Writeback driver info and allocate memory
506  *
507  * @adev: amdgpu_device pointer
508  *
509  * Initializes writeback and allocates writeback memory (all asics).
510  * Used at driver startup.
511  * Returns 0 on success or an -error on failure.
512  */
513 static int amdgpu_wb_init(struct amdgpu_device *adev)
514 {
515         int r;
516
517         if (adev->wb.wb_obj == NULL) {
518                 /* AMDGPU_MAX_WB * sizeof(uint32_t) * 8 = AMDGPU_MAX_WB 256bit slots */
519                 r = amdgpu_bo_create_kernel(adev, AMDGPU_MAX_WB * sizeof(uint32_t) * 8,
520                                             PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
521                                             &adev->wb.wb_obj, &adev->wb.gpu_addr,
522                                             (void **)&adev->wb.wb);
523                 if (r) {
524                         dev_warn(adev->dev, "(%d) create WB bo failed\n", r);
525                         return r;
526                 }
527
528                 adev->wb.num_wb = AMDGPU_MAX_WB;
529                 memset(&adev->wb.used, 0, sizeof(adev->wb.used));
530
531                 /* clear wb memory */
532                 memset((char *)adev->wb.wb, 0, AMDGPU_MAX_WB * sizeof(uint32_t));
533         }
534
535         return 0;
536 }
537
538 /**
539  * amdgpu_wb_get - Allocate a wb entry
540  *
541  * @adev: amdgpu_device pointer
542  * @wb: wb index
543  *
544  * Allocate a wb slot for use by the driver (all asics).
545  * Returns 0 on success or -EINVAL on failure.
546  */
547 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb)
548 {
549         unsigned long offset = find_first_zero_bit(adev->wb.used, adev->wb.num_wb);
550
551         if (offset < adev->wb.num_wb) {
552                 __set_bit(offset, adev->wb.used);
553                 *wb = offset << 3; /* convert to dw offset */
554                 return 0;
555         } else {
556                 return -EINVAL;
557         }
558 }
559
560 /**
561  * amdgpu_wb_free - Free a wb entry
562  *
563  * @adev: amdgpu_device pointer
564  * @wb: wb index
565  *
566  * Free a wb slot allocated for use by the driver (all asics)
567  */
568 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb)
569 {
570         if (wb < adev->wb.num_wb)
571                 __clear_bit(wb >> 3, adev->wb.used);
572 }
573
574 /**
575  * amdgpu_vram_location - try to find VRAM location
576  * @adev: amdgpu device structure holding all necessary informations
577  * @mc: memory controller structure holding memory informations
578  * @base: base address at which to put VRAM
579  *
580  * Function will try to place VRAM at base address provided
581  * as parameter (which is so far either PCI aperture address or
582  * for IGP TOM base address).
583  *
584  * If there is not enough space to fit the unvisible VRAM in the 32bits
585  * address space then we limit the VRAM size to the aperture.
586  *
587  * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
588  * this shouldn't be a problem as we are using the PCI aperture as a reference.
589  * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
590  * not IGP.
591  *
592  * Note: we use mc_vram_size as on some board we need to program the mc to
593  * cover the whole aperture even if VRAM size is inferior to aperture size
594  * Novell bug 204882 + along with lots of ubuntu ones
595  *
596  * Note: when limiting vram it's safe to overwritte real_vram_size because
597  * we are not in case where real_vram_size is inferior to mc_vram_size (ie
598  * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
599  * ones)
600  *
601  * Note: IGP TOM addr should be the same as the aperture addr, we don't
602  * explicitly check for that though.
603  *
604  * FIXME: when reducing VRAM size align new size on power of 2.
605  */
606 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base)
607 {
608         uint64_t limit = (uint64_t)amdgpu_vram_limit << 20;
609
610         mc->vram_start = base;
611         if (mc->mc_vram_size > (adev->mc.mc_mask - base + 1)) {
612                 dev_warn(adev->dev, "limiting VRAM to PCI aperture size\n");
613                 mc->real_vram_size = mc->aper_size;
614                 mc->mc_vram_size = mc->aper_size;
615         }
616         mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
617         if (limit && limit < mc->real_vram_size)
618                 mc->real_vram_size = limit;
619         dev_info(adev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
620                         mc->mc_vram_size >> 20, mc->vram_start,
621                         mc->vram_end, mc->real_vram_size >> 20);
622 }
623
624 /**
625  * amdgpu_gart_location - try to find GTT location
626  * @adev: amdgpu device structure holding all necessary informations
627  * @mc: memory controller structure holding memory informations
628  *
629  * Function will place try to place GTT before or after VRAM.
630  *
631  * If GTT size is bigger than space left then we ajust GTT size.
632  * Thus function will never fails.
633  *
634  * FIXME: when reducing GTT size align new size on power of 2.
635  */
636 void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc)
637 {
638         u64 size_af, size_bf;
639
640         size_af = adev->mc.mc_mask - mc->vram_end;
641         size_bf = mc->vram_start;
642         if (size_bf > size_af) {
643                 if (mc->gart_size > size_bf) {
644                         dev_warn(adev->dev, "limiting GTT\n");
645                         mc->gart_size = size_bf;
646                 }
647                 mc->gart_start = 0;
648         } else {
649                 if (mc->gart_size > size_af) {
650                         dev_warn(adev->dev, "limiting GTT\n");
651                         mc->gart_size = size_af;
652                 }
653                 mc->gart_start = mc->vram_end + 1;
654         }
655         mc->gart_end = mc->gart_start + mc->gart_size - 1;
656         dev_info(adev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
657                         mc->gart_size >> 20, mc->gart_start, mc->gart_end);
658 }
659
660 /*
661  * Firmware Reservation functions
662  */
663 /**
664  * amdgpu_fw_reserve_vram_fini - free fw reserved vram
665  *
666  * @adev: amdgpu_device pointer
667  *
668  * free fw reserved vram if it has been reserved.
669  */
670 void amdgpu_fw_reserve_vram_fini(struct amdgpu_device *adev)
671 {
672         amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
673                 NULL, &adev->fw_vram_usage.va);
674 }
675
676 /**
677  * amdgpu_fw_reserve_vram_init - create bo vram reservation from fw
678  *
679  * @adev: amdgpu_device pointer
680  *
681  * create bo vram reservation from fw.
682  */
683 int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev)
684 {
685         int r = 0;
686         int i;
687         u64 gpu_addr;
688         u64 vram_size = adev->mc.visible_vram_size;
689         u64 offset = adev->fw_vram_usage.start_offset;
690         u64 size = adev->fw_vram_usage.size;
691         struct amdgpu_bo *bo;
692
693         adev->fw_vram_usage.va = NULL;
694         adev->fw_vram_usage.reserved_bo = NULL;
695
696         if (adev->fw_vram_usage.size > 0 &&
697                 adev->fw_vram_usage.size <= vram_size) {
698
699                 r = amdgpu_bo_create(adev, adev->fw_vram_usage.size,
700                         PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_VRAM,
701                         AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
702                         AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS, NULL, NULL, 0,
703                         &adev->fw_vram_usage.reserved_bo);
704                 if (r)
705                         goto error_create;
706
707                 r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false);
708                 if (r)
709                         goto error_reserve;
710
711                 /* remove the original mem node and create a new one at the
712                  * request position
713                  */
714                 bo = adev->fw_vram_usage.reserved_bo;
715                 offset = ALIGN(offset, PAGE_SIZE);
716                 for (i = 0; i < bo->placement.num_placement; ++i) {
717                         bo->placements[i].fpfn = offset >> PAGE_SHIFT;
718                         bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
719                 }
720
721                 ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
722                 r = ttm_bo_mem_space(&bo->tbo, &bo->placement, &bo->tbo.mem,
723                                      false, false);
724                 if (r)
725                         goto error_pin;
726
727                 r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo,
728                         AMDGPU_GEM_DOMAIN_VRAM,
729                         adev->fw_vram_usage.start_offset,
730                         (adev->fw_vram_usage.start_offset +
731                         adev->fw_vram_usage.size), &gpu_addr);
732                 if (r)
733                         goto error_pin;
734                 r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo,
735                         &adev->fw_vram_usage.va);
736                 if (r)
737                         goto error_kmap;
738
739                 amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
740         }
741         return r;
742
743 error_kmap:
744         amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
745 error_pin:
746         amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
747 error_reserve:
748         amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo);
749 error_create:
750         adev->fw_vram_usage.va = NULL;
751         adev->fw_vram_usage.reserved_bo = NULL;
752         return r;
753 }
754
755 /**
756  * amdgpu_device_resize_fb_bar - try to resize FB BAR
757  *
758  * @adev: amdgpu_device pointer
759  *
760  * Try to resize FB BAR to make all VRAM CPU accessible. We try very hard not
761  * to fail, but if any of the BARs is not accessible after the size we abort
762  * driver loading by returning -ENODEV.
763  */
764 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev)
765 {
766         u64 space_needed = roundup_pow_of_two(adev->mc.real_vram_size);
767         u32 rbar_size = order_base_2(((space_needed >> 20) | 1)) - 1;
768         u16 cmd;
769         int r;
770
771         /* Disable memory decoding while we change the BAR addresses and size */
772         pci_read_config_word(adev->pdev, PCI_COMMAND, &cmd);
773         pci_write_config_word(adev->pdev, PCI_COMMAND,
774                               cmd & ~PCI_COMMAND_MEMORY);
775
776         /* Free the VRAM and doorbell BAR, we most likely need to move both. */
777         amdgpu_doorbell_fini(adev);
778         if (adev->asic_type >= CHIP_BONAIRE)
779                 pci_release_resource(adev->pdev, 2);
780
781         pci_release_resource(adev->pdev, 0);
782
783         r = pci_resize_resource(adev->pdev, 0, rbar_size);
784         if (r == -ENOSPC)
785                 DRM_INFO("Not enough PCI address space for a large BAR.");
786         else if (r && r != -ENOTSUPP)
787                 DRM_ERROR("Problem resizing BAR0 (%d).", r);
788
789         pci_assign_unassigned_bus_resources(adev->pdev->bus);
790
791         /* When the doorbell or fb BAR isn't available we have no chance of
792          * using the device.
793          */
794         r = amdgpu_doorbell_init(adev);
795         if (r || (pci_resource_flags(adev->pdev, 0) & IORESOURCE_UNSET))
796                 return -ENODEV;
797
798         pci_write_config_word(adev->pdev, PCI_COMMAND, cmd);
799
800         return 0;
801 }
802
803 /*
804  * GPU helpers function.
805  */
806 /**
807  * amdgpu_need_post - check if the hw need post or not
808  *
809  * @adev: amdgpu_device pointer
810  *
811  * Check if the asic has been initialized (all asics) at driver startup
812  * or post is needed if  hw reset is performed.
813  * Returns true if need or false if not.
814  */
815 bool amdgpu_need_post(struct amdgpu_device *adev)
816 {
817         uint32_t reg;
818
819         if (amdgpu_sriov_vf(adev))
820                 return false;
821
822         if (amdgpu_passthrough(adev)) {
823                 /* for FIJI: In whole GPU pass-through virtualization case, after VM reboot
824                  * some old smc fw still need driver do vPost otherwise gpu hang, while
825                  * those smc fw version above 22.15 doesn't have this flaw, so we force
826                  * vpost executed for smc version below 22.15
827                  */
828                 if (adev->asic_type == CHIP_FIJI) {
829                         int err;
830                         uint32_t fw_ver;
831                         err = request_firmware(&adev->pm.fw, "amdgpu/fiji_smc.bin", adev->dev);
832                         /* force vPost if error occured */
833                         if (err)
834                                 return true;
835
836                         fw_ver = *((uint32_t *)adev->pm.fw->data + 69);
837                         if (fw_ver < 0x00160e00)
838                                 return true;
839                 }
840         }
841
842         if (adev->has_hw_reset) {
843                 adev->has_hw_reset = false;
844                 return true;
845         }
846
847         /* bios scratch used on CIK+ */
848         if (adev->asic_type >= CHIP_BONAIRE)
849                 return amdgpu_atombios_scratch_need_asic_init(adev);
850
851         /* check MEM_SIZE for older asics */
852         reg = amdgpu_asic_get_config_memsize(adev);
853
854         if ((reg != 0) && (reg != 0xffffffff))
855                 return false;
856
857         return true;
858 }
859
860 /**
861  * amdgpu_dummy_page_init - init dummy page used by the driver
862  *
863  * @adev: amdgpu_device pointer
864  *
865  * Allocate the dummy page used by the driver (all asics).
866  * This dummy page is used by the driver as a filler for gart entries
867  * when pages are taken out of the GART
868  * Returns 0 on sucess, -ENOMEM on failure.
869  */
870 int amdgpu_dummy_page_init(struct amdgpu_device *adev)
871 {
872         if (adev->dummy_page.page)
873                 return 0;
874         adev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
875         if (adev->dummy_page.page == NULL)
876                 return -ENOMEM;
877         adev->dummy_page.addr = pci_map_page(adev->pdev, adev->dummy_page.page,
878                                         0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
879         if (pci_dma_mapping_error(adev->pdev, adev->dummy_page.addr)) {
880                 dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
881                 __free_page(adev->dummy_page.page);
882                 adev->dummy_page.page = NULL;
883                 return -ENOMEM;
884         }
885         return 0;
886 }
887
888 /**
889  * amdgpu_dummy_page_fini - free dummy page used by the driver
890  *
891  * @adev: amdgpu_device pointer
892  *
893  * Frees the dummy page used by the driver (all asics).
894  */
895 void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
896 {
897         if (adev->dummy_page.page == NULL)
898                 return;
899         pci_unmap_page(adev->pdev, adev->dummy_page.addr,
900                         PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
901         __free_page(adev->dummy_page.page);
902         adev->dummy_page.page = NULL;
903 }
904
905
906 /* ATOM accessor methods */
907 /*
908  * ATOM is an interpreted byte code stored in tables in the vbios.  The
909  * driver registers callbacks to access registers and the interpreter
910  * in the driver parses the tables and executes then to program specific
911  * actions (set display modes, asic init, etc.).  See amdgpu_atombios.c,
912  * atombios.h, and atom.c
913  */
914
915 /**
916  * cail_pll_read - read PLL register
917  *
918  * @info: atom card_info pointer
919  * @reg: PLL register offset
920  *
921  * Provides a PLL register accessor for the atom interpreter (r4xx+).
922  * Returns the value of the PLL register.
923  */
924 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
925 {
926         return 0;
927 }
928
929 /**
930  * cail_pll_write - write PLL register
931  *
932  * @info: atom card_info pointer
933  * @reg: PLL register offset
934  * @val: value to write to the pll register
935  *
936  * Provides a PLL register accessor for the atom interpreter (r4xx+).
937  */
938 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
939 {
940
941 }
942
943 /**
944  * cail_mc_read - read MC (Memory Controller) register
945  *
946  * @info: atom card_info pointer
947  * @reg: MC register offset
948  *
949  * Provides an MC register accessor for the atom interpreter (r4xx+).
950  * Returns the value of the MC register.
951  */
952 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
953 {
954         return 0;
955 }
956
957 /**
958  * cail_mc_write - write MC (Memory Controller) register
959  *
960  * @info: atom card_info pointer
961  * @reg: MC register offset
962  * @val: value to write to the pll register
963  *
964  * Provides a MC register accessor for the atom interpreter (r4xx+).
965  */
966 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
967 {
968
969 }
970
971 /**
972  * cail_reg_write - write MMIO register
973  *
974  * @info: atom card_info pointer
975  * @reg: MMIO register offset
976  * @val: value to write to the pll register
977  *
978  * Provides a MMIO register accessor for the atom interpreter (r4xx+).
979  */
980 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
981 {
982         struct amdgpu_device *adev = info->dev->dev_private;
983
984         WREG32(reg, val);
985 }
986
987 /**
988  * cail_reg_read - read MMIO register
989  *
990  * @info: atom card_info pointer
991  * @reg: MMIO register offset
992  *
993  * Provides an MMIO register accessor for the atom interpreter (r4xx+).
994  * Returns the value of the MMIO register.
995  */
996 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
997 {
998         struct amdgpu_device *adev = info->dev->dev_private;
999         uint32_t r;
1000
1001         r = RREG32(reg);
1002         return r;
1003 }
1004
1005 /**
1006  * cail_ioreg_write - write IO register
1007  *
1008  * @info: atom card_info pointer
1009  * @reg: IO register offset
1010  * @val: value to write to the pll register
1011  *
1012  * Provides a IO register accessor for the atom interpreter (r4xx+).
1013  */
1014 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
1015 {
1016         struct amdgpu_device *adev = info->dev->dev_private;
1017
1018         WREG32_IO(reg, val);
1019 }
1020
1021 /**
1022  * cail_ioreg_read - read IO register
1023  *
1024  * @info: atom card_info pointer
1025  * @reg: IO register offset
1026  *
1027  * Provides an IO register accessor for the atom interpreter (r4xx+).
1028  * Returns the value of the IO register.
1029  */
1030 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
1031 {
1032         struct amdgpu_device *adev = info->dev->dev_private;
1033         uint32_t r;
1034
1035         r = RREG32_IO(reg);
1036         return r;
1037 }
1038
1039 static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev,
1040                                                  struct device_attribute *attr,
1041                                                  char *buf)
1042 {
1043         struct drm_device *ddev = dev_get_drvdata(dev);
1044         struct amdgpu_device *adev = ddev->dev_private;
1045         struct atom_context *ctx = adev->mode_info.atom_context;
1046
1047         return snprintf(buf, PAGE_SIZE, "%s\n", ctx->vbios_version);
1048 }
1049
1050 static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version,
1051                    NULL);
1052
1053 /**
1054  * amdgpu_atombios_fini - free the driver info and callbacks for atombios
1055  *
1056  * @adev: amdgpu_device pointer
1057  *
1058  * Frees the driver info and register access callbacks for the ATOM
1059  * interpreter (r4xx+).
1060  * Called at driver shutdown.
1061  */
1062 static void amdgpu_atombios_fini(struct amdgpu_device *adev)
1063 {
1064         if (adev->mode_info.atom_context) {
1065                 kfree(adev->mode_info.atom_context->scratch);
1066                 kfree(adev->mode_info.atom_context->iio);
1067         }
1068         kfree(adev->mode_info.atom_context);
1069         adev->mode_info.atom_context = NULL;
1070         kfree(adev->mode_info.atom_card_info);
1071         adev->mode_info.atom_card_info = NULL;
1072         device_remove_file(adev->dev, &dev_attr_vbios_version);
1073 }
1074
1075 /**
1076  * amdgpu_atombios_init - init the driver info and callbacks for atombios
1077  *
1078  * @adev: amdgpu_device pointer
1079  *
1080  * Initializes the driver info and register access callbacks for the
1081  * ATOM interpreter (r4xx+).
1082  * Returns 0 on sucess, -ENOMEM on failure.
1083  * Called at driver startup.
1084  */
1085 static int amdgpu_atombios_init(struct amdgpu_device *adev)
1086 {
1087         struct card_info *atom_card_info =
1088             kzalloc(sizeof(struct card_info), GFP_KERNEL);
1089         int ret;
1090
1091         if (!atom_card_info)
1092                 return -ENOMEM;
1093
1094         adev->mode_info.atom_card_info = atom_card_info;
1095         atom_card_info->dev = adev->ddev;
1096         atom_card_info->reg_read = cail_reg_read;
1097         atom_card_info->reg_write = cail_reg_write;
1098         /* needed for iio ops */
1099         if (adev->rio_mem) {
1100                 atom_card_info->ioreg_read = cail_ioreg_read;
1101                 atom_card_info->ioreg_write = cail_ioreg_write;
1102         } else {
1103                 DRM_DEBUG("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n");
1104                 atom_card_info->ioreg_read = cail_reg_read;
1105                 atom_card_info->ioreg_write = cail_reg_write;
1106         }
1107         atom_card_info->mc_read = cail_mc_read;
1108         atom_card_info->mc_write = cail_mc_write;
1109         atom_card_info->pll_read = cail_pll_read;
1110         atom_card_info->pll_write = cail_pll_write;
1111
1112         adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
1113         if (!adev->mode_info.atom_context) {
1114                 amdgpu_atombios_fini(adev);
1115                 return -ENOMEM;
1116         }
1117
1118         mutex_init(&adev->mode_info.atom_context->mutex);
1119         if (adev->is_atom_fw) {
1120                 amdgpu_atomfirmware_scratch_regs_init(adev);
1121                 amdgpu_atomfirmware_allocate_fb_scratch(adev);
1122         } else {
1123                 amdgpu_atombios_scratch_regs_init(adev);
1124                 amdgpu_atombios_allocate_fb_scratch(adev);
1125         }
1126
1127         ret = device_create_file(adev->dev, &dev_attr_vbios_version);
1128         if (ret) {
1129                 DRM_ERROR("Failed to create device file for VBIOS version\n");
1130                 return ret;
1131         }
1132
1133         return 0;
1134 }
1135
1136 /* if we get transitioned to only one device, take VGA back */
1137 /**
1138  * amdgpu_vga_set_decode - enable/disable vga decode
1139  *
1140  * @cookie: amdgpu_device pointer
1141  * @state: enable/disable vga decode
1142  *
1143  * Enable/disable vga decode (all asics).
1144  * Returns VGA resource flags.
1145  */
1146 static unsigned int amdgpu_vga_set_decode(void *cookie, bool state)
1147 {
1148         struct amdgpu_device *adev = cookie;
1149         amdgpu_asic_set_vga_state(adev, state);
1150         if (state)
1151                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1152                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1153         else
1154                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1155 }
1156
1157 static void amdgpu_check_block_size(struct amdgpu_device *adev)
1158 {
1159         /* defines number of bits in page table versus page directory,
1160          * a page is 4KB so we have 12 bits offset, minimum 9 bits in the
1161          * page table and the remaining bits are in the page directory */
1162         if (amdgpu_vm_block_size == -1)
1163                 return;
1164
1165         if (amdgpu_vm_block_size < 9) {
1166                 dev_warn(adev->dev, "VM page table size (%d) too small\n",
1167                          amdgpu_vm_block_size);
1168                 goto def_value;
1169         }
1170
1171         if (amdgpu_vm_block_size > 24 ||
1172             (amdgpu_vm_size * 1024) < (1ull << amdgpu_vm_block_size)) {
1173                 dev_warn(adev->dev, "VM page table size (%d) too large\n",
1174                          amdgpu_vm_block_size);
1175                 goto def_value;
1176         }
1177
1178         return;
1179
1180 def_value:
1181         amdgpu_vm_block_size = -1;
1182 }
1183
1184 static void amdgpu_check_vm_size(struct amdgpu_device *adev)
1185 {
1186         /* no need to check the default value */
1187         if (amdgpu_vm_size == -1)
1188                 return;
1189
1190         if (!is_power_of_2(amdgpu_vm_size)) {
1191                 dev_warn(adev->dev, "VM size (%d) must be a power of 2\n",
1192                          amdgpu_vm_size);
1193                 goto def_value;
1194         }
1195
1196         if (amdgpu_vm_size < 1) {
1197                 dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
1198                          amdgpu_vm_size);
1199                 goto def_value;
1200         }
1201
1202         /*
1203          * Max GPUVM size for Cayman, SI, CI VI are 40 bits.
1204          */
1205         if (amdgpu_vm_size > 1024) {
1206                 dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
1207                          amdgpu_vm_size);
1208                 goto def_value;
1209         }
1210
1211         return;
1212
1213 def_value:
1214         amdgpu_vm_size = -1;
1215 }
1216
1217 /**
1218  * amdgpu_check_arguments - validate module params
1219  *
1220  * @adev: amdgpu_device pointer
1221  *
1222  * Validates certain module parameters and updates
1223  * the associated values used by the driver (all asics).
1224  */
1225 static void amdgpu_check_arguments(struct amdgpu_device *adev)
1226 {
1227         if (amdgpu_sched_jobs < 4) {
1228                 dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n",
1229                          amdgpu_sched_jobs);
1230                 amdgpu_sched_jobs = 4;
1231         } else if (!is_power_of_2(amdgpu_sched_jobs)){
1232                 dev_warn(adev->dev, "sched jobs (%d) must be a power of 2\n",
1233                          amdgpu_sched_jobs);
1234                 amdgpu_sched_jobs = roundup_pow_of_two(amdgpu_sched_jobs);
1235         }
1236
1237         if (amdgpu_gart_size != -1 && amdgpu_gart_size < 32) {
1238                 /* gart size must be greater or equal to 32M */
1239                 dev_warn(adev->dev, "gart size (%d) too small\n",
1240                          amdgpu_gart_size);
1241                 amdgpu_gart_size = -1;
1242         }
1243
1244         if (amdgpu_gtt_size != -1 && amdgpu_gtt_size < 32) {
1245                 /* gtt size must be greater or equal to 32M */
1246                 dev_warn(adev->dev, "gtt size (%d) too small\n",
1247                                  amdgpu_gtt_size);
1248                 amdgpu_gtt_size = -1;
1249         }
1250
1251         /* valid range is between 4 and 9 inclusive */
1252         if (amdgpu_vm_fragment_size != -1 &&
1253             (amdgpu_vm_fragment_size > 9 || amdgpu_vm_fragment_size < 4)) {
1254                 dev_warn(adev->dev, "valid range is between 4 and 9\n");
1255                 amdgpu_vm_fragment_size = -1;
1256         }
1257
1258         amdgpu_check_vm_size(adev);
1259
1260         amdgpu_check_block_size(adev);
1261
1262         if (amdgpu_vram_page_split != -1 && (amdgpu_vram_page_split < 16 ||
1263             !is_power_of_2(amdgpu_vram_page_split))) {
1264                 dev_warn(adev->dev, "invalid VRAM page split (%d)\n",
1265                          amdgpu_vram_page_split);
1266                 amdgpu_vram_page_split = 1024;
1267         }
1268 }
1269
1270 /**
1271  * amdgpu_switcheroo_set_state - set switcheroo state
1272  *
1273  * @pdev: pci dev pointer
1274  * @state: vga_switcheroo state
1275  *
1276  * Callback for the switcheroo driver.  Suspends or resumes the
1277  * the asics before or after it is powered up using ACPI methods.
1278  */
1279 static void amdgpu_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1280 {
1281         struct drm_device *dev = pci_get_drvdata(pdev);
1282
1283         if (amdgpu_device_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1284                 return;
1285
1286         if (state == VGA_SWITCHEROO_ON) {
1287                 pr_info("amdgpu: switched on\n");
1288                 /* don't suspend or resume card normally */
1289                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1290
1291                 amdgpu_device_resume(dev, true, true);
1292
1293                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1294                 drm_kms_helper_poll_enable(dev);
1295         } else {
1296                 pr_info("amdgpu: switched off\n");
1297                 drm_kms_helper_poll_disable(dev);
1298                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1299                 amdgpu_device_suspend(dev, true, true);
1300                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1301         }
1302 }
1303
1304 /**
1305  * amdgpu_switcheroo_can_switch - see if switcheroo state can change
1306  *
1307  * @pdev: pci dev pointer
1308  *
1309  * Callback for the switcheroo driver.  Check of the switcheroo
1310  * state can be changed.
1311  * Returns true if the state can be changed, false if not.
1312  */
1313 static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev)
1314 {
1315         struct drm_device *dev = pci_get_drvdata(pdev);
1316
1317         /*
1318         * FIXME: open_count is protected by drm_global_mutex but that would lead to
1319         * locking inversion with the driver load path. And the access here is
1320         * completely racy anyway. So don't bother with locking for now.
1321         */
1322         return dev->open_count == 0;
1323 }
1324
1325 static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = {
1326         .set_gpu_state = amdgpu_switcheroo_set_state,
1327         .reprobe = NULL,
1328         .can_switch = amdgpu_switcheroo_can_switch,
1329 };
1330
1331 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
1332                                   enum amd_ip_block_type block_type,
1333                                   enum amd_clockgating_state state)
1334 {
1335         int i, r = 0;
1336
1337         for (i = 0; i < adev->num_ip_blocks; i++) {
1338                 if (!adev->ip_blocks[i].status.valid)
1339                         continue;
1340                 if (adev->ip_blocks[i].version->type != block_type)
1341                         continue;
1342                 if (!adev->ip_blocks[i].version->funcs->set_clockgating_state)
1343                         continue;
1344                 r = adev->ip_blocks[i].version->funcs->set_clockgating_state(
1345                         (void *)adev, state);
1346                 if (r)
1347                         DRM_ERROR("set_clockgating_state of IP block <%s> failed %d\n",
1348                                   adev->ip_blocks[i].version->funcs->name, r);
1349         }
1350         return r;
1351 }
1352
1353 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
1354                                   enum amd_ip_block_type block_type,
1355                                   enum amd_powergating_state state)
1356 {
1357         int i, r = 0;
1358
1359         for (i = 0; i < adev->num_ip_blocks; i++) {
1360                 if (!adev->ip_blocks[i].status.valid)
1361                         continue;
1362                 if (adev->ip_blocks[i].version->type != block_type)
1363                         continue;
1364                 if (!adev->ip_blocks[i].version->funcs->set_powergating_state)
1365                         continue;
1366                 r = adev->ip_blocks[i].version->funcs->set_powergating_state(
1367                         (void *)adev, state);
1368                 if (r)
1369                         DRM_ERROR("set_powergating_state of IP block <%s> failed %d\n",
1370                                   adev->ip_blocks[i].version->funcs->name, r);
1371         }
1372         return r;
1373 }
1374
1375 void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags)
1376 {
1377         int i;
1378
1379         for (i = 0; i < adev->num_ip_blocks; i++) {
1380                 if (!adev->ip_blocks[i].status.valid)
1381                         continue;
1382                 if (adev->ip_blocks[i].version->funcs->get_clockgating_state)
1383                         adev->ip_blocks[i].version->funcs->get_clockgating_state((void *)adev, flags);
1384         }
1385 }
1386
1387 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
1388                          enum amd_ip_block_type block_type)
1389 {
1390         int i, r;
1391
1392         for (i = 0; i < adev->num_ip_blocks; i++) {
1393                 if (!adev->ip_blocks[i].status.valid)
1394                         continue;
1395                 if (adev->ip_blocks[i].version->type == block_type) {
1396                         r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev);
1397                         if (r)
1398                                 return r;
1399                         break;
1400                 }
1401         }
1402         return 0;
1403
1404 }
1405
1406 bool amdgpu_is_idle(struct amdgpu_device *adev,
1407                     enum amd_ip_block_type block_type)
1408 {
1409         int i;
1410
1411         for (i = 0; i < adev->num_ip_blocks; i++) {
1412                 if (!adev->ip_blocks[i].status.valid)
1413                         continue;
1414                 if (adev->ip_blocks[i].version->type == block_type)
1415                         return adev->ip_blocks[i].version->funcs->is_idle((void *)adev);
1416         }
1417         return true;
1418
1419 }
1420
1421 struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
1422                                              enum amd_ip_block_type type)
1423 {
1424         int i;
1425
1426         for (i = 0; i < adev->num_ip_blocks; i++)
1427                 if (adev->ip_blocks[i].version->type == type)
1428                         return &adev->ip_blocks[i];
1429
1430         return NULL;
1431 }
1432
1433 /**
1434  * amdgpu_ip_block_version_cmp
1435  *
1436  * @adev: amdgpu_device pointer
1437  * @type: enum amd_ip_block_type
1438  * @major: major version
1439  * @minor: minor version
1440  *
1441  * return 0 if equal or greater
1442  * return 1 if smaller or the ip_block doesn't exist
1443  */
1444 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
1445                                 enum amd_ip_block_type type,
1446                                 u32 major, u32 minor)
1447 {
1448         struct amdgpu_ip_block *ip_block = amdgpu_get_ip_block(adev, type);
1449
1450         if (ip_block && ((ip_block->version->major > major) ||
1451                         ((ip_block->version->major == major) &&
1452                         (ip_block->version->minor >= minor))))
1453                 return 0;
1454
1455         return 1;
1456 }
1457
1458 /**
1459  * amdgpu_ip_block_add
1460  *
1461  * @adev: amdgpu_device pointer
1462  * @ip_block_version: pointer to the IP to add
1463  *
1464  * Adds the IP block driver information to the collection of IPs
1465  * on the asic.
1466  */
1467 int amdgpu_ip_block_add(struct amdgpu_device *adev,
1468                         const struct amdgpu_ip_block_version *ip_block_version)
1469 {
1470         if (!ip_block_version)
1471                 return -EINVAL;
1472
1473         DRM_DEBUG("add ip block number %d <%s>\n", adev->num_ip_blocks,
1474                   ip_block_version->funcs->name);
1475
1476         adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version;
1477
1478         return 0;
1479 }
1480
1481 static void amdgpu_device_enable_virtual_display(struct amdgpu_device *adev)
1482 {
1483         adev->enable_virtual_display = false;
1484
1485         if (amdgpu_virtual_display) {
1486                 struct drm_device *ddev = adev->ddev;
1487                 const char *pci_address_name = pci_name(ddev->pdev);
1488                 char *pciaddstr, *pciaddstr_tmp, *pciaddname_tmp, *pciaddname;
1489
1490                 pciaddstr = kstrdup(amdgpu_virtual_display, GFP_KERNEL);
1491                 pciaddstr_tmp = pciaddstr;
1492                 while ((pciaddname_tmp = strsep(&pciaddstr_tmp, ";"))) {
1493                         pciaddname = strsep(&pciaddname_tmp, ",");
1494                         if (!strcmp("all", pciaddname)
1495                             || !strcmp(pci_address_name, pciaddname)) {
1496                                 long num_crtc;
1497                                 int res = -1;
1498
1499                                 adev->enable_virtual_display = true;
1500
1501                                 if (pciaddname_tmp)
1502                                         res = kstrtol(pciaddname_tmp, 10,
1503                                                       &num_crtc);
1504
1505                                 if (!res) {
1506                                         if (num_crtc < 1)
1507                                                 num_crtc = 1;
1508                                         if (num_crtc > 6)
1509                                                 num_crtc = 6;
1510                                         adev->mode_info.num_crtc = num_crtc;
1511                                 } else {
1512                                         adev->mode_info.num_crtc = 1;
1513                                 }
1514                                 break;
1515                         }
1516                 }
1517
1518                 DRM_INFO("virtual display string:%s, %s:virtual_display:%d, num_crtc:%d\n",
1519                          amdgpu_virtual_display, pci_address_name,
1520                          adev->enable_virtual_display, adev->mode_info.num_crtc);
1521
1522                 kfree(pciaddstr);
1523         }
1524 }
1525
1526 static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
1527 {
1528         const char *chip_name;
1529         char fw_name[30];
1530         int err;
1531         const struct gpu_info_firmware_header_v1_0 *hdr;
1532
1533         adev->firmware.gpu_info_fw = NULL;
1534
1535         switch (adev->asic_type) {
1536         case CHIP_TOPAZ:
1537         case CHIP_TONGA:
1538         case CHIP_FIJI:
1539         case CHIP_POLARIS11:
1540         case CHIP_POLARIS10:
1541         case CHIP_POLARIS12:
1542         case CHIP_CARRIZO:
1543         case CHIP_STONEY:
1544 #ifdef CONFIG_DRM_AMDGPU_SI
1545         case CHIP_VERDE:
1546         case CHIP_TAHITI:
1547         case CHIP_PITCAIRN:
1548         case CHIP_OLAND:
1549         case CHIP_HAINAN:
1550 #endif
1551 #ifdef CONFIG_DRM_AMDGPU_CIK
1552         case CHIP_BONAIRE:
1553         case CHIP_HAWAII:
1554         case CHIP_KAVERI:
1555         case CHIP_KABINI:
1556         case CHIP_MULLINS:
1557 #endif
1558         default:
1559                 return 0;
1560         case CHIP_VEGA10:
1561                 chip_name = "vega10";
1562                 break;
1563         case CHIP_RAVEN:
1564                 chip_name = "raven";
1565                 break;
1566         }
1567
1568         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_gpu_info.bin", chip_name);
1569         err = request_firmware(&adev->firmware.gpu_info_fw, fw_name, adev->dev);
1570         if (err) {
1571                 dev_err(adev->dev,
1572                         "Failed to load gpu_info firmware \"%s\"\n",
1573                         fw_name);
1574                 goto out;
1575         }
1576         err = amdgpu_ucode_validate(adev->firmware.gpu_info_fw);
1577         if (err) {
1578                 dev_err(adev->dev,
1579                         "Failed to validate gpu_info firmware \"%s\"\n",
1580                         fw_name);
1581                 goto out;
1582         }
1583
1584         hdr = (const struct gpu_info_firmware_header_v1_0 *)adev->firmware.gpu_info_fw->data;
1585         amdgpu_ucode_print_gpu_info_hdr(&hdr->header);
1586
1587         switch (hdr->version_major) {
1588         case 1:
1589         {
1590                 const struct gpu_info_firmware_v1_0 *gpu_info_fw =
1591                         (const struct gpu_info_firmware_v1_0 *)(adev->firmware.gpu_info_fw->data +
1592                                                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1593
1594                 adev->gfx.config.max_shader_engines = le32_to_cpu(gpu_info_fw->gc_num_se);
1595                 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gpu_info_fw->gc_num_cu_per_sh);
1596                 adev->gfx.config.max_sh_per_se = le32_to_cpu(gpu_info_fw->gc_num_sh_per_se);
1597                 adev->gfx.config.max_backends_per_se = le32_to_cpu(gpu_info_fw->gc_num_rb_per_se);
1598                 adev->gfx.config.max_texture_channel_caches =
1599                         le32_to_cpu(gpu_info_fw->gc_num_tccs);
1600                 adev->gfx.config.max_gprs = le32_to_cpu(gpu_info_fw->gc_num_gprs);
1601                 adev->gfx.config.max_gs_threads = le32_to_cpu(gpu_info_fw->gc_num_max_gs_thds);
1602                 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gpu_info_fw->gc_gs_table_depth);
1603                 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gpu_info_fw->gc_gsprim_buff_depth);
1604                 adev->gfx.config.double_offchip_lds_buf =
1605                         le32_to_cpu(gpu_info_fw->gc_double_offchip_lds_buffer);
1606                 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gpu_info_fw->gc_wave_size);
1607                 adev->gfx.cu_info.max_waves_per_simd =
1608                         le32_to_cpu(gpu_info_fw->gc_max_waves_per_simd);
1609                 adev->gfx.cu_info.max_scratch_slots_per_cu =
1610                         le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);
1611                 adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);
1612                 break;
1613         }
1614         default:
1615                 dev_err(adev->dev,
1616                         "Unsupported gpu_info table %d\n", hdr->header.ucode_version);
1617                 err = -EINVAL;
1618                 goto out;
1619         }
1620 out:
1621         return err;
1622 }
1623
1624 static int amdgpu_early_init(struct amdgpu_device *adev)
1625 {
1626         int i, r;
1627
1628         amdgpu_device_enable_virtual_display(adev);
1629
1630         switch (adev->asic_type) {
1631         case CHIP_TOPAZ:
1632         case CHIP_TONGA:
1633         case CHIP_FIJI:
1634         case CHIP_POLARIS11:
1635         case CHIP_POLARIS10:
1636         case CHIP_POLARIS12:
1637         case CHIP_CARRIZO:
1638         case CHIP_STONEY:
1639                 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY)
1640                         adev->family = AMDGPU_FAMILY_CZ;
1641                 else
1642                         adev->family = AMDGPU_FAMILY_VI;
1643
1644                 r = vi_set_ip_blocks(adev);
1645                 if (r)
1646                         return r;
1647                 break;
1648 #ifdef CONFIG_DRM_AMDGPU_SI
1649         case CHIP_VERDE:
1650         case CHIP_TAHITI:
1651         case CHIP_PITCAIRN:
1652         case CHIP_OLAND:
1653         case CHIP_HAINAN:
1654                 adev->family = AMDGPU_FAMILY_SI;
1655                 r = si_set_ip_blocks(adev);
1656                 if (r)
1657                         return r;
1658                 break;
1659 #endif
1660 #ifdef CONFIG_DRM_AMDGPU_CIK
1661         case CHIP_BONAIRE:
1662         case CHIP_HAWAII:
1663         case CHIP_KAVERI:
1664         case CHIP_KABINI:
1665         case CHIP_MULLINS:
1666                 if ((adev->asic_type == CHIP_BONAIRE) || (adev->asic_type == CHIP_HAWAII))
1667                         adev->family = AMDGPU_FAMILY_CI;
1668                 else
1669                         adev->family = AMDGPU_FAMILY_KV;
1670
1671                 r = cik_set_ip_blocks(adev);
1672                 if (r)
1673                         return r;
1674                 break;
1675 #endif
1676         case  CHIP_VEGA10:
1677         case  CHIP_RAVEN:
1678                 if (adev->asic_type == CHIP_RAVEN)
1679                         adev->family = AMDGPU_FAMILY_RV;
1680                 else
1681                         adev->family = AMDGPU_FAMILY_AI;
1682
1683                 r = soc15_set_ip_blocks(adev);
1684                 if (r)
1685                         return r;
1686                 break;
1687         default:
1688                 /* FIXME: not supported yet */
1689                 return -EINVAL;
1690         }
1691
1692         r = amdgpu_device_parse_gpu_info_fw(adev);
1693         if (r)
1694                 return r;
1695
1696         if (amdgpu_sriov_vf(adev)) {
1697                 r = amdgpu_virt_request_full_gpu(adev, true);
1698                 if (r)
1699                         return -EAGAIN;
1700         }
1701
1702         for (i = 0; i < adev->num_ip_blocks; i++) {
1703                 if ((amdgpu_ip_block_mask & (1 << i)) == 0) {
1704                         DRM_ERROR("disabled ip block: %d <%s>\n",
1705                                   i, adev->ip_blocks[i].version->funcs->name);
1706                         adev->ip_blocks[i].status.valid = false;
1707                 } else {
1708                         if (adev->ip_blocks[i].version->funcs->early_init) {
1709                                 r = adev->ip_blocks[i].version->funcs->early_init((void *)adev);
1710                                 if (r == -ENOENT) {
1711                                         adev->ip_blocks[i].status.valid = false;
1712                                 } else if (r) {
1713                                         DRM_ERROR("early_init of IP block <%s> failed %d\n",
1714                                                   adev->ip_blocks[i].version->funcs->name, r);
1715                                         return r;
1716                                 } else {
1717                                         adev->ip_blocks[i].status.valid = true;
1718                                 }
1719                         } else {
1720                                 adev->ip_blocks[i].status.valid = true;
1721                         }
1722                 }
1723         }
1724
1725         adev->cg_flags &= amdgpu_cg_mask;
1726         adev->pg_flags &= amdgpu_pg_mask;
1727
1728         return 0;
1729 }
1730
1731 static int amdgpu_init(struct amdgpu_device *adev)
1732 {
1733         int i, r;
1734
1735         for (i = 0; i < adev->num_ip_blocks; i++) {
1736                 if (!adev->ip_blocks[i].status.valid)
1737                         continue;
1738                 r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev);
1739                 if (r) {
1740                         DRM_ERROR("sw_init of IP block <%s> failed %d\n",
1741                                   adev->ip_blocks[i].version->funcs->name, r);
1742                         return r;
1743                 }
1744                 adev->ip_blocks[i].status.sw = true;
1745                 /* need to do gmc hw init early so we can allocate gpu mem */
1746                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1747                         r = amdgpu_vram_scratch_init(adev);
1748                         if (r) {
1749                                 DRM_ERROR("amdgpu_vram_scratch_init failed %d\n", r);
1750                                 return r;
1751                         }
1752                         r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1753                         if (r) {
1754                                 DRM_ERROR("hw_init %d failed %d\n", i, r);
1755                                 return r;
1756                         }
1757                         r = amdgpu_wb_init(adev);
1758                         if (r) {
1759                                 DRM_ERROR("amdgpu_wb_init failed %d\n", r);
1760                                 return r;
1761                         }
1762                         adev->ip_blocks[i].status.hw = true;
1763
1764                         /* right after GMC hw init, we create CSA */
1765                         if (amdgpu_sriov_vf(adev)) {
1766                                 r = amdgpu_allocate_static_csa(adev);
1767                                 if (r) {
1768                                         DRM_ERROR("allocate CSA failed %d\n", r);
1769                                         return r;
1770                                 }
1771                         }
1772                 }
1773         }
1774
1775         for (i = 0; i < adev->num_ip_blocks; i++) {
1776                 if (!adev->ip_blocks[i].status.sw)
1777                         continue;
1778                 /* gmc hw init is done early */
1779                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC)
1780                         continue;
1781                 r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev);
1782                 if (r) {
1783                         DRM_ERROR("hw_init of IP block <%s> failed %d\n",
1784                                   adev->ip_blocks[i].version->funcs->name, r);
1785                         return r;
1786                 }
1787                 adev->ip_blocks[i].status.hw = true;
1788         }
1789
1790         return 0;
1791 }
1792
1793 static void amdgpu_fill_reset_magic(struct amdgpu_device *adev)
1794 {
1795         memcpy(adev->reset_magic, adev->gart.ptr, AMDGPU_RESET_MAGIC_NUM);
1796 }
1797
1798 static bool amdgpu_check_vram_lost(struct amdgpu_device *adev)
1799 {
1800         return !!memcmp(adev->gart.ptr, adev->reset_magic,
1801                         AMDGPU_RESET_MAGIC_NUM);
1802 }
1803
1804 static int amdgpu_late_set_cg_state(struct amdgpu_device *adev)
1805 {
1806         int i = 0, r;
1807
1808         for (i = 0; i < adev->num_ip_blocks; i++) {
1809                 if (!adev->ip_blocks[i].status.valid)
1810                         continue;
1811                 /* skip CG for VCE/UVD, it's handled specially */
1812                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1813                     adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1814                         /* enable clockgating to save power */
1815                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1816                                                                                      AMD_CG_STATE_GATE);
1817                         if (r) {
1818                                 DRM_ERROR("set_clockgating_state(gate) of IP block <%s> failed %d\n",
1819                                           adev->ip_blocks[i].version->funcs->name, r);
1820                                 return r;
1821                         }
1822                 }
1823         }
1824         return 0;
1825 }
1826
1827 static int amdgpu_late_init(struct amdgpu_device *adev)
1828 {
1829         int i = 0, r;
1830
1831         for (i = 0; i < adev->num_ip_blocks; i++) {
1832                 if (!adev->ip_blocks[i].status.valid)
1833                         continue;
1834                 if (adev->ip_blocks[i].version->funcs->late_init) {
1835                         r = adev->ip_blocks[i].version->funcs->late_init((void *)adev);
1836                         if (r) {
1837                                 DRM_ERROR("late_init of IP block <%s> failed %d\n",
1838                                           adev->ip_blocks[i].version->funcs->name, r);
1839                                 return r;
1840                         }
1841                         adev->ip_blocks[i].status.late_initialized = true;
1842                 }
1843         }
1844
1845         mod_delayed_work(system_wq, &adev->late_init_work,
1846                         msecs_to_jiffies(AMDGPU_RESUME_MS));
1847
1848         amdgpu_fill_reset_magic(adev);
1849
1850         return 0;
1851 }
1852
1853 static int amdgpu_fini(struct amdgpu_device *adev)
1854 {
1855         int i, r;
1856
1857         /* need to disable SMC first */
1858         for (i = 0; i < adev->num_ip_blocks; i++) {
1859                 if (!adev->ip_blocks[i].status.hw)
1860                         continue;
1861                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) {
1862                         /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1863                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1864                                                                                      AMD_CG_STATE_UNGATE);
1865                         if (r) {
1866                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1867                                           adev->ip_blocks[i].version->funcs->name, r);
1868                                 return r;
1869                         }
1870                         r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1871                         /* XXX handle errors */
1872                         if (r) {
1873                                 DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1874                                           adev->ip_blocks[i].version->funcs->name, r);
1875                         }
1876                         adev->ip_blocks[i].status.hw = false;
1877                         break;
1878                 }
1879         }
1880
1881         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1882                 if (!adev->ip_blocks[i].status.hw)
1883                         continue;
1884                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) {
1885                         amdgpu_wb_fini(adev);
1886                         amdgpu_vram_scratch_fini(adev);
1887                 }
1888
1889                 if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
1890                         adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
1891                         /* ungate blocks before hw fini so that we can shutdown the blocks safely */
1892                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1893                                                                                      AMD_CG_STATE_UNGATE);
1894                         if (r) {
1895                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1896                                           adev->ip_blocks[i].version->funcs->name, r);
1897                                 return r;
1898                         }
1899                 }
1900
1901                 r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
1902                 /* XXX handle errors */
1903                 if (r) {
1904                         DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
1905                                   adev->ip_blocks[i].version->funcs->name, r);
1906                 }
1907
1908                 adev->ip_blocks[i].status.hw = false;
1909         }
1910
1911         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1912                 if (!adev->ip_blocks[i].status.sw)
1913                         continue;
1914                 r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev);
1915                 /* XXX handle errors */
1916                 if (r) {
1917                         DRM_DEBUG("sw_fini of IP block <%s> failed %d\n",
1918                                   adev->ip_blocks[i].version->funcs->name, r);
1919                 }
1920                 adev->ip_blocks[i].status.sw = false;
1921                 adev->ip_blocks[i].status.valid = false;
1922         }
1923
1924         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1925                 if (!adev->ip_blocks[i].status.late_initialized)
1926                         continue;
1927                 if (adev->ip_blocks[i].version->funcs->late_fini)
1928                         adev->ip_blocks[i].version->funcs->late_fini((void *)adev);
1929                 adev->ip_blocks[i].status.late_initialized = false;
1930         }
1931
1932         if (amdgpu_sriov_vf(adev))
1933                 amdgpu_virt_release_full_gpu(adev, false);
1934
1935         return 0;
1936 }
1937
1938 static void amdgpu_late_init_func_handler(struct work_struct *work)
1939 {
1940         struct amdgpu_device *adev =
1941                 container_of(work, struct amdgpu_device, late_init_work.work);
1942         amdgpu_late_set_cg_state(adev);
1943 }
1944
1945 int amdgpu_suspend(struct amdgpu_device *adev)
1946 {
1947         int i, r;
1948
1949         if (amdgpu_sriov_vf(adev))
1950                 amdgpu_virt_request_full_gpu(adev, false);
1951
1952         /* ungate SMC block first */
1953         r = amdgpu_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_SMC,
1954                                          AMD_CG_STATE_UNGATE);
1955         if (r) {
1956                 DRM_ERROR("set_clockgating_state(ungate) SMC failed %d\n",r);
1957         }
1958
1959         for (i = adev->num_ip_blocks - 1; i >= 0; i--) {
1960                 if (!adev->ip_blocks[i].status.valid)
1961                         continue;
1962                 /* ungate blocks so that suspend can properly shut them down */
1963                 if (i != AMD_IP_BLOCK_TYPE_SMC) {
1964                         r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
1965                                                                                      AMD_CG_STATE_UNGATE);
1966                         if (r) {
1967                                 DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
1968                                           adev->ip_blocks[i].version->funcs->name, r);
1969                         }
1970                 }
1971                 /* XXX handle errors */
1972                 r = adev->ip_blocks[i].version->funcs->suspend(adev);
1973                 /* XXX handle errors */
1974                 if (r) {
1975                         DRM_ERROR("suspend of IP block <%s> failed %d\n",
1976                                   adev->ip_blocks[i].version->funcs->name, r);
1977                 }
1978         }
1979
1980         if (amdgpu_sriov_vf(adev))
1981                 amdgpu_virt_release_full_gpu(adev, false);
1982
1983         return 0;
1984 }
1985
1986 static int amdgpu_sriov_reinit_early(struct amdgpu_device *adev)
1987 {
1988         int i, r;
1989
1990         static enum amd_ip_block_type ip_order[] = {
1991                 AMD_IP_BLOCK_TYPE_GMC,
1992                 AMD_IP_BLOCK_TYPE_COMMON,
1993                 AMD_IP_BLOCK_TYPE_IH,
1994         };
1995
1996         for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
1997                 int j;
1998                 struct amdgpu_ip_block *block;
1999
2000                 for (j = 0; j < adev->num_ip_blocks; j++) {
2001                         block = &adev->ip_blocks[j];
2002
2003                         if (block->version->type != ip_order[i] ||
2004                                 !block->status.valid)
2005                                 continue;
2006
2007                         r = block->version->funcs->hw_init(adev);
2008                         DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
2009                 }
2010         }
2011
2012         return 0;
2013 }
2014
2015 static int amdgpu_sriov_reinit_late(struct amdgpu_device *adev)
2016 {
2017         int i, r;
2018
2019         static enum amd_ip_block_type ip_order[] = {
2020                 AMD_IP_BLOCK_TYPE_SMC,
2021                 AMD_IP_BLOCK_TYPE_PSP,
2022                 AMD_IP_BLOCK_TYPE_DCE,
2023                 AMD_IP_BLOCK_TYPE_GFX,
2024                 AMD_IP_BLOCK_TYPE_SDMA,
2025                 AMD_IP_BLOCK_TYPE_UVD,
2026                 AMD_IP_BLOCK_TYPE_VCE
2027         };
2028
2029         for (i = 0; i < ARRAY_SIZE(ip_order); i++) {
2030                 int j;
2031                 struct amdgpu_ip_block *block;
2032
2033                 for (j = 0; j < adev->num_ip_blocks; j++) {
2034                         block = &adev->ip_blocks[j];
2035
2036                         if (block->version->type != ip_order[i] ||
2037                                 !block->status.valid)
2038                                 continue;
2039
2040                         r = block->version->funcs->hw_init(adev);
2041                         DRM_INFO("RE-INIT: %s %s\n", block->version->funcs->name, r?"failed":"successed");
2042                 }
2043         }
2044
2045         return 0;
2046 }
2047
2048 static int amdgpu_resume_phase1(struct amdgpu_device *adev)
2049 {
2050         int i, r;
2051
2052         for (i = 0; i < adev->num_ip_blocks; i++) {
2053                 if (!adev->ip_blocks[i].status.valid)
2054                         continue;
2055                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2056                                 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2057                                 adev->ip_blocks[i].version->type ==
2058                                 AMD_IP_BLOCK_TYPE_IH) {
2059                         r = adev->ip_blocks[i].version->funcs->resume(adev);
2060                         if (r) {
2061                                 DRM_ERROR("resume of IP block <%s> failed %d\n",
2062                                           adev->ip_blocks[i].version->funcs->name, r);
2063                                 return r;
2064                         }
2065                 }
2066         }
2067
2068         return 0;
2069 }
2070
2071 static int amdgpu_resume_phase2(struct amdgpu_device *adev)
2072 {
2073         int i, r;
2074
2075         for (i = 0; i < adev->num_ip_blocks; i++) {
2076                 if (!adev->ip_blocks[i].status.valid)
2077                         continue;
2078                 if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON ||
2079                                 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC ||
2080                                 adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH )
2081                         continue;
2082                 r = adev->ip_blocks[i].version->funcs->resume(adev);
2083                 if (r) {
2084                         DRM_ERROR("resume of IP block <%s> failed %d\n",
2085                                   adev->ip_blocks[i].version->funcs->name, r);
2086                         return r;
2087                 }
2088         }
2089
2090         return 0;
2091 }
2092
2093 static int amdgpu_resume(struct amdgpu_device *adev)
2094 {
2095         int r;
2096
2097         r = amdgpu_resume_phase1(adev);
2098         if (r)
2099                 return r;
2100         r = amdgpu_resume_phase2(adev);
2101
2102         return r;
2103 }
2104
2105 static void amdgpu_device_detect_sriov_bios(struct amdgpu_device *adev)
2106 {
2107         if (amdgpu_sriov_vf(adev)) {
2108                 if (adev->is_atom_fw) {
2109                         if (amdgpu_atomfirmware_gpu_supports_virtualization(adev))
2110                                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2111                 } else {
2112                         if (amdgpu_atombios_has_gpu_virtualization_table(adev))
2113                                 adev->virt.caps |= AMDGPU_SRIOV_CAPS_SRIOV_VBIOS;
2114                 }
2115
2116                 if (!(adev->virt.caps & AMDGPU_SRIOV_CAPS_SRIOV_VBIOS))
2117                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_NO_VBIOS, 0, 0);
2118         }
2119 }
2120
2121 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type)
2122 {
2123         switch (asic_type) {
2124 #if defined(CONFIG_DRM_AMD_DC)
2125         case CHIP_BONAIRE:
2126         case CHIP_HAWAII:
2127         case CHIP_KAVERI:
2128         case CHIP_CARRIZO:
2129         case CHIP_STONEY:
2130         case CHIP_POLARIS11:
2131         case CHIP_POLARIS10:
2132         case CHIP_POLARIS12:
2133         case CHIP_TONGA:
2134         case CHIP_FIJI:
2135 #if defined(CONFIG_DRM_AMD_DC_PRE_VEGA)
2136                 return amdgpu_dc != 0;
2137 #endif
2138         case CHIP_KABINI:
2139         case CHIP_MULLINS:
2140                 return amdgpu_dc > 0;
2141         case CHIP_VEGA10:
2142 #if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2143         case CHIP_RAVEN:
2144 #endif
2145                 return amdgpu_dc != 0;
2146 #endif
2147         default:
2148                 return false;
2149         }
2150 }
2151
2152 /**
2153  * amdgpu_device_has_dc_support - check if dc is supported
2154  *
2155  * @adev: amdgpu_device_pointer
2156  *
2157  * Returns true for supported, false for not supported
2158  */
2159 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev)
2160 {
2161         if (amdgpu_sriov_vf(adev))
2162                 return false;
2163
2164         return amdgpu_device_asic_has_dc_support(adev->asic_type);
2165 }
2166
2167 /**
2168  * amdgpu_device_init - initialize the driver
2169  *
2170  * @adev: amdgpu_device pointer
2171  * @pdev: drm dev pointer
2172  * @pdev: pci dev pointer
2173  * @flags: driver flags
2174  *
2175  * Initializes the driver info and hw (all asics).
2176  * Returns 0 for success or an error on failure.
2177  * Called at driver startup.
2178  */
2179 int amdgpu_device_init(struct amdgpu_device *adev,
2180                        struct drm_device *ddev,
2181                        struct pci_dev *pdev,
2182                        uint32_t flags)
2183 {
2184         int r, i;
2185         bool runtime = false;
2186         u32 max_MBps;
2187
2188         adev->shutdown = false;
2189         adev->dev = &pdev->dev;
2190         adev->ddev = ddev;
2191         adev->pdev = pdev;
2192         adev->flags = flags;
2193         adev->asic_type = flags & AMD_ASIC_MASK;
2194         adev->usec_timeout = AMDGPU_MAX_USEC_TIMEOUT;
2195         adev->mc.gart_size = 512 * 1024 * 1024;
2196         adev->accel_working = false;
2197         adev->num_rings = 0;
2198         adev->mman.buffer_funcs = NULL;
2199         adev->mman.buffer_funcs_ring = NULL;
2200         adev->vm_manager.vm_pte_funcs = NULL;
2201         adev->vm_manager.vm_pte_num_rings = 0;
2202         adev->gart.gart_funcs = NULL;
2203         adev->fence_context = dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2204         bitmap_zero(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2205
2206         adev->smc_rreg = &amdgpu_invalid_rreg;
2207         adev->smc_wreg = &amdgpu_invalid_wreg;
2208         adev->pcie_rreg = &amdgpu_invalid_rreg;
2209         adev->pcie_wreg = &amdgpu_invalid_wreg;
2210         adev->pciep_rreg = &amdgpu_invalid_rreg;
2211         adev->pciep_wreg = &amdgpu_invalid_wreg;
2212         adev->uvd_ctx_rreg = &amdgpu_invalid_rreg;
2213         adev->uvd_ctx_wreg = &amdgpu_invalid_wreg;
2214         adev->didt_rreg = &amdgpu_invalid_rreg;
2215         adev->didt_wreg = &amdgpu_invalid_wreg;
2216         adev->gc_cac_rreg = &amdgpu_invalid_rreg;
2217         adev->gc_cac_wreg = &amdgpu_invalid_wreg;
2218         adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg;
2219         adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg;
2220
2221         DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
2222                  amdgpu_asic_name[adev->asic_type], pdev->vendor, pdev->device,
2223                  pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
2224
2225         /* mutex initialization are all done here so we
2226          * can recall function without having locking issues */
2227         atomic_set(&adev->irq.ih.lock, 0);
2228         mutex_init(&adev->firmware.mutex);
2229         mutex_init(&adev->pm.mutex);
2230         mutex_init(&adev->gfx.gpu_clock_mutex);
2231         mutex_init(&adev->srbm_mutex);
2232         mutex_init(&adev->gfx.pipe_reserve_mutex);
2233         mutex_init(&adev->grbm_idx_mutex);
2234         mutex_init(&adev->mn_lock);
2235         mutex_init(&adev->virt.vf_errors.lock);
2236         hash_init(adev->mn_hash);
2237         mutex_init(&adev->lock_reset);
2238
2239         amdgpu_check_arguments(adev);
2240
2241         spin_lock_init(&adev->mmio_idx_lock);
2242         spin_lock_init(&adev->smc_idx_lock);
2243         spin_lock_init(&adev->pcie_idx_lock);
2244         spin_lock_init(&adev->uvd_ctx_idx_lock);
2245         spin_lock_init(&adev->didt_idx_lock);
2246         spin_lock_init(&adev->gc_cac_idx_lock);
2247         spin_lock_init(&adev->se_cac_idx_lock);
2248         spin_lock_init(&adev->audio_endpt_idx_lock);
2249         spin_lock_init(&adev->mm_stats.lock);
2250
2251         INIT_LIST_HEAD(&adev->shadow_list);
2252         mutex_init(&adev->shadow_list_lock);
2253
2254         INIT_LIST_HEAD(&adev->ring_lru_list);
2255         spin_lock_init(&adev->ring_lru_list_lock);
2256
2257         INIT_DELAYED_WORK(&adev->late_init_work, amdgpu_late_init_func_handler);
2258
2259         /* Registers mapping */
2260         /* TODO: block userspace mapping of io register */
2261         if (adev->asic_type >= CHIP_BONAIRE) {
2262                 adev->rmmio_base = pci_resource_start(adev->pdev, 5);
2263                 adev->rmmio_size = pci_resource_len(adev->pdev, 5);
2264         } else {
2265                 adev->rmmio_base = pci_resource_start(adev->pdev, 2);
2266                 adev->rmmio_size = pci_resource_len(adev->pdev, 2);
2267         }
2268
2269         adev->rmmio = ioremap(adev->rmmio_base, adev->rmmio_size);
2270         if (adev->rmmio == NULL) {
2271                 return -ENOMEM;
2272         }
2273         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)adev->rmmio_base);
2274         DRM_INFO("register mmio size: %u\n", (unsigned)adev->rmmio_size);
2275
2276         /* doorbell bar mapping */
2277         amdgpu_doorbell_init(adev);
2278
2279         /* io port mapping */
2280         for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
2281                 if (pci_resource_flags(adev->pdev, i) & IORESOURCE_IO) {
2282                         adev->rio_mem_size = pci_resource_len(adev->pdev, i);
2283                         adev->rio_mem = pci_iomap(adev->pdev, i, adev->rio_mem_size);
2284                         break;
2285                 }
2286         }
2287         if (adev->rio_mem == NULL)
2288                 DRM_INFO("PCI I/O BAR is not found.\n");
2289
2290         /* early init functions */
2291         r = amdgpu_early_init(adev);
2292         if (r)
2293                 return r;
2294
2295         /* if we have > 1 VGA cards, then disable the amdgpu VGA resources */
2296         /* this will fail for cards that aren't VGA class devices, just
2297          * ignore it */
2298         vga_client_register(adev->pdev, adev, NULL, amdgpu_vga_set_decode);
2299
2300         if (amdgpu_runtime_pm == 1)
2301                 runtime = true;
2302         if (amdgpu_device_is_px(ddev))
2303                 runtime = true;
2304         if (!pci_is_thunderbolt_attached(adev->pdev))
2305                 vga_switcheroo_register_client(adev->pdev,
2306                                                &amdgpu_switcheroo_ops, runtime);
2307         if (runtime)
2308                 vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain);
2309
2310         /* Read BIOS */
2311         if (!amdgpu_get_bios(adev)) {
2312                 r = -EINVAL;
2313                 goto failed;
2314         }
2315
2316         r = amdgpu_atombios_init(adev);
2317         if (r) {
2318                 dev_err(adev->dev, "amdgpu_atombios_init failed\n");
2319                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
2320                 goto failed;
2321         }
2322
2323         /* detect if we are with an SRIOV vbios */
2324         amdgpu_device_detect_sriov_bios(adev);
2325
2326         /* Post card if necessary */
2327         if (amdgpu_need_post(adev)) {
2328                 if (!adev->bios) {
2329                         dev_err(adev->dev, "no vBIOS found\n");
2330                         r = -EINVAL;
2331                         goto failed;
2332                 }
2333                 DRM_INFO("GPU posting now...\n");
2334                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2335                 if (r) {
2336                         dev_err(adev->dev, "gpu post error!\n");
2337                         goto failed;
2338                 }
2339         }
2340
2341         if (adev->is_atom_fw) {
2342                 /* Initialize clocks */
2343                 r = amdgpu_atomfirmware_get_clock_info(adev);
2344                 if (r) {
2345                         dev_err(adev->dev, "amdgpu_atomfirmware_get_clock_info failed\n");
2346                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2347                         goto failed;
2348                 }
2349         } else {
2350                 /* Initialize clocks */
2351                 r = amdgpu_atombios_get_clock_info(adev);
2352                 if (r) {
2353                         dev_err(adev->dev, "amdgpu_atombios_get_clock_info failed\n");
2354                         amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_GET_CLOCK_FAIL, 0, 0);
2355                         goto failed;
2356                 }
2357                 /* init i2c buses */
2358                 if (!amdgpu_device_has_dc_support(adev))
2359                         amdgpu_atombios_i2c_init(adev);
2360         }
2361
2362         /* Fence driver */
2363         r = amdgpu_fence_driver_init(adev);
2364         if (r) {
2365                 dev_err(adev->dev, "amdgpu_fence_driver_init failed\n");
2366                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_FENCE_INIT_FAIL, 0, 0);
2367                 goto failed;
2368         }
2369
2370         /* init the mode config */
2371         drm_mode_config_init(adev->ddev);
2372
2373         r = amdgpu_init(adev);
2374         if (r) {
2375                 /* failed in exclusive mode due to timeout */
2376                 if (amdgpu_sriov_vf(adev) &&
2377                     !amdgpu_sriov_runtime(adev) &&
2378                     amdgpu_virt_mmio_blocked(adev) &&
2379                     !amdgpu_virt_wait_reset(adev)) {
2380                         dev_err(adev->dev, "VF exclusive mode timeout\n");
2381                         r = -EAGAIN;
2382                         goto failed;
2383                 }
2384                 dev_err(adev->dev, "amdgpu_init failed\n");
2385                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_INIT_FAIL, 0, 0);
2386                 amdgpu_fini(adev);
2387                 goto failed;
2388         }
2389
2390         adev->accel_working = true;
2391
2392         amdgpu_vm_check_compute_bug(adev);
2393
2394         /* Initialize the buffer migration limit. */
2395         if (amdgpu_moverate >= 0)
2396                 max_MBps = amdgpu_moverate;
2397         else
2398                 max_MBps = 8; /* Allow 8 MB/s. */
2399         /* Get a log2 for easy divisions. */
2400         adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps));
2401
2402         r = amdgpu_ib_pool_init(adev);
2403         if (r) {
2404                 dev_err(adev->dev, "IB initialization failed (%d).\n", r);
2405                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_IB_INIT_FAIL, 0, r);
2406                 goto failed;
2407         }
2408
2409         r = amdgpu_ib_ring_tests(adev);
2410         if (r)
2411                 DRM_ERROR("ib ring test failed (%d).\n", r);
2412
2413         if (amdgpu_sriov_vf(adev))
2414                 amdgpu_virt_init_data_exchange(adev);
2415
2416         amdgpu_fbdev_init(adev);
2417
2418         r = amdgpu_pm_sysfs_init(adev);
2419         if (r)
2420                 DRM_ERROR("registering pm debugfs failed (%d).\n", r);
2421
2422         r = amdgpu_gem_debugfs_init(adev);
2423         if (r)
2424                 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
2425
2426         r = amdgpu_debugfs_regs_init(adev);
2427         if (r)
2428                 DRM_ERROR("registering register debugfs failed (%d).\n", r);
2429
2430         r = amdgpu_debugfs_test_ib_ring_init(adev);
2431         if (r)
2432                 DRM_ERROR("registering register test ib ring debugfs failed (%d).\n", r);
2433
2434         r = amdgpu_debugfs_firmware_init(adev);
2435         if (r)
2436                 DRM_ERROR("registering firmware debugfs failed (%d).\n", r);
2437
2438         r = amdgpu_debugfs_vbios_dump_init(adev);
2439         if (r)
2440                 DRM_ERROR("Creating vbios dump debugfs failed (%d).\n", r);
2441
2442         if ((amdgpu_testing & 1)) {
2443                 if (adev->accel_working)
2444                         amdgpu_test_moves(adev);
2445                 else
2446                         DRM_INFO("amdgpu: acceleration disabled, skipping move tests\n");
2447         }
2448         if (amdgpu_benchmarking) {
2449                 if (adev->accel_working)
2450                         amdgpu_benchmark(adev, amdgpu_benchmarking);
2451                 else
2452                         DRM_INFO("amdgpu: acceleration disabled, skipping benchmarks\n");
2453         }
2454
2455         /* enable clockgating, etc. after ib tests, etc. since some blocks require
2456          * explicit gating rather than handling it automatically.
2457          */
2458         r = amdgpu_late_init(adev);
2459         if (r) {
2460                 dev_err(adev->dev, "amdgpu_late_init failed\n");
2461                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_AMDGPU_LATE_INIT_FAIL, 0, r);
2462                 goto failed;
2463         }
2464
2465         return 0;
2466
2467 failed:
2468         amdgpu_vf_error_trans_all(adev);
2469         if (runtime)
2470                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2471
2472         return r;
2473 }
2474
2475 /**
2476  * amdgpu_device_fini - tear down the driver
2477  *
2478  * @adev: amdgpu_device pointer
2479  *
2480  * Tear down the driver info (all asics).
2481  * Called at driver shutdown.
2482  */
2483 void amdgpu_device_fini(struct amdgpu_device *adev)
2484 {
2485         int r;
2486
2487         DRM_INFO("amdgpu: finishing device.\n");
2488         adev->shutdown = true;
2489         if (adev->mode_info.mode_config_initialized)
2490                 drm_crtc_force_disable_all(adev->ddev);
2491         /* evict vram memory */
2492         amdgpu_bo_evict_vram(adev);
2493         amdgpu_ib_pool_fini(adev);
2494         amdgpu_fw_reserve_vram_fini(adev);
2495         amdgpu_fence_driver_fini(adev);
2496         amdgpu_fbdev_fini(adev);
2497         r = amdgpu_fini(adev);
2498         if (adev->firmware.gpu_info_fw) {
2499                 release_firmware(adev->firmware.gpu_info_fw);
2500                 adev->firmware.gpu_info_fw = NULL;
2501         }
2502         adev->accel_working = false;
2503         cancel_delayed_work_sync(&adev->late_init_work);
2504         /* free i2c buses */
2505         if (!amdgpu_device_has_dc_support(adev))
2506                 amdgpu_i2c_fini(adev);
2507         amdgpu_atombios_fini(adev);
2508         kfree(adev->bios);
2509         adev->bios = NULL;
2510         if (!pci_is_thunderbolt_attached(adev->pdev))
2511                 vga_switcheroo_unregister_client(adev->pdev);
2512         if (adev->flags & AMD_IS_PX)
2513                 vga_switcheroo_fini_domain_pm_ops(adev->dev);
2514         vga_client_register(adev->pdev, NULL, NULL, NULL);
2515         if (adev->rio_mem)
2516                 pci_iounmap(adev->pdev, adev->rio_mem);
2517         adev->rio_mem = NULL;
2518         iounmap(adev->rmmio);
2519         adev->rmmio = NULL;
2520         amdgpu_doorbell_fini(adev);
2521         amdgpu_pm_sysfs_fini(adev);
2522         amdgpu_debugfs_regs_cleanup(adev);
2523 }
2524
2525
2526 /*
2527  * Suspend & resume.
2528  */
2529 /**
2530  * amdgpu_device_suspend - initiate device suspend
2531  *
2532  * @pdev: drm dev pointer
2533  * @state: suspend state
2534  *
2535  * Puts the hw in the suspend state (all asics).
2536  * Returns 0 for success or an error on failure.
2537  * Called at driver suspend.
2538  */
2539 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon)
2540 {
2541         struct amdgpu_device *adev;
2542         struct drm_crtc *crtc;
2543         struct drm_connector *connector;
2544         int r;
2545
2546         if (dev == NULL || dev->dev_private == NULL) {
2547                 return -ENODEV;
2548         }
2549
2550         adev = dev->dev_private;
2551
2552         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2553                 return 0;
2554
2555         drm_kms_helper_poll_disable(dev);
2556
2557         if (!amdgpu_device_has_dc_support(adev)) {
2558                 /* turn off display hw */
2559                 drm_modeset_lock_all(dev);
2560                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2561                         drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
2562                 }
2563                 drm_modeset_unlock_all(dev);
2564         }
2565
2566         amdgpu_amdkfd_suspend(adev);
2567
2568         /* unpin the front buffers and cursors */
2569         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2570                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2571                 struct amdgpu_framebuffer *rfb = to_amdgpu_framebuffer(crtc->primary->fb);
2572                 struct amdgpu_bo *robj;
2573
2574                 if (amdgpu_crtc->cursor_bo) {
2575                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2576                         r = amdgpu_bo_reserve(aobj, true);
2577                         if (r == 0) {
2578                                 amdgpu_bo_unpin(aobj);
2579                                 amdgpu_bo_unreserve(aobj);
2580                         }
2581                 }
2582
2583                 if (rfb == NULL || rfb->obj == NULL) {
2584                         continue;
2585                 }
2586                 robj = gem_to_amdgpu_bo(rfb->obj);
2587                 /* don't unpin kernel fb objects */
2588                 if (!amdgpu_fbdev_robj_is_fb(adev, robj)) {
2589                         r = amdgpu_bo_reserve(robj, true);
2590                         if (r == 0) {
2591                                 amdgpu_bo_unpin(robj);
2592                                 amdgpu_bo_unreserve(robj);
2593                         }
2594                 }
2595         }
2596         /* evict vram memory */
2597         amdgpu_bo_evict_vram(adev);
2598
2599         amdgpu_fence_driver_suspend(adev);
2600
2601         r = amdgpu_suspend(adev);
2602
2603         /* evict remaining vram memory
2604          * This second call to evict vram is to evict the gart page table
2605          * using the CPU.
2606          */
2607         amdgpu_bo_evict_vram(adev);
2608
2609         amdgpu_atombios_scratch_regs_save(adev);
2610         pci_save_state(dev->pdev);
2611         if (suspend) {
2612                 /* Shut down the device */
2613                 pci_disable_device(dev->pdev);
2614                 pci_set_power_state(dev->pdev, PCI_D3hot);
2615         } else {
2616                 r = amdgpu_asic_reset(adev);
2617                 if (r)
2618                         DRM_ERROR("amdgpu asic reset failed\n");
2619         }
2620
2621         if (fbcon) {
2622                 console_lock();
2623                 amdgpu_fbdev_set_suspend(adev, 1);
2624                 console_unlock();
2625         }
2626         return 0;
2627 }
2628
2629 /**
2630  * amdgpu_device_resume - initiate device resume
2631  *
2632  * @pdev: drm dev pointer
2633  *
2634  * Bring the hw back to operating state (all asics).
2635  * Returns 0 for success or an error on failure.
2636  * Called at driver resume.
2637  */
2638 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon)
2639 {
2640         struct drm_connector *connector;
2641         struct amdgpu_device *adev = dev->dev_private;
2642         struct drm_crtc *crtc;
2643         int r = 0;
2644
2645         if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
2646                 return 0;
2647
2648         if (fbcon)
2649                 console_lock();
2650
2651         if (resume) {
2652                 pci_set_power_state(dev->pdev, PCI_D0);
2653                 pci_restore_state(dev->pdev);
2654                 r = pci_enable_device(dev->pdev);
2655                 if (r)
2656                         goto unlock;
2657         }
2658         amdgpu_atombios_scratch_regs_restore(adev);
2659
2660         /* post card */
2661         if (amdgpu_need_post(adev)) {
2662                 r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
2663                 if (r)
2664                         DRM_ERROR("amdgpu asic init failed\n");
2665         }
2666
2667         r = amdgpu_resume(adev);
2668         if (r) {
2669                 DRM_ERROR("amdgpu_resume failed (%d).\n", r);
2670                 goto unlock;
2671         }
2672         amdgpu_fence_driver_resume(adev);
2673
2674         if (resume) {
2675                 r = amdgpu_ib_ring_tests(adev);
2676                 if (r)
2677                         DRM_ERROR("ib ring test failed (%d).\n", r);
2678         }
2679
2680         r = amdgpu_late_init(adev);
2681         if (r)
2682                 goto unlock;
2683
2684         /* pin cursors */
2685         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2686                 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2687
2688                 if (amdgpu_crtc->cursor_bo) {
2689                         struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2690                         r = amdgpu_bo_reserve(aobj, true);
2691                         if (r == 0) {
2692                                 r = amdgpu_bo_pin(aobj,
2693                                                   AMDGPU_GEM_DOMAIN_VRAM,
2694                                                   &amdgpu_crtc->cursor_addr);
2695                                 if (r != 0)
2696                                         DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
2697                                 amdgpu_bo_unreserve(aobj);
2698                         }
2699                 }
2700         }
2701         r = amdgpu_amdkfd_resume(adev);
2702         if (r)
2703                 return r;
2704
2705         /* blat the mode back in */
2706         if (fbcon) {
2707                 if (!amdgpu_device_has_dc_support(adev)) {
2708                         /* pre DCE11 */
2709                         drm_helper_resume_force_mode(dev);
2710
2711                         /* turn on display hw */
2712                         drm_modeset_lock_all(dev);
2713                         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2714                                 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
2715                         }
2716                         drm_modeset_unlock_all(dev);
2717                 } else {
2718                         /*
2719                          * There is no equivalent atomic helper to turn on
2720                          * display, so we defined our own function for this,
2721                          * once suspend resume is supported by the atomic
2722                          * framework this will be reworked
2723                          */
2724                         amdgpu_dm_display_resume(adev);
2725                 }
2726         }
2727
2728         drm_kms_helper_poll_enable(dev);
2729
2730         /*
2731          * Most of the connector probing functions try to acquire runtime pm
2732          * refs to ensure that the GPU is powered on when connector polling is
2733          * performed. Since we're calling this from a runtime PM callback,
2734          * trying to acquire rpm refs will cause us to deadlock.
2735          *
2736          * Since we're guaranteed to be holding the rpm lock, it's safe to
2737          * temporarily disable the rpm helpers so this doesn't deadlock us.
2738          */
2739 #ifdef CONFIG_PM
2740         dev->dev->power.disable_depth++;
2741 #endif
2742         if (!amdgpu_device_has_dc_support(adev))
2743                 drm_helper_hpd_irq_event(dev);
2744         else
2745                 drm_kms_helper_hotplug_event(dev);
2746 #ifdef CONFIG_PM
2747         dev->dev->power.disable_depth--;
2748 #endif
2749
2750         if (fbcon)
2751                 amdgpu_fbdev_set_suspend(adev, 0);
2752
2753 unlock:
2754         if (fbcon)
2755                 console_unlock();
2756
2757         return r;
2758 }
2759
2760 static bool amdgpu_check_soft_reset(struct amdgpu_device *adev)
2761 {
2762         int i;
2763         bool asic_hang = false;
2764
2765         if (amdgpu_sriov_vf(adev))
2766                 return true;
2767
2768         for (i = 0; i < adev->num_ip_blocks; i++) {
2769                 if (!adev->ip_blocks[i].status.valid)
2770                         continue;
2771                 if (adev->ip_blocks[i].version->funcs->check_soft_reset)
2772                         adev->ip_blocks[i].status.hang =
2773                                 adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
2774                 if (adev->ip_blocks[i].status.hang) {
2775                         DRM_INFO("IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
2776                         asic_hang = true;
2777                 }
2778         }
2779         return asic_hang;
2780 }
2781
2782 static int amdgpu_pre_soft_reset(struct amdgpu_device *adev)
2783 {
2784         int i, r = 0;
2785
2786         for (i = 0; i < adev->num_ip_blocks; i++) {
2787                 if (!adev->ip_blocks[i].status.valid)
2788                         continue;
2789                 if (adev->ip_blocks[i].status.hang &&
2790                     adev->ip_blocks[i].version->funcs->pre_soft_reset) {
2791                         r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev);
2792                         if (r)
2793                                 return r;
2794                 }
2795         }
2796
2797         return 0;
2798 }
2799
2800 static bool amdgpu_need_full_reset(struct amdgpu_device *adev)
2801 {
2802         int i;
2803
2804         for (i = 0; i < adev->num_ip_blocks; i++) {
2805                 if (!adev->ip_blocks[i].status.valid)
2806                         continue;
2807                 if ((adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC) ||
2808                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) ||
2809                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_ACP) ||
2810                     (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) ||
2811                      adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) {
2812                         if (adev->ip_blocks[i].status.hang) {
2813                                 DRM_INFO("Some block need full reset!\n");
2814                                 return true;
2815                         }
2816                 }
2817         }
2818         return false;
2819 }
2820
2821 static int amdgpu_soft_reset(struct amdgpu_device *adev)
2822 {
2823         int i, r = 0;
2824
2825         for (i = 0; i < adev->num_ip_blocks; i++) {
2826                 if (!adev->ip_blocks[i].status.valid)
2827                         continue;
2828                 if (adev->ip_blocks[i].status.hang &&
2829                     adev->ip_blocks[i].version->funcs->soft_reset) {
2830                         r = adev->ip_blocks[i].version->funcs->soft_reset(adev);
2831                         if (r)
2832                                 return r;
2833                 }
2834         }
2835
2836         return 0;
2837 }
2838
2839 static int amdgpu_post_soft_reset(struct amdgpu_device *adev)
2840 {
2841         int i, r = 0;
2842
2843         for (i = 0; i < adev->num_ip_blocks; i++) {
2844                 if (!adev->ip_blocks[i].status.valid)
2845                         continue;
2846                 if (adev->ip_blocks[i].status.hang &&
2847                     adev->ip_blocks[i].version->funcs->post_soft_reset)
2848                         r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev);
2849                 if (r)
2850                         return r;
2851         }
2852
2853         return 0;
2854 }
2855
2856 bool amdgpu_need_backup(struct amdgpu_device *adev)
2857 {
2858         if (adev->flags & AMD_IS_APU)
2859                 return false;
2860
2861         return amdgpu_lockup_timeout > 0 ? true : false;
2862 }
2863
2864 static int amdgpu_recover_vram_from_shadow(struct amdgpu_device *adev,
2865                                            struct amdgpu_ring *ring,
2866                                            struct amdgpu_bo *bo,
2867                                            struct dma_fence **fence)
2868 {
2869         uint32_t domain;
2870         int r;
2871
2872         if (!bo->shadow)
2873                 return 0;
2874
2875         r = amdgpu_bo_reserve(bo, true);
2876         if (r)
2877                 return r;
2878         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
2879         /* if bo has been evicted, then no need to recover */
2880         if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
2881                 r = amdgpu_bo_validate(bo->shadow);
2882                 if (r) {
2883                         DRM_ERROR("bo validate failed!\n");
2884                         goto err;
2885                 }
2886
2887                 r = amdgpu_bo_restore_from_shadow(adev, ring, bo,
2888                                                  NULL, fence, true);
2889                 if (r) {
2890                         DRM_ERROR("recover page table failed!\n");
2891                         goto err;
2892                 }
2893         }
2894 err:
2895         amdgpu_bo_unreserve(bo);
2896         return r;
2897 }
2898
2899 /*
2900  * amdgpu_reset - reset ASIC/GPU for bare-metal or passthrough
2901  *
2902  * @adev: amdgpu device pointer
2903  * @reset_flags: output param tells caller the reset result
2904  *
2905  * attempt to do soft-reset or full-reset and reinitialize Asic
2906  * return 0 means successed otherwise failed
2907 */
2908 static int amdgpu_reset(struct amdgpu_device *adev, uint64_t* reset_flags)
2909 {
2910         bool need_full_reset, vram_lost = 0;
2911         int r;
2912
2913         need_full_reset = amdgpu_need_full_reset(adev);
2914
2915         if (!need_full_reset) {
2916                 amdgpu_pre_soft_reset(adev);
2917                 r = amdgpu_soft_reset(adev);
2918                 amdgpu_post_soft_reset(adev);
2919                 if (r || amdgpu_check_soft_reset(adev)) {
2920                         DRM_INFO("soft reset failed, will fallback to full reset!\n");
2921                         need_full_reset = true;
2922                 }
2923
2924         }
2925
2926         if (need_full_reset) {
2927                 r = amdgpu_suspend(adev);
2928
2929 retry:
2930                 amdgpu_atombios_scratch_regs_save(adev);
2931                 r = amdgpu_asic_reset(adev);
2932                 amdgpu_atombios_scratch_regs_restore(adev);
2933                 /* post card */
2934                 amdgpu_atom_asic_init(adev->mode_info.atom_context);
2935
2936                 if (!r) {
2937                         dev_info(adev->dev, "GPU reset succeeded, trying to resume\n");
2938                         r = amdgpu_resume_phase1(adev);
2939                         if (r)
2940                                 goto out;
2941
2942                         vram_lost = amdgpu_check_vram_lost(adev);
2943                         if (vram_lost) {
2944                                 DRM_ERROR("VRAM is lost!\n");
2945                                 atomic_inc(&adev->vram_lost_counter);
2946                         }
2947
2948                         r = amdgpu_gtt_mgr_recover(
2949                                 &adev->mman.bdev.man[TTM_PL_TT]);
2950                         if (r)
2951                                 goto out;
2952
2953                         r = amdgpu_resume_phase2(adev);
2954                         if (r)
2955                                 goto out;
2956
2957                         if (vram_lost)
2958                                 amdgpu_fill_reset_magic(adev);
2959                 }
2960         }
2961
2962 out:
2963         if (!r) {
2964                 amdgpu_irq_gpu_reset_resume_helper(adev);
2965                 r = amdgpu_ib_ring_tests(adev);
2966                 if (r) {
2967                         dev_err(adev->dev, "ib ring test failed (%d).\n", r);
2968                         r = amdgpu_suspend(adev);
2969                         need_full_reset = true;
2970                         goto retry;
2971                 }
2972         }
2973
2974         if (reset_flags) {
2975                 if (vram_lost)
2976                         (*reset_flags) |= AMDGPU_RESET_INFO_VRAM_LOST;
2977
2978                 if (need_full_reset)
2979                         (*reset_flags) |= AMDGPU_RESET_INFO_FULLRESET;
2980         }
2981
2982         return r;
2983 }
2984
2985 /*
2986  * amdgpu_reset_sriov - reset ASIC for SR-IOV vf
2987  *
2988  * @adev: amdgpu device pointer
2989  * @reset_flags: output param tells caller the reset result
2990  *
2991  * do VF FLR and reinitialize Asic
2992  * return 0 means successed otherwise failed
2993 */
2994 static int amdgpu_reset_sriov(struct amdgpu_device *adev, uint64_t *reset_flags, bool from_hypervisor)
2995 {
2996         int r;
2997
2998         if (from_hypervisor)
2999                 r = amdgpu_virt_request_full_gpu(adev, true);
3000         else
3001                 r = amdgpu_virt_reset_gpu(adev);
3002         if (r)
3003                 return r;
3004
3005         /* Resume IP prior to SMC */
3006         r = amdgpu_sriov_reinit_early(adev);
3007         if (r)
3008                 goto error;
3009
3010         /* we need recover gart prior to run SMC/CP/SDMA resume */
3011         amdgpu_gtt_mgr_recover(&adev->mman.bdev.man[TTM_PL_TT]);
3012
3013         /* now we are okay to resume SMC/CP/SDMA */
3014         r = amdgpu_sriov_reinit_late(adev);
3015         if (r)
3016                 goto error;
3017
3018         amdgpu_irq_gpu_reset_resume_helper(adev);
3019         r = amdgpu_ib_ring_tests(adev);
3020         if (r)
3021                 dev_err(adev->dev, "[GPU_RESET] ib ring test failed (%d).\n", r);
3022
3023 error:
3024         /* release full control of GPU after ib test */
3025         amdgpu_virt_release_full_gpu(adev, true);
3026
3027         if (reset_flags) {
3028                 /* will get vram_lost from GIM in future, now all
3029                  * reset request considered VRAM LOST
3030                  */
3031                 (*reset_flags) |= ~AMDGPU_RESET_INFO_VRAM_LOST;
3032                 atomic_inc(&adev->vram_lost_counter);
3033
3034                 /* VF FLR or hotlink reset is always full-reset */
3035                 (*reset_flags) |= AMDGPU_RESET_INFO_FULLRESET;
3036         }
3037
3038         return r;
3039 }
3040
3041 /**
3042  * amdgpu_gpu_recover - reset the asic and recover scheduler
3043  *
3044  * @adev: amdgpu device pointer
3045  * @job: which job trigger hang
3046  *
3047  * Attempt to reset the GPU if it has hung (all asics).
3048  * Returns 0 for success or an error on failure.
3049  */
3050 int amdgpu_gpu_recover(struct amdgpu_device *adev, struct amdgpu_job *job)
3051 {
3052         struct drm_atomic_state *state = NULL;
3053         uint64_t reset_flags = 0;
3054         int i, r, resched;
3055
3056         if (!amdgpu_check_soft_reset(adev)) {
3057                 DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
3058                 return 0;
3059         }
3060
3061         dev_info(adev->dev, "GPU reset begin!\n");
3062
3063         mutex_lock(&adev->lock_reset);
3064         atomic_inc(&adev->gpu_reset_counter);
3065         adev->in_gpu_reset = 1;
3066
3067         /* block TTM */
3068         resched = ttm_bo_lock_delayed_workqueue(&adev->mman.bdev);
3069         /* store modesetting */
3070         if (amdgpu_device_has_dc_support(adev))
3071                 state = drm_atomic_helper_suspend(adev->ddev);
3072
3073         /* block scheduler */
3074         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3075                 struct amdgpu_ring *ring = adev->rings[i];
3076
3077                 if (!ring || !ring->sched.thread)
3078                         continue;
3079
3080                 /* only focus on the ring hit timeout if &job not NULL */
3081                 if (job && job->ring->idx != i)
3082                         continue;
3083
3084                 kthread_park(ring->sched.thread);
3085                 amd_sched_hw_job_reset(&ring->sched, &job->base);
3086
3087                 /* after all hw jobs are reset, hw fence is meaningless, so force_completion */
3088                 amdgpu_fence_driver_force_completion(ring);
3089         }
3090
3091         if (amdgpu_sriov_vf(adev))
3092                 r = amdgpu_reset_sriov(adev, &reset_flags, job ? false : true);
3093         else
3094                 r = amdgpu_reset(adev, &reset_flags);
3095
3096         if (!r) {
3097                 if (((reset_flags & AMDGPU_RESET_INFO_FULLRESET) && !(adev->flags & AMD_IS_APU)) ||
3098                         (reset_flags & AMDGPU_RESET_INFO_VRAM_LOST)) {
3099                         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
3100                         struct amdgpu_bo *bo, *tmp;
3101                         struct dma_fence *fence = NULL, *next = NULL;
3102
3103                         DRM_INFO("recover vram bo from shadow\n");
3104                         mutex_lock(&adev->shadow_list_lock);
3105                         list_for_each_entry_safe(bo, tmp, &adev->shadow_list, shadow_list) {
3106                                 next = NULL;
3107                                 amdgpu_recover_vram_from_shadow(adev, ring, bo, &next);
3108                                 if (fence) {
3109                                         r = dma_fence_wait(fence, false);
3110                                         if (r) {
3111                                                 WARN(r, "recovery from shadow isn't completed\n");
3112                                                 break;
3113                                         }
3114                                 }
3115
3116                                 dma_fence_put(fence);
3117                                 fence = next;
3118                         }
3119                         mutex_unlock(&adev->shadow_list_lock);
3120                         if (fence) {
3121                                 r = dma_fence_wait(fence, false);
3122                                 if (r)
3123                                         WARN(r, "recovery from shadow isn't completed\n");
3124                         }
3125                         dma_fence_put(fence);
3126                 }
3127
3128                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3129                         struct amdgpu_ring *ring = adev->rings[i];
3130
3131                         if (!ring || !ring->sched.thread)
3132                                 continue;
3133
3134                         /* only focus on the ring hit timeout if &job not NULL */
3135                         if (job && job->ring->idx != i)
3136                                 continue;
3137
3138                         amd_sched_job_recovery(&ring->sched);
3139                         kthread_unpark(ring->sched.thread);
3140                 }
3141         } else {
3142                 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
3143                         struct amdgpu_ring *ring = adev->rings[i];
3144
3145                         if (!ring || !ring->sched.thread)
3146                                 continue;
3147
3148                         /* only focus on the ring hit timeout if &job not NULL */
3149                         if (job && job->ring->idx != i)
3150                                 continue;
3151
3152                         kthread_unpark(adev->rings[i]->sched.thread);
3153                 }
3154         }
3155
3156         if (amdgpu_device_has_dc_support(adev)) {
3157                 if (drm_atomic_helper_resume(adev->ddev, state))
3158                         dev_info(adev->dev, "drm resume failed:%d\n", r);
3159                 amdgpu_dm_display_resume(adev);
3160         } else {
3161                 drm_helper_resume_force_mode(adev->ddev);
3162         }
3163
3164         ttm_bo_unlock_delayed_workqueue(&adev->mman.bdev, resched);
3165
3166         if (r) {
3167                 /* bad news, how to tell it to userspace ? */
3168                 dev_info(adev->dev, "GPU reset(%d) failed\n", atomic_read(&adev->gpu_reset_counter));
3169                 amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_GPU_RESET_FAIL, 0, r);
3170         } else {
3171                 dev_info(adev->dev, "GPU reset(%d) successed!\n",atomic_read(&adev->gpu_reset_counter));
3172         }
3173
3174         amdgpu_vf_error_trans_all(adev);
3175         adev->in_gpu_reset = 0;
3176         mutex_unlock(&adev->lock_reset);
3177         return r;
3178 }
3179
3180 void amdgpu_get_pcie_info(struct amdgpu_device *adev)
3181 {
3182         u32 mask;
3183         int ret;
3184
3185         if (amdgpu_pcie_gen_cap)
3186                 adev->pm.pcie_gen_mask = amdgpu_pcie_gen_cap;
3187
3188         if (amdgpu_pcie_lane_cap)
3189                 adev->pm.pcie_mlw_mask = amdgpu_pcie_lane_cap;
3190
3191         /* covers APUs as well */
3192         if (pci_is_root_bus(adev->pdev->bus)) {
3193                 if (adev->pm.pcie_gen_mask == 0)
3194                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
3195                 if (adev->pm.pcie_mlw_mask == 0)
3196                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3197                 return;
3198         }
3199
3200         if (adev->pm.pcie_gen_mask == 0) {
3201                 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
3202                 if (!ret) {
3203                         adev->pm.pcie_gen_mask = (CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 |
3204                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 |
3205                                                   CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3);
3206
3207                         if (mask & DRM_PCIE_SPEED_25)
3208                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1;
3209                         if (mask & DRM_PCIE_SPEED_50)
3210                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2;
3211                         if (mask & DRM_PCIE_SPEED_80)
3212                                 adev->pm.pcie_gen_mask |= CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3;
3213                 } else {
3214                         adev->pm.pcie_gen_mask = AMDGPU_DEFAULT_PCIE_GEN_MASK;
3215                 }
3216         }
3217         if (adev->pm.pcie_mlw_mask == 0) {
3218                 ret = drm_pcie_get_max_link_width(adev->ddev, &mask);
3219                 if (!ret) {
3220                         switch (mask) {
3221                         case 32:
3222                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 |
3223                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3224                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3225                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3226                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3227                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3228                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3229                                 break;
3230                         case 16:
3231                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 |
3232                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3233                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3234                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3235                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3236                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3237                                 break;
3238                         case 12:
3239                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 |
3240                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3241                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3242                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3243                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3244                                 break;
3245                         case 8:
3246                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 |
3247                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3248                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3249                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3250                                 break;
3251                         case 4:
3252                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 |
3253                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3254                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3255                                 break;
3256                         case 2:
3257                                 adev->pm.pcie_mlw_mask = (CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 |
3258                                                           CAIL_PCIE_LINK_WIDTH_SUPPORT_X1);
3259                                 break;
3260                         case 1:
3261                                 adev->pm.pcie_mlw_mask = CAIL_PCIE_LINK_WIDTH_SUPPORT_X1;
3262                                 break;
3263                         default:
3264                                 break;
3265                         }
3266                 } else {
3267                         adev->pm.pcie_mlw_mask = AMDGPU_DEFAULT_PCIE_MLW_MASK;
3268                 }
3269         }
3270 }
3271
3272 /*
3273  * Debugfs
3274  */
3275 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
3276                              const struct drm_info_list *files,
3277                              unsigned nfiles)
3278 {
3279         unsigned i;
3280
3281         for (i = 0; i < adev->debugfs_count; i++) {
3282                 if (adev->debugfs[i].files == files) {
3283                         /* Already registered */
3284                         return 0;
3285                 }
3286         }
3287
3288         i = adev->debugfs_count + 1;
3289         if (i > AMDGPU_DEBUGFS_MAX_COMPONENTS) {
3290                 DRM_ERROR("Reached maximum number of debugfs components.\n");
3291                 DRM_ERROR("Report so we increase "
3292                           "AMDGPU_DEBUGFS_MAX_COMPONENTS.\n");
3293                 return -EINVAL;
3294         }
3295         adev->debugfs[adev->debugfs_count].files = files;
3296         adev->debugfs[adev->debugfs_count].num_files = nfiles;
3297         adev->debugfs_count = i;
3298 #if defined(CONFIG_DEBUG_FS)
3299         drm_debugfs_create_files(files, nfiles,
3300                                  adev->ddev->primary->debugfs_root,
3301                                  adev->ddev->primary);
3302 #endif
3303         return 0;
3304 }
3305
3306 #if defined(CONFIG_DEBUG_FS)
3307
3308 static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
3309                                         size_t size, loff_t *pos)
3310 {
3311         struct amdgpu_device *adev = file_inode(f)->i_private;
3312         ssize_t result = 0;
3313         int r;
3314         bool pm_pg_lock, use_bank;
3315         unsigned instance_bank, sh_bank, se_bank;
3316
3317         if (size & 0x3 || *pos & 0x3)
3318                 return -EINVAL;
3319
3320         /* are we reading registers for which a PG lock is necessary? */
3321         pm_pg_lock = (*pos >> 23) & 1;
3322
3323         if (*pos & (1ULL << 62)) {
3324                 se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
3325                 sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
3326                 instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
3327
3328                 if (se_bank == 0x3FF)
3329                         se_bank = 0xFFFFFFFF;
3330                 if (sh_bank == 0x3FF)
3331                         sh_bank = 0xFFFFFFFF;
3332                 if (instance_bank == 0x3FF)
3333                         instance_bank = 0xFFFFFFFF;
3334                 use_bank = 1;
3335         } else {
3336                 use_bank = 0;
3337         }
3338
3339         *pos &= (1UL << 22) - 1;
3340
3341         if (use_bank) {
3342                 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
3343                     (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
3344                         return -EINVAL;
3345                 mutex_lock(&adev->grbm_idx_mutex);
3346                 amdgpu_gfx_select_se_sh(adev, se_bank,
3347                                         sh_bank, instance_bank);
3348         }
3349
3350         if (pm_pg_lock)
3351                 mutex_lock(&adev->pm.mutex);
3352
3353         while (size) {
3354                 uint32_t value;
3355
3356                 if (*pos > adev->rmmio_size)
3357                         goto end;
3358
3359                 value = RREG32(*pos >> 2);
3360                 r = put_user(value, (uint32_t *)buf);
3361                 if (r) {
3362                         result = r;
3363                         goto end;
3364                 }
3365
3366                 result += 4;
3367                 buf += 4;
3368                 *pos += 4;
3369                 size -= 4;
3370         }
3371
3372 end:
3373         if (use_bank) {
3374                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3375                 mutex_unlock(&adev->grbm_idx_mutex);
3376         }
3377
3378         if (pm_pg_lock)
3379                 mutex_unlock(&adev->pm.mutex);
3380
3381         return result;
3382 }
3383
3384 static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
3385                                          size_t size, loff_t *pos)
3386 {
3387         struct amdgpu_device *adev = file_inode(f)->i_private;
3388         ssize_t result = 0;
3389         int r;
3390         bool pm_pg_lock, use_bank;
3391         unsigned instance_bank, sh_bank, se_bank;
3392
3393         if (size & 0x3 || *pos & 0x3)
3394                 return -EINVAL;
3395
3396         /* are we reading registers for which a PG lock is necessary? */
3397         pm_pg_lock = (*pos >> 23) & 1;
3398
3399         if (*pos & (1ULL << 62)) {
3400                 se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
3401                 sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
3402                 instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
3403
3404                 if (se_bank == 0x3FF)
3405                         se_bank = 0xFFFFFFFF;
3406                 if (sh_bank == 0x3FF)
3407                         sh_bank = 0xFFFFFFFF;
3408                 if (instance_bank == 0x3FF)
3409                         instance_bank = 0xFFFFFFFF;
3410                 use_bank = 1;
3411         } else {
3412                 use_bank = 0;
3413         }
3414
3415         *pos &= (1UL << 22) - 1;
3416
3417         if (use_bank) {
3418                 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
3419                     (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
3420                         return -EINVAL;
3421                 mutex_lock(&adev->grbm_idx_mutex);
3422                 amdgpu_gfx_select_se_sh(adev, se_bank,
3423                                         sh_bank, instance_bank);
3424         }
3425
3426         if (pm_pg_lock)
3427                 mutex_lock(&adev->pm.mutex);
3428
3429         while (size) {
3430                 uint32_t value;
3431
3432                 if (*pos > adev->rmmio_size)
3433                         return result;
3434
3435                 r = get_user(value, (uint32_t *)buf);
3436                 if (r)
3437                         return r;
3438
3439                 WREG32(*pos >> 2, value);
3440
3441                 result += 4;
3442                 buf += 4;
3443                 *pos += 4;
3444                 size -= 4;
3445         }
3446
3447         if (use_bank) {
3448                 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3449                 mutex_unlock(&adev->grbm_idx_mutex);
3450         }
3451
3452         if (pm_pg_lock)
3453                 mutex_unlock(&adev->pm.mutex);
3454
3455         return result;
3456 }
3457
3458 static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,
3459                                         size_t size, loff_t *pos)
3460 {
3461         struct amdgpu_device *adev = file_inode(f)->i_private;
3462         ssize_t result = 0;
3463         int r;
3464
3465         if (size & 0x3 || *pos & 0x3)
3466                 return -EINVAL;
3467
3468         while (size) {
3469                 uint32_t value;
3470
3471                 value = RREG32_PCIE(*pos >> 2);
3472                 r = put_user(value, (uint32_t *)buf);
3473                 if (r)
3474                         return r;
3475
3476                 result += 4;
3477                 buf += 4;
3478                 *pos += 4;
3479                 size -= 4;
3480         }
3481
3482         return result;
3483 }
3484
3485 static ssize_t amdgpu_debugfs_regs_pcie_write(struct file *f, const char __user *buf,
3486                                          size_t size, loff_t *pos)
3487 {
3488         struct amdgpu_device *adev = file_inode(f)->i_private;
3489         ssize_t result = 0;
3490         int r;
3491
3492         if (size & 0x3 || *pos & 0x3)
3493                 return -EINVAL;
3494
3495         while (size) {
3496                 uint32_t value;
3497
3498                 r = get_user(value, (uint32_t *)buf);
3499                 if (r)
3500                         return r;
3501
3502                 WREG32_PCIE(*pos >> 2, value);
3503
3504                 result += 4;
3505                 buf += 4;
3506                 *pos += 4;
3507                 size -= 4;
3508         }
3509
3510         return result;
3511 }
3512
3513 static ssize_t amdgpu_debugfs_regs_didt_read(struct file *f, char __user *buf,
3514                                         size_t size, loff_t *pos)
3515 {
3516         struct amdgpu_device *adev = file_inode(f)->i_private;
3517         ssize_t result = 0;
3518         int r;
3519
3520         if (size & 0x3 || *pos & 0x3)
3521                 return -EINVAL;
3522
3523         while (size) {
3524                 uint32_t value;
3525
3526                 value = RREG32_DIDT(*pos >> 2);
3527                 r = put_user(value, (uint32_t *)buf);
3528                 if (r)
3529                         return r;
3530
3531                 result += 4;
3532                 buf += 4;
3533                 *pos += 4;
3534                 size -= 4;
3535         }
3536
3537         return result;
3538 }
3539
3540 static ssize_t amdgpu_debugfs_regs_didt_write(struct file *f, const char __user *buf,
3541                                          size_t size, loff_t *pos)
3542 {
3543         struct amdgpu_device *adev = file_inode(f)->i_private;
3544         ssize_t result = 0;
3545         int r;
3546
3547         if (size & 0x3 || *pos & 0x3)
3548                 return -EINVAL;
3549
3550         while (size) {
3551                 uint32_t value;
3552
3553                 r = get_user(value, (uint32_t *)buf);
3554                 if (r)
3555                         return r;
3556
3557                 WREG32_DIDT(*pos >> 2, value);
3558
3559                 result += 4;
3560                 buf += 4;
3561                 *pos += 4;
3562                 size -= 4;
3563         }
3564
3565         return result;
3566 }
3567
3568 static ssize_t amdgpu_debugfs_regs_smc_read(struct file *f, char __user *buf,
3569                                         size_t size, loff_t *pos)
3570 {
3571         struct amdgpu_device *adev = file_inode(f)->i_private;
3572         ssize_t result = 0;
3573         int r;
3574
3575         if (size & 0x3 || *pos & 0x3)
3576                 return -EINVAL;
3577
3578         while (size) {
3579                 uint32_t value;
3580
3581                 value = RREG32_SMC(*pos);
3582                 r = put_user(value, (uint32_t *)buf);
3583                 if (r)
3584                         return r;
3585
3586                 result += 4;
3587                 buf += 4;
3588                 *pos += 4;
3589                 size -= 4;
3590         }
3591
3592         return result;
3593 }
3594
3595 static ssize_t amdgpu_debugfs_regs_smc_write(struct file *f, const char __user *buf,
3596                                          size_t size, loff_t *pos)
3597 {
3598         struct amdgpu_device *adev = file_inode(f)->i_private;
3599         ssize_t result = 0;
3600         int r;
3601
3602         if (size & 0x3 || *pos & 0x3)
3603                 return -EINVAL;
3604
3605         while (size) {
3606                 uint32_t value;
3607
3608                 r = get_user(value, (uint32_t *)buf);
3609                 if (r)
3610                         return r;
3611
3612                 WREG32_SMC(*pos, value);
3613
3614                 result += 4;
3615                 buf += 4;
3616                 *pos += 4;
3617                 size -= 4;
3618         }
3619
3620         return result;
3621 }
3622
3623 static ssize_t amdgpu_debugfs_gca_config_read(struct file *f, char __user *buf,
3624                                         size_t size, loff_t *pos)
3625 {
3626         struct amdgpu_device *adev = file_inode(f)->i_private;
3627         ssize_t result = 0;
3628         int r;
3629         uint32_t *config, no_regs = 0;
3630
3631         if (size & 0x3 || *pos & 0x3)
3632                 return -EINVAL;
3633
3634         config = kmalloc_array(256, sizeof(*config), GFP_KERNEL);
3635         if (!config)
3636                 return -ENOMEM;
3637
3638         /* version, increment each time something is added */
3639         config[no_regs++] = 3;
3640         config[no_regs++] = adev->gfx.config.max_shader_engines;
3641         config[no_regs++] = adev->gfx.config.max_tile_pipes;
3642         config[no_regs++] = adev->gfx.config.max_cu_per_sh;
3643         config[no_regs++] = adev->gfx.config.max_sh_per_se;
3644         config[no_regs++] = adev->gfx.config.max_backends_per_se;
3645         config[no_regs++] = adev->gfx.config.max_texture_channel_caches;
3646         config[no_regs++] = adev->gfx.config.max_gprs;
3647         config[no_regs++] = adev->gfx.config.max_gs_threads;
3648         config[no_regs++] = adev->gfx.config.max_hw_contexts;
3649         config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_frontend;
3650         config[no_regs++] = adev->gfx.config.sc_prim_fifo_size_backend;
3651         config[no_regs++] = adev->gfx.config.sc_hiz_tile_fifo_size;
3652         config[no_regs++] = adev->gfx.config.sc_earlyz_tile_fifo_size;
3653         config[no_regs++] = adev->gfx.config.num_tile_pipes;
3654         config[no_regs++] = adev->gfx.config.backend_enable_mask;
3655         config[no_regs++] = adev->gfx.config.mem_max_burst_length_bytes;
3656         config[no_regs++] = adev->gfx.config.mem_row_size_in_kb;
3657         config[no_regs++] = adev->gfx.config.shader_engine_tile_size;
3658         config[no_regs++] = adev->gfx.config.num_gpus;
3659         config[no_regs++] = adev->gfx.config.multi_gpu_tile_size;
3660         config[no_regs++] = adev->gfx.config.mc_arb_ramcfg;
3661         config[no_regs++] = adev->gfx.config.gb_addr_config;
3662         config[no_regs++] = adev->gfx.config.num_rbs;
3663
3664         /* rev==1 */
3665         config[no_regs++] = adev->rev_id;
3666         config[no_regs++] = adev->pg_flags;
3667         config[no_regs++] = adev->cg_flags;
3668
3669         /* rev==2 */
3670         config[no_regs++] = adev->family;
3671         config[no_regs++] = adev->external_rev_id;
3672
3673         /* rev==3 */
3674         config[no_regs++] = adev->pdev->device;
3675         config[no_regs++] = adev->pdev->revision;
3676         config[no_regs++] = adev->pdev->subsystem_device;
3677         config[no_regs++] = adev->pdev->subsystem_vendor;
3678
3679         while (size && (*pos < no_regs * 4)) {
3680                 uint32_t value;
3681
3682                 value = config[*pos >> 2];
3683                 r = put_user(value, (uint32_t *)buf);
3684                 if (r) {
3685                         kfree(config);
3686                         return r;
3687                 }
3688
3689                 result += 4;
3690                 buf += 4;
3691                 *pos += 4;
3692                 size -= 4;
3693         }
3694
3695         kfree(config);
3696         return result;
3697 }
3698
3699 static ssize_t amdgpu_debugfs_sensor_read(struct file *f, char __user *buf,
3700                                         size_t size, loff_t *pos)
3701 {
3702         struct amdgpu_device *adev = file_inode(f)->i_private;
3703         int idx, x, outsize, r, valuesize;
3704         uint32_t values[16];
3705
3706         if (size & 3 || *pos & 0x3)
3707                 return -EINVAL;
3708
3709         if (amdgpu_dpm == 0)
3710                 return -EINVAL;
3711
3712         /* convert offset to sensor number */
3713         idx = *pos >> 2;
3714
3715         valuesize = sizeof(values);
3716         if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->read_sensor)
3717                 r = amdgpu_dpm_read_sensor(adev, idx, &values[0], &valuesize);
3718         else
3719                 return -EINVAL;
3720
3721         if (size > valuesize)
3722                 return -EINVAL;
3723
3724         outsize = 0;
3725         x = 0;
3726         if (!r) {
3727                 while (size) {
3728                         r = put_user(values[x++], (int32_t *)buf);
3729                         buf += 4;
3730                         size -= 4;
3731                         outsize += 4;
3732                 }
3733         }
3734
3735         return !r ? outsize : r;
3736 }
3737
3738 static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
3739                                         size_t size, loff_t *pos)
3740 {
3741         struct amdgpu_device *adev = f->f_inode->i_private;
3742         int r, x;
3743         ssize_t result=0;
3744         uint32_t offset, se, sh, cu, wave, simd, data[32];
3745
3746         if (size & 3 || *pos & 3)
3747                 return -EINVAL;
3748
3749         /* decode offset */
3750         offset = (*pos & GENMASK_ULL(6, 0));
3751         se = (*pos & GENMASK_ULL(14, 7)) >> 7;
3752         sh = (*pos & GENMASK_ULL(22, 15)) >> 15;
3753         cu = (*pos & GENMASK_ULL(30, 23)) >> 23;
3754         wave = (*pos & GENMASK_ULL(36, 31)) >> 31;
3755         simd = (*pos & GENMASK_ULL(44, 37)) >> 37;
3756
3757         /* switch to the specific se/sh/cu */
3758         mutex_lock(&adev->grbm_idx_mutex);
3759         amdgpu_gfx_select_se_sh(adev, se, sh, cu);
3760
3761         x = 0;
3762         if (adev->gfx.funcs->read_wave_data)
3763                 adev->gfx.funcs->read_wave_data(adev, simd, wave, data, &x);
3764
3765         amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
3766         mutex_unlock(&adev->grbm_idx_mutex);
3767
3768         if (!x)
3769                 return -EINVAL;
3770
3771         while (size && (offset < x * 4)) {
3772                 uint32_t value;
3773
3774                 value = data[offset >> 2];
3775                 r = put_user(value, (uint32_t *)buf);
3776                 if (r)
3777                         return r;
3778
3779                 result += 4;
3780                 buf += 4;
3781                 offset += 4;
3782                 size -= 4;
3783         }
3784
3785         return result;
3786 }
3787
3788 static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
3789                                         size_t size, loff_t *pos)
3790 {
3791         struct amdgpu_device *adev = f->f_inode->i_private;
3792         int r;
3793         ssize_t result = 0;
3794         uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
3795
3796         if (size & 3 || *pos & 3)
3797                 return -EINVAL;
3798
3799         /* decode offset */
3800         offset = *pos & GENMASK_ULL(11, 0);
3801         se = (*pos & GENMASK_ULL(19, 12)) >> 12;
3802         sh = (*pos & GENMASK_ULL(27, 20)) >> 20;
3803         cu = (*pos & GENMASK_ULL(35, 28)) >> 28;
3804         wave = (*pos & GENMASK_ULL(43, 36)) >> 36;
3805         simd = (*pos & GENMASK_ULL(51, 44)) >> 44;
3806         thread = (*pos & GENMASK_ULL(59, 52)) >> 52;
3807         bank = (*pos & GENMASK_ULL(61, 60)) >> 60;
3808
3809         data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);
3810         if (!data)
3811                 return -ENOMEM;
3812
3813         /* switch to the specific se/sh/cu */
3814         mutex_lock(&adev->grbm_idx_mutex);
3815         amdgpu_gfx_select_se_sh(adev, se, sh, cu);
3816
3817         if (bank == 0) {
3818                 if (adev->gfx.funcs->read_wave_vgprs)
3819                         adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);
3820         } else {
3821                 if (adev->gfx.funcs->read_wave_sgprs)
3822                         adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);
3823         }
3824
3825         amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
3826         mutex_unlock(&adev->grbm_idx_mutex);
3827
3828         while (size) {
3829                 uint32_t value;
3830
3831                 value = data[offset++];
3832                 r = put_user(value, (uint32_t *)buf);
3833                 if (r) {
3834                         result = r;
3835                         goto err;
3836                 }
3837
3838                 result += 4;
3839                 buf += 4;
3840                 size -= 4;
3841         }
3842
3843 err:
3844         kfree(data);
3845         return result;
3846 }
3847
3848 static const struct file_operations amdgpu_debugfs_regs_fops = {
3849         .owner = THIS_MODULE,
3850         .read = amdgpu_debugfs_regs_read,
3851         .write = amdgpu_debugfs_regs_write,
3852         .llseek = default_llseek
3853 };
3854 static const struct file_operations amdgpu_debugfs_regs_didt_fops = {
3855         .owner = THIS_MODULE,
3856         .read = amdgpu_debugfs_regs_didt_read,
3857         .write = amdgpu_debugfs_regs_didt_write,
3858         .llseek = default_llseek
3859 };
3860 static const struct file_operations amdgpu_debugfs_regs_pcie_fops = {
3861         .owner = THIS_MODULE,
3862         .read = amdgpu_debugfs_regs_pcie_read,
3863         .write = amdgpu_debugfs_regs_pcie_write,
3864         .llseek = default_llseek
3865 };
3866 static const struct file_operations amdgpu_debugfs_regs_smc_fops = {
3867         .owner = THIS_MODULE,
3868         .read = amdgpu_debugfs_regs_smc_read,
3869         .write = amdgpu_debugfs_regs_smc_write,
3870         .llseek = default_llseek
3871 };
3872
3873 static const struct file_operations amdgpu_debugfs_gca_config_fops = {
3874         .owner = THIS_MODULE,
3875         .read = amdgpu_debugfs_gca_config_read,
3876         .llseek = default_llseek
3877 };
3878
3879 static const struct file_operations amdgpu_debugfs_sensors_fops = {
3880         .owner = THIS_MODULE,
3881         .read = amdgpu_debugfs_sensor_read,
3882         .llseek = default_llseek
3883 };
3884
3885 static const struct file_operations amdgpu_debugfs_wave_fops = {
3886         .owner = THIS_MODULE,
3887         .read = amdgpu_debugfs_wave_read,
3888         .llseek = default_llseek
3889 };
3890 static const struct file_operations amdgpu_debugfs_gpr_fops = {
3891         .owner = THIS_MODULE,
3892         .read = amdgpu_debugfs_gpr_read,
3893         .llseek = default_llseek
3894 };
3895
3896 static const struct file_operations *debugfs_regs[] = {
3897         &amdgpu_debugfs_regs_fops,
3898         &amdgpu_debugfs_regs_didt_fops,
3899         &amdgpu_debugfs_regs_pcie_fops,
3900         &amdgpu_debugfs_regs_smc_fops,
3901         &amdgpu_debugfs_gca_config_fops,
3902         &amdgpu_debugfs_sensors_fops,
3903         &amdgpu_debugfs_wave_fops,
3904         &amdgpu_debugfs_gpr_fops,
3905 };
3906
3907 static const char *debugfs_regs_names[] = {
3908         "amdgpu_regs",
3909         "amdgpu_regs_didt",
3910         "amdgpu_regs_pcie",
3911         "amdgpu_regs_smc",
3912         "amdgpu_gca_config",
3913         "amdgpu_sensors",
3914         "amdgpu_wave",
3915         "amdgpu_gpr",
3916 };
3917
3918 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
3919 {
3920         struct drm_minor *minor = adev->ddev->primary;
3921         struct dentry *ent, *root = minor->debugfs_root;
3922         unsigned i, j;
3923
3924         for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
3925                 ent = debugfs_create_file(debugfs_regs_names[i],
3926                                           S_IFREG | S_IRUGO, root,
3927                                           adev, debugfs_regs[i]);
3928                 if (IS_ERR(ent)) {
3929                         for (j = 0; j < i; j++) {
3930                                 debugfs_remove(adev->debugfs_regs[i]);
3931                                 adev->debugfs_regs[i] = NULL;
3932                         }
3933                         return PTR_ERR(ent);
3934                 }
3935
3936                 if (!i)
3937                         i_size_write(ent->d_inode, adev->rmmio_size);
3938                 adev->debugfs_regs[i] = ent;
3939         }
3940
3941         return 0;
3942 }
3943
3944 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev)
3945 {
3946         unsigned i;
3947
3948         for (i = 0; i < ARRAY_SIZE(debugfs_regs); i++) {
3949                 if (adev->debugfs_regs[i]) {
3950                         debugfs_remove(adev->debugfs_regs[i]);
3951                         adev->debugfs_regs[i] = NULL;
3952                 }
3953         }
3954 }
3955
3956 static int amdgpu_debugfs_test_ib(struct seq_file *m, void *data)
3957 {
3958         struct drm_info_node *node = (struct drm_info_node *) m->private;
3959         struct drm_device *dev = node->minor->dev;
3960         struct amdgpu_device *adev = dev->dev_private;
3961         int r = 0, i;
3962
3963         /* hold on the scheduler */
3964         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
3965                 struct amdgpu_ring *ring = adev->rings[i];
3966
3967                 if (!ring || !ring->sched.thread)
3968                         continue;
3969                 kthread_park(ring->sched.thread);
3970         }
3971
3972         seq_printf(m, "run ib test:\n");
3973         r = amdgpu_ib_ring_tests(adev);
3974         if (r)
3975                 seq_printf(m, "ib ring tests failed (%d).\n", r);
3976         else
3977                 seq_printf(m, "ib ring tests passed.\n");
3978
3979         /* go on the scheduler */
3980         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
3981                 struct amdgpu_ring *ring = adev->rings[i];
3982
3983                 if (!ring || !ring->sched.thread)
3984                         continue;
3985                 kthread_unpark(ring->sched.thread);
3986         }
3987
3988         return 0;
3989 }
3990
3991 static const struct drm_info_list amdgpu_debugfs_test_ib_ring_list[] = {
3992         {"amdgpu_test_ib", &amdgpu_debugfs_test_ib}
3993 };
3994
3995 static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev)
3996 {
3997         return amdgpu_debugfs_add_files(adev,
3998                                         amdgpu_debugfs_test_ib_ring_list, 1);
3999 }
4000
4001 int amdgpu_debugfs_init(struct drm_minor *minor)
4002 {
4003         return 0;
4004 }
4005
4006 static int amdgpu_debugfs_get_vbios_dump(struct seq_file *m, void *data)
4007 {
4008         struct drm_info_node *node = (struct drm_info_node *) m->private;
4009         struct drm_device *dev = node->minor->dev;
4010         struct amdgpu_device *adev = dev->dev_private;
4011
4012         seq_write(m, adev->bios, adev->bios_size);
4013         return 0;
4014 }
4015
4016 static const struct drm_info_list amdgpu_vbios_dump_list[] = {
4017                 {"amdgpu_vbios",
4018                  amdgpu_debugfs_get_vbios_dump,
4019                  0, NULL},
4020 };
4021
4022 static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev)
4023 {
4024         return amdgpu_debugfs_add_files(adev,
4025                                         amdgpu_vbios_dump_list, 1);
4026 }
4027 #else
4028 static int amdgpu_debugfs_test_ib_ring_init(struct amdgpu_device *adev)
4029 {
4030         return 0;
4031 }
4032 static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)
4033 {
4034         return 0;
4035 }
4036 static int amdgpu_debugfs_vbios_dump_init(struct amdgpu_device *adev)
4037 {
4038         return 0;
4039 }
4040 static void amdgpu_debugfs_regs_cleanup(struct amdgpu_device *adev) { }
4041 #endif
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