drivers/gpu/drm/radeon/radeon_dp_mst.c

   1 // SPDX-License-Identifier: MIT
   2
   3 #include <drm/drm_dp_mst_helper.h>
   4 #include <drm/drm_fb_helper.h>
   5 #include <drm/drm_file.h>
   6 #include <drm/drm_probe_helper.h>
   7
   8 #include "atom.h"
   9 #include "ni_reg.h"
  10 #include "radeon.h"
  11
  12 static struct radeon_encoder *radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector);
  13
  14 static int radeon_atom_set_enc_offset(int id)
  15 {
  16         static const int offsets[] = { EVERGREEN_CRTC0_REGISTER_OFFSET,
  17                                        EVERGREEN_CRTC1_REGISTER_OFFSET,
  18                                        EVERGREEN_CRTC2_REGISTER_OFFSET,
  19                                        EVERGREEN_CRTC3_REGISTER_OFFSET,
  20                                        EVERGREEN_CRTC4_REGISTER_OFFSET,
  21                                        EVERGREEN_CRTC5_REGISTER_OFFSET,
  22                                        0x13830 - 0x7030 };
  23
  24         return offsets[id];
  25 }
  26
  27 static int radeon_dp_mst_set_be_cntl(struct radeon_encoder *primary,
  28                                      struct radeon_encoder_mst *mst_enc,
  29                                      enum radeon_hpd_id hpd, bool enable)
  30 {
  31         struct drm_device *dev = primary->base.dev;
  32         struct radeon_device *rdev = dev->dev_private;
  33         uint32_t reg;
  34         int retries = 0;
  35         uint32_t temp;
  36
  37         reg = RREG32(NI_DIG_BE_CNTL + primary->offset);
  38
  39         /* set MST mode */
  40         reg &= ~NI_DIG_FE_DIG_MODE(7);
  41         reg |= NI_DIG_FE_DIG_MODE(NI_DIG_MODE_DP_MST);
  42
  43         if (enable)
  44                 reg |= NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);
  45         else
  46                 reg &= ~NI_DIG_FE_SOURCE_SELECT(1 << mst_enc->fe);
  47
  48         reg |= NI_DIG_HPD_SELECT(hpd);
  49         DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DIG_BE_CNTL + primary->offset, reg);
  50         WREG32(NI_DIG_BE_CNTL + primary->offset, reg);
  51
  52         if (enable) {
  53                 uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
  54
  55                 do {
  56                         temp = RREG32(NI_DIG_FE_CNTL + offset);
  57                 } while ((temp & NI_DIG_SYMCLK_FE_ON) && retries++ < 10000);
  58                 if (retries == 10000)
  59                         DRM_ERROR("timed out waiting for FE %d %d\n", primary->offset, mst_enc->fe);
  60         }
  61         return 0;
  62 }
  63
  64 static int radeon_dp_mst_set_stream_attrib(struct radeon_encoder *primary,
  65                                            int stream_number,
  66                                            int fe,
  67                                            int slots)
  68 {
  69         struct drm_device *dev = primary->base.dev;
  70         struct radeon_device *rdev = dev->dev_private;
  71         u32 temp, val;
  72         int retries  = 0;
  73         int satreg, satidx;
  74
  75         satreg = stream_number >> 1;
  76         satidx = stream_number & 1;
  77
  78         temp = RREG32(NI_DP_MSE_SAT0 + satreg + primary->offset);
  79
  80         val = NI_DP_MSE_SAT_SLOT_COUNT0(slots) | NI_DP_MSE_SAT_SRC0(fe);
  81
  82         val <<= (16 * satidx);
  83
  84         temp &= ~(0xffff << (16 * satidx));
  85
  86         temp |= val;
  87
  88         DRM_DEBUG_KMS("writing 0x%08x 0x%08x\n", NI_DP_MSE_SAT0 + satreg + primary->offset, temp);
  89         WREG32(NI_DP_MSE_SAT0 + satreg + primary->offset, temp);
  90
  91         WREG32(NI_DP_MSE_SAT_UPDATE + primary->offset, 1);
  92
  93         do {
  94                 unsigned value1, value2;
  95                 udelay(10);
  96                 temp = RREG32(NI_DP_MSE_SAT_UPDATE + primary->offset);
  97
  98                 value1 = temp & NI_DP_MSE_SAT_UPDATE_MASK;
  99                 value2 = temp & NI_DP_MSE_16_MTP_KEEPOUT;
 100
 101                 if (!value1 && !value2)
 102                         break;
 103         } while (retries++ < 50);
 104
 105         if (retries == 10000)
 106                 DRM_ERROR("timed out waitin for SAT update %d\n", primary->offset);
 107
 108         /* MTP 16 ? */
 109         return 0;
 110 }
 111
 112 static int radeon_dp_mst_update_stream_attribs(struct radeon_connector *mst_conn,
 113                                                struct radeon_encoder *primary)
 114 {
 115         struct drm_device *dev = mst_conn->base.dev;
 116         struct stream_attribs new_attribs[6];
 117         int i;
 118         int idx = 0;
 119         struct radeon_connector *radeon_connector;
 120         struct drm_connector *connector;
 121
 122         memset(new_attribs, 0, sizeof(new_attribs));
 123         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 124                 struct radeon_encoder *subenc;
 125                 struct radeon_encoder_mst *mst_enc;
 126
 127                 radeon_connector = to_radeon_connector(connector);
 128                 if (!radeon_connector->is_mst_connector)
 129                         continue;
 130
 131                 if (radeon_connector->mst_port != mst_conn)
 132                         continue;
 133
 134                 subenc = radeon_connector->mst_encoder;
 135                 mst_enc = subenc->enc_priv;
 136
 137                 if (!mst_enc->enc_active)
 138                         continue;
 139
 140                 new_attribs[idx].fe = mst_enc->fe;
 141                 new_attribs[idx].slots = drm_dp_mst_get_vcpi_slots(&mst_conn->mst_mgr, mst_enc->port);
 142                 idx++;
 143         }
 144
 145         for (i = 0; i < idx; i++) {
 146                 if (new_attribs[i].fe != mst_conn->cur_stream_attribs[i].fe ||
 147                     new_attribs[i].slots != mst_conn->cur_stream_attribs[i].slots) {
 148                         radeon_dp_mst_set_stream_attrib(primary, i, new_attribs[i].fe, new_attribs[i].slots);
 149                         mst_conn->cur_stream_attribs[i].fe = new_attribs[i].fe;
 150                         mst_conn->cur_stream_attribs[i].slots = new_attribs[i].slots;
 151                 }
 152         }
 153
 154         for (i = idx; i < mst_conn->enabled_attribs; i++) {
 155                 radeon_dp_mst_set_stream_attrib(primary, i, 0, 0);
 156                 mst_conn->cur_stream_attribs[i].fe = 0;
 157                 mst_conn->cur_stream_attribs[i].slots = 0;
 158         }
 159         mst_conn->enabled_attribs = idx;
 160         return 0;
 161 }
 162
 163 static int radeon_dp_mst_set_vcp_size(struct radeon_encoder *mst, s64 avg_time_slots_per_mtp)
 164 {
 165         struct drm_device *dev = mst->base.dev;
 166         struct radeon_device *rdev = dev->dev_private;
 167         struct radeon_encoder_mst *mst_enc = mst->enc_priv;
 168         uint32_t val, temp;
 169         uint32_t offset = radeon_atom_set_enc_offset(mst_enc->fe);
 170         int retries = 0;
 171         uint32_t x = drm_fixp2int(avg_time_slots_per_mtp);
 172         uint32_t y = drm_fixp2int_ceil((avg_time_slots_per_mtp - x) << 26);
 173
 174         val = NI_DP_MSE_RATE_X(x) | NI_DP_MSE_RATE_Y(y);
 175
 176         WREG32(NI_DP_MSE_RATE_CNTL + offset, val);
 177
 178         do {
 179                 temp = RREG32(NI_DP_MSE_RATE_UPDATE + offset);
 180                 udelay(10);
 181         } while ((temp & 0x1) && (retries++ < 10000));
 182
 183         if (retries >= 10000)
 184                 DRM_ERROR("timed out wait for rate cntl %d\n", mst_enc->fe);
 185         return 0;
 186 }
 187
 188 static int radeon_dp_mst_get_ddc_modes(struct drm_connector *connector)
 189 {
 190         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 191         struct radeon_connector *master = radeon_connector->mst_port;
 192         struct edid *edid;
 193         int ret = 0;
 194
 195         edid = drm_dp_mst_get_edid(connector, &master->mst_mgr, radeon_connector->port);
 196         radeon_connector->edid = edid;
 197         DRM_DEBUG_KMS("edid retrieved %p\n", edid);
 198         if (radeon_connector->edid) {
 199                 drm_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
 200                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
 201                 return ret;
 202         }
 203         drm_connector_update_edid_property(&radeon_connector->base, NULL);
 204
 205         return ret;
 206 }
 207
 208 static int radeon_dp_mst_get_modes(struct drm_connector *connector)
 209 {
 210         return radeon_dp_mst_get_ddc_modes(connector);
 211 }
 212
 213 static enum drm_mode_status
 214 radeon_dp_mst_mode_valid(struct drm_connector *connector,
 215                         struct drm_display_mode *mode)
 216 {
 217         /* TODO - validate mode against available PBN for link */
 218         if (mode->clock < 10000)
 219                 return MODE_CLOCK_LOW;
 220
 221         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 222                 return MODE_H_ILLEGAL;
 223
 224         return MODE_OK;
 225 }
 226
 227 static struct
 228 drm_encoder *radeon_mst_best_encoder(struct drm_connector *connector)
 229 {
 230         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 231
 232         return &radeon_connector->mst_encoder->base;
 233 }
 234
 235 static int
 236 radeon_dp_mst_detect(struct drm_connector *connector,
 237                      struct drm_modeset_acquire_ctx *ctx,
 238                      bool force)
 239 {
 240         struct radeon_connector *radeon_connector =
 241                 to_radeon_connector(connector);
 242         struct radeon_connector *master = radeon_connector->mst_port;
 243
 244         if (drm_connector_is_unregistered(connector))
 245                 return connector_status_disconnected;
 246
 247         return drm_dp_mst_detect_port(connector, ctx, &master->mst_mgr,
 248                                       radeon_connector->port);
 249 }
 250
 251 static const struct drm_connector_helper_funcs radeon_dp_mst_connector_helper_funcs = {
 252         .get_modes = radeon_dp_mst_get_modes,
 253         .mode_valid = radeon_dp_mst_mode_valid,
 254         .best_encoder = radeon_mst_best_encoder,
 255         .detect_ctx = radeon_dp_mst_detect,
 256 };
 257
 258 static void
 259 radeon_dp_mst_connector_destroy(struct drm_connector *connector)
 260 {
 261         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 262         struct radeon_encoder *radeon_encoder = radeon_connector->mst_encoder;
 263
 264         drm_encoder_cleanup(&radeon_encoder->base);
 265         kfree(radeon_encoder);
 266         drm_connector_cleanup(connector);
 267         kfree(radeon_connector);
 268 }
 269
 270 static const struct drm_connector_funcs radeon_dp_mst_connector_funcs = {
 271         .dpms = drm_helper_connector_dpms,
 272         .fill_modes = drm_helper_probe_single_connector_modes,
 273         .destroy = radeon_dp_mst_connector_destroy,
 274 };
 275
 276 static struct drm_connector *radeon_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
 277                                                          struct drm_dp_mst_port *port,
 278                                                          const char *pathprop)
 279 {
 280         struct radeon_connector *master = container_of(mgr, struct radeon_connector, mst_mgr);
 281         struct drm_device *dev = master->base.dev;
 282         struct radeon_connector *radeon_connector;
 283         struct drm_connector *connector;
 284
 285         radeon_connector = kzalloc(sizeof(*radeon_connector), GFP_KERNEL);
 286         if (!radeon_connector)
 287                 return NULL;
 288
 289         radeon_connector->is_mst_connector = true;
 290         connector = &radeon_connector->base;
 291         radeon_connector->port = port;
 292         radeon_connector->mst_port = master;
 293         DRM_DEBUG_KMS("\n");
 294
 295         drm_connector_init(dev, connector, &radeon_dp_mst_connector_funcs, DRM_MODE_CONNECTOR_DisplayPort);
 296         drm_connector_helper_add(connector, &radeon_dp_mst_connector_helper_funcs);
 297         radeon_connector->mst_encoder = radeon_dp_create_fake_mst_encoder(master);
 298
 299         drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0);
 300         drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0);
 301         drm_connector_set_path_property(connector, pathprop);
 302
 303         return connector;
 304 }
 305
 306 static const struct drm_dp_mst_topology_cbs mst_cbs = {
 307         .add_connector = radeon_dp_add_mst_connector,
 308 };
 309
 310 static struct
 311 radeon_connector *radeon_mst_find_connector(struct drm_encoder *encoder)
 312 {
 313         struct drm_device *dev = encoder->dev;
 314         struct drm_connector *connector;
 315
 316         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 317                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 318                 if (!connector->encoder)
 319                         continue;
 320                 if (!radeon_connector->is_mst_connector)
 321                         continue;
 322
 323                 DRM_DEBUG_KMS("checking %p vs %p\n", connector->encoder, encoder);
 324                 if (connector->encoder == encoder)
 325                         return radeon_connector;
 326         }
 327         return NULL;
 328 }
 329
 330 void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
 331 {
 332         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 333         struct drm_device *dev = crtc->dev;
 334         struct radeon_device *rdev = dev->dev_private;
 335         struct radeon_encoder *radeon_encoder = to_radeon_encoder(radeon_crtc->encoder);
 336         struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv;
 337         struct radeon_connector *radeon_connector = radeon_mst_find_connector(&radeon_encoder->base);
 338         int dp_clock;
 339         struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv;
 340
 341         if (radeon_connector) {
 342                 radeon_connector->pixelclock_for_modeset = mode->clock;
 343                 if (radeon_connector->base.display_info.bpc)
 344                         radeon_crtc->bpc = radeon_connector->base.display_info.bpc;
 345                 else
 346                         radeon_crtc->bpc = 8;
 347         }
 348
 349         DRM_DEBUG_KMS("dp_clock %p %d\n", dig_connector, dig_connector->dp_clock);
 350         dp_clock = dig_connector->dp_clock;
 351         radeon_crtc->ss_enabled =
 352                 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
 353                                                  ASIC_INTERNAL_SS_ON_DP,
 354                                                  dp_clock);
 355 }
 356
 357 static void
 358 radeon_mst_encoder_dpms(struct drm_encoder *encoder, int mode)
 359 {
 360         struct drm_device *dev = encoder->dev;
 361         struct radeon_device *rdev = dev->dev_private;
 362         struct radeon_encoder *radeon_encoder, *primary;
 363         struct radeon_encoder_mst *mst_enc;
 364         struct radeon_encoder_atom_dig *dig_enc;
 365         struct radeon_connector *radeon_connector;
 366         struct drm_crtc *crtc;
 367         struct radeon_crtc *radeon_crtc;
 368         int slots;
 369         s64 fixed_pbn, fixed_pbn_per_slot, avg_time_slots_per_mtp;
 370         if (!ASIC_IS_DCE5(rdev)) {
 371                 DRM_ERROR("got mst dpms on non-DCE5\n");
 372                 return;
 373         }
 374
 375         radeon_connector = radeon_mst_find_connector(encoder);
 376         if (!radeon_connector)
 377                 return;
 378
 379         radeon_encoder = to_radeon_encoder(encoder);
 380
 381         mst_enc = radeon_encoder->enc_priv;
 382
 383         primary = mst_enc->primary;
 384
 385         dig_enc = primary->enc_priv;
 386
 387         crtc = encoder->crtc;
 388         DRM_DEBUG_KMS("got connector %d\n", dig_enc->active_mst_links);
 389
 390         switch (mode) {
 391         case DRM_MODE_DPMS_ON:
 392                 dig_enc->active_mst_links++;
 393
 394                 radeon_crtc = to_radeon_crtc(crtc);
 395
 396                 if (dig_enc->active_mst_links == 1) {
 397                         mst_enc->fe = dig_enc->dig_encoder;
 398                         mst_enc->fe_from_be = true;
 399                         atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe);
 400
 401                         atombios_dig_encoder_setup(&primary->base, ATOM_ENCODER_CMD_SETUP, 0);
 402                         atombios_dig_transmitter_setup2(&primary->base, ATOM_TRANSMITTER_ACTION_ENABLE,
 403                                                         0, 0, dig_enc->dig_encoder);
 404
 405                         if (radeon_dp_needs_link_train(mst_enc->connector) ||
 406                             dig_enc->active_mst_links == 1) {
 407                                 radeon_dp_link_train(&primary->base, &mst_enc->connector->base);
 408                         }
 409
 410                 } else {
 411                         mst_enc->fe = radeon_atom_pick_dig_encoder(encoder, radeon_crtc->crtc_id);
 412                         if (mst_enc->fe == -1)
 413                                 DRM_ERROR("failed to get frontend for dig encoder\n");
 414                         mst_enc->fe_from_be = false;
 415                         atombios_set_mst_encoder_crtc_source(encoder, mst_enc->fe);
 416                 }
 417
 418                 DRM_DEBUG_KMS("dig encoder is %d %d %d\n", dig_enc->dig_encoder,
 419                               dig_enc->linkb, radeon_crtc->crtc_id);
 420
 421                 slots = drm_dp_find_vcpi_slots(&radeon_connector->mst_port->mst_mgr,
 422                                                mst_enc->pbn);
 423                 drm_dp_mst_allocate_vcpi(&radeon_connector->mst_port->mst_mgr,
 424                                          radeon_connector->port,
 425                                          mst_enc->pbn, slots);
 426                 drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr);
 427
 428                 radeon_dp_mst_set_be_cntl(primary, mst_enc,
 429                                           radeon_connector->mst_port->hpd.hpd, true);
 430
 431                 mst_enc->enc_active = true;
 432                 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
 433
 434                 fixed_pbn = drm_int2fixp(mst_enc->pbn);
 435                 fixed_pbn_per_slot = drm_int2fixp(radeon_connector->mst_port->mst_mgr.pbn_div);
 436                 avg_time_slots_per_mtp = drm_fixp_div(fixed_pbn, fixed_pbn_per_slot);
 437                 radeon_dp_mst_set_vcp_size(radeon_encoder, avg_time_slots_per_mtp);
 438
 439                 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0,
 440                                             mst_enc->fe);
 441                 drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr);
 442
 443                 drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr);
 444
 445                 break;
 446         case DRM_MODE_DPMS_STANDBY:
 447         case DRM_MODE_DPMS_SUSPEND:
 448         case DRM_MODE_DPMS_OFF:
 449                 DRM_ERROR("DPMS OFF %d\n", dig_enc->active_mst_links);
 450
 451                 if (!mst_enc->enc_active)
 452                         return;
 453
 454                 drm_dp_mst_reset_vcpi_slots(&radeon_connector->mst_port->mst_mgr, mst_enc->port);
 455                 drm_dp_update_payload_part1(&radeon_connector->mst_port->mst_mgr);
 456
 457                 drm_dp_check_act_status(&radeon_connector->mst_port->mst_mgr);
 458                 /* and this can also fail */
 459                 drm_dp_update_payload_part2(&radeon_connector->mst_port->mst_mgr);
 460
 461                 drm_dp_mst_deallocate_vcpi(&radeon_connector->mst_port->mst_mgr, mst_enc->port);
 462
 463                 mst_enc->enc_active = false;
 464                 radeon_dp_mst_update_stream_attribs(radeon_connector->mst_port, primary);
 465
 466                 radeon_dp_mst_set_be_cntl(primary, mst_enc,
 467                                           radeon_connector->mst_port->hpd.hpd, false);
 468                 atombios_dig_encoder_setup2(&primary->base, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0,
 469                                             mst_enc->fe);
 470
 471                 if (!mst_enc->fe_from_be)
 472                         radeon_atom_release_dig_encoder(rdev, mst_enc->fe);
 473
 474                 mst_enc->fe_from_be = false;
 475                 dig_enc->active_mst_links--;
 476                 if (dig_enc->active_mst_links == 0) {
 477                         /* drop link */
 478                 }
 479
 480                 break;
 481         }
 482
 483 }
 484
 485 static bool radeon_mst_mode_fixup(struct drm_encoder *encoder,
 486                                    const struct drm_display_mode *mode,
 487                                    struct drm_display_mode *adjusted_mode)
 488 {
 489         struct radeon_encoder_mst *mst_enc;
 490         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 491         struct radeon_connector_atom_dig *dig_connector;
 492         int bpp = 24;
 493
 494         mst_enc = radeon_encoder->enc_priv;
 495
 496         mst_enc->pbn = drm_dp_calc_pbn_mode(adjusted_mode->clock, bpp, false);
 497
 498         mst_enc->primary->active_device = mst_enc->primary->devices & mst_enc->connector->devices;
 499         DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
 500                       mst_enc->primary->active_device, mst_enc->primary->devices,
 501                       mst_enc->connector->devices, mst_enc->primary->base.encoder_type);
 502
 503
 504         drm_mode_set_crtcinfo(adjusted_mode, 0);
 505         dig_connector = mst_enc->connector->con_priv;
 506         dig_connector->dp_lane_count = drm_dp_max_lane_count(dig_connector->dpcd);
 507         dig_connector->dp_clock = drm_dp_max_link_rate(dig_connector->dpcd);
 508         DRM_DEBUG_KMS("dig clock %p %d %d\n", dig_connector,
 509                       dig_connector->dp_lane_count, dig_connector->dp_clock);
 510         return true;
 511 }
 512
 513 static void radeon_mst_encoder_prepare(struct drm_encoder *encoder)
 514 {
 515         struct radeon_connector *radeon_connector;
 516         struct radeon_encoder *radeon_encoder, *primary;
 517         struct radeon_encoder_mst *mst_enc;
 518         struct radeon_encoder_atom_dig *dig_enc;
 519
 520         radeon_connector = radeon_mst_find_connector(encoder);
 521         if (!radeon_connector) {
 522                 DRM_DEBUG_KMS("failed to find connector %p\n", encoder);
 523                 return;
 524         }
 525         radeon_encoder = to_radeon_encoder(encoder);
 526
 527         radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
 528
 529         mst_enc = radeon_encoder->enc_priv;
 530
 531         primary = mst_enc->primary;
 532
 533         dig_enc = primary->enc_priv;
 534
 535         mst_enc->port = radeon_connector->port;
 536
 537         if (dig_enc->dig_encoder == -1) {
 538                 dig_enc->dig_encoder = radeon_atom_pick_dig_encoder(&primary->base, -1);
 539                 primary->offset = radeon_atom_set_enc_offset(dig_enc->dig_encoder);
 540                 atombios_set_mst_encoder_crtc_source(encoder, dig_enc->dig_encoder);
 541
 542
 543         }
 544         DRM_DEBUG_KMS("%d %d\n", dig_enc->dig_encoder, primary->offset);
 545 }
 546
 547 static void
 548 radeon_mst_encoder_mode_set(struct drm_encoder *encoder,
 549                              struct drm_display_mode *mode,
 550                              struct drm_display_mode *adjusted_mode)
 551 {
 552         DRM_DEBUG_KMS("\n");
 553 }
 554
 555 static void radeon_mst_encoder_commit(struct drm_encoder *encoder)
 556 {
 557         radeon_mst_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
 558         DRM_DEBUG_KMS("\n");
 559 }
 560
 561 static const struct drm_encoder_helper_funcs radeon_mst_helper_funcs = {
 562         .dpms = radeon_mst_encoder_dpms,
 563         .mode_fixup = radeon_mst_mode_fixup,
 564         .prepare = radeon_mst_encoder_prepare,
 565         .mode_set = radeon_mst_encoder_mode_set,
 566         .commit = radeon_mst_encoder_commit,
 567 };
 568
 569 static void radeon_dp_mst_encoder_destroy(struct drm_encoder *encoder)
 570 {
 571         drm_encoder_cleanup(encoder);
 572         kfree(encoder);
 573 }
 574
 575 static const struct drm_encoder_funcs radeon_dp_mst_enc_funcs = {
 576         .destroy = radeon_dp_mst_encoder_destroy,
 577 };
 578
 579 static struct radeon_encoder *
 580 radeon_dp_create_fake_mst_encoder(struct radeon_connector *connector)
 581 {
 582         struct drm_device *dev = connector->base.dev;
 583         struct radeon_device *rdev = dev->dev_private;
 584         struct radeon_encoder *radeon_encoder;
 585         struct radeon_encoder_mst *mst_enc;
 586         struct drm_encoder *encoder;
 587         const struct drm_connector_helper_funcs *connector_funcs = connector->base.helper_private;
 588         struct drm_encoder *enc_master = connector_funcs->best_encoder(&connector->base);
 589
 590         DRM_DEBUG_KMS("enc master is %p\n", enc_master);
 591         radeon_encoder = kzalloc(sizeof(*radeon_encoder), GFP_KERNEL);
 592         if (!radeon_encoder)
 593                 return NULL;
 594
 595         radeon_encoder->enc_priv = kzalloc(sizeof(*mst_enc), GFP_KERNEL);
 596         if (!radeon_encoder->enc_priv) {
 597                 kfree(radeon_encoder);
 598                 return NULL;
 599         }
 600         encoder = &radeon_encoder->base;
 601         switch (rdev->num_crtc) {
 602         case 1:
 603                 encoder->possible_crtcs = 0x1;
 604                 break;
 605         case 2:
 606         default:
 607                 encoder->possible_crtcs = 0x3;
 608                 break;
 609         case 4:
 610                 encoder->possible_crtcs = 0xf;
 611                 break;
 612         case 6:
 613                 encoder->possible_crtcs = 0x3f;
 614                 break;
 615         }
 616
 617         drm_encoder_init(dev, &radeon_encoder->base, &radeon_dp_mst_enc_funcs,
 618                          DRM_MODE_ENCODER_DPMST, NULL);
 619         drm_encoder_helper_add(encoder, &radeon_mst_helper_funcs);
 620
 621         mst_enc = radeon_encoder->enc_priv;
 622         mst_enc->connector = connector;
 623         mst_enc->primary = to_radeon_encoder(enc_master);
 624         radeon_encoder->is_mst_encoder = true;
 625         return radeon_encoder;
 626 }
 627
 628 int
 629 radeon_dp_mst_init(struct radeon_connector *radeon_connector)
 630 {
 631         struct drm_device *dev = radeon_connector->base.dev;
 632
 633         if (!radeon_connector->ddc_bus->has_aux)
 634                 return 0;
 635
 636         radeon_connector->mst_mgr.cbs = &mst_cbs;
 637         return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev,
 638                                             &radeon_connector->ddc_bus->aux, 16, 6,
 639                                             radeon_connector->base.base.id);
 640 }
 641
 642 int
 643 radeon_dp_mst_probe(struct radeon_connector *radeon_connector)
 644 {
 645         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 646         struct drm_device *dev = radeon_connector->base.dev;
 647         struct radeon_device *rdev = dev->dev_private;
 648         int ret;
 649         u8 msg[1];
 650
 651         if (!radeon_mst)
 652                 return 0;
 653
 654         if (!ASIC_IS_DCE5(rdev))
 655                 return 0;
 656
 657         if (dig_connector->dpcd[DP_DPCD_REV] < 0x12)
 658                 return 0;
 659
 660         ret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux, DP_MSTM_CAP, msg,
 661                                1);
 662         if (ret) {
 663                 if (msg[0] & DP_MST_CAP) {
 664                         DRM_DEBUG_KMS("Sink is MST capable\n");
 665                         dig_connector->is_mst = true;
 666                 } else {
 667                         DRM_DEBUG_KMS("Sink is not MST capable\n");
 668                         dig_connector->is_mst = false;
 669                 }
 670
 671         }
 672         drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr,
 673                                         dig_connector->is_mst);
 674         return dig_connector->is_mst;
 675 }
 676
 677 int
 678 radeon_dp_mst_check_status(struct radeon_connector *radeon_connector)
 679 {
 680         struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
 681         int retry;
 682
 683         if (dig_connector->is_mst) {
 684                 u8 esi[16] = { 0 };
 685                 int dret;
 686                 int ret = 0;
 687                 bool handled;
 688
 689                 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux,
 690                                        DP_SINK_COUNT_ESI, esi, 8);
 691 go_again:
 692                 if (dret == 8) {
 693                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
 694                         ret = drm_dp_mst_hpd_irq(&radeon_connector->mst_mgr, esi, &handled);
 695
 696                         if (handled) {
 697                                 for (retry = 0; retry < 3; retry++) {
 698                                         int wret;
 699                                         wret = drm_dp_dpcd_write(&radeon_connector->ddc_bus->aux,
 700                                                                  DP_SINK_COUNT_ESI + 1, &esi[1], 3);
 701                                         if (wret == 3)
 702                                                 break;
 703                                 }
 704
 705                                 dret = drm_dp_dpcd_read(&radeon_connector->ddc_bus->aux,
 706                                                         DP_SINK_COUNT_ESI, esi, 8);
 707                                 if (dret == 8) {
 708                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
 709                                         goto go_again;
 710                                 }
 711                         } else
 712                                 ret = 0;
 713
 714                         return ret;
 715                 } else {
 716                         DRM_DEBUG_KMS("failed to get ESI - device may have failed %d\n", ret);
 717                         dig_connector->is_mst = false;
 718                         drm_dp_mst_topology_mgr_set_mst(&radeon_connector->mst_mgr,
 719                                                         dig_connector->is_mst);
 720                         /* send a hotplug event */
 721                 }
 722         }
 723         return -EINVAL;
 724 }
 725
 726 #if defined(CONFIG_DEBUG_FS)
 727
 728 static int radeon_debugfs_mst_info_show(struct seq_file *m, void *unused)
 729 {
 730         struct radeon_device *rdev = (struct radeon_device *)m->private;
 731         struct drm_device *dev = rdev->ddev;
 732         struct drm_connector *connector;
 733         struct radeon_connector *radeon_connector;
 734         struct radeon_connector_atom_dig *dig_connector;
 735         int i;
 736
 737         drm_modeset_lock_all(dev);
 738         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 739                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
 740                         continue;
 741
 742                 radeon_connector = to_radeon_connector(connector);
 743                 dig_connector = radeon_connector->con_priv;
 744                 if (radeon_connector->is_mst_connector)
 745                         continue;
 746                 if (!dig_connector->is_mst)
 747                         continue;
 748                 drm_dp_mst_dump_topology(m, &radeon_connector->mst_mgr);
 749
 750                 for (i = 0; i < radeon_connector->enabled_attribs; i++)
 751                         seq_printf(m, "attrib %d: %d %d\n", i,
 752                                    radeon_connector->cur_stream_attribs[i].fe,
 753                                    radeon_connector->cur_stream_attribs[i].slots);
 754         }
 755         drm_modeset_unlock_all(dev);
 756         return 0;
 757 }
 758
 759 DEFINE_SHOW_ATTRIBUTE(radeon_debugfs_mst_info);
 760 #endif
 761
 762 void radeon_mst_debugfs_init(struct radeon_device *rdev)
 763 {
 764 #if defined(CONFIG_DEBUG_FS)
 765         struct dentry *root = rdev->ddev->primary->debugfs_root;
 766
 767         debugfs_create_file("radeon_mst_info", 0444, root, rdev,
 768                             &radeon_debugfs_mst_info_fops);
 769
 770 #endif
 771 }