drivers/gpu/drm/armada/armada_plane.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2012 Russell King
   4  *  Rewritten from the dovefb driver, and Armada510 manuals.
   5  */
   6
   7 #include <drm/drm_atomic.h>
   8 #include <drm/drm_atomic_helper.h>
   9 #include <drm/drm_fourcc.h>
  10 #include <drm/drm_plane_helper.h>
  11
  12 #include "armada_crtc.h"
  13 #include "armada_drm.h"
  14 #include "armada_fb.h"
  15 #include "armada_gem.h"
  16 #include "armada_hw.h"
  17 #include "armada_plane.h"
  18 #include "armada_trace.h"
  19
  20 static const uint32_t armada_primary_formats[] = {
  21         DRM_FORMAT_UYVY,
  22         DRM_FORMAT_YUYV,
  23         DRM_FORMAT_VYUY,
  24         DRM_FORMAT_YVYU,
  25         DRM_FORMAT_ARGB8888,
  26         DRM_FORMAT_ABGR8888,
  27         DRM_FORMAT_XRGB8888,
  28         DRM_FORMAT_XBGR8888,
  29         DRM_FORMAT_RGB888,
  30         DRM_FORMAT_BGR888,
  31         DRM_FORMAT_ARGB1555,
  32         DRM_FORMAT_ABGR1555,
  33         DRM_FORMAT_RGB565,
  34         DRM_FORMAT_BGR565,
  35 };
  36
  37 void armada_drm_plane_calc(struct drm_plane_state *state, u32 addrs[2][3],
  38         u16 pitches[3], bool interlaced)
  39 {
  40         struct drm_framebuffer *fb = state->fb;
  41         const struct drm_format_info *format = fb->format;
  42         unsigned int num_planes = format->num_planes;
  43         unsigned int x = state->src.x1 >> 16;
  44         unsigned int y = state->src.y1 >> 16;
  45         u32 addr = drm_fb_obj(fb)->dev_addr;
  46         int i;
  47
  48         DRM_DEBUG_KMS("pitch %u x %d y %d bpp %d\n",
  49                       fb->pitches[0], x, y, format->cpp[0] * 8);
  50
  51         if (num_planes > 3)
  52                 num_planes = 3;
  53
  54         addrs[0][0] = addr + fb->offsets[0] + y * fb->pitches[0] +
  55                       x * format->cpp[0];
  56         pitches[0] = fb->pitches[0];
  57
  58         y /= format->vsub;
  59         x /= format->hsub;
  60
  61         for (i = 1; i < num_planes; i++) {
  62                 addrs[0][i] = addr + fb->offsets[i] + y * fb->pitches[i] +
  63                               x * format->cpp[i];
  64                 pitches[i] = fb->pitches[i];
  65         }
  66         for (; i < 3; i++) {
  67                 addrs[0][i] = 0;
  68                 pitches[i] = 0;
  69         }
  70         if (interlaced) {
  71                 for (i = 0; i < 3; i++) {
  72                         addrs[1][i] = addrs[0][i] + pitches[i];
  73                         pitches[i] *= 2;
  74                 }
  75         } else {
  76                 for (i = 0; i < 3; i++)
  77                         addrs[1][i] = addrs[0][i];
  78         }
  79 }
  80
  81 int armada_drm_plane_prepare_fb(struct drm_plane *plane,
  82         struct drm_plane_state *state)
  83 {
  84         DRM_DEBUG_KMS("[PLANE:%d:%s] [FB:%d]\n",
  85                 plane->base.id, plane->name,
  86                 state->fb ? state->fb->base.id : 0);
  87
  88         /*
  89          * Take a reference on the new framebuffer - we want to
  90          * hold on to it while the hardware is displaying it.
  91          */
  92         if (state->fb)
  93                 drm_framebuffer_get(state->fb);
  94         return 0;
  95 }
  96
  97 void armada_drm_plane_cleanup_fb(struct drm_plane *plane,
  98         struct drm_plane_state *old_state)
  99 {
 100         DRM_DEBUG_KMS("[PLANE:%d:%s] [FB:%d]\n",
 101                 plane->base.id, plane->name,
 102                 old_state->fb ? old_state->fb->base.id : 0);
 103
 104         if (old_state->fb)
 105                 drm_framebuffer_put(old_state->fb);
 106 }
 107
 108 int armada_drm_plane_atomic_check(struct drm_plane *plane,
 109         struct drm_atomic_state *state)
 110 {
 111         struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
 112                                                                                  plane);
 113         struct armada_plane_state *st = to_armada_plane_state(new_plane_state);
 114         struct drm_crtc *crtc = new_plane_state->crtc;
 115         struct drm_crtc_state *crtc_state;
 116         bool interlace;
 117         int ret;
 118
 119         if (!new_plane_state->fb || WARN_ON(!new_plane_state->crtc)) {
 120                 new_plane_state->visible = false;
 121                 return 0;
 122         }
 123
 124         if (state)
 125                 crtc_state = drm_atomic_get_existing_crtc_state(state,
 126                                                                 crtc);
 127         else
 128                 crtc_state = crtc->state;
 129
 130         ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
 131                                                   0,
 132                                                   INT_MAX, true, false);
 133         if (ret)
 134                 return ret;
 135
 136         interlace = crtc_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE;
 137         if (interlace) {
 138                 if ((new_plane_state->dst.y1 | new_plane_state->dst.y2) & 1)
 139                         return -EINVAL;
 140                 st->src_hw = drm_rect_height(&new_plane_state->src) >> 17;
 141                 st->dst_yx = new_plane_state->dst.y1 >> 1;
 142                 st->dst_hw = drm_rect_height(&new_plane_state->dst) >> 1;
 143         } else {
 144                 st->src_hw = drm_rect_height(&new_plane_state->src) >> 16;
 145                 st->dst_yx = new_plane_state->dst.y1;
 146                 st->dst_hw = drm_rect_height(&new_plane_state->dst);
 147         }
 148
 149         st->src_hw <<= 16;
 150         st->src_hw |= drm_rect_width(&new_plane_state->src) >> 16;
 151         st->dst_yx <<= 16;
 152         st->dst_yx |= new_plane_state->dst.x1 & 0x0000ffff;
 153         st->dst_hw <<= 16;
 154         st->dst_hw |= drm_rect_width(&new_plane_state->dst) & 0x0000ffff;
 155
 156         armada_drm_plane_calc(new_plane_state, st->addrs, st->pitches,
 157                               interlace);
 158         st->interlace = interlace;
 159
 160         return 0;
 161 }
 162
 163 static void armada_drm_primary_plane_atomic_update(struct drm_plane *plane,
 164         struct drm_atomic_state *state)
 165 {
 166         struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
 167                                                                            plane);
 168         struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
 169                                                                            plane);
 170         struct armada_crtc *dcrtc;
 171         struct armada_regs *regs;
 172         u32 cfg, cfg_mask, val;
 173         unsigned int idx;
 174
 175         DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name);
 176
 177         if (!new_state->fb || WARN_ON(!new_state->crtc))
 178                 return;
 179
 180         DRM_DEBUG_KMS("[PLANE:%d:%s] is on [CRTC:%d:%s] with [FB:%d] visible %u->%u\n",
 181                 plane->base.id, plane->name,
 182                 new_state->crtc->base.id, new_state->crtc->name,
 183                 new_state->fb->base.id,
 184                 old_state->visible, new_state->visible);
 185
 186         dcrtc = drm_to_armada_crtc(new_state->crtc);
 187         regs = dcrtc->regs + dcrtc->regs_idx;
 188
 189         idx = 0;
 190         if (!old_state->visible && new_state->visible) {
 191                 val = CFG_PDWN64x66;
 192                 if (drm_fb_to_armada_fb(new_state->fb)->fmt > CFG_420)
 193                         val |= CFG_PDWN256x24;
 194                 armada_reg_queue_mod(regs, idx, 0, val, LCD_SPU_SRAM_PARA1);
 195         }
 196         val = armada_src_hw(new_state);
 197         if (armada_src_hw(old_state) != val)
 198                 armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_HPXL_VLN);
 199         val = armada_dst_yx(new_state);
 200         if (armada_dst_yx(old_state) != val)
 201                 armada_reg_queue_set(regs, idx, val, LCD_SPU_GRA_OVSA_HPXL_VLN);
 202         val = armada_dst_hw(new_state);
 203         if (armada_dst_hw(old_state) != val)
 204                 armada_reg_queue_set(regs, idx, val, LCD_SPU_GZM_HPXL_VLN);
 205         if (old_state->src.x1 != new_state->src.x1 ||
 206             old_state->src.y1 != new_state->src.y1 ||
 207             old_state->fb != new_state->fb ||
 208             new_state->crtc->state->mode_changed) {
 209                 armada_reg_queue_set(regs, idx, armada_addr(new_state, 0, 0),
 210                                      LCD_CFG_GRA_START_ADDR0);
 211                 armada_reg_queue_set(regs, idx, armada_addr(new_state, 1, 0),
 212                                      LCD_CFG_GRA_START_ADDR1);
 213                 armada_reg_queue_mod(regs, idx, armada_pitch(new_state, 0),
 214                                      0xffff,
 215                                      LCD_CFG_GRA_PITCH);
 216         }
 217         if (old_state->fb != new_state->fb ||
 218             new_state->crtc->state->mode_changed) {
 219                 cfg = CFG_GRA_FMT(drm_fb_to_armada_fb(new_state->fb)->fmt) |
 220                       CFG_GRA_MOD(drm_fb_to_armada_fb(new_state->fb)->mod);
 221                 if (drm_fb_to_armada_fb(new_state->fb)->fmt > CFG_420)
 222                         cfg |= CFG_PALETTE_ENA;
 223                 if (new_state->visible)
 224                         cfg |= CFG_GRA_ENA;
 225                 if (to_armada_plane_state(new_state)->interlace)
 226                         cfg |= CFG_GRA_FTOGGLE;
 227                 cfg_mask = CFG_GRAFORMAT |
 228                            CFG_GRA_MOD(CFG_SWAPRB | CFG_SWAPUV |
 229                                        CFG_SWAPYU | CFG_YUV2RGB) |
 230                            CFG_PALETTE_ENA | CFG_GRA_FTOGGLE |
 231                            CFG_GRA_ENA;
 232         } else if (old_state->visible != new_state->visible) {
 233                 cfg = new_state->visible ? CFG_GRA_ENA : 0;
 234                 cfg_mask = CFG_GRA_ENA;
 235         } else {
 236                 cfg = cfg_mask = 0;
 237         }
 238         if (drm_rect_width(&old_state->src) != drm_rect_width(&new_state->src) ||
 239             drm_rect_width(&old_state->dst) != drm_rect_width(&new_state->dst)) {
 240                 cfg_mask |= CFG_GRA_HSMOOTH;
 241                 if (drm_rect_width(&new_state->src) >> 16 !=
 242                     drm_rect_width(&new_state->dst))
 243                         cfg |= CFG_GRA_HSMOOTH;
 244         }
 245
 246         if (cfg_mask)
 247                 armada_reg_queue_mod(regs, idx, cfg, cfg_mask,
 248                                      LCD_SPU_DMA_CTRL0);
 249
 250         dcrtc->regs_idx += idx;
 251 }
 252
 253 static void armada_drm_primary_plane_atomic_disable(struct drm_plane *plane,
 254         struct drm_atomic_state *state)
 255 {
 256         struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
 257                                                                            plane);
 258         struct armada_crtc *dcrtc;
 259         struct armada_regs *regs;
 260         unsigned int idx = 0;
 261
 262         DRM_DEBUG_KMS("[PLANE:%d:%s]\n", plane->base.id, plane->name);
 263
 264         if (!old_state->crtc)
 265                 return;
 266
 267         DRM_DEBUG_KMS("[PLANE:%d:%s] was on [CRTC:%d:%s] with [FB:%d]\n",
 268                 plane->base.id, plane->name,
 269                 old_state->crtc->base.id, old_state->crtc->name,
 270                 old_state->fb->base.id);
 271
 272         dcrtc = drm_to_armada_crtc(old_state->crtc);
 273         regs = dcrtc->regs + dcrtc->regs_idx;
 274
 275         /* Disable plane and power down most RAMs and FIFOs */
 276         armada_reg_queue_mod(regs, idx, 0, CFG_GRA_ENA, LCD_SPU_DMA_CTRL0);
 277         armada_reg_queue_mod(regs, idx, CFG_PDWN256x32 | CFG_PDWN256x24 |
 278                              CFG_PDWN32x32 | CFG_PDWN64x66,
 279                              0, LCD_SPU_SRAM_PARA1);
 280
 281         dcrtc->regs_idx += idx;
 282 }
 283
 284 static const struct drm_plane_helper_funcs armada_primary_plane_helper_funcs = {
 285         .prepare_fb     = armada_drm_plane_prepare_fb,
 286         .cleanup_fb     = armada_drm_plane_cleanup_fb,
 287         .atomic_check   = armada_drm_plane_atomic_check,
 288         .atomic_update  = armada_drm_primary_plane_atomic_update,
 289         .atomic_disable = armada_drm_primary_plane_atomic_disable,
 290 };
 291
 292 void armada_plane_reset(struct drm_plane *plane)
 293 {
 294         struct armada_plane_state *st;
 295         if (plane->state)
 296                 __drm_atomic_helper_plane_destroy_state(plane->state);
 297         kfree(plane->state);
 298         st = kzalloc(sizeof(*st), GFP_KERNEL);
 299         if (st)
 300                 __drm_atomic_helper_plane_reset(plane, &st->base);
 301 }
 302
 303 struct drm_plane_state *armada_plane_duplicate_state(struct drm_plane *plane)
 304 {
 305         struct armada_plane_state *st;
 306
 307         if (WARN_ON(!plane->state))
 308                 return NULL;
 309
 310         st = kmemdup(plane->state, sizeof(*st), GFP_KERNEL);
 311         if (st)
 312                 __drm_atomic_helper_plane_duplicate_state(plane, &st->base);
 313
 314         return &st->base;
 315 }
 316
 317 static const struct drm_plane_funcs armada_primary_plane_funcs = {
 318         .update_plane   = drm_atomic_helper_update_plane,
 319         .disable_plane  = drm_atomic_helper_disable_plane,
 320         .destroy        = drm_primary_helper_destroy,
 321         .reset          = armada_plane_reset,
 322         .atomic_duplicate_state = armada_plane_duplicate_state,
 323         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
 324 };
 325
 326 int armada_drm_primary_plane_init(struct drm_device *drm,
 327         struct drm_plane *primary)
 328 {
 329         int ret;
 330
 331         drm_plane_helper_add(primary, &armada_primary_plane_helper_funcs);
 332
 333         ret = drm_universal_plane_init(drm, primary, 0,
 334                                        &armada_primary_plane_funcs,
 335                                        armada_primary_formats,
 336                                        ARRAY_SIZE(armada_primary_formats),
 337                                        NULL,
 338                                        DRM_PLANE_TYPE_PRIMARY, NULL);
 339
 340         return ret;
 341 }