drivers/spi/omap_spi_100k.c

   1 /*
   2  * OMAP7xx SPI 100k controller driver
   3  * Author: Fabrice Crohas <[email protected]>
   4  * from original omap1_mcspi driver
   5  *
   6  * Copyright (C) 2005, 2006 Nokia Corporation
   7  * Author:      Samuel Ortiz <[email protected]> and
   8  *              Juha Yrj�l� <[email protected]>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23  *
  24  */
  25 #include <linux/kernel.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/module.h>
  29 #include <linux/device.h>
  30 #include <linux/delay.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/err.h>
  33 #include <linux/clk.h>
  34 #include <linux/io.h>
  35 #include <linux/gpio.h>
  36 #include <linux/slab.h>
  37
  38 #include <linux/spi/spi.h>
  39
  40 #include <plat/clock.h>
  41
  42 #define OMAP1_SPI100K_MAX_FREQ          48000000
  43
  44 #define ICR_SPITAS      (OMAP7XX_ICR_BASE + 0x12)
  45
  46 #define SPI_SETUP1      0x00
  47 #define SPI_SETUP2      0x02
  48 #define SPI_CTRL        0x04
  49 #define SPI_STATUS      0x06
  50 #define SPI_TX_LSB      0x08
  51 #define SPI_TX_MSB      0x0a
  52 #define SPI_RX_LSB      0x0c
  53 #define SPI_RX_MSB      0x0e
  54
  55 #define SPI_SETUP1_INT_READ_ENABLE      (1UL << 5)
  56 #define SPI_SETUP1_INT_WRITE_ENABLE     (1UL << 4)
  57 #define SPI_SETUP1_CLOCK_DIVISOR(x)     ((x) << 1)
  58 #define SPI_SETUP1_CLOCK_ENABLE         (1UL << 0)
  59
  60 #define SPI_SETUP2_ACTIVE_EDGE_FALLING  (0UL << 0)
  61 #define SPI_SETUP2_ACTIVE_EDGE_RISING   (1UL << 0)
  62 #define SPI_SETUP2_NEGATIVE_LEVEL       (0UL << 5)
  63 #define SPI_SETUP2_POSITIVE_LEVEL       (1UL << 5)
  64 #define SPI_SETUP2_LEVEL_TRIGGER        (0UL << 10)
  65 #define SPI_SETUP2_EDGE_TRIGGER         (1UL << 10)
  66
  67 #define SPI_CTRL_SEN(x)                 ((x) << 7)
  68 #define SPI_CTRL_WORD_SIZE(x)           (((x) - 1) << 2)
  69 #define SPI_CTRL_WR                     (1UL << 1)
  70 #define SPI_CTRL_RD                     (1UL << 0)
  71
  72 #define SPI_STATUS_WE                   (1UL << 1)
  73 #define SPI_STATUS_RD                   (1UL << 0)
  74
  75 #define WRITE 0
  76 #define READ  1
  77
  78
  79 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
  80  * cache operations; better heuristics consider wordsize and bitrate.
  81  */
  82 #define DMA_MIN_BYTES                   8
  83
  84 #define SPI_RUNNING     0
  85 #define SPI_SHUTDOWN    1
  86
  87 struct omap1_spi100k {
  88         struct work_struct      work;
  89
  90         /* lock protects queue and registers */
  91         spinlock_t              lock;
  92         struct list_head        msg_queue;
  93         struct spi_master       *master;
  94         struct clk              *ick;
  95         struct clk              *fck;
  96
  97         /* Virtual base address of the controller */
  98         void __iomem            *base;
  99
 100         /* State of the SPI */
 101         unsigned int            state;
 102 };
 103
 104 struct omap1_spi100k_cs {
 105         void __iomem            *base;
 106         int                     word_len;
 107 };
 108
 109 static struct workqueue_struct *omap1_spi100k_wq;
 110
 111 #define MOD_REG_BIT(val, mask, set) do { \
 112         if (set) \
 113                 val |= mask; \
 114         else \
 115                 val &= ~mask; \
 116 } while (0)
 117
 118 static void spi100k_enable_clock(struct spi_master *master)
 119 {
 120         unsigned int val;
 121         struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
 122
 123         /* enable SPI */
 124         val = readw(spi100k->base + SPI_SETUP1);
 125         val |= SPI_SETUP1_CLOCK_ENABLE;
 126         writew(val, spi100k->base + SPI_SETUP1);
 127 }
 128
 129 static void spi100k_disable_clock(struct spi_master *master)
 130 {
 131         unsigned int val;
 132         struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
 133
 134         /* disable SPI */
 135         val = readw(spi100k->base + SPI_SETUP1);
 136         val &= ~SPI_SETUP1_CLOCK_ENABLE;
 137         writew(val, spi100k->base + SPI_SETUP1);
 138 }
 139
 140 static void spi100k_write_data(struct spi_master *master, int len, int data)
 141 {
 142         struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
 143
 144         /* write 16-bit word, shifting 8-bit data if necessary */
 145         if (len <= 8) {
 146                 data <<= 8;
 147                 len = 16;
 148         }
 149
 150         spi100k_enable_clock(master);
 151         writew( data , spi100k->base + SPI_TX_MSB);
 152
 153         writew(SPI_CTRL_SEN(0) |
 154                SPI_CTRL_WORD_SIZE(len) |
 155                SPI_CTRL_WR,
 156                spi100k->base + SPI_CTRL);
 157
 158         /* Wait for bit ack send change */
 159         while((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_WE) != SPI_STATUS_WE);
 160         udelay(1000);
 161
 162         spi100k_disable_clock(master);
 163 }
 164
 165 static int spi100k_read_data(struct spi_master *master, int len)
 166 {
 167         int dataH,dataL;
 168         struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
 169
 170         /* Always do at least 16 bits */
 171         if (len <= 8)
 172                 len = 16;
 173
 174         spi100k_enable_clock(master);
 175         writew(SPI_CTRL_SEN(0) |
 176                SPI_CTRL_WORD_SIZE(len) |
 177                SPI_CTRL_RD,
 178                spi100k->base + SPI_CTRL);
 179
 180         while((readw(spi100k->base + SPI_STATUS) & SPI_STATUS_RD) != SPI_STATUS_RD);
 181         udelay(1000);
 182
 183         dataL = readw(spi100k->base + SPI_RX_LSB);
 184         dataH = readw(spi100k->base + SPI_RX_MSB);
 185         spi100k_disable_clock(master);
 186
 187         return dataL;
 188 }
 189
 190 static void spi100k_open(struct spi_master *master)
 191 {
 192         /* get control of SPI */
 193         struct omap1_spi100k *spi100k = spi_master_get_devdata(master);
 194
 195         writew(SPI_SETUP1_INT_READ_ENABLE |
 196                SPI_SETUP1_INT_WRITE_ENABLE |
 197                SPI_SETUP1_CLOCK_DIVISOR(0), spi100k->base + SPI_SETUP1);
 198
 199         /* configure clock and interrupts */
 200         writew(SPI_SETUP2_ACTIVE_EDGE_FALLING |
 201                SPI_SETUP2_NEGATIVE_LEVEL |
 202                SPI_SETUP2_LEVEL_TRIGGER, spi100k->base + SPI_SETUP2);
 203 }
 204
 205 static void omap1_spi100k_force_cs(struct omap1_spi100k *spi100k, int enable)
 206 {
 207         if (enable)
 208                 writew(0x05fc, spi100k->base + SPI_CTRL);
 209         else
 210                 writew(0x05fd, spi100k->base + SPI_CTRL);
 211 }
 212
 213 static unsigned
 214 omap1_spi100k_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 215 {
 216         struct omap1_spi100k    *spi100k;
 217         struct omap1_spi100k_cs *cs = spi->controller_state;
 218         unsigned int            count, c;
 219         int                     word_len;
 220
 221         spi100k = spi_master_get_devdata(spi->master);
 222         count = xfer->len;
 223         c = count;
 224         word_len = cs->word_len;
 225
 226         if (word_len <= 8) {
 227                 u8              *rx;
 228                 const u8        *tx;
 229
 230                 rx = xfer->rx_buf;
 231                 tx = xfer->tx_buf;
 232                 do {
 233                         c-=1;
 234                         if (xfer->tx_buf != NULL)
 235                                 spi100k_write_data(spi->master, word_len, *tx++);
 236                         if (xfer->rx_buf != NULL)
 237                                 *rx++ = spi100k_read_data(spi->master, word_len);
 238                 } while(c);
 239         } else if (word_len <= 16) {
 240                 u16             *rx;
 241                 const u16       *tx;
 242
 243                 rx = xfer->rx_buf;
 244                 tx = xfer->tx_buf;
 245                 do {
 246                         c-=2;
 247                         if (xfer->tx_buf != NULL)
 248                                 spi100k_write_data(spi->master,word_len, *tx++);
 249                         if (xfer->rx_buf != NULL)
 250                                 *rx++ = spi100k_read_data(spi->master,word_len);
 251                 } while(c);
 252         } else if (word_len <= 32) {
 253                 u32             *rx;
 254                 const u32       *tx;
 255
 256                 rx = xfer->rx_buf;
 257                 tx = xfer->tx_buf;
 258                 do {
 259                         c-=4;
 260                         if (xfer->tx_buf != NULL)
 261                                 spi100k_write_data(spi->master,word_len, *tx);
 262                         if (xfer->rx_buf != NULL)
 263                                 *rx = spi100k_read_data(spi->master,word_len);
 264                 } while(c);
 265         }
 266         return count - c;
 267 }
 268
 269 /* called only when no transfer is active to this device */
 270 static int omap1_spi100k_setup_transfer(struct spi_device *spi,
 271                 struct spi_transfer *t)
 272 {
 273         struct omap1_spi100k *spi100k = spi_master_get_devdata(spi->master);
 274         struct omap1_spi100k_cs *cs = spi->controller_state;
 275         u8 word_len = spi->bits_per_word;
 276
 277         if (t != NULL && t->bits_per_word)
 278                 word_len = t->bits_per_word;
 279         if (!word_len)
 280                 word_len = 8;
 281
 282         if (spi->bits_per_word > 32)
 283                 return -EINVAL;
 284         cs->word_len = word_len;
 285
 286         /* SPI init before transfer */
 287         writew(0x3e , spi100k->base + SPI_SETUP1);
 288         writew(0x00 , spi100k->base + SPI_STATUS);
 289         writew(0x3e , spi100k->base + SPI_CTRL);
 290
 291         return 0;
 292 }
 293
 294 /* the spi->mode bits understood by this driver: */
 295 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
 296
 297 static int omap1_spi100k_setup(struct spi_device *spi)
 298 {
 299         int                     ret;
 300         struct omap1_spi100k    *spi100k;
 301         struct omap1_spi100k_cs *cs = spi->controller_state;
 302
 303         if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
 304                  dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
 305                         spi->bits_per_word);
 306                  return -EINVAL;
 307         }
 308
 309         spi100k = spi_master_get_devdata(spi->master);
 310
 311         if (!cs) {
 312                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 313                 if (!cs)
 314                         return -ENOMEM;
 315                 cs->base = spi100k->base + spi->chip_select * 0x14;
 316                 spi->controller_state = cs;
 317         }
 318
 319         spi100k_open(spi->master);
 320
 321         clk_enable(spi100k->ick);
 322         clk_enable(spi100k->fck);
 323
 324         ret = omap1_spi100k_setup_transfer(spi, NULL);
 325
 326         clk_disable(spi100k->ick);
 327         clk_disable(spi100k->fck);
 328
 329         return ret;
 330 }
 331
 332 static void omap1_spi100k_work(struct work_struct *work)
 333 {
 334         struct omap1_spi100k    *spi100k;
 335         int status = 0;
 336
 337         spi100k = container_of(work, struct omap1_spi100k, work);
 338         spin_lock_irq(&spi100k->lock);
 339
 340         clk_enable(spi100k->ick);
 341         clk_enable(spi100k->fck);
 342
 343         /* We only enable one channel at a time -- the one whose message is
 344          * at the head of the queue -- although this controller would gladly
 345          * arbitrate among multiple channels.  This corresponds to "single
 346          * channel" master mode.  As a side effect, we need to manage the
 347          * chipselect with the FORCE bit ... CS != channel enable.
 348          */
 349          while (!list_empty(&spi100k->msg_queue)) {
 350                 struct spi_message              *m;
 351                 struct spi_device               *spi;
 352                 struct spi_transfer             *t = NULL;
 353                 int                             cs_active = 0;
 354                 struct omap1_spi100k_cs         *cs;
 355                 int                             par_override = 0;
 356
 357                 m = container_of(spi100k->msg_queue.next, struct spi_message,
 358                                  queue);
 359
 360                 list_del_init(&m->queue);
 361                 spin_unlock_irq(&spi100k->lock);
 362
 363                 spi = m->spi;
 364                 cs = spi->controller_state;
 365
 366                 list_for_each_entry(t, &m->transfers, transfer_list) {
 367                         if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
 368                                 status = -EINVAL;
 369                                 break;
 370                         }
 371                         if (par_override || t->speed_hz || t->bits_per_word) {
 372                                 par_override = 1;
 373                                 status = omap1_spi100k_setup_transfer(spi, t);
 374                                 if (status < 0)
 375                                         break;
 376                                 if (!t->speed_hz && !t->bits_per_word)
 377                                         par_override = 0;
 378                         }
 379
 380                         if (!cs_active) {
 381                                 omap1_spi100k_force_cs(spi100k, 1);
 382                                 cs_active = 1;
 383                         }
 384
 385                         if (t->len) {
 386                                 unsigned count;
 387
 388                                 count = omap1_spi100k_txrx_pio(spi, t);
 389                                 m->actual_length += count;
 390
 391                                 if (count != t->len) {
 392                                         status = -EIO;
 393                                         break;
 394                                 }
 395                         }
 396
 397                         if (t->delay_usecs)
 398                                 udelay(t->delay_usecs);
 399
 400                         /* ignore the "leave it on after last xfer" hint */
 401
 402                         if (t->cs_change) {
 403                                 omap1_spi100k_force_cs(spi100k, 0);
 404                                 cs_active = 0;
 405                         }
 406                 }
 407
 408                 /* Restore defaults if they were overriden */
 409                 if (par_override) {
 410                         par_override = 0;
 411                         status = omap1_spi100k_setup_transfer(spi, NULL);
 412                 }
 413
 414                 if (cs_active)
 415                         omap1_spi100k_force_cs(spi100k, 0);
 416
 417                 m->status = status;
 418                 m->complete(m->context);
 419
 420                 spin_lock_irq(&spi100k->lock);
 421         }
 422
 423         clk_disable(spi100k->ick);
 424         clk_disable(spi100k->fck);
 425         spin_unlock_irq(&spi100k->lock);
 426
 427         if (status < 0)
 428                 printk(KERN_WARNING "spi transfer failed with %d\n", status);
 429 }
 430
 431 static int omap1_spi100k_transfer(struct spi_device *spi, struct spi_message *m)
 432 {
 433         struct omap1_spi100k    *spi100k;
 434         unsigned long           flags;
 435         struct spi_transfer     *t;
 436
 437         m->actual_length = 0;
 438         m->status = -EINPROGRESS;
 439
 440         spi100k = spi_master_get_devdata(spi->master);
 441
 442         /* Don't accept new work if we're shutting down */
 443         if (spi100k->state == SPI_SHUTDOWN)
 444                 return -ESHUTDOWN;
 445
 446         /* reject invalid messages and transfers */
 447         if (list_empty(&m->transfers) || !m->complete)
 448                 return -EINVAL;
 449
 450         list_for_each_entry(t, &m->transfers, transfer_list) {
 451                 const void      *tx_buf = t->tx_buf;
 452                 void            *rx_buf = t->rx_buf;
 453                 unsigned        len = t->len;
 454
 455                 if (t->speed_hz > OMAP1_SPI100K_MAX_FREQ
 456                                 || (len && !(rx_buf || tx_buf))
 457                                 || (t->bits_per_word &&
 458                                         (  t->bits_per_word < 4
 459                                         || t->bits_per_word > 32))) {
 460                         dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
 461                                         t->speed_hz,
 462                                         len,
 463                                         tx_buf ? "tx" : "",
 464                                         rx_buf ? "rx" : "",
 465                                         t->bits_per_word);
 466                         return -EINVAL;
 467                 }
 468
 469                 if (t->speed_hz && t->speed_hz < OMAP1_SPI100K_MAX_FREQ/(1<<16)) {
 470                         dev_dbg(&spi->dev, "%d Hz max exceeds %d\n",
 471                                         t->speed_hz,
 472                                         OMAP1_SPI100K_MAX_FREQ/(1<<16));
 473                         return -EINVAL;
 474                 }
 475
 476         }
 477
 478         spin_lock_irqsave(&spi100k->lock, flags);
 479         list_add_tail(&m->queue, &spi100k->msg_queue);
 480         queue_work(omap1_spi100k_wq, &spi100k->work);
 481         spin_unlock_irqrestore(&spi100k->lock, flags);
 482
 483         return 0;
 484 }
 485
 486 static int __init omap1_spi100k_reset(struct omap1_spi100k *spi100k)
 487 {
 488         return 0;
 489 }
 490
 491 static int __devinit omap1_spi100k_probe(struct platform_device *pdev)
 492 {
 493         struct spi_master       *master;
 494         struct omap1_spi100k    *spi100k;
 495         int                     status = 0;
 496
 497         if (!pdev->id)
 498                 return -EINVAL;
 499
 500         master = spi_alloc_master(&pdev->dev, sizeof *spi100k);
 501         if (master == NULL) {
 502                 dev_dbg(&pdev->dev, "master allocation failed\n");
 503                 return -ENOMEM;
 504         }
 505
 506         if (pdev->id != -1)
 507                master->bus_num = pdev->id;
 508
 509         master->setup = omap1_spi100k_setup;
 510         master->transfer = omap1_spi100k_transfer;
 511         master->cleanup = NULL;
 512         master->num_chipselect = 2;
 513         master->mode_bits = MODEBITS;
 514
 515         dev_set_drvdata(&pdev->dev, master);
 516
 517         spi100k = spi_master_get_devdata(master);
 518         spi100k->master = master;
 519
 520         /*
 521          * The memory region base address is taken as the platform_data.
 522          * You should allocate this with ioremap() before initializing
 523          * the SPI.
 524          */
 525         spi100k->base = (void __iomem *) pdev->dev.platform_data;
 526
 527         INIT_WORK(&spi100k->work, omap1_spi100k_work);
 528
 529         spin_lock_init(&spi100k->lock);
 530         INIT_LIST_HEAD(&spi100k->msg_queue);
 531         spi100k->ick = clk_get(&pdev->dev, "ick");
 532         if (IS_ERR(spi100k->ick)) {
 533                 dev_dbg(&pdev->dev, "can't get spi100k_ick\n");
 534                 status = PTR_ERR(spi100k->ick);
 535                 goto err1;
 536         }
 537
 538         spi100k->fck = clk_get(&pdev->dev, "fck");
 539         if (IS_ERR(spi100k->fck)) {
 540                 dev_dbg(&pdev->dev, "can't get spi100k_fck\n");
 541                 status = PTR_ERR(spi100k->fck);
 542                 goto err2;
 543         }
 544
 545         if (omap1_spi100k_reset(spi100k) < 0)
 546                 goto err3;
 547
 548         status = spi_register_master(master);
 549         if (status < 0)
 550                 goto err3;
 551
 552         spi100k->state = SPI_RUNNING;
 553
 554         return status;
 555
 556 err3:
 557         clk_put(spi100k->fck);
 558 err2:
 559         clk_put(spi100k->ick);
 560 err1:
 561         spi_master_put(master);
 562         return status;
 563 }
 564
 565 static int __exit omap1_spi100k_remove(struct platform_device *pdev)
 566 {
 567         struct spi_master       *master;
 568         struct omap1_spi100k    *spi100k;
 569         struct resource         *r;
 570         unsigned                limit = 500;
 571         unsigned long           flags;
 572         int                     status = 0;
 573
 574         master = dev_get_drvdata(&pdev->dev);
 575         spi100k = spi_master_get_devdata(master);
 576
 577         spin_lock_irqsave(&spi100k->lock, flags);
 578
 579         spi100k->state = SPI_SHUTDOWN;
 580         while (!list_empty(&spi100k->msg_queue) && limit--) {
 581                 spin_unlock_irqrestore(&spi100k->lock, flags);
 582                 msleep(10);
 583                 spin_lock_irqsave(&spi100k->lock, flags);
 584         }
 585
 586         if (!list_empty(&spi100k->msg_queue))
 587                 status = -EBUSY;
 588
 589         spin_unlock_irqrestore(&spi100k->lock, flags);
 590
 591         if (status != 0)
 592                 return status;
 593
 594         clk_put(spi100k->fck);
 595         clk_put(spi100k->ick);
 596
 597         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 598
 599         spi_unregister_master(master);
 600
 601         return 0;
 602 }
 603
 604 static struct platform_driver omap1_spi100k_driver = {
 605         .driver = {
 606                 .name           = "omap1_spi100k",
 607                 .owner          = THIS_MODULE,
 608         },
 609         .remove         = __exit_p(omap1_spi100k_remove),
 610 };
 611
 612
 613 static int __init omap1_spi100k_init(void)
 614 {
 615         omap1_spi100k_wq = create_singlethread_workqueue(
 616                         omap1_spi100k_driver.driver.name);
 617
 618         if (omap1_spi100k_wq == NULL)
 619                 return -1;
 620
 621         return platform_driver_probe(&omap1_spi100k_driver, omap1_spi100k_probe);
 622 }
 623
 624 static void __exit omap1_spi100k_exit(void)
 625 {
 626         platform_driver_unregister(&omap1_spi100k_driver);
 627
 628         destroy_workqueue(omap1_spi100k_wq);
 629 }
 630
 631 module_init(omap1_spi100k_init);
 632 module_exit(omap1_spi100k_exit);
 633
 634 MODULE_DESCRIPTION("OMAP7xx SPI 100k controller driver");
 635 MODULE_AUTHOR("Fabrice Crohas <[email protected]>");
 636 MODULE_LICENSE("GPL");
 637