drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "amdgpu_smu.h"
  33 #include "nv.h"
  34 #include "nvd.h"
  35
  36 #include "gc/gc_10_1_0_offset.h"
  37 #include "gc/gc_10_1_0_sh_mask.h"
  38 #include "smuio/smuio_11_0_0_offset.h"
  39 #include "smuio/smuio_11_0_0_sh_mask.h"
  40 #include "navi10_enum.h"
  41 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  42
  43 #include "soc15.h"
  44 #include "soc15d.h"
  45 #include "soc15_common.h"
  46 #include "clearstate_gfx10.h"
  47 #include "v10_structs.h"
  48 #include "gfx_v10_0.h"
  49 #include "nbio_v2_3.h"
  50
  51 /**
  52  * Navi10 has two graphic rings to share each graphic pipe.
  53  * 1. Primary ring
  54  * 2. Async ring
  55  */
  56 #define GFX10_NUM_GFX_RINGS_NV1X        1
  57 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      1
  58 #define GFX10_MEC_HPD_SIZE      2048
  59
  60 #define F32_CE_PROGRAM_RAM_SIZE         65536
  61 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  62
  63 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  64 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  65 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  66 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  67 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  68 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  69
  70 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  71 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  72
  73 #define mmCGTS_TCC_DISABLE_gc_10_3                 0x5006
  74 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX        1
  75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3            0x5007
  76 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX   1
  77
  78 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  79 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  80 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  81 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  83 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  85 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  87 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  89 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  91 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  93 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  95 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  97 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  99 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
 100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
 101 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
 102 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
 103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 104 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 105
 106 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh                0x0025
 107 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX       1
 108 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh                0x0026
 109 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX       1
 110 #define mmSPI_CONFIG_CNTL_1_Vangogh              0x2441
 111 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX     1
 112 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh          0x2261
 113 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
 114 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh           0x224f
 115 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX  1
 116 #define mmVGT_TF_RING_SIZE_Vangogh               0x224e
 117 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX      1
 118 #define mmVGT_GSVS_RING_SIZE_Vangogh             0x2241
 119 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX    1
 120 #define mmVGT_TF_MEMORY_BASE_Vangogh             0x2250
 121 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX    1
 122 #define mmVGT_ESGS_RING_SIZE_Vangogh             0x2240
 123 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX    1
 124 #define mmSPI_CONFIG_CNTL_Vangogh                0x2440
 125 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX       1
 126 #define mmGCR_GENERAL_CNTL_Vangogh               0x1580
 127 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX      0
 128 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh   0x0000FFFFL
 129
 130 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 131 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 132 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 133 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 134 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 135 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 136 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 137 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 138 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 139 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 140 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 141 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 142
 143 #define mmCPG_PSP_DEBUG                         0x5c10
 144 #define mmCPG_PSP_DEBUG_BASE_IDX                1
 145 #define mmCPC_PSP_DEBUG                         0x5c11
 146 #define mmCPC_PSP_DEBUG_BASE_IDX                1
 147 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 148 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK        0x00000008L
 149
 150 //CC_GC_SA_UNIT_DISABLE
 151 #define mmCC_GC_SA_UNIT_DISABLE                 0x0fe9
 152 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX        0
 153 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT        0x8
 154 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK          0x0000FF00L
 155 //GC_USER_SA_UNIT_DISABLE
 156 #define mmGC_USER_SA_UNIT_DISABLE               0x0fea
 157 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX      0
 158 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT      0x8
 159 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK        0x0000FF00L
 160 //PA_SC_ENHANCE_3
 161 #define mmPA_SC_ENHANCE_3                       0x1085
 162 #define mmPA_SC_ENHANCE_3_BASE_IDX              0
 163 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
 164 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK   0x00000008L
 165
 166 #define mmCGTT_SPI_CS_CLK_CTRL                  0x507c
 167 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX         1
 168
 169 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid          0x16f3
 170 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 171 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid          0x15db
 172 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
 173
 174 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid              0x2030
 175 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX     0
 176
 177 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 178 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 179 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 180 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 181 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 182 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 183
 184 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 185 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 186 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 187 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 188 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 189 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 190 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 191 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 192 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 193 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 194 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 195
 196 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 197 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 198 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 199 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 200 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 201 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 202
 203 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 204 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 205 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 206 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 207 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 208 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 209
 210 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 211 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 212 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 213 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 214 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 215 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 216
 217 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
 218 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
 219 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
 220 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
 221 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
 222 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
 223
 224 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
 225 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
 226 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
 227 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
 228 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
 229 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
 230
 231 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 232 {
 233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 273 };
 274
 275 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 276 {
 277         /* Pending on emulation bring up */
 278 };
 279
 280 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
 281 {
 282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1334 };
1335
1336 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1337 {
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1376 };
1377
1378 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1379 {
1380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
1395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
1420 };
1421
1422 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
1423 {
1424         static void *scratch_reg0;
1425         static void *scratch_reg1;
1426         static void *spare_int;
1427         uint32_t i = 0;
1428         uint32_t retries = 50000;
1429
1430         scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
1431         scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
1432         spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;
1433
1434         if (amdgpu_sriov_runtime(adev)) {
1435                 pr_err("shouldn't call rlcg write register during runtime\n");
1436                 return;
1437         }
1438
1439         writel(v, scratch_reg0);
1440         writel(offset | 0x80000000, scratch_reg1);
1441         writel(1, spare_int);
1442         for (i = 0; i < retries; i++) {
1443                 u32 tmp;
1444
1445                 tmp = readl(scratch_reg1);
1446                 if (!(tmp & 0x80000000))
1447                         break;
1448
1449                 udelay(10);
1450         }
1451
1452         if (i >= retries)
1453                 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
1454 }
1455
1456 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1457 {
1458         /* Pending on emulation bring up */
1459 };
1460
1461 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1462 {
1463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2083 };
2084
2085 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2086 {
2087         /* Pending on emulation bring up */
2088 };
2089
2090 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2091 {
2092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3144 };
3145
3146 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3147 {
3148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3156         SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3190 };
3191
3192 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3193 {
3194         /* Pending on emulation bring up */
3195 };
3196
3197 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3198 {
3199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3240
3241         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3243 };
3244
3245 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
3246 {
3247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3270
3271         /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020),
3273 };
3274
3275 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
3276 {
3277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00001d00, 0x00000500),
3284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG,  0x00000020, 0x00000020)
3312 };
3313
3314 #define DEFAULT_SH_MEM_CONFIG \
3315         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3316          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3317          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3318          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3319
3320
3321 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3322 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3323 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3324 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3325 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3326                                  struct amdgpu_cu_info *cu_info);
3327 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3328 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3329                                    u32 sh_num, u32 instance);
3330 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3331
3332 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3333 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3334 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3335 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3336 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3337 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3338 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3339 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3340 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3341 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3342
3343 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3344 {
3345         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3346         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3347                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3348         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3349         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3350         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3351         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3352         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3353         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3354 }
3355
3356 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3357                                  struct amdgpu_ring *ring)
3358 {
3359         struct amdgpu_device *adev = kiq_ring->adev;
3360         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3361         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3362         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3363
3364         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3365         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3366         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3367                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3368                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3369                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3370                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3371                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3372                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3373                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3374                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3375                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3376         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3377         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3378         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3379         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3380         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3381 }
3382
3383 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3384                                    struct amdgpu_ring *ring,
3385                                    enum amdgpu_unmap_queues_action action,
3386                                    u64 gpu_addr, u64 seq)
3387 {
3388         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3389
3390         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3391         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3392                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3393                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3394                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3395                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3396         amdgpu_ring_write(kiq_ring,
3397                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3398
3399         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3400                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3401                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3402                 amdgpu_ring_write(kiq_ring, seq);
3403         } else {
3404                 amdgpu_ring_write(kiq_ring, 0);
3405                 amdgpu_ring_write(kiq_ring, 0);
3406                 amdgpu_ring_write(kiq_ring, 0);
3407         }
3408 }
3409
3410 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3411                                    struct amdgpu_ring *ring,
3412                                    u64 addr,
3413                                    u64 seq)
3414 {
3415         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3416
3417         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3418         amdgpu_ring_write(kiq_ring,
3419                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3420                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3421                           PACKET3_QUERY_STATUS_COMMAND(2));
3422         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3423                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3424                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3425         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3426         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3427         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3428         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3429 }
3430
3431 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3432                                 uint16_t pasid, uint32_t flush_type,
3433                                 bool all_hub)
3434 {
3435         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3436         amdgpu_ring_write(kiq_ring,
3437                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3438                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3439                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3440                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3441 }
3442
3443 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3444         .kiq_set_resources = gfx10_kiq_set_resources,
3445         .kiq_map_queues = gfx10_kiq_map_queues,
3446         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3447         .kiq_query_status = gfx10_kiq_query_status,
3448         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3449         .set_resources_size = 8,
3450         .map_queues_size = 7,
3451         .unmap_queues_size = 6,
3452         .query_status_size = 7,
3453         .invalidate_tlbs_size = 2,
3454 };
3455
3456 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3457 {
3458         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3459 }
3460
3461 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3462 {
3463         switch (adev->asic_type) {
3464         case CHIP_NAVI10:
3465                 soc15_program_register_sequence(adev,
3466                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3467                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3468                 break;
3469         case CHIP_NAVI14:
3470                 soc15_program_register_sequence(adev,
3471                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3472                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3473                 break;
3474         case CHIP_NAVI12:
3475                 soc15_program_register_sequence(adev,
3476                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3477                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3478                 break;
3479         default:
3480                 break;
3481         }
3482 }
3483
3484 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3485 {
3486         switch (adev->asic_type) {
3487         case CHIP_NAVI10:
3488                 soc15_program_register_sequence(adev,
3489                                                 golden_settings_gc_10_1,
3490                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3491                 soc15_program_register_sequence(adev,
3492                                                 golden_settings_gc_10_0_nv10,
3493                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3494                 break;
3495         case CHIP_NAVI14:
3496                 soc15_program_register_sequence(adev,
3497                                                 golden_settings_gc_10_1_1,
3498                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3499                 soc15_program_register_sequence(adev,
3500                                                 golden_settings_gc_10_1_nv14,
3501                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3502                 break;
3503         case CHIP_NAVI12:
3504                 soc15_program_register_sequence(adev,
3505                                                 golden_settings_gc_10_1_2,
3506                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3507                 soc15_program_register_sequence(adev,
3508                                                 golden_settings_gc_10_1_2_nv12,
3509                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3510                 break;
3511         case CHIP_SIENNA_CICHLID:
3512                 soc15_program_register_sequence(adev,
3513                                                 golden_settings_gc_10_3,
3514                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3515                 soc15_program_register_sequence(adev,
3516                                                 golden_settings_gc_10_3_sienna_cichlid,
3517                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3518                 break;
3519         case CHIP_NAVY_FLOUNDER:
3520                 soc15_program_register_sequence(adev,
3521                                                 golden_settings_gc_10_3_2,
3522                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3523                 break;
3524         case CHIP_VANGOGH:
3525                 soc15_program_register_sequence(adev,
3526                                                 golden_settings_gc_10_3_vangogh,
3527                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3528                 break;
3529         case CHIP_DIMGREY_CAVEFISH:
3530                 soc15_program_register_sequence(adev,
3531                                                 golden_settings_gc_10_3_4,
3532                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3533                 break;
3534         default:
3535                 break;
3536         }
3537         gfx_v10_0_init_spm_golden_registers(adev);
3538 }
3539
3540 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3541 {
3542         adev->gfx.scratch.num_reg = 8;
3543         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3544         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3545 }
3546
3547 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3548                                        bool wc, uint32_t reg, uint32_t val)
3549 {
3550         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3551         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3552                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3553         amdgpu_ring_write(ring, reg);
3554         amdgpu_ring_write(ring, 0);
3555         amdgpu_ring_write(ring, val);
3556 }
3557
3558 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3559                                   int mem_space, int opt, uint32_t addr0,
3560                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3561                                   uint32_t inv)
3562 {
3563         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3564         amdgpu_ring_write(ring,
3565                           /* memory (1) or register (0) */
3566                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3567                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3568                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3569                            WAIT_REG_MEM_ENGINE(eng_sel)));
3570
3571         if (mem_space)
3572                 BUG_ON(addr0 & 0x3); /* Dword align */
3573         amdgpu_ring_write(ring, addr0);
3574         amdgpu_ring_write(ring, addr1);
3575         amdgpu_ring_write(ring, ref);
3576         amdgpu_ring_write(ring, mask);
3577         amdgpu_ring_write(ring, inv); /* poll interval */
3578 }
3579
3580 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3581 {
3582         struct amdgpu_device *adev = ring->adev;
3583         uint32_t scratch;
3584         uint32_t tmp = 0;
3585         unsigned i;
3586         int r;
3587
3588         r = amdgpu_gfx_scratch_get(adev, &scratch);
3589         if (r) {
3590                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3591                 return r;
3592         }
3593
3594         WREG32(scratch, 0xCAFEDEAD);
3595
3596         r = amdgpu_ring_alloc(ring, 3);
3597         if (r) {
3598                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3599                           ring->idx, r);
3600                 amdgpu_gfx_scratch_free(adev, scratch);
3601                 return r;
3602         }
3603
3604         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3605         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3606         amdgpu_ring_write(ring, 0xDEADBEEF);
3607         amdgpu_ring_commit(ring);
3608
3609         for (i = 0; i < adev->usec_timeout; i++) {
3610                 tmp = RREG32(scratch);
3611                 if (tmp == 0xDEADBEEF)
3612                         break;
3613                 if (amdgpu_emu_mode == 1)
3614                         msleep(1);
3615                 else
3616                         udelay(1);
3617         }
3618
3619         if (i >= adev->usec_timeout)
3620                 r = -ETIMEDOUT;
3621
3622         amdgpu_gfx_scratch_free(adev, scratch);
3623
3624         return r;
3625 }
3626
3627 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3628 {
3629         struct amdgpu_device *adev = ring->adev;
3630         struct amdgpu_ib ib;
3631         struct dma_fence *f = NULL;
3632         unsigned index;
3633         uint64_t gpu_addr;
3634         uint32_t tmp;
3635         long r;
3636
3637         r = amdgpu_device_wb_get(adev, &index);
3638         if (r)
3639                 return r;
3640
3641         gpu_addr = adev->wb.gpu_addr + (index * 4);
3642         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3643         memset(&ib, 0, sizeof(ib));
3644         r = amdgpu_ib_get(adev, NULL, 16,
3645                                         AMDGPU_IB_POOL_DIRECT, &ib);
3646         if (r)
3647                 goto err1;
3648
3649         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3650         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3651         ib.ptr[2] = lower_32_bits(gpu_addr);
3652         ib.ptr[3] = upper_32_bits(gpu_addr);
3653         ib.ptr[4] = 0xDEADBEEF;
3654         ib.length_dw = 5;
3655
3656         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3657         if (r)
3658                 goto err2;
3659
3660         r = dma_fence_wait_timeout(f, false, timeout);
3661         if (r == 0) {
3662                 r = -ETIMEDOUT;
3663                 goto err2;
3664         } else if (r < 0) {
3665                 goto err2;
3666         }
3667
3668         tmp = adev->wb.wb[index];
3669         if (tmp == 0xDEADBEEF)
3670                 r = 0;
3671         else
3672                 r = -EINVAL;
3673 err2:
3674         amdgpu_ib_free(adev, &ib, NULL);
3675         dma_fence_put(f);
3676 err1:
3677         amdgpu_device_wb_free(adev, index);
3678         return r;
3679 }
3680
3681 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3682 {
3683         release_firmware(adev->gfx.pfp_fw);
3684         adev->gfx.pfp_fw = NULL;
3685         release_firmware(adev->gfx.me_fw);
3686         adev->gfx.me_fw = NULL;
3687         release_firmware(adev->gfx.ce_fw);
3688         adev->gfx.ce_fw = NULL;
3689         release_firmware(adev->gfx.rlc_fw);
3690         adev->gfx.rlc_fw = NULL;
3691         release_firmware(adev->gfx.mec_fw);
3692         adev->gfx.mec_fw = NULL;
3693         release_firmware(adev->gfx.mec2_fw);
3694         adev->gfx.mec2_fw = NULL;
3695
3696         kfree(adev->gfx.rlc.register_list_format);
3697 }
3698
3699 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3700 {
3701         adev->gfx.cp_fw_write_wait = false;
3702
3703         switch (adev->asic_type) {
3704         case CHIP_NAVI10:
3705         case CHIP_NAVI12:
3706         case CHIP_NAVI14:
3707                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3708                     (adev->gfx.me_feature_version >= 27) &&
3709                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3710                     (adev->gfx.pfp_feature_version >= 27) &&
3711                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3712                     (adev->gfx.mec_feature_version >= 27))
3713                         adev->gfx.cp_fw_write_wait = true;
3714                 break;
3715         case CHIP_SIENNA_CICHLID:
3716         case CHIP_NAVY_FLOUNDER:
3717         case CHIP_VANGOGH:
3718         case CHIP_DIMGREY_CAVEFISH:
3719                 adev->gfx.cp_fw_write_wait = true;
3720                 break;
3721         default:
3722                 break;
3723         }
3724
3725         if (!adev->gfx.cp_fw_write_wait)
3726                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3727 }
3728
3729
3730 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3731 {
3732         const struct rlc_firmware_header_v2_1 *rlc_hdr;
3733
3734         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3735         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3736         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3737         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3738         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3739         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3740         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3741         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3742         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3743         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3744         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3745         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3746         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3747         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3748                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3749 }
3750
3751 static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
3752 {
3753         const struct rlc_firmware_header_v2_2 *rlc_hdr;
3754
3755         rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
3756         adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
3757         adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
3758         adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
3759         adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
3760 }
3761
3762 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3763 {
3764         bool ret = false;
3765
3766         switch (adev->pdev->revision) {
3767         case 0xc2:
3768         case 0xc3:
3769                 ret = true;
3770                 break;
3771         default:
3772                 ret = false;
3773                 break;
3774         }
3775
3776         return ret ;
3777 }
3778
3779 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3780 {
3781         switch (adev->asic_type) {
3782         case CHIP_NAVI10:
3783                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3784                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3785                 break;
3786         default:
3787                 break;
3788         }
3789 }
3790
3791 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3792 {
3793         const char *chip_name;
3794         char fw_name[40];
3795         char wks[10];
3796         int err;
3797         struct amdgpu_firmware_info *info = NULL;
3798         const struct common_firmware_header *header = NULL;
3799         const struct gfx_firmware_header_v1_0 *cp_hdr;
3800         const struct rlc_firmware_header_v2_0 *rlc_hdr;
3801         unsigned int *tmp = NULL;
3802         unsigned int i = 0;
3803         uint16_t version_major;
3804         uint16_t version_minor;
3805
3806         DRM_DEBUG("\n");
3807
3808         memset(wks, 0, sizeof(wks));
3809         switch (adev->asic_type) {
3810         case CHIP_NAVI10:
3811                 chip_name = "navi10";
3812                 break;
3813         case CHIP_NAVI14:
3814                 chip_name = "navi14";
3815                 if (!(adev->pdev->device == 0x7340 &&
3816                       adev->pdev->revision != 0x00))
3817                         snprintf(wks, sizeof(wks), "_wks");
3818                 break;
3819         case CHIP_NAVI12:
3820                 chip_name = "navi12";
3821                 break;
3822         case CHIP_SIENNA_CICHLID:
3823                 chip_name = "sienna_cichlid";
3824                 break;
3825         case CHIP_NAVY_FLOUNDER:
3826                 chip_name = "navy_flounder";
3827                 break;
3828         case CHIP_VANGOGH:
3829                 chip_name = "vangogh";
3830                 break;
3831         case CHIP_DIMGREY_CAVEFISH:
3832                 chip_name = "dimgrey_cavefish";
3833                 break;
3834         default:
3835                 BUG();
3836         }
3837
3838         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
3839         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
3840         if (err)
3841                 goto out;
3842         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
3843         if (err)
3844                 goto out;
3845         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3846         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3847         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3848
3849         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
3850         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
3851         if (err)
3852                 goto out;
3853         err = amdgpu_ucode_validate(adev->gfx.me_fw);
3854         if (err)
3855                 goto out;
3856         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3857         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3858         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3859
3860         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
3861         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
3862         if (err)
3863                 goto out;
3864         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
3865         if (err)
3866                 goto out;
3867         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3868         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3869         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3870
3871         if (!amdgpu_sriov_vf(adev)) {
3872                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
3873                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
3874                 if (err)
3875                         goto out;
3876                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
3877                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3878                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
3879                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
3880
3881                 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
3882                 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
3883                 adev->gfx.rlc.save_and_restore_offset =
3884                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
3885                 adev->gfx.rlc.clear_state_descriptor_offset =
3886                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
3887                 adev->gfx.rlc.avail_scratch_ram_locations =
3888                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
3889                 adev->gfx.rlc.reg_restore_list_size =
3890                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
3891                 adev->gfx.rlc.reg_list_format_start =
3892                         le32_to_cpu(rlc_hdr->reg_list_format_start);
3893                 adev->gfx.rlc.reg_list_format_separate_start =
3894                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
3895                 adev->gfx.rlc.starting_offsets_start =
3896                         le32_to_cpu(rlc_hdr->starting_offsets_start);
3897                 adev->gfx.rlc.reg_list_format_size_bytes =
3898                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
3899                 adev->gfx.rlc.reg_list_size_bytes =
3900                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
3901                 adev->gfx.rlc.register_list_format =
3902                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
3903                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
3904                 if (!adev->gfx.rlc.register_list_format) {
3905                         err = -ENOMEM;
3906                         goto out;
3907                 }
3908
3909                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3910                                                            le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
3911                 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
3912                         adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
3913
3914                 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
3915
3916                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3917                                                            le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
3918                 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
3919                         adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
3920
3921                 if (version_major == 2) {
3922                         if (version_minor >= 1)
3923                                 gfx_v10_0_init_rlc_ext_microcode(adev);
3924                         if (version_minor == 2)
3925                                 gfx_v10_0_init_rlc_iram_dram_microcode(adev);
3926                 }
3927         }
3928
3929         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
3930         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
3931         if (err)
3932                 goto out;
3933         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
3934         if (err)
3935                 goto out;
3936         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3937         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3938         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3939
3940         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
3941         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
3942         if (!err) {
3943                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
3944                 if (err)
3945                         goto out;
3946                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
3947                 adev->gfx.mec2_fw->data;
3948                 adev->gfx.mec2_fw_version =
3949                 le32_to_cpu(cp_hdr->header.ucode_version);
3950                 adev->gfx.mec2_feature_version =
3951                 le32_to_cpu(cp_hdr->ucode_feature_version);
3952         } else {
3953                 err = 0;
3954                 adev->gfx.mec2_fw = NULL;
3955         }
3956
3957         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
3958                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
3959                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
3960                 info->fw = adev->gfx.pfp_fw;
3961                 header = (const struct common_firmware_header *)info->fw->data;
3962                 adev->firmware.fw_size +=
3963                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3964
3965                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
3966                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
3967                 info->fw = adev->gfx.me_fw;
3968                 header = (const struct common_firmware_header *)info->fw->data;
3969                 adev->firmware.fw_size +=
3970                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3971
3972                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
3973                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
3974                 info->fw = adev->gfx.ce_fw;
3975                 header = (const struct common_firmware_header *)info->fw->data;
3976                 adev->firmware.fw_size +=
3977                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3978
3979                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
3980                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
3981                 info->fw = adev->gfx.rlc_fw;
3982                 if (info->fw) {
3983                         header = (const struct common_firmware_header *)info->fw->data;
3984                         adev->firmware.fw_size +=
3985                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3986                 }
3987                 if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
3988                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
3989                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
3990                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
3991                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
3992                         info->fw = adev->gfx.rlc_fw;
3993                         adev->firmware.fw_size +=
3994                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
3995
3996                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
3997                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
3998                         info->fw = adev->gfx.rlc_fw;
3999                         adev->firmware.fw_size +=
4000                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
4001
4002                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
4003                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
4004                         info->fw = adev->gfx.rlc_fw;
4005                         adev->firmware.fw_size +=
4006                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
4007
4008                         if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
4009                             adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
4010                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
4011                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
4012                                 info->fw = adev->gfx.rlc_fw;
4013                                 adev->firmware.fw_size +=
4014                                         ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
4015
4016                                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
4017                                 info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
4018                                 info->fw = adev->gfx.rlc_fw;
4019                                 adev->firmware.fw_size +=
4020                                         ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
4021                         }
4022                 }
4023
4024                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
4025                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
4026                 info->fw = adev->gfx.mec_fw;
4027                 header = (const struct common_firmware_header *)info->fw->data;
4028                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4029                 adev->firmware.fw_size +=
4030                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4031                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4032
4033                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
4034                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
4035                 info->fw = adev->gfx.mec_fw;
4036                 adev->firmware.fw_size +=
4037                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
4038
4039                 if (adev->gfx.mec2_fw) {
4040                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
4041                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
4042                         info->fw = adev->gfx.mec2_fw;
4043                         header = (const struct common_firmware_header *)info->fw->data;
4044                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
4045                         adev->firmware.fw_size +=
4046                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
4047                                       le32_to_cpu(cp_hdr->jt_size) * 4,
4048                                       PAGE_SIZE);
4049                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
4050                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
4051                         info->fw = adev->gfx.mec2_fw;
4052                         adev->firmware.fw_size +=
4053                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
4054                                       PAGE_SIZE);
4055                 }
4056         }
4057
4058         gfx_v10_0_check_fw_write_wait(adev);
4059 out:
4060         if (err) {
4061                 dev_err(adev->dev,
4062                         "gfx10: Failed to load firmware \"%s\"\n",
4063                         fw_name);
4064                 release_firmware(adev->gfx.pfp_fw);
4065                 adev->gfx.pfp_fw = NULL;
4066                 release_firmware(adev->gfx.me_fw);
4067                 adev->gfx.me_fw = NULL;
4068                 release_firmware(adev->gfx.ce_fw);
4069                 adev->gfx.ce_fw = NULL;
4070                 release_firmware(adev->gfx.rlc_fw);
4071                 adev->gfx.rlc_fw = NULL;
4072                 release_firmware(adev->gfx.mec_fw);
4073                 adev->gfx.mec_fw = NULL;
4074                 release_firmware(adev->gfx.mec2_fw);
4075                 adev->gfx.mec2_fw = NULL;
4076         }
4077
4078         gfx_v10_0_check_gfxoff_flag(adev);
4079
4080         return err;
4081 }
4082
4083 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4084 {
4085         u32 count = 0;
4086         const struct cs_section_def *sect = NULL;
4087         const struct cs_extent_def *ext = NULL;
4088
4089         /* begin clear state */
4090         count += 2;
4091         /* context control state */
4092         count += 3;
4093
4094         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4095                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4096                         if (sect->id == SECT_CONTEXT)
4097                                 count += 2 + ext->reg_count;
4098                         else
4099                                 return 0;
4100                 }
4101         }
4102
4103         /* set PA_SC_TILE_STEERING_OVERRIDE */
4104         count += 3;
4105         /* end clear state */
4106         count += 2;
4107         /* clear state */
4108         count += 2;
4109
4110         return count;
4111 }
4112
4113 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4114                                     volatile u32 *buffer)
4115 {
4116         u32 count = 0, i;
4117         const struct cs_section_def *sect = NULL;
4118         const struct cs_extent_def *ext = NULL;
4119         int ctx_reg_offset;
4120
4121         if (adev->gfx.rlc.cs_data == NULL)
4122                 return;
4123         if (buffer == NULL)
4124                 return;
4125
4126         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4127         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4128
4129         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4130         buffer[count++] = cpu_to_le32(0x80000000);
4131         buffer[count++] = cpu_to_le32(0x80000000);
4132
4133         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4134                 for (ext = sect->section; ext->extent != NULL; ++ext) {
4135                         if (sect->id == SECT_CONTEXT) {
4136                                 buffer[count++] =
4137                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4138                                 buffer[count++] = cpu_to_le32(ext->reg_index -
4139                                                 PACKET3_SET_CONTEXT_REG_START);
4140                                 for (i = 0; i < ext->reg_count; i++)
4141                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
4142                         } else {
4143                                 return;
4144                         }
4145                 }
4146         }
4147
4148         ctx_reg_offset =
4149                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4150         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4151         buffer[count++] = cpu_to_le32(ctx_reg_offset);
4152         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4153
4154         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4155         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4156
4157         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4158         buffer[count++] = cpu_to_le32(0);
4159 }
4160
4161 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4162 {
4163         /* clear state block */
4164         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4165                         &adev->gfx.rlc.clear_state_gpu_addr,
4166                         (void **)&adev->gfx.rlc.cs_ptr);
4167
4168         /* jump table block */
4169         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4170                         &adev->gfx.rlc.cp_table_gpu_addr,
4171                         (void **)&adev->gfx.rlc.cp_table_ptr);
4172 }
4173
4174 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4175 {
4176         const struct cs_section_def *cs_data;
4177         int r;
4178
4179         adev->gfx.rlc.cs_data = gfx10_cs_data;
4180
4181         cs_data = adev->gfx.rlc.cs_data;
4182
4183         if (cs_data) {
4184                 /* init clear state block */
4185                 r = amdgpu_gfx_rlc_init_csb(adev);
4186                 if (r)
4187                         return r;
4188         }
4189
4190         /* init spm vmid with 0xf */
4191         if (adev->gfx.rlc.funcs->update_spm_vmid)
4192                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4193
4194         return 0;
4195 }
4196
4197 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4198 {
4199         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4200         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4201 }
4202
4203 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4204 {
4205         int r;
4206
4207         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4208
4209         amdgpu_gfx_graphics_queue_acquire(adev);
4210
4211         r = gfx_v10_0_init_microcode(adev);
4212         if (r)
4213                 DRM_ERROR("Failed to load gfx firmware!\n");
4214
4215         return r;
4216 }
4217
4218 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4219 {
4220         int r;
4221         u32 *hpd;
4222         const __le32 *fw_data = NULL;
4223         unsigned fw_size;
4224         u32 *fw = NULL;
4225         size_t mec_hpd_size;
4226
4227         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4228
4229         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4230
4231         /* take ownership of the relevant compute queues */
4232         amdgpu_gfx_compute_queue_acquire(adev);
4233         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4234
4235         if (mec_hpd_size) {
4236                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4237                                               AMDGPU_GEM_DOMAIN_GTT,
4238                                               &adev->gfx.mec.hpd_eop_obj,
4239                                               &adev->gfx.mec.hpd_eop_gpu_addr,
4240                                               (void **)&hpd);
4241                 if (r) {
4242                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4243                         gfx_v10_0_mec_fini(adev);
4244                         return r;
4245                 }
4246
4247                 memset(hpd, 0, mec_hpd_size);
4248
4249                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4250                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4251         }
4252
4253         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4254                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4255
4256                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4257                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4258                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4259
4260                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4261                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4262                                               &adev->gfx.mec.mec_fw_obj,
4263                                               &adev->gfx.mec.mec_fw_gpu_addr,
4264                                               (void **)&fw);
4265                 if (r) {
4266                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4267                         gfx_v10_0_mec_fini(adev);
4268                         return r;
4269                 }
4270
4271                 memcpy(fw, fw_data, fw_size);
4272
4273                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4274                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4275         }
4276
4277         return 0;
4278 }
4279
4280 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4281 {
4282         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4283                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4284                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4285         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4286 }
4287
4288 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4289                            uint32_t thread, uint32_t regno,
4290                            uint32_t num, uint32_t *out)
4291 {
4292         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4293                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4294                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4295                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4296                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4297         while (num--)
4298                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4299 }
4300
4301 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4302 {
4303         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4304          * field when performing a select_se_sh so it should be
4305          * zero here */
4306         WARN_ON(simd != 0);
4307
4308         /* type 2 wave data */
4309         dst[(*no_fields)++] = 2;
4310         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4311         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4312         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4313         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4314         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4315         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4316         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4317         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4318         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4319         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4320         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4321         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4322         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4323         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4324         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4325 }
4326
4327 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4328                                      uint32_t wave, uint32_t start,
4329                                      uint32_t size, uint32_t *dst)
4330 {
4331         WARN_ON(simd != 0);
4332
4333         wave_read_regs(
4334                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4335                 dst);
4336 }
4337
4338 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4339                                       uint32_t wave, uint32_t thread,
4340                                       uint32_t start, uint32_t size,
4341                                       uint32_t *dst)
4342 {
4343         wave_read_regs(
4344                 adev, wave, thread,
4345                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4346 }
4347
4348 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4349                                        u32 me, u32 pipe, u32 q, u32 vm)
4350 {
4351         nv_grbm_select(adev, me, pipe, q, vm);
4352 }
4353
4354 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4355                                           bool enable)
4356 {
4357         uint32_t data, def;
4358
4359         data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4360
4361         if (enable)
4362                 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4363         else
4364                 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4365
4366         if (data != def)
4367                 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4368 }
4369
4370 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4371         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4372         .select_se_sh = &gfx_v10_0_select_se_sh,
4373         .read_wave_data = &gfx_v10_0_read_wave_data,
4374         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4375         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4376         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4377         .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4378         .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4379 };
4380
4381 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4382 {
4383         u32 gb_addr_config;
4384
4385         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4386
4387         switch (adev->asic_type) {
4388         case CHIP_NAVI10:
4389         case CHIP_NAVI14:
4390         case CHIP_NAVI12:
4391                 adev->gfx.config.max_hw_contexts = 8;
4392                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4393                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4394                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4395                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4396                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4397                 break;
4398         case CHIP_SIENNA_CICHLID:
4399         case CHIP_NAVY_FLOUNDER:
4400         case CHIP_VANGOGH:
4401         case CHIP_DIMGREY_CAVEFISH:
4402                 adev->gfx.config.max_hw_contexts = 8;
4403                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4404                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4405                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4406                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4407                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4408                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4409                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4410                 break;
4411         default:
4412                 BUG();
4413                 break;
4414         }
4415
4416         adev->gfx.config.gb_addr_config = gb_addr_config;
4417
4418         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4419                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4420                                       GB_ADDR_CONFIG, NUM_PIPES);
4421
4422         adev->gfx.config.max_tile_pipes =
4423                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4424
4425         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4426                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4427                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4428         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4429                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4430                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4431         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4432                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4433                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4434         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4435                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4436                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4437 }
4438
4439 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4440                                    int me, int pipe, int queue)
4441 {
4442         int r;
4443         struct amdgpu_ring *ring;
4444         unsigned int irq_type;
4445
4446         ring = &adev->gfx.gfx_ring[ring_id];
4447
4448         ring->me = me;
4449         ring->pipe = pipe;
4450         ring->queue = queue;
4451
4452         ring->ring_obj = NULL;
4453         ring->use_doorbell = true;
4454
4455         if (!ring_id)
4456                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4457         else
4458                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4459         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4460
4461         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4462         r = amdgpu_ring_init(adev, ring, 1024,
4463                              &adev->gfx.eop_irq, irq_type,
4464                              AMDGPU_RING_PRIO_DEFAULT);
4465         if (r)
4466                 return r;
4467         return 0;
4468 }
4469
4470 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4471                                        int mec, int pipe, int queue)
4472 {
4473         int r;
4474         unsigned irq_type;
4475         struct amdgpu_ring *ring;
4476         unsigned int hw_prio;
4477
4478         ring = &adev->gfx.compute_ring[ring_id];
4479
4480         /* mec0 is me1 */
4481         ring->me = mec + 1;
4482         ring->pipe = pipe;
4483         ring->queue = queue;
4484
4485         ring->ring_obj = NULL;
4486         ring->use_doorbell = true;
4487         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4488         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4489                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4490         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4491
4492         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4493                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4494                 + ring->pipe;
4495         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4496                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4497         /* type-2 packets are deprecated on MEC, use type-3 instead */
4498         r = amdgpu_ring_init(adev, ring, 1024,
4499                              &adev->gfx.eop_irq, irq_type, hw_prio);
4500         if (r)
4501                 return r;
4502
4503         return 0;
4504 }
4505
4506 static int gfx_v10_0_sw_init(void *handle)
4507 {
4508         int i, j, k, r, ring_id = 0;
4509         struct amdgpu_kiq *kiq;
4510         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4511
4512         switch (adev->asic_type) {
4513         case CHIP_NAVI10:
4514         case CHIP_NAVI14:
4515         case CHIP_NAVI12:
4516                 adev->gfx.me.num_me = 1;
4517                 adev->gfx.me.num_pipe_per_me = 1;
4518                 adev->gfx.me.num_queue_per_pipe = 1;
4519                 adev->gfx.mec.num_mec = 2;
4520                 adev->gfx.mec.num_pipe_per_mec = 4;
4521                 adev->gfx.mec.num_queue_per_pipe = 8;
4522                 break;
4523         case CHIP_SIENNA_CICHLID:
4524         case CHIP_NAVY_FLOUNDER:
4525         case CHIP_VANGOGH:
4526         case CHIP_DIMGREY_CAVEFISH:
4527                 adev->gfx.me.num_me = 1;
4528                 adev->gfx.me.num_pipe_per_me = 1;
4529                 adev->gfx.me.num_queue_per_pipe = 1;
4530                 adev->gfx.mec.num_mec = 2;
4531                 adev->gfx.mec.num_pipe_per_mec = 4;
4532                 adev->gfx.mec.num_queue_per_pipe = 4;
4533                 break;
4534         default:
4535                 adev->gfx.me.num_me = 1;
4536                 adev->gfx.me.num_pipe_per_me = 1;
4537                 adev->gfx.me.num_queue_per_pipe = 1;
4538                 adev->gfx.mec.num_mec = 1;
4539                 adev->gfx.mec.num_pipe_per_mec = 4;
4540                 adev->gfx.mec.num_queue_per_pipe = 8;
4541                 break;
4542         }
4543
4544         /* KIQ event */
4545         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4546                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4547                               &adev->gfx.kiq.irq);
4548         if (r)
4549                 return r;
4550
4551         /* EOP Event */
4552         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4553                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4554                               &adev->gfx.eop_irq);
4555         if (r)
4556                 return r;
4557
4558         /* Privileged reg */
4559         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4560                               &adev->gfx.priv_reg_irq);
4561         if (r)
4562                 return r;
4563
4564         /* Privileged inst */
4565         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4566                               &adev->gfx.priv_inst_irq);
4567         if (r)
4568                 return r;
4569
4570         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4571
4572         gfx_v10_0_scratch_init(adev);
4573
4574         r = gfx_v10_0_me_init(adev);
4575         if (r)
4576                 return r;
4577
4578         r = gfx_v10_0_rlc_init(adev);
4579         if (r) {
4580                 DRM_ERROR("Failed to init rlc BOs!\n");
4581                 return r;
4582         }
4583
4584         r = gfx_v10_0_mec_init(adev);
4585         if (r) {
4586                 DRM_ERROR("Failed to init MEC BOs!\n");
4587                 return r;
4588         }
4589
4590         /* set up the gfx ring */
4591         for (i = 0; i < adev->gfx.me.num_me; i++) {
4592                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4593                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4594                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4595                                         continue;
4596
4597                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4598                                                             i, k, j);
4599                                 if (r)
4600                                         return r;
4601                                 ring_id++;
4602                         }
4603                 }
4604         }
4605
4606         ring_id = 0;
4607         /* set up the compute queues - allocate horizontally across pipes */
4608         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4609                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4610                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4611                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4612                                                                      j))
4613                                         continue;
4614
4615                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4616                                                                 i, k, j);
4617                                 if (r)
4618                                         return r;
4619
4620                                 ring_id++;
4621                         }
4622                 }
4623         }
4624
4625         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4626         if (r) {
4627                 DRM_ERROR("Failed to init KIQ BOs!\n");
4628                 return r;
4629         }
4630
4631         kiq = &adev->gfx.kiq;
4632         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4633         if (r)
4634                 return r;
4635
4636         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4637         if (r)
4638                 return r;
4639
4640         /* allocate visible FB for rlc auto-loading fw */
4641         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4642                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4643                 if (r)
4644                         return r;
4645         }
4646
4647         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4648
4649         gfx_v10_0_gpu_early_init(adev);
4650
4651         return 0;
4652 }
4653
4654 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4655 {
4656         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4657                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4658                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4659 }
4660
4661 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4662 {
4663         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4664                               &adev->gfx.ce.ce_fw_gpu_addr,
4665                               (void **)&adev->gfx.ce.ce_fw_ptr);
4666 }
4667
4668 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4669 {
4670         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4671                               &adev->gfx.me.me_fw_gpu_addr,
4672                               (void **)&adev->gfx.me.me_fw_ptr);
4673 }
4674
4675 static int gfx_v10_0_sw_fini(void *handle)
4676 {
4677         int i;
4678         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4679
4680         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4681                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4682         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4683                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4684
4685         amdgpu_gfx_mqd_sw_fini(adev);
4686         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4687         amdgpu_gfx_kiq_fini(adev);
4688
4689         gfx_v10_0_pfp_fini(adev);
4690         gfx_v10_0_ce_fini(adev);
4691         gfx_v10_0_me_fini(adev);
4692         gfx_v10_0_rlc_fini(adev);
4693         gfx_v10_0_mec_fini(adev);
4694
4695         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4696                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4697
4698         gfx_v10_0_free_microcode(adev);
4699
4700         return 0;
4701 }
4702
4703 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4704                                    u32 sh_num, u32 instance)
4705 {
4706         u32 data;
4707
4708         if (instance == 0xffffffff)
4709                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4710                                      INSTANCE_BROADCAST_WRITES, 1);
4711         else
4712                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4713                                      instance);
4714
4715         if (se_num == 0xffffffff)
4716                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4717                                      1);
4718         else
4719                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4720
4721         if (sh_num == 0xffffffff)
4722                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4723                                      1);
4724         else
4725                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4726
4727         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4728 }
4729
4730 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4731 {
4732         u32 data, mask;
4733
4734         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4735         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4736
4737         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4738         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4739
4740         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4741                                          adev->gfx.config.max_sh_per_se);
4742
4743         return (~data) & mask;
4744 }
4745
4746 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4747 {
4748         int i, j;
4749         u32 data;
4750         u32 active_rbs = 0;
4751         u32 bitmap;
4752         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4753                                         adev->gfx.config.max_sh_per_se;
4754
4755         mutex_lock(&adev->grbm_idx_mutex);
4756         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4757                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4758                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
4759                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
4760                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4761                                 continue;
4762                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4763                         data = gfx_v10_0_get_rb_active_bitmap(adev);
4764                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4765                                                rb_bitmap_width_per_sh);
4766                 }
4767         }
4768         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4769         mutex_unlock(&adev->grbm_idx_mutex);
4770
4771         adev->gfx.config.backend_enable_mask = active_rbs;
4772         adev->gfx.config.num_rbs = hweight32(active_rbs);
4773 }
4774
4775 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4776 {
4777         uint32_t num_sc;
4778         uint32_t enabled_rb_per_sh;
4779         uint32_t active_rb_bitmap;
4780         uint32_t num_rb_per_sc;
4781         uint32_t num_packer_per_sc;
4782         uint32_t pa_sc_tile_steering_override;
4783
4784         /* for ASICs that integrates GFX v10.3
4785          * pa_sc_tile_steering_override should be set to 0 */
4786         if (adev->asic_type >= CHIP_SIENNA_CICHLID)
4787                 return 0;
4788
4789         /* init num_sc */
4790         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4791                         adev->gfx.config.num_sc_per_sh;
4792         /* init num_rb_per_sc */
4793         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4794         enabled_rb_per_sh = hweight32(active_rb_bitmap);
4795         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4796         /* init num_packer_per_sc */
4797         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4798
4799         pa_sc_tile_steering_override = 0;
4800         pa_sc_tile_steering_override |=
4801                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4802                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4803         pa_sc_tile_steering_override |=
4804                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4805                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4806         pa_sc_tile_steering_override |=
4807                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4808                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4809
4810         return pa_sc_tile_steering_override;
4811 }
4812
4813 #define DEFAULT_SH_MEM_BASES    (0x6000)
4814
4815 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4816 {
4817         int i;
4818         uint32_t sh_mem_bases;
4819
4820         /*
4821          * Configure apertures:
4822          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
4823          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
4824          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
4825          */
4826         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4827
4828         mutex_lock(&adev->srbm_mutex);
4829         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4830                 nv_grbm_select(adev, 0, 0, 0, i);
4831                 /* CP and shaders */
4832                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4833                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4834         }
4835         nv_grbm_select(adev, 0, 0, 0, 0);
4836         mutex_unlock(&adev->srbm_mutex);
4837
4838         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
4839            acccess. These should be enabled by FW for target VMIDs. */
4840         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4841                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4842                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4843                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4844                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4845         }
4846 }
4847
4848 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4849 {
4850         int vmid;
4851
4852         /*
4853          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4854          * access. Compute VMIDs should be enabled by FW for target VMIDs,
4855          * the driver can enable them for graphics. VMID0 should maintain
4856          * access so that HWS firmware can save/restore entries.
4857          */
4858         for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
4859                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4860                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
4861                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
4862                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
4863         }
4864 }
4865
4866
4867 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4868 {
4869         int i, j, k;
4870         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4871         u32 tmp, wgp_active_bitmap = 0;
4872         u32 gcrd_targets_disable_tcp = 0;
4873         u32 utcl_invreq_disable = 0;
4874         /*
4875          * GCRD_TARGETS_DISABLE field contains
4876          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4877          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4878          */
4879         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4880                 2 * max_wgp_per_sh + /* TCP */
4881                 max_wgp_per_sh + /* SQC */
4882                 4); /* GL1C */
4883         /*
4884          * UTCL1_UTCL0_INVREQ_DISABLE field contains
4885          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4886          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4887          */
4888         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4889                 2 * max_wgp_per_sh + /* TCP */
4890                 2 * max_wgp_per_sh + /* SQC */
4891                 4 + /* RMI */
4892                 1); /* SQG */
4893
4894         if (adev->asic_type == CHIP_NAVI10 ||
4895             adev->asic_type == CHIP_NAVI14 ||
4896             adev->asic_type == CHIP_NAVI12) {
4897                 mutex_lock(&adev->grbm_idx_mutex);
4898                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4899                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4900                                 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4901                                 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4902                                 /*
4903                                  * Set corresponding TCP bits for the inactive WGPs in
4904                                  * GCRD_SA_TARGETS_DISABLE
4905                                  */
4906                                 gcrd_targets_disable_tcp = 0;
4907                                 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
4908                                 utcl_invreq_disable = 0;
4909
4910                                 for (k = 0; k < max_wgp_per_sh; k++) {
4911                                         if (!(wgp_active_bitmap & (1 << k))) {
4912                                                 gcrd_targets_disable_tcp |= 3 << (2 * k);
4913                                                 utcl_invreq_disable |= (3 << (2 * k)) |
4914                                                         (3 << (2 * (max_wgp_per_sh + k)));
4915                                         }
4916                                 }
4917
4918                                 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
4919                                 /* only override TCP & SQC bits */
4920                                 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
4921                                 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
4922                                 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
4923
4924                                 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
4925                                 /* only override TCP bits */
4926                                 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
4927                                 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
4928                                 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
4929                         }
4930                 }
4931
4932                 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4933                 mutex_unlock(&adev->grbm_idx_mutex);
4934         }
4935 }
4936
4937 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
4938 {
4939         /* TCCs are global (not instanced). */
4940         uint32_t tcc_disable;
4941
4942         if (adev->asic_type >= CHIP_SIENNA_CICHLID) {
4943                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
4944                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
4945         } else {
4946                 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
4947                               RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
4948         }
4949
4950         adev->gfx.config.tcc_disabled_mask =
4951                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
4952                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
4953 }
4954
4955 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
4956 {
4957         u32 tmp;
4958         int i;
4959
4960         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
4961
4962         gfx_v10_0_setup_rb(adev);
4963         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
4964         gfx_v10_0_get_tcc_info(adev);
4965         adev->gfx.config.pa_sc_tile_steering_override =
4966                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
4967
4968         /* XXX SH_MEM regs */
4969         /* where to put LDS, scratch, GPUVM in FSA64 space */
4970         mutex_lock(&adev->srbm_mutex);
4971         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
4972                 nv_grbm_select(adev, 0, 0, 0, i);
4973                 /* CP and shaders */
4974                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4975                 if (i != 0) {
4976                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
4977                                 (adev->gmc.private_aperture_start >> 48));
4978                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
4979                                 (adev->gmc.shared_aperture_start >> 48));
4980                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
4981                 }
4982         }
4983         nv_grbm_select(adev, 0, 0, 0, 0);
4984
4985         mutex_unlock(&adev->srbm_mutex);
4986
4987         gfx_v10_0_init_compute_vmid(adev);
4988         gfx_v10_0_init_gds_vmid(adev);
4989
4990 }
4991
4992 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
4993                                                bool enable)
4994 {
4995         u32 tmp;
4996
4997         if (amdgpu_sriov_vf(adev))
4998                 return;
4999
5000         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
5001
5002         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5003                             enable ? 1 : 0);
5004         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5005                             enable ? 1 : 0);
5006         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5007                             enable ? 1 : 0);
5008         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5009                             enable ? 1 : 0);
5010
5011         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
5012 }
5013
5014 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5015 {
5016         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5017
5018         /* csib */
5019         if (adev->asic_type == CHIP_NAVI12) {
5020                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5021                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5022                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5023                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5024                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5025         } else {
5026                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5027                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5028                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5029                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5030                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5031         }
5032         return 0;
5033 }
5034
5035 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5036 {
5037         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5038
5039         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5040         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5041 }
5042
5043 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5044 {
5045         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5046         udelay(50);
5047         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5048         udelay(50);
5049 }
5050
5051 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5052                                              bool enable)
5053 {
5054         uint32_t rlc_pg_cntl;
5055
5056         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5057
5058         if (!enable) {
5059                 /* RLC_PG_CNTL[23] = 0 (default)
5060                  * RLC will wait for handshake acks with SMU
5061                  * GFXOFF will be enabled
5062                  * RLC_PG_CNTL[23] = 1
5063                  * RLC will not issue any message to SMU
5064                  * hence no handshake between SMU & RLC
5065                  * GFXOFF will be disabled
5066                  */
5067                 rlc_pg_cntl |= 0x800000;
5068         } else
5069                 rlc_pg_cntl &= ~0x800000;
5070         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5071 }
5072
5073 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5074 {
5075         /* TODO: enable rlc & smu handshake until smu
5076          * and gfxoff feature works as expected */
5077         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5078                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5079
5080         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5081         udelay(50);
5082 }
5083
5084 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5085 {
5086         uint32_t tmp;
5087
5088         /* enable Save Restore Machine */
5089         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
5090         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5091         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5092         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
5093 }
5094
5095 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5096 {
5097         const struct rlc_firmware_header_v2_0 *hdr;
5098         const __le32 *fw_data;
5099         unsigned i, fw_size;
5100
5101         if (!adev->gfx.rlc_fw)
5102                 return -EINVAL;
5103
5104         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5105         amdgpu_ucode_print_rlc_hdr(&hdr->header);
5106
5107         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5108                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5109         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5110
5111         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5112                      RLCG_UCODE_LOADING_START_ADDRESS);
5113
5114         for (i = 0; i < fw_size; i++)
5115                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5116                              le32_to_cpup(fw_data++));
5117
5118         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5119
5120         return 0;
5121 }
5122
5123 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5124 {
5125         int r;
5126
5127         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
5128
5129                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5130                 if (r)
5131                         return r;
5132
5133                 gfx_v10_0_init_csb(adev);
5134
5135                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5136                         gfx_v10_0_rlc_enable_srm(adev);
5137         } else {
5138                 if (amdgpu_sriov_vf(adev)) {
5139                         gfx_v10_0_init_csb(adev);
5140                         return 0;
5141                 }
5142
5143                 adev->gfx.rlc.funcs->stop(adev);
5144
5145                 /* disable CG */
5146                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5147
5148                 /* disable PG */
5149                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5150
5151                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5152                         /* legacy rlc firmware loading */
5153                         r = gfx_v10_0_rlc_load_microcode(adev);
5154                         if (r)
5155                                 return r;
5156                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5157                         /* rlc backdoor autoload firmware */
5158                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5159                         if (r)
5160                                 return r;
5161                 }
5162
5163                 gfx_v10_0_init_csb(adev);
5164
5165                 adev->gfx.rlc.funcs->start(adev);
5166
5167                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5168                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5169                         if (r)
5170                                 return r;
5171                 }
5172         }
5173         return 0;
5174 }
5175
5176 static struct {
5177         FIRMWARE_ID     id;
5178         unsigned int    offset;
5179         unsigned int    size;
5180 } rlc_autoload_info[FIRMWARE_ID_MAX];
5181
5182 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5183 {
5184         int ret;
5185         RLC_TABLE_OF_CONTENT *rlc_toc;
5186
5187         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
5188                                         AMDGPU_GEM_DOMAIN_GTT,
5189                                         &adev->gfx.rlc.rlc_toc_bo,
5190                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
5191                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
5192         if (ret) {
5193                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5194                 return ret;
5195         }
5196
5197         /* Copy toc from psp sos fw to rlc toc buffer */
5198         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
5199
5200         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5201         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5202                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5203                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5204                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5205                         /* Offset needs 4KB alignment */
5206                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5207                 }
5208
5209                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5210                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5211                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5212
5213                 rlc_toc++;
5214         }
5215
5216         return 0;
5217 }
5218
5219 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5220 {
5221         uint32_t total_size = 0;
5222         FIRMWARE_ID id;
5223         int ret;
5224
5225         ret = gfx_v10_0_parse_rlc_toc(adev);
5226         if (ret) {
5227                 dev_err(adev->dev, "failed to parse rlc toc\n");
5228                 return 0;
5229         }
5230
5231         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5232                 total_size += rlc_autoload_info[id].size;
5233
5234         /* In case the offset in rlc toc ucode is aligned */
5235         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5236                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5237                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5238
5239         return total_size;
5240 }
5241
5242 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5243 {
5244         int r;
5245         uint32_t total_size;
5246
5247         total_size = gfx_v10_0_calc_toc_total_size(adev);
5248
5249         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5250                                       AMDGPU_GEM_DOMAIN_GTT,
5251                                       &adev->gfx.rlc.rlc_autoload_bo,
5252                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5253                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5254         if (r) {
5255                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5256                 return r;
5257         }
5258
5259         return 0;
5260 }
5261
5262 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5263 {
5264         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5265                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5266                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5267         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5268                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5269                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5270 }
5271
5272 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5273                                                        FIRMWARE_ID id,
5274                                                        const void *fw_data,
5275                                                        uint32_t fw_size)
5276 {
5277         uint32_t toc_offset;
5278         uint32_t toc_fw_size;
5279         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5280
5281         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5282                 return;
5283
5284         toc_offset = rlc_autoload_info[id].offset;
5285         toc_fw_size = rlc_autoload_info[id].size;
5286
5287         if (fw_size == 0)
5288                 fw_size = toc_fw_size;
5289
5290         if (fw_size > toc_fw_size)
5291                 fw_size = toc_fw_size;
5292
5293         memcpy(ptr + toc_offset, fw_data, fw_size);
5294
5295         if (fw_size < toc_fw_size)
5296                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5297 }
5298
5299 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5300 {
5301         void *data;
5302         uint32_t size;
5303
5304         data = adev->gfx.rlc.rlc_toc_buf;
5305         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5306
5307         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5308                                                    FIRMWARE_ID_RLC_TOC,
5309                                                    data, size);
5310 }
5311
5312 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5313 {
5314         const __le32 *fw_data;
5315         uint32_t fw_size;
5316         const struct gfx_firmware_header_v1_0 *cp_hdr;
5317         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5318
5319         /* pfp ucode */
5320         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5321                 adev->gfx.pfp_fw->data;
5322         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5323                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5324         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5325         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5326                                                    FIRMWARE_ID_CP_PFP,
5327                                                    fw_data, fw_size);
5328
5329         /* ce ucode */
5330         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5331                 adev->gfx.ce_fw->data;
5332         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5333                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5334         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5335         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5336                                                    FIRMWARE_ID_CP_CE,
5337                                                    fw_data, fw_size);
5338
5339         /* me ucode */
5340         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5341                 adev->gfx.me_fw->data;
5342         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5343                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5344         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5345         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5346                                                    FIRMWARE_ID_CP_ME,
5347                                                    fw_data, fw_size);
5348
5349         /* rlc ucode */
5350         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5351                 adev->gfx.rlc_fw->data;
5352         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5353                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5354         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5355         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5356                                                    FIRMWARE_ID_RLC_G_UCODE,
5357                                                    fw_data, fw_size);
5358
5359         /* mec1 ucode */
5360         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5361                 adev->gfx.mec_fw->data;
5362         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5363                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5364         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5365                 cp_hdr->jt_size * 4;
5366         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5367                                                    FIRMWARE_ID_CP_MEC,
5368                                                    fw_data, fw_size);
5369         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5370 }
5371
5372 /* Temporarily put sdma part here */
5373 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5374 {
5375         const __le32 *fw_data;
5376         uint32_t fw_size;
5377         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5378         int i;
5379
5380         for (i = 0; i < adev->sdma.num_instances; i++) {
5381                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5382                         adev->sdma.instance[i].fw->data;
5383                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5384                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5385                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5386
5387                 if (i == 0) {
5388                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5389                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5390                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5391                                 FIRMWARE_ID_SDMA0_JT,
5392                                 (uint32_t *)fw_data +
5393                                 sdma_hdr->jt_offset,
5394                                 sdma_hdr->jt_size * 4);
5395                 } else if (i == 1) {
5396                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5397                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5398                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5399                                 FIRMWARE_ID_SDMA1_JT,
5400                                 (uint32_t *)fw_data +
5401                                 sdma_hdr->jt_offset,
5402                                 sdma_hdr->jt_size * 4);
5403                 }
5404         }
5405 }
5406
5407 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5408 {
5409         uint32_t rlc_g_offset, rlc_g_size, tmp;
5410         uint64_t gpu_addr;
5411
5412         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5413         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5414         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5415
5416         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5417         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5418         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5419
5420         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5421         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5422         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5423
5424         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5425         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5426                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5427                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5428                 return -EINVAL;
5429         }
5430
5431         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5432         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5433                 DRM_ERROR("RLC ROM should halt itself\n");
5434                 return -EINVAL;
5435         }
5436
5437         return 0;
5438 }
5439
5440 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5441 {
5442         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5443         uint32_t tmp;
5444         int i;
5445         uint64_t addr;
5446
5447         /* Trigger an invalidation of the L1 instruction caches */
5448         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5449         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5450         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5451
5452         /* Wait for invalidation complete */
5453         for (i = 0; i < usec_timeout; i++) {
5454                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5455                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5456                         INVALIDATE_CACHE_COMPLETE))
5457                         break;
5458                 udelay(1);
5459         }
5460
5461         if (i >= usec_timeout) {
5462                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5463                 return -EINVAL;
5464         }
5465
5466         /* Program me ucode address into intruction cache address register */
5467         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5468                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5469         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5470                         lower_32_bits(addr) & 0xFFFFF000);
5471         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5472                         upper_32_bits(addr));
5473
5474         return 0;
5475 }
5476
5477 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5478 {
5479         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5480         uint32_t tmp;
5481         int i;
5482         uint64_t addr;
5483
5484         /* Trigger an invalidation of the L1 instruction caches */
5485         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5486         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5487         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5488
5489         /* Wait for invalidation complete */
5490         for (i = 0; i < usec_timeout; i++) {
5491                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5492                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5493                         INVALIDATE_CACHE_COMPLETE))
5494                         break;
5495                 udelay(1);
5496         }
5497
5498         if (i >= usec_timeout) {
5499                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5500                 return -EINVAL;
5501         }
5502
5503         /* Program ce ucode address into intruction cache address register */
5504         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5505                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5506         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5507                         lower_32_bits(addr) & 0xFFFFF000);
5508         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5509                         upper_32_bits(addr));
5510
5511         return 0;
5512 }
5513
5514 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5515 {
5516         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5517         uint32_t tmp;
5518         int i;
5519         uint64_t addr;
5520
5521         /* Trigger an invalidation of the L1 instruction caches */
5522         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5523         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5524         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5525
5526         /* Wait for invalidation complete */
5527         for (i = 0; i < usec_timeout; i++) {
5528                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5529                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5530                         INVALIDATE_CACHE_COMPLETE))
5531                         break;
5532                 udelay(1);
5533         }
5534
5535         if (i >= usec_timeout) {
5536                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5537                 return -EINVAL;
5538         }
5539
5540         /* Program pfp ucode address into intruction cache address register */
5541         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5542                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5543         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5544                         lower_32_bits(addr) & 0xFFFFF000);
5545         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5546                         upper_32_bits(addr));
5547
5548         return 0;
5549 }
5550
5551 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5552 {
5553         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5554         uint32_t tmp;
5555         int i;
5556         uint64_t addr;
5557
5558         /* Trigger an invalidation of the L1 instruction caches */
5559         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5560         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5561         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5562
5563         /* Wait for invalidation complete */
5564         for (i = 0; i < usec_timeout; i++) {
5565                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5566                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5567                         INVALIDATE_CACHE_COMPLETE))
5568                         break;
5569                 udelay(1);
5570         }
5571
5572         if (i >= usec_timeout) {
5573                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5574                 return -EINVAL;
5575         }
5576
5577         /* Program mec1 ucode address into intruction cache address register */
5578         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5579                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5580         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5581                         lower_32_bits(addr) & 0xFFFFF000);
5582         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5583                         upper_32_bits(addr));
5584
5585         return 0;
5586 }
5587
5588 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5589 {
5590         uint32_t cp_status;
5591         uint32_t bootload_status;
5592         int i, r;
5593
5594         for (i = 0; i < adev->usec_timeout; i++) {
5595                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5596                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5597                 if ((cp_status == 0) &&
5598                     (REG_GET_FIELD(bootload_status,
5599                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5600                         break;
5601                 }
5602                 udelay(1);
5603         }
5604
5605         if (i >= adev->usec_timeout) {
5606                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5607                 return -ETIMEDOUT;
5608         }
5609
5610         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5611                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5612                 if (r)
5613                         return r;
5614
5615                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5616                 if (r)
5617                         return r;
5618
5619                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5620                 if (r)
5621                         return r;
5622
5623                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5624                 if (r)
5625                         return r;
5626         }
5627
5628         return 0;
5629 }
5630
5631 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5632 {
5633         int i;
5634         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5635
5636         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5637         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5638         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5639
5640         if (adev->asic_type == CHIP_NAVI12) {
5641                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5642         } else {
5643                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5644         }
5645
5646         for (i = 0; i < adev->usec_timeout; i++) {
5647                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5648                         break;
5649                 udelay(1);
5650         }
5651
5652         if (i >= adev->usec_timeout)
5653                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5654
5655         return 0;
5656 }
5657
5658 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5659 {
5660         int r;
5661         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5662         const __le32 *fw_data;
5663         unsigned i, fw_size;
5664         uint32_t tmp;
5665         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5666
5667         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5668                 adev->gfx.pfp_fw->data;
5669
5670         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5671
5672         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5673                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5674         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5675
5676         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5677                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5678                                       &adev->gfx.pfp.pfp_fw_obj,
5679                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5680                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5681         if (r) {
5682                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5683                 gfx_v10_0_pfp_fini(adev);
5684                 return r;
5685         }
5686
5687         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5688
5689         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5690         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5691
5692         /* Trigger an invalidation of the L1 instruction caches */
5693         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5694         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5695         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5696
5697         /* Wait for invalidation complete */
5698         for (i = 0; i < usec_timeout; i++) {
5699                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5700                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5701                         INVALIDATE_CACHE_COMPLETE))
5702                         break;
5703                 udelay(1);
5704         }
5705
5706         if (i >= usec_timeout) {
5707                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5708                 return -EINVAL;
5709         }
5710
5711         if (amdgpu_emu_mode == 1)
5712                 adev->hdp.funcs->flush_hdp(adev, NULL);
5713
5714         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5715         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5716         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5717         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5718         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5719         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5720         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5721                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5722         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5723                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5724
5725         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5726
5727         for (i = 0; i < pfp_hdr->jt_size; i++)
5728                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5729                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5730
5731         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5732
5733         return 0;
5734 }
5735
5736 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5737 {
5738         int r;
5739         const struct gfx_firmware_header_v1_0 *ce_hdr;
5740         const __le32 *fw_data;
5741         unsigned i, fw_size;
5742         uint32_t tmp;
5743         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5744
5745         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5746                 adev->gfx.ce_fw->data;
5747
5748         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5749
5750         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5751                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5752         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5753
5754         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5755                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5756                                       &adev->gfx.ce.ce_fw_obj,
5757                                       &adev->gfx.ce.ce_fw_gpu_addr,
5758                                       (void **)&adev->gfx.ce.ce_fw_ptr);
5759         if (r) {
5760                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5761                 gfx_v10_0_ce_fini(adev);
5762                 return r;
5763         }
5764
5765         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5766
5767         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5768         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5769
5770         /* Trigger an invalidation of the L1 instruction caches */
5771         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5772         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5773         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5774
5775         /* Wait for invalidation complete */
5776         for (i = 0; i < usec_timeout; i++) {
5777                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5778                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5779                         INVALIDATE_CACHE_COMPLETE))
5780                         break;
5781                 udelay(1);
5782         }
5783
5784         if (i >= usec_timeout) {
5785                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5786                 return -EINVAL;
5787         }
5788
5789         if (amdgpu_emu_mode == 1)
5790                 adev->hdp.funcs->flush_hdp(adev, NULL);
5791
5792         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5793         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5794         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5795         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5796         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5797         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5798                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5799         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5800                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5801
5802         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5803
5804         for (i = 0; i < ce_hdr->jt_size; i++)
5805                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5806                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5807
5808         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5809
5810         return 0;
5811 }
5812
5813 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5814 {
5815         int r;
5816         const struct gfx_firmware_header_v1_0 *me_hdr;
5817         const __le32 *fw_data;
5818         unsigned i, fw_size;
5819         uint32_t tmp;
5820         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5821
5822         me_hdr = (const struct gfx_firmware_header_v1_0 *)
5823                 adev->gfx.me_fw->data;
5824
5825         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5826
5827         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5828                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5829         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5830
5831         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5832                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5833                                       &adev->gfx.me.me_fw_obj,
5834                                       &adev->gfx.me.me_fw_gpu_addr,
5835                                       (void **)&adev->gfx.me.me_fw_ptr);
5836         if (r) {
5837                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5838                 gfx_v10_0_me_fini(adev);
5839                 return r;
5840         }
5841
5842         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5843
5844         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5845         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5846
5847         /* Trigger an invalidation of the L1 instruction caches */
5848         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5849         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5850         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5851
5852         /* Wait for invalidation complete */
5853         for (i = 0; i < usec_timeout; i++) {
5854                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5855                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5856                         INVALIDATE_CACHE_COMPLETE))
5857                         break;
5858                 udelay(1);
5859         }
5860
5861         if (i >= usec_timeout) {
5862                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5863                 return -EINVAL;
5864         }
5865
5866         if (amdgpu_emu_mode == 1)
5867                 adev->hdp.funcs->flush_hdp(adev, NULL);
5868
5869         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
5870         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
5871         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
5872         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
5873         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5874         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5875                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5876         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5877                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5878
5879         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
5880
5881         for (i = 0; i < me_hdr->jt_size; i++)
5882                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
5883                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
5884
5885         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
5886
5887         return 0;
5888 }
5889
5890 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5891 {
5892         int r;
5893
5894         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5895                 return -EINVAL;
5896
5897         gfx_v10_0_cp_gfx_enable(adev, false);
5898
5899         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5900         if (r) {
5901                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
5902                 return r;
5903         }
5904
5905         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
5906         if (r) {
5907                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
5908                 return r;
5909         }
5910
5911         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
5912         if (r) {
5913                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
5914                 return r;
5915         }
5916
5917         return 0;
5918 }
5919
5920 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
5921 {
5922         struct amdgpu_ring *ring;
5923         const struct cs_section_def *sect = NULL;
5924         const struct cs_extent_def *ext = NULL;
5925         int r, i;
5926         int ctx_reg_offset;
5927
5928         /* init the CP */
5929         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
5930                      adev->gfx.config.max_hw_contexts - 1);
5931         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
5932
5933         gfx_v10_0_cp_gfx_enable(adev, true);
5934
5935         ring = &adev->gfx.gfx_ring[0];
5936         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
5937         if (r) {
5938                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5939                 return r;
5940         }
5941
5942         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5943         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5944
5945         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5946         amdgpu_ring_write(ring, 0x80000000);
5947         amdgpu_ring_write(ring, 0x80000000);
5948
5949         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
5950                 for (ext = sect->section; ext->extent != NULL; ++ext) {
5951                         if (sect->id == SECT_CONTEXT) {
5952                                 amdgpu_ring_write(ring,
5953                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
5954                                                           ext->reg_count));
5955                                 amdgpu_ring_write(ring, ext->reg_index -
5956                                                   PACKET3_SET_CONTEXT_REG_START);
5957                                 for (i = 0; i < ext->reg_count; i++)
5958                                         amdgpu_ring_write(ring, ext->extent[i]);
5959                         }
5960                 }
5961         }
5962
5963         ctx_reg_offset =
5964                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
5965         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
5966         amdgpu_ring_write(ring, ctx_reg_offset);
5967         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
5968
5969         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5970         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
5971
5972         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5973         amdgpu_ring_write(ring, 0);
5974
5975         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
5976         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
5977         amdgpu_ring_write(ring, 0x8000);
5978         amdgpu_ring_write(ring, 0x8000);
5979
5980         amdgpu_ring_commit(ring);
5981
5982         /* submit cs packet to copy state 0 to next available state */
5983         if (adev->gfx.num_gfx_rings > 1) {
5984                 /* maximum supported gfx ring is 2 */
5985                 ring = &adev->gfx.gfx_ring[1];
5986                 r = amdgpu_ring_alloc(ring, 2);
5987                 if (r) {
5988                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5989                         return r;
5990                 }
5991
5992                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5993                 amdgpu_ring_write(ring, 0);
5994
5995                 amdgpu_ring_commit(ring);
5996         }
5997         return 0;
5998 }
5999
6000 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6001                                          CP_PIPE_ID pipe)
6002 {
6003         u32 tmp;
6004
6005         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6006         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6007
6008         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6009 }
6010
6011 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6012                                           struct amdgpu_ring *ring)
6013 {
6014         u32 tmp;
6015
6016         if (!amdgpu_async_gfx_ring) {
6017                 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6018                 if (ring->use_doorbell) {
6019                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6020                                                 DOORBELL_OFFSET, ring->doorbell_index);
6021                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6022                                                 DOORBELL_EN, 1);
6023                 } else {
6024                         tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6025                                                 DOORBELL_EN, 0);
6026                 }
6027                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6028         }
6029         switch (adev->asic_type) {
6030         case CHIP_SIENNA_CICHLID:
6031         case CHIP_NAVY_FLOUNDER:
6032         case CHIP_VANGOGH:
6033         case CHIP_DIMGREY_CAVEFISH:
6034                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6035                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6036                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6037
6038                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6039                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6040                 break;
6041         default:
6042                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6043                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
6044                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6045
6046                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6047                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6048                 break;
6049         }
6050 }
6051
6052 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6053 {
6054         struct amdgpu_ring *ring;
6055         u32 tmp;
6056         u32 rb_bufsz;
6057         u64 rb_addr, rptr_addr, wptr_gpu_addr;
6058         u32 i;
6059
6060         /* Set the write pointer delay */
6061         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6062
6063         /* set the RB to use vmid 0 */
6064         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6065
6066         /* Init gfx ring 0 for pipe 0 */
6067         mutex_lock(&adev->srbm_mutex);
6068         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6069
6070         /* Set ring buffer size */
6071         ring = &adev->gfx.gfx_ring[0];
6072         rb_bufsz = order_base_2(ring->ring_size / 8);
6073         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6074         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6075 #ifdef __BIG_ENDIAN
6076         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6077 #endif
6078         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6079
6080         /* Initialize the ring buffer's write pointers */
6081         ring->wptr = 0;
6082         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6083         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6084
6085         /* set the wb address wether it's enabled or not */
6086         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6087         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6088         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6089                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6090
6091         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6092         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6093                      lower_32_bits(wptr_gpu_addr));
6094         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6095                      upper_32_bits(wptr_gpu_addr));
6096
6097         mdelay(1);
6098         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6099
6100         rb_addr = ring->gpu_addr >> 8;
6101         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6102         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6103
6104         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6105
6106         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6107         mutex_unlock(&adev->srbm_mutex);
6108
6109         /* Init gfx ring 1 for pipe 1 */
6110         if (adev->gfx.num_gfx_rings > 1) {
6111                 mutex_lock(&adev->srbm_mutex);
6112                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6113                 /* maximum supported gfx ring is 2 */
6114                 ring = &adev->gfx.gfx_ring[1];
6115                 rb_bufsz = order_base_2(ring->ring_size / 8);
6116                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6117                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6118                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6119                 /* Initialize the ring buffer's write pointers */
6120                 ring->wptr = 0;
6121                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6122                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6123                 /* Set the wb address wether it's enabled or not */
6124                 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6125                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6126                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6127                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6128                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6129                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6130                              lower_32_bits(wptr_gpu_addr));
6131                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6132                              upper_32_bits(wptr_gpu_addr));
6133
6134                 mdelay(1);
6135                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6136
6137                 rb_addr = ring->gpu_addr >> 8;
6138                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6139                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6140                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6141
6142                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6143                 mutex_unlock(&adev->srbm_mutex);
6144         }
6145         /* Switch to pipe 0 */
6146         mutex_lock(&adev->srbm_mutex);
6147         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6148         mutex_unlock(&adev->srbm_mutex);
6149
6150         /* start the ring */
6151         gfx_v10_0_cp_gfx_start(adev);
6152
6153         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6154                 ring = &adev->gfx.gfx_ring[i];
6155                 ring->sched.ready = true;
6156         }
6157
6158         return 0;
6159 }
6160
6161 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6162 {
6163         if (enable) {
6164                 switch (adev->asic_type) {
6165                 case CHIP_SIENNA_CICHLID:
6166                 case CHIP_NAVY_FLOUNDER:
6167                 case CHIP_VANGOGH:
6168                 case CHIP_DIMGREY_CAVEFISH:
6169                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6170                         break;
6171                 default:
6172                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6173                         break;
6174                 }
6175         } else {
6176                 switch (adev->asic_type) {
6177                 case CHIP_SIENNA_CICHLID:
6178                 case CHIP_NAVY_FLOUNDER:
6179                 case CHIP_VANGOGH:
6180                 case CHIP_DIMGREY_CAVEFISH:
6181                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6182                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6183                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6184                         break;
6185                 default:
6186                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6187                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6188                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6189                         break;
6190                 }
6191                 adev->gfx.kiq.ring.sched.ready = false;
6192         }
6193         udelay(50);
6194 }
6195
6196 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6197 {
6198         const struct gfx_firmware_header_v1_0 *mec_hdr;
6199         const __le32 *fw_data;
6200         unsigned i;
6201         u32 tmp;
6202         u32 usec_timeout = 50000; /* Wait for 50 ms */
6203
6204         if (!adev->gfx.mec_fw)
6205                 return -EINVAL;
6206
6207         gfx_v10_0_cp_compute_enable(adev, false);
6208
6209         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6210         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6211
6212         fw_data = (const __le32 *)
6213                 (adev->gfx.mec_fw->data +
6214                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6215
6216         /* Trigger an invalidation of the L1 instruction caches */
6217         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6218         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6219         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6220
6221         /* Wait for invalidation complete */
6222         for (i = 0; i < usec_timeout; i++) {
6223                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6224                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6225                                        INVALIDATE_CACHE_COMPLETE))
6226                         break;
6227                 udelay(1);
6228         }
6229
6230         if (i >= usec_timeout) {
6231                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6232                 return -EINVAL;
6233         }
6234
6235         if (amdgpu_emu_mode == 1)
6236                 adev->hdp.funcs->flush_hdp(adev, NULL);
6237
6238         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6239         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6240         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6241         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6242         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6243
6244         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6245                      0xFFFFF000);
6246         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6247                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6248
6249         /* MEC1 */
6250         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6251
6252         for (i = 0; i < mec_hdr->jt_size; i++)
6253                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6254                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6255
6256         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6257
6258         /*
6259          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6260          * different microcode than MEC1.
6261          */
6262
6263         return 0;
6264 }
6265
6266 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6267 {
6268         uint32_t tmp;
6269         struct amdgpu_device *adev = ring->adev;
6270
6271         /* tell RLC which is KIQ queue */
6272         switch (adev->asic_type) {
6273         case CHIP_SIENNA_CICHLID:
6274         case CHIP_NAVY_FLOUNDER:
6275         case CHIP_VANGOGH:
6276         case CHIP_DIMGREY_CAVEFISH:
6277                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6278                 tmp &= 0xffffff00;
6279                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6280                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6281                 tmp |= 0x80;
6282                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6283                 break;
6284         default:
6285                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6286                 tmp &= 0xffffff00;
6287                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6288                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6289                 tmp |= 0x80;
6290                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6291                 break;
6292         }
6293 }
6294
6295 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
6296 {
6297         struct amdgpu_device *adev = ring->adev;
6298         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6299         uint64_t hqd_gpu_addr, wb_gpu_addr;
6300         uint32_t tmp;
6301         uint32_t rb_bufsz;
6302
6303         /* set up gfx hqd wptr */
6304         mqd->cp_gfx_hqd_wptr = 0;
6305         mqd->cp_gfx_hqd_wptr_hi = 0;
6306
6307         /* set the pointer to the MQD */
6308         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
6309         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6310
6311         /* set up mqd control */
6312         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6313         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6314         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6315         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6316         mqd->cp_gfx_mqd_control = tmp;
6317
6318         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6319         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6320         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6321         mqd->cp_gfx_hqd_vmid = 0;
6322
6323         /* set up default queue priority level
6324          * 0x0 = low priority, 0x1 = high priority */
6325         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6326         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
6327         mqd->cp_gfx_hqd_queue_priority = tmp;
6328
6329         /* set up time quantum */
6330         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6331         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6332         mqd->cp_gfx_hqd_quantum = tmp;
6333
6334         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6335         hqd_gpu_addr = ring->gpu_addr >> 8;
6336         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6337         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6338
6339         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6340         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6341         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6342         mqd->cp_gfx_hqd_rptr_addr_hi =
6343                 upper_32_bits(wb_gpu_addr) & 0xffff;
6344
6345         /* set up rb_wptr_poll addr */
6346         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6347         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6348         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6349
6350         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6351         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
6352         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6353         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6354         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6355 #ifdef __BIG_ENDIAN
6356         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6357 #endif
6358         mqd->cp_gfx_hqd_cntl = tmp;
6359
6360         /* set up cp_doorbell_control */
6361         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6362         if (ring->use_doorbell) {
6363                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6364                                     DOORBELL_OFFSET, ring->doorbell_index);
6365                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6366                                     DOORBELL_EN, 1);
6367         } else
6368                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6369                                     DOORBELL_EN, 0);
6370         mqd->cp_rb_doorbell_control = tmp;
6371
6372         /*if there are 2 gfx rings, set the lower doorbell range of the first ring,
6373          *otherwise the range of the second ring will override the first ring */
6374         if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6375                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6376
6377         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6378         ring->wptr = 0;
6379         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6380
6381         /* active the queue */
6382         mqd->cp_gfx_hqd_active = 1;
6383
6384         return 0;
6385 }
6386
6387 #ifdef BRING_UP_DEBUG
6388 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6389 {
6390         struct amdgpu_device *adev = ring->adev;
6391         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6392
6393         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6394         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6395         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6396
6397         /* set GFX_MQD_BASE */
6398         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6399         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6400
6401         /* set GFX_MQD_CONTROL */
6402         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6403
6404         /* set GFX_HQD_VMID to 0 */
6405         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6406
6407         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6408                         mqd->cp_gfx_hqd_queue_priority);
6409         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6410
6411         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6412         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6413         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6414
6415         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6416         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6417         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6418
6419         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6420         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6421
6422         /* set RB_WPTR_POLL_ADDR */
6423         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6424         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6425
6426         /* set RB_DOORBELL_CONTROL */
6427         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6428
6429         /* active the queue */
6430         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6431
6432         return 0;
6433 }
6434 #endif
6435
6436 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6437 {
6438         struct amdgpu_device *adev = ring->adev;
6439         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6440         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6441
6442         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6443                 memset((void *)mqd, 0, sizeof(*mqd));
6444                 mutex_lock(&adev->srbm_mutex);
6445                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6446                 gfx_v10_0_gfx_mqd_init(ring);
6447 #ifdef BRING_UP_DEBUG
6448                 gfx_v10_0_gfx_queue_init_register(ring);
6449 #endif
6450                 nv_grbm_select(adev, 0, 0, 0, 0);
6451                 mutex_unlock(&adev->srbm_mutex);
6452                 if (adev->gfx.me.mqd_backup[mqd_idx])
6453                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6454         } else if (amdgpu_in_reset(adev)) {
6455                 /* reset mqd with the backup copy */
6456                 if (adev->gfx.me.mqd_backup[mqd_idx])
6457                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6458                 /* reset the ring */
6459                 ring->wptr = 0;
6460                 adev->wb.wb[ring->wptr_offs] = 0;
6461                 amdgpu_ring_clear_ring(ring);
6462 #ifdef BRING_UP_DEBUG
6463                 mutex_lock(&adev->srbm_mutex);
6464                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6465                 gfx_v10_0_gfx_queue_init_register(ring);
6466                 nv_grbm_select(adev, 0, 0, 0, 0);
6467                 mutex_unlock(&adev->srbm_mutex);
6468 #endif
6469         } else {
6470                 amdgpu_ring_clear_ring(ring);
6471         }
6472
6473         return 0;
6474 }
6475
6476 #ifndef BRING_UP_DEBUG
6477 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6478 {
6479         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6480         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6481         int r, i;
6482
6483         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6484                 return -EINVAL;
6485
6486         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6487                                         adev->gfx.num_gfx_rings);
6488         if (r) {
6489                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6490                 return r;
6491         }
6492
6493         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6494                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6495
6496         return amdgpu_ring_test_helper(kiq_ring);
6497 }
6498 #endif
6499
6500 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6501 {
6502         int r, i;
6503         struct amdgpu_ring *ring;
6504
6505         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6506                 ring = &adev->gfx.gfx_ring[i];
6507
6508                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6509                 if (unlikely(r != 0))
6510                         goto done;
6511
6512                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6513                 if (!r) {
6514                         r = gfx_v10_0_gfx_init_queue(ring);
6515                         amdgpu_bo_kunmap(ring->mqd_obj);
6516                         ring->mqd_ptr = NULL;
6517                 }
6518                 amdgpu_bo_unreserve(ring->mqd_obj);
6519                 if (r)
6520                         goto done;
6521         }
6522 #ifndef BRING_UP_DEBUG
6523         r = gfx_v10_0_kiq_enable_kgq(adev);
6524         if (r)
6525                 goto done;
6526 #endif
6527         r = gfx_v10_0_cp_gfx_start(adev);
6528         if (r)
6529                 goto done;
6530
6531         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6532                 ring = &adev->gfx.gfx_ring[i];
6533                 ring->sched.ready = true;
6534         }
6535 done:
6536         return r;
6537 }
6538
6539 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6540 {
6541         struct amdgpu_device *adev = ring->adev;
6542
6543         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6544                 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) {
6545                         mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6546                         mqd->cp_hqd_queue_priority =
6547                                 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6548                 }
6549         }
6550 }
6551
6552 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6553 {
6554         struct amdgpu_device *adev = ring->adev;
6555         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6556         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6557         uint32_t tmp;
6558
6559         mqd->header = 0xC0310800;
6560         mqd->compute_pipelinestat_enable = 0x00000001;
6561         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6562         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6563         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6564         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6565         mqd->compute_misc_reserved = 0x00000003;
6566
6567         eop_base_addr = ring->eop_gpu_addr >> 8;
6568         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6569         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6570
6571         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6572         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6573         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6574                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6575
6576         mqd->cp_hqd_eop_control = tmp;
6577
6578         /* enable doorbell? */
6579         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6580
6581         if (ring->use_doorbell) {
6582                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6583                                     DOORBELL_OFFSET, ring->doorbell_index);
6584                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6585                                     DOORBELL_EN, 1);
6586                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6587                                     DOORBELL_SOURCE, 0);
6588                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6589                                     DOORBELL_HIT, 0);
6590         } else {
6591                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6592                                     DOORBELL_EN, 0);
6593         }
6594
6595         mqd->cp_hqd_pq_doorbell_control = tmp;
6596
6597         /* disable the queue if it's active */
6598         ring->wptr = 0;
6599         mqd->cp_hqd_dequeue_request = 0;
6600         mqd->cp_hqd_pq_rptr = 0;
6601         mqd->cp_hqd_pq_wptr_lo = 0;
6602         mqd->cp_hqd_pq_wptr_hi = 0;
6603
6604         /* set the pointer to the MQD */
6605         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6606         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6607
6608         /* set MQD vmid to 0 */
6609         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6610         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6611         mqd->cp_mqd_control = tmp;
6612
6613         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6614         hqd_gpu_addr = ring->gpu_addr >> 8;
6615         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6616         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6617
6618         /* set up the HQD, this is similar to CP_RB0_CNTL */
6619         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6620         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6621                             (order_base_2(ring->ring_size / 4) - 1));
6622         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6623                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6624 #ifdef __BIG_ENDIAN
6625         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6626 #endif
6627         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6628         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6629         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6630         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6631         mqd->cp_hqd_pq_control = tmp;
6632
6633         /* set the wb address whether it's enabled or not */
6634         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6635         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6636         mqd->cp_hqd_pq_rptr_report_addr_hi =
6637                 upper_32_bits(wb_gpu_addr) & 0xffff;
6638
6639         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6640         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6641         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6642         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6643
6644         tmp = 0;
6645         /* enable the doorbell if requested */
6646         if (ring->use_doorbell) {
6647                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6648                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6649                                 DOORBELL_OFFSET, ring->doorbell_index);
6650
6651                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6652                                     DOORBELL_EN, 1);
6653                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6654                                     DOORBELL_SOURCE, 0);
6655                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6656                                     DOORBELL_HIT, 0);
6657         }
6658
6659         mqd->cp_hqd_pq_doorbell_control = tmp;
6660
6661         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6662         ring->wptr = 0;
6663         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6664
6665         /* set the vmid for the queue */
6666         mqd->cp_hqd_vmid = 0;
6667
6668         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6669         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6670         mqd->cp_hqd_persistent_state = tmp;
6671
6672         /* set MIN_IB_AVAIL_SIZE */
6673         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6674         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6675         mqd->cp_hqd_ib_control = tmp;
6676
6677         /* set static priority for a compute queue/ring */
6678         gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6679
6680         /* map_queues packet doesn't need activate the queue,
6681          * so only kiq need set this field.
6682          */
6683         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6684                 mqd->cp_hqd_active = 1;
6685
6686         return 0;
6687 }
6688
6689 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6690 {
6691         struct amdgpu_device *adev = ring->adev;
6692         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6693         int j;
6694
6695         /* inactivate the queue */
6696         if (amdgpu_sriov_vf(adev))
6697                 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6698
6699         /* disable wptr polling */
6700         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6701
6702         /* write the EOP addr */
6703         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6704                mqd->cp_hqd_eop_base_addr_lo);
6705         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6706                mqd->cp_hqd_eop_base_addr_hi);
6707
6708         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6709         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6710                mqd->cp_hqd_eop_control);
6711
6712         /* enable doorbell? */
6713         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6714                mqd->cp_hqd_pq_doorbell_control);
6715
6716         /* disable the queue if it's active */
6717         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6718                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6719                 for (j = 0; j < adev->usec_timeout; j++) {
6720                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6721                                 break;
6722                         udelay(1);
6723                 }
6724                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6725                        mqd->cp_hqd_dequeue_request);
6726                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6727                        mqd->cp_hqd_pq_rptr);
6728                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6729                        mqd->cp_hqd_pq_wptr_lo);
6730                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6731                        mqd->cp_hqd_pq_wptr_hi);
6732         }
6733
6734         /* set the pointer to the MQD */
6735         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6736                mqd->cp_mqd_base_addr_lo);
6737         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6738                mqd->cp_mqd_base_addr_hi);
6739
6740         /* set MQD vmid to 0 */
6741         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6742                mqd->cp_mqd_control);
6743
6744         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6745         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6746                mqd->cp_hqd_pq_base_lo);
6747         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6748                mqd->cp_hqd_pq_base_hi);
6749
6750         /* set up the HQD, this is similar to CP_RB0_CNTL */
6751         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6752                mqd->cp_hqd_pq_control);
6753
6754         /* set the wb address whether it's enabled or not */
6755         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6756                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6757         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6758                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6759
6760         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6761         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6762                mqd->cp_hqd_pq_wptr_poll_addr_lo);
6763         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6764                mqd->cp_hqd_pq_wptr_poll_addr_hi);
6765
6766         /* enable the doorbell if requested */
6767         if (ring->use_doorbell) {
6768                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6769                         (adev->doorbell_index.kiq * 2) << 2);
6770                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6771                         (adev->doorbell_index.userqueue_end * 2) << 2);
6772         }
6773
6774         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6775                mqd->cp_hqd_pq_doorbell_control);
6776
6777         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6778         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6779                mqd->cp_hqd_pq_wptr_lo);
6780         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6781                mqd->cp_hqd_pq_wptr_hi);
6782
6783         /* set the vmid for the queue */
6784         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6785
6786         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6787                mqd->cp_hqd_persistent_state);
6788
6789         /* activate the queue */
6790         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6791                mqd->cp_hqd_active);
6792
6793         if (ring->use_doorbell)
6794                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6795
6796         return 0;
6797 }
6798
6799 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6800 {
6801         struct amdgpu_device *adev = ring->adev;
6802         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6803         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
6804
6805         gfx_v10_0_kiq_setting(ring);
6806
6807         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6808                 /* reset MQD to a clean status */
6809                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6810                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6811
6812                 /* reset ring buffer */
6813                 ring->wptr = 0;
6814                 amdgpu_ring_clear_ring(ring);
6815
6816                 mutex_lock(&adev->srbm_mutex);
6817                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6818                 gfx_v10_0_kiq_init_register(ring);
6819                 nv_grbm_select(adev, 0, 0, 0, 0);
6820                 mutex_unlock(&adev->srbm_mutex);
6821         } else {
6822                 memset((void *)mqd, 0, sizeof(*mqd));
6823                 mutex_lock(&adev->srbm_mutex);
6824                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6825                 gfx_v10_0_compute_mqd_init(ring);
6826                 gfx_v10_0_kiq_init_register(ring);
6827                 nv_grbm_select(adev, 0, 0, 0, 0);
6828                 mutex_unlock(&adev->srbm_mutex);
6829
6830                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6831                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6832         }
6833
6834         return 0;
6835 }
6836
6837 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6838 {
6839         struct amdgpu_device *adev = ring->adev;
6840         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6841         int mqd_idx = ring - &adev->gfx.compute_ring[0];
6842
6843         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6844                 memset((void *)mqd, 0, sizeof(*mqd));
6845                 mutex_lock(&adev->srbm_mutex);
6846                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6847                 gfx_v10_0_compute_mqd_init(ring);
6848                 nv_grbm_select(adev, 0, 0, 0, 0);
6849                 mutex_unlock(&adev->srbm_mutex);
6850
6851                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6852                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6853         } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6854                 /* reset MQD to a clean status */
6855                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6856                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6857
6858                 /* reset ring buffer */
6859                 ring->wptr = 0;
6860                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
6861                 amdgpu_ring_clear_ring(ring);
6862         } else {
6863                 amdgpu_ring_clear_ring(ring);
6864         }
6865
6866         return 0;
6867 }
6868
6869 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6870 {
6871         struct amdgpu_ring *ring;
6872         int r;
6873
6874         ring = &adev->gfx.kiq.ring;
6875
6876         r = amdgpu_bo_reserve(ring->mqd_obj, false);
6877         if (unlikely(r != 0))
6878                 return r;
6879
6880         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6881         if (unlikely(r != 0))
6882                 return r;
6883
6884         gfx_v10_0_kiq_init_queue(ring);
6885         amdgpu_bo_kunmap(ring->mqd_obj);
6886         ring->mqd_ptr = NULL;
6887         amdgpu_bo_unreserve(ring->mqd_obj);
6888         ring->sched.ready = true;
6889         return 0;
6890 }
6891
6892 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6893 {
6894         struct amdgpu_ring *ring = NULL;
6895         int r = 0, i;
6896
6897         gfx_v10_0_cp_compute_enable(adev, true);
6898
6899         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6900                 ring = &adev->gfx.compute_ring[i];
6901
6902                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6903                 if (unlikely(r != 0))
6904                         goto done;
6905                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6906                 if (!r) {
6907                         r = gfx_v10_0_kcq_init_queue(ring);
6908                         amdgpu_bo_kunmap(ring->mqd_obj);
6909                         ring->mqd_ptr = NULL;
6910                 }
6911                 amdgpu_bo_unreserve(ring->mqd_obj);
6912                 if (r)
6913                         goto done;
6914         }
6915
6916         r = amdgpu_gfx_enable_kcq(adev);
6917 done:
6918         return r;
6919 }
6920
6921 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
6922 {
6923         int r, i;
6924         struct amdgpu_ring *ring;
6925
6926         if (!(adev->flags & AMD_IS_APU))
6927                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6928
6929         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6930                 /* legacy firmware loading */
6931                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
6932                 if (r)
6933                         return r;
6934
6935                 r = gfx_v10_0_cp_compute_load_microcode(adev);
6936                 if (r)
6937                         return r;
6938         }
6939
6940         r = gfx_v10_0_kiq_resume(adev);
6941         if (r)
6942                 return r;
6943
6944         r = gfx_v10_0_kcq_resume(adev);
6945         if (r)
6946                 return r;
6947
6948         if (!amdgpu_async_gfx_ring) {
6949                 r = gfx_v10_0_cp_gfx_resume(adev);
6950                 if (r)
6951                         return r;
6952         } else {
6953                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
6954                 if (r)
6955                         return r;
6956         }
6957
6958         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6959                 ring = &adev->gfx.gfx_ring[i];
6960                 r = amdgpu_ring_test_helper(ring);
6961                 if (r)
6962                         return r;
6963         }
6964
6965         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6966                 ring = &adev->gfx.compute_ring[i];
6967                 r = amdgpu_ring_test_helper(ring);
6968                 if (r)
6969                         return r;
6970         }
6971
6972         return 0;
6973 }
6974
6975 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
6976 {
6977         gfx_v10_0_cp_gfx_enable(adev, enable);
6978         gfx_v10_0_cp_compute_enable(adev, enable);
6979 }
6980
6981 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
6982 {
6983         uint32_t data, pattern = 0xDEADBEEF;
6984
6985         /* check if mmVGT_ESGS_RING_SIZE_UMD
6986          * has been remapped to mmVGT_ESGS_RING_SIZE */
6987         switch (adev->asic_type) {
6988         case CHIP_SIENNA_CICHLID:
6989         case CHIP_NAVY_FLOUNDER:
6990         case CHIP_DIMGREY_CAVEFISH:
6991                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
6992                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
6993                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6994
6995                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
6996                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
6997                         return true;
6998                 } else {
6999                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
7000                         return false;
7001                 }
7002                 break;
7003         case CHIP_VANGOGH:
7004                 return true;
7005         default:
7006                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
7007                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
7008                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7009
7010                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7011                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7012                         return true;
7013                 } else {
7014                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7015                         return false;
7016                 }
7017                 break;
7018         }
7019 }
7020
7021 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7022 {
7023         uint32_t data;
7024
7025         /* initialize cam_index to 0
7026          * index will auto-inc after each data writting */
7027         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7028
7029         switch (adev->asic_type) {
7030         case CHIP_SIENNA_CICHLID:
7031         case CHIP_NAVY_FLOUNDER:
7032         case CHIP_VANGOGH:
7033         case CHIP_DIMGREY_CAVEFISH:
7034                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7035                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7036                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7037                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7038                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7039                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7040                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7041
7042                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7043                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7044                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7045                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7046                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7047                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7048                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7049
7050                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7051                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7052                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7053                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7054                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7055                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7056                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7057
7058                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7059                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7060                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7061                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7062                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7063                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7064                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7065
7066                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7067                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7068                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7069                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7070                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7071                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7072                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7073
7074                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7075                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7076                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7077                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7078                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7079                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7080                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7081
7082                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7083                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7084                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7085                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7086                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7087                 break;
7088         default:
7089                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7090                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7091                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7092                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7093                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7094                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7095                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7096
7097                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7098                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7099                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7100                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7101                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7102                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7103                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7104
7105                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7106                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7107                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7108                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7109                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7110                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7111                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7112
7113                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7114                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7115                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7116                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7117                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7118                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7119                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7120
7121                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7122                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7123                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7124                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7125                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7126                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7127                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7128
7129                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7130                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7131                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7132                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7133                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7134                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7135                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7136
7137                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7138                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7139                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7140                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7141                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7142                 break;
7143         }
7144
7145         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7146         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7147 }
7148
7149 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7150 {
7151         uint32_t data;
7152         data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7153         data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7154         WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7155
7156         data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7157         data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7158         WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7159 }
7160
7161 static int gfx_v10_0_hw_init(void *handle)
7162 {
7163         int r;
7164         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7165
7166         if (!amdgpu_emu_mode)
7167                 gfx_v10_0_init_golden_registers(adev);
7168
7169         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7170                 /**
7171                  * For gfx 10, rlc firmware loading relies on smu firmware is
7172                  * loaded firstly, so in direct type, it has to load smc ucode
7173                  * here before rlc.
7174                  */
7175                 if (adev->smu.ppt_funcs != NULL && !(adev->flags & AMD_IS_APU)) {
7176                         r = smu_load_microcode(&adev->smu);
7177                         if (r)
7178                                 return r;
7179
7180                         r = smu_check_fw_status(&adev->smu);
7181                         if (r) {
7182                                 pr_err("SMC firmware status is not correct\n");
7183                                 return r;
7184                         }
7185                 }
7186                 gfx_v10_0_disable_gpa_mode(adev);
7187         }
7188
7189         /* if GRBM CAM not remapped, set up the remapping */
7190         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7191                 gfx_v10_0_setup_grbm_cam_remapping(adev);
7192
7193         gfx_v10_0_constants_init(adev);
7194
7195         r = gfx_v10_0_rlc_resume(adev);
7196         if (r)
7197                 return r;
7198
7199         /*
7200          * init golden registers and rlc resume may override some registers,
7201          * reconfig them here
7202          */
7203         gfx_v10_0_tcp_harvest(adev);
7204
7205         r = gfx_v10_0_cp_resume(adev);
7206         if (r)
7207                 return r;
7208
7209         if (adev->asic_type == CHIP_SIENNA_CICHLID)
7210                 gfx_v10_3_program_pbb_mode(adev);
7211
7212         if (adev->asic_type >= CHIP_SIENNA_CICHLID)
7213                 gfx_v10_3_set_power_brake_sequence(adev);
7214
7215         return r;
7216 }
7217
7218 #ifndef BRING_UP_DEBUG
7219 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7220 {
7221         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7222         struct amdgpu_ring *kiq_ring = &kiq->ring;
7223         int i;
7224
7225         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7226                 return -EINVAL;
7227
7228         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7229                                         adev->gfx.num_gfx_rings))
7230                 return -ENOMEM;
7231
7232         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7233                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7234                                            PREEMPT_QUEUES, 0, 0);
7235
7236         return amdgpu_ring_test_helper(kiq_ring);
7237 }
7238 #endif
7239
7240 static int gfx_v10_0_hw_fini(void *handle)
7241 {
7242         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7243         int r;
7244         uint32_t tmp;
7245
7246         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7247         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7248
7249         if (!adev->in_pci_err_recovery) {
7250 #ifndef BRING_UP_DEBUG
7251                 if (amdgpu_async_gfx_ring) {
7252                         r = gfx_v10_0_kiq_disable_kgq(adev);
7253                         if (r)
7254                                 DRM_ERROR("KGQ disable failed\n");
7255                 }
7256 #endif
7257                 if (amdgpu_gfx_disable_kcq(adev))
7258                         DRM_ERROR("KCQ disable failed\n");
7259         }
7260
7261         if (amdgpu_sriov_vf(adev)) {
7262                 gfx_v10_0_cp_gfx_enable(adev, false);
7263                 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7264                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7265                 tmp &= 0xffffff00;
7266                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7267
7268                 return 0;
7269         }
7270         gfx_v10_0_cp_enable(adev, false);
7271         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7272
7273         return 0;
7274 }
7275
7276 static int gfx_v10_0_suspend(void *handle)
7277 {
7278         return gfx_v10_0_hw_fini(handle);
7279 }
7280
7281 static int gfx_v10_0_resume(void *handle)
7282 {
7283         return gfx_v10_0_hw_init(handle);
7284 }
7285
7286 static bool gfx_v10_0_is_idle(void *handle)
7287 {
7288         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7289
7290         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7291                                 GRBM_STATUS, GUI_ACTIVE))
7292                 return false;
7293         else
7294                 return true;
7295 }
7296
7297 static int gfx_v10_0_wait_for_idle(void *handle)
7298 {
7299         unsigned i;
7300         u32 tmp;
7301         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7302
7303         for (i = 0; i < adev->usec_timeout; i++) {
7304                 /* read MC_STATUS */
7305                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7306                         GRBM_STATUS__GUI_ACTIVE_MASK;
7307
7308                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7309                         return 0;
7310                 udelay(1);
7311         }
7312         return -ETIMEDOUT;
7313 }
7314
7315 static int gfx_v10_0_soft_reset(void *handle)
7316 {
7317         u32 grbm_soft_reset = 0;
7318         u32 tmp;
7319         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7320
7321         /* GRBM_STATUS */
7322         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7323         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7324                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7325                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7326                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7327                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7328                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7329                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7330                                                 1);
7331                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7332                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7333                                                 1);
7334         }
7335
7336         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7337                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7338                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7339                                                 1);
7340         }
7341
7342         /* GRBM_STATUS2 */
7343         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7344         switch (adev->asic_type) {
7345         case CHIP_SIENNA_CICHLID:
7346         case CHIP_NAVY_FLOUNDER:
7347         case CHIP_VANGOGH:
7348         case CHIP_DIMGREY_CAVEFISH:
7349                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7350                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7351                                                         GRBM_SOFT_RESET,
7352                                                         SOFT_RESET_RLC,
7353                                                         1);
7354                 break;
7355         default:
7356                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7357                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7358                                                         GRBM_SOFT_RESET,
7359                                                         SOFT_RESET_RLC,
7360                                                         1);
7361                 break;
7362         }
7363
7364         if (grbm_soft_reset) {
7365                 /* stop the rlc */
7366                 gfx_v10_0_rlc_stop(adev);
7367
7368                 /* Disable GFX parsing/prefetching */
7369                 gfx_v10_0_cp_gfx_enable(adev, false);
7370
7371                 /* Disable MEC parsing/prefetching */
7372                 gfx_v10_0_cp_compute_enable(adev, false);
7373
7374                 if (grbm_soft_reset) {
7375                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7376                         tmp |= grbm_soft_reset;
7377                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7378                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7379                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7380
7381                         udelay(50);
7382
7383                         tmp &= ~grbm_soft_reset;
7384                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7385                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7386                 }
7387
7388                 /* Wait a little for things to settle down */
7389                 udelay(50);
7390         }
7391         return 0;
7392 }
7393
7394 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7395 {
7396         uint64_t clock;
7397
7398         amdgpu_gfx_off_ctrl(adev, false);
7399         mutex_lock(&adev->gfx.gpu_clock_mutex);
7400         switch (adev->asic_type) {
7401         case CHIP_VANGOGH:
7402                 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh) |
7403                         ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);
7404                 break;
7405         default:
7406                 clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
7407                         ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
7408                 break;
7409         }
7410         mutex_unlock(&adev->gfx.gpu_clock_mutex);
7411         amdgpu_gfx_off_ctrl(adev, true);
7412         return clock;
7413 }
7414
7415 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7416                                            uint32_t vmid,
7417                                            uint32_t gds_base, uint32_t gds_size,
7418                                            uint32_t gws_base, uint32_t gws_size,
7419                                            uint32_t oa_base, uint32_t oa_size)
7420 {
7421         struct amdgpu_device *adev = ring->adev;
7422
7423         /* GDS Base */
7424         gfx_v10_0_write_data_to_reg(ring, 0, false,
7425                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7426                                     gds_base);
7427
7428         /* GDS Size */
7429         gfx_v10_0_write_data_to_reg(ring, 0, false,
7430                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7431                                     gds_size);
7432
7433         /* GWS */
7434         gfx_v10_0_write_data_to_reg(ring, 0, false,
7435                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7436                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7437
7438         /* OA */
7439         gfx_v10_0_write_data_to_reg(ring, 0, false,
7440                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7441                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7442 }
7443
7444 static int gfx_v10_0_early_init(void *handle)
7445 {
7446         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7447
7448         switch (adev->asic_type) {
7449         case CHIP_NAVI10:
7450         case CHIP_NAVI14:
7451         case CHIP_NAVI12:
7452                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7453                 break;
7454         case CHIP_SIENNA_CICHLID:
7455         case CHIP_NAVY_FLOUNDER:
7456         case CHIP_VANGOGH:
7457         case CHIP_DIMGREY_CAVEFISH:
7458                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7459                 break;
7460         default:
7461                 break;
7462         }
7463
7464         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7465                                           AMDGPU_MAX_COMPUTE_RINGS);
7466
7467         gfx_v10_0_set_kiq_pm4_funcs(adev);
7468         gfx_v10_0_set_ring_funcs(adev);
7469         gfx_v10_0_set_irq_funcs(adev);
7470         gfx_v10_0_set_gds_init(adev);
7471         gfx_v10_0_set_rlc_funcs(adev);
7472
7473         return 0;
7474 }
7475
7476 static int gfx_v10_0_late_init(void *handle)
7477 {
7478         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7479         int r;
7480
7481         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7482         if (r)
7483                 return r;
7484
7485         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7486         if (r)
7487                 return r;
7488
7489         return 0;
7490 }
7491
7492 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7493 {
7494         uint32_t rlc_cntl;
7495
7496         /* if RLC is not enabled, do nothing */
7497         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7498         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7499 }
7500
7501 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7502 {
7503         uint32_t data;
7504         unsigned i;
7505
7506         data = RLC_SAFE_MODE__CMD_MASK;
7507         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7508
7509         switch (adev->asic_type) {
7510         case CHIP_SIENNA_CICHLID:
7511         case CHIP_NAVY_FLOUNDER:
7512         case CHIP_VANGOGH:
7513         case CHIP_DIMGREY_CAVEFISH:
7514                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7515
7516                 /* wait for RLC_SAFE_MODE */
7517                 for (i = 0; i < adev->usec_timeout; i++) {
7518                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7519                                            RLC_SAFE_MODE, CMD))
7520                                 break;
7521                         udelay(1);
7522                 }
7523                 break;
7524         default:
7525                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7526
7527                 /* wait for RLC_SAFE_MODE */
7528                 for (i = 0; i < adev->usec_timeout; i++) {
7529                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7530                                            RLC_SAFE_MODE, CMD))
7531                                 break;
7532                         udelay(1);
7533                 }
7534                 break;
7535         }
7536 }
7537
7538 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7539 {
7540         uint32_t data;
7541
7542         data = RLC_SAFE_MODE__CMD_MASK;
7543         switch (adev->asic_type) {
7544         case CHIP_SIENNA_CICHLID:
7545         case CHIP_NAVY_FLOUNDER:
7546         case CHIP_VANGOGH:
7547         case CHIP_DIMGREY_CAVEFISH:
7548                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7549                 break;
7550         default:
7551                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7552                 break;
7553         }
7554 }
7555
7556 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7557                                                       bool enable)
7558 {
7559         uint32_t data, def;
7560
7561         /* It is disabled by HW by default */
7562         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7563                 /* 0 - Disable some blocks' MGCG */
7564                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7565                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7566                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7567                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7568
7569                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7570                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7571                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7572                           RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7573                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7574                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7575                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7576
7577                 if (def != data)
7578                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7579
7580                 /* MGLS is a global flag to control all MGLS in GFX */
7581                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7582                         /* 2 - RLC memory Light sleep */
7583                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7584                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7585                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7586                                 if (def != data)
7587                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7588                         }
7589                         /* 3 - CP memory Light sleep */
7590                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7591                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7592                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7593                                 if (def != data)
7594                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7595                         }
7596                 }
7597         } else {
7598                 /* 1 - MGCG_OVERRIDE */
7599                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7600                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7601                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7602                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7603                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
7604                 if (def != data)
7605                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7606
7607                 /* 2 - disable MGLS in CP */
7608                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7609                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7610                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7611                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7612                 }
7613
7614                 /* 3 - disable MGLS in RLC */
7615                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7616                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7617                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7618                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7619                 }
7620
7621         }
7622 }
7623
7624 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7625                                            bool enable)
7626 {
7627         uint32_t data, def;
7628
7629         /* Enable 3D CGCG/CGLS */
7630         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
7631                 /* write cmd to clear cgcg/cgls ov */
7632                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7633                 /* unset CGCG override */
7634                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7635                 /* update CGCG and CGLS override bits */
7636                 if (def != data)
7637                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7638                 /* enable 3Dcgcg FSM(0x0000363f) */
7639                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7640                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7641                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7642                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7643                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7644                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7645                 if (def != data)
7646                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7647
7648                 /* set IDLE_POLL_COUNT(0x00900100) */
7649                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7650                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7651                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7652                 if (def != data)
7653                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7654         } else {
7655                 /* Disable CGCG/CGLS */
7656                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7657                 /* disable cgcg, cgls should be disabled */
7658                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
7659                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
7660                 /* disable cgcg and cgls in FSM */
7661                 if (def != data)
7662                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7663         }
7664 }
7665
7666 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7667                                                       bool enable)
7668 {
7669         uint32_t def, data;
7670
7671         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
7672                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7673                 /* unset CGCG override */
7674                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7675                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7676                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7677                 else
7678                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7679                 /* update CGCG and CGLS override bits */
7680                 if (def != data)
7681                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7682
7683                 /* enable cgcg FSM(0x0000363F) */
7684                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7685                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7686                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7687                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7688                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7689                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7690                 if (def != data)
7691                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7692
7693                 /* set IDLE_POLL_COUNT(0x00900100) */
7694                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7695                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7696                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7697                 if (def != data)
7698                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7699         } else {
7700                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7701                 /* reset CGCG/CGLS bits */
7702                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
7703                 /* disable cgcg and cgls in FSM */
7704                 if (def != data)
7705                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7706         }
7707 }
7708
7709 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
7710                                                       bool enable)
7711 {
7712         uint32_t def, data;
7713
7714         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) {
7715                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7716                 /* unset FGCG override */
7717                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7718                 /* update FGCG override bits */
7719                 if (def != data)
7720                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7721
7722                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7723                 /* unset RLC SRAM CLK GATER override */
7724                 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7725                 /* update RLC SRAM CLK GATER override bits */
7726                 if (def != data)
7727                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7728         } else {
7729                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7730                 /* reset FGCG bits */
7731                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7732                 /* disable FGCG*/
7733                 if (def != data)
7734                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7735
7736                 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7737                 /* reset RLC SRAM CLK GATER bits */
7738                 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7739                 /* disable RLC SRAM CLK*/
7740                 if (def != data)
7741                         WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7742         }
7743 }
7744
7745 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7746                                             bool enable)
7747 {
7748         amdgpu_gfx_rlc_enter_safe_mode(adev);
7749
7750         if (enable) {
7751                 /* enable FGCG firstly*/
7752                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7753                 /* CGCG/CGLS should be enabled after MGCG/MGLS
7754                  * ===  MGCG + MGLS ===
7755                  */
7756                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7757                 /* ===  CGCG /CGLS for GFX 3D Only === */
7758                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7759                 /* ===  CGCG + CGLS === */
7760                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7761         } else {
7762                 /* CGCG/CGLS should be disabled before MGCG/MGLS
7763                  * ===  CGCG + CGLS ===
7764                  */
7765                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7766                 /* ===  CGCG /CGLS for GFX 3D Only === */
7767                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7768                 /* ===  MGCG + MGLS === */
7769                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7770                 /* disable fgcg at last*/
7771                 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
7772         }
7773
7774         if (adev->cg_flags &
7775             (AMD_CG_SUPPORT_GFX_MGCG |
7776              AMD_CG_SUPPORT_GFX_CGLS |
7777              AMD_CG_SUPPORT_GFX_CGCG |
7778              AMD_CG_SUPPORT_GFX_3D_CGCG |
7779              AMD_CG_SUPPORT_GFX_3D_CGLS))
7780                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7781
7782         amdgpu_gfx_rlc_exit_safe_mode(adev);
7783
7784         return 0;
7785 }
7786
7787 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
7788 {
7789         u32 reg, data;
7790
7791         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
7792         if (amdgpu_sriov_is_pp_one_vf(adev))
7793                 data = RREG32_NO_KIQ(reg);
7794         else
7795                 data = RREG32(reg);
7796
7797         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7798         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7799
7800         if (amdgpu_sriov_is_pp_one_vf(adev))
7801                 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7802         else
7803                 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
7804 }
7805
7806 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7807                                         uint32_t offset,
7808                                         struct soc15_reg_rlcg *entries, int arr_size)
7809 {
7810         int i;
7811         uint32_t reg;
7812
7813         if (!entries)
7814                 return false;
7815
7816         for (i = 0; i < arr_size; i++) {
7817                 const struct soc15_reg_rlcg *entry;
7818
7819                 entry = &entries[i];
7820                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7821                 if (offset == reg)
7822                         return true;
7823         }
7824
7825         return false;
7826 }
7827
7828 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7829 {
7830         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7831 }
7832
7833 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
7834 {
7835         u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
7836
7837         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
7838                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7839         else
7840                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
7841
7842         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
7843
7844         /*
7845          * CGPG enablement required and the register to program the hysteresis value
7846          * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
7847          * in refclk count. Note that RLC FW is modified to take 16 bits from
7848          * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
7849          *
7850          * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us(0x4E20)
7851          * as part of CGPG enablement starting point.
7852          */
7853         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && adev->asic_type == CHIP_VANGOGH) {
7854                 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
7855                 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
7856         }
7857 }
7858
7859 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
7860 {
7861         amdgpu_gfx_rlc_enter_safe_mode(adev);
7862
7863         gfx_v10_cntl_power_gating(adev, enable);
7864
7865         amdgpu_gfx_rlc_exit_safe_mode(adev);
7866 }
7867
7868 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
7869         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7870         .set_safe_mode = gfx_v10_0_set_safe_mode,
7871         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7872         .init = gfx_v10_0_rlc_init,
7873         .get_csb_size = gfx_v10_0_get_csb_size,
7874         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7875         .resume = gfx_v10_0_rlc_resume,
7876         .stop = gfx_v10_0_rlc_stop,
7877         .reset = gfx_v10_0_rlc_reset,
7878         .start = gfx_v10_0_rlc_start,
7879         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7880 };
7881
7882 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
7883         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7884         .set_safe_mode = gfx_v10_0_set_safe_mode,
7885         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7886         .init = gfx_v10_0_rlc_init,
7887         .get_csb_size = gfx_v10_0_get_csb_size,
7888         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7889         .resume = gfx_v10_0_rlc_resume,
7890         .stop = gfx_v10_0_rlc_stop,
7891         .reset = gfx_v10_0_rlc_reset,
7892         .start = gfx_v10_0_rlc_start,
7893         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7894         .rlcg_wreg = gfx_v10_rlcg_wreg,
7895         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
7896 };
7897
7898 static int gfx_v10_0_set_powergating_state(void *handle,
7899                                           enum amd_powergating_state state)
7900 {
7901         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7902         bool enable = (state == AMD_PG_STATE_GATE);
7903
7904         if (amdgpu_sriov_vf(adev))
7905                 return 0;
7906
7907         switch (adev->asic_type) {
7908         case CHIP_NAVI10:
7909         case CHIP_NAVI14:
7910         case CHIP_NAVI12:
7911         case CHIP_SIENNA_CICHLID:
7912         case CHIP_NAVY_FLOUNDER:
7913         case CHIP_DIMGREY_CAVEFISH:
7914                 amdgpu_gfx_off_ctrl(adev, enable);
7915                 break;
7916         case CHIP_VANGOGH:
7917                 gfx_v10_cntl_pg(adev, enable);
7918                 amdgpu_gfx_off_ctrl(adev, enable);
7919                 break;
7920         default:
7921                 break;
7922         }
7923         return 0;
7924 }
7925
7926 static int gfx_v10_0_set_clockgating_state(void *handle,
7927                                           enum amd_clockgating_state state)
7928 {
7929         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7930
7931         if (amdgpu_sriov_vf(adev))
7932                 return 0;
7933
7934         switch (adev->asic_type) {
7935         case CHIP_NAVI10:
7936         case CHIP_NAVI14:
7937         case CHIP_NAVI12:
7938         case CHIP_SIENNA_CICHLID:
7939         case CHIP_NAVY_FLOUNDER:
7940         case CHIP_VANGOGH:
7941         case CHIP_DIMGREY_CAVEFISH:
7942                 gfx_v10_0_update_gfx_clock_gating(adev,
7943                                                  state == AMD_CG_STATE_GATE);
7944                 break;
7945         default:
7946                 break;
7947         }
7948         return 0;
7949 }
7950
7951 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
7952 {
7953         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7954         int data;
7955
7956         /* AMD_CG_SUPPORT_GFX_FGCG */
7957         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
7958         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
7959                 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
7960
7961         /* AMD_CG_SUPPORT_GFX_MGCG */
7962         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
7963         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
7964                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
7965
7966         /* AMD_CG_SUPPORT_GFX_CGCG */
7967         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
7968         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
7969                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
7970
7971         /* AMD_CG_SUPPORT_GFX_CGLS */
7972         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
7973                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
7974
7975         /* AMD_CG_SUPPORT_GFX_RLC_LS */
7976         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
7977         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
7978                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
7979
7980         /* AMD_CG_SUPPORT_GFX_CP_LS */
7981         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
7982         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
7983                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
7984
7985         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
7986         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
7987         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
7988                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
7989
7990         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
7991         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
7992                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
7993 }
7994
7995 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
7996 {
7997         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
7998 }
7999
8000 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8001 {
8002         struct amdgpu_device *adev = ring->adev;
8003         u64 wptr;
8004
8005         /* XXX check if swapping is necessary on BE */
8006         if (ring->use_doorbell) {
8007                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
8008         } else {
8009                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8010                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8011         }
8012
8013         return wptr;
8014 }
8015
8016 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8017 {
8018         struct amdgpu_device *adev = ring->adev;
8019
8020         if (ring->use_doorbell) {
8021                 /* XXX check if swapping is necessary on BE */
8022                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8023                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8024         } else {
8025                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
8026                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
8027         }
8028 }
8029
8030 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8031 {
8032         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
8033 }
8034
8035 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8036 {
8037         u64 wptr;
8038
8039         /* XXX check if swapping is necessary on BE */
8040         if (ring->use_doorbell)
8041                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
8042         else
8043                 BUG();
8044         return wptr;
8045 }
8046
8047 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8048 {
8049         struct amdgpu_device *adev = ring->adev;
8050
8051         /* XXX check if swapping is necessary on BE */
8052         if (ring->use_doorbell) {
8053                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
8054                 WDOORBELL64(ring->doorbell_index, ring->wptr);
8055         } else {
8056                 BUG(); /* only DOORBELL method supported on gfx10 now */
8057         }
8058 }
8059
8060 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8061 {
8062         struct amdgpu_device *adev = ring->adev;
8063         u32 ref_and_mask, reg_mem_engine;
8064         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8065
8066         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8067                 switch (ring->me) {
8068                 case 1:
8069                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8070                         break;
8071                 case 2:
8072                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8073                         break;
8074                 default:
8075                         return;
8076                 }
8077                 reg_mem_engine = 0;
8078         } else {
8079                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
8080                 reg_mem_engine = 1; /* pfp */
8081         }
8082
8083         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8084                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8085                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8086                                ref_and_mask, ref_and_mask, 0x20);
8087 }
8088
8089 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8090                                        struct amdgpu_job *job,
8091                                        struct amdgpu_ib *ib,
8092                                        uint32_t flags)
8093 {
8094         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8095         u32 header, control = 0;
8096
8097         if (ib->flags & AMDGPU_IB_FLAG_CE)
8098                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8099         else
8100                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8101
8102         control |= ib->length_dw | (vmid << 24);
8103
8104         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8105                 control |= INDIRECT_BUFFER_PRE_ENB(1);
8106
8107                 if (flags & AMDGPU_IB_PREEMPTED)
8108                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
8109
8110                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8111                         gfx_v10_0_ring_emit_de_meta(ring,
8112                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8113         }
8114
8115         amdgpu_ring_write(ring, header);
8116         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8117         amdgpu_ring_write(ring,
8118 #ifdef __BIG_ENDIAN
8119                 (2 << 0) |
8120 #endif
8121                 lower_32_bits(ib->gpu_addr));
8122         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8123         amdgpu_ring_write(ring, control);
8124 }
8125
8126 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8127                                            struct amdgpu_job *job,
8128                                            struct amdgpu_ib *ib,
8129                                            uint32_t flags)
8130 {
8131         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8132         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8133
8134         /* Currently, there is a high possibility to get wave ID mismatch
8135          * between ME and GDS, leading to a hw deadlock, because ME generates
8136          * different wave IDs than the GDS expects. This situation happens
8137          * randomly when at least 5 compute pipes use GDS ordered append.
8138          * The wave IDs generated by ME are also wrong after suspend/resume.
8139          * Those are probably bugs somewhere else in the kernel driver.
8140          *
8141          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8142          * GDS to 0 for this ring (me/pipe).
8143          */
8144         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8145                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8146                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8147                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8148         }
8149
8150         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8151         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8152         amdgpu_ring_write(ring,
8153 #ifdef __BIG_ENDIAN
8154                                 (2 << 0) |
8155 #endif
8156                                 lower_32_bits(ib->gpu_addr));
8157         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8158         amdgpu_ring_write(ring, control);
8159 }
8160
8161 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8162                                      u64 seq, unsigned flags)
8163 {
8164         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8165         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8166
8167         /* RELEASE_MEM - flush caches, send int */
8168         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8169         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8170                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
8171                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8172                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
8173                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8174                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8175                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8176         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8177                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8178
8179         /*
8180          * the address should be Qword aligned if 64bit write, Dword
8181          * aligned if only send 32bit data low (discard data high)
8182          */
8183         if (write64bit)
8184                 BUG_ON(addr & 0x7);
8185         else
8186                 BUG_ON(addr & 0x3);
8187         amdgpu_ring_write(ring, lower_32_bits(addr));
8188         amdgpu_ring_write(ring, upper_32_bits(addr));
8189         amdgpu_ring_write(ring, lower_32_bits(seq));
8190         amdgpu_ring_write(ring, upper_32_bits(seq));
8191         amdgpu_ring_write(ring, 0);
8192 }
8193
8194 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8195 {
8196         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8197         uint32_t seq = ring->fence_drv.sync_seq;
8198         uint64_t addr = ring->fence_drv.gpu_addr;
8199
8200         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8201                                upper_32_bits(addr), seq, 0xffffffff, 4);
8202 }
8203
8204 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8205                                          unsigned vmid, uint64_t pd_addr)
8206 {
8207         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8208
8209         /* compute doesn't have PFP */
8210         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8211                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
8212                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8213                 amdgpu_ring_write(ring, 0x0);
8214         }
8215 }
8216
8217 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8218                                           u64 seq, unsigned int flags)
8219 {
8220         struct amdgpu_device *adev = ring->adev;
8221
8222         /* we only allocate 32bit for each seq wb address */
8223         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8224
8225         /* write fence seq to the "addr" */
8226         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8227         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8228                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8229         amdgpu_ring_write(ring, lower_32_bits(addr));
8230         amdgpu_ring_write(ring, upper_32_bits(addr));
8231         amdgpu_ring_write(ring, lower_32_bits(seq));
8232
8233         if (flags & AMDGPU_FENCE_FLAG_INT) {
8234                 /* set register to trigger INT */
8235                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8236                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8237                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8238                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8239                 amdgpu_ring_write(ring, 0);
8240                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8241         }
8242 }
8243
8244 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8245 {
8246         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8247         amdgpu_ring_write(ring, 0);
8248 }
8249
8250 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8251                                          uint32_t flags)
8252 {
8253         uint32_t dw2 = 0;
8254
8255         if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
8256                 gfx_v10_0_ring_emit_ce_meta(ring,
8257                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8258
8259         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8260         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8261                 /* set load_global_config & load_global_uconfig */
8262                 dw2 |= 0x8001;
8263                 /* set load_cs_sh_regs */
8264                 dw2 |= 0x01000000;
8265                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
8266                 dw2 |= 0x10002;
8267
8268                 /* set load_ce_ram if preamble presented */
8269                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8270                         dw2 |= 0x10000000;
8271         } else {
8272                 /* still load_ce_ram if this is the first time preamble presented
8273                  * although there is no context switch happens.
8274                  */
8275                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8276                         dw2 |= 0x10000000;
8277         }
8278
8279         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8280         amdgpu_ring_write(ring, dw2);
8281         amdgpu_ring_write(ring, 0);
8282 }
8283
8284 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
8285 {
8286         unsigned ret;
8287
8288         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8289         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
8290         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
8291         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
8292         ret = ring->wptr & ring->buf_mask;
8293         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8294
8295         return ret;
8296 }
8297
8298 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
8299 {
8300         unsigned cur;
8301         BUG_ON(offset > ring->buf_mask);
8302         BUG_ON(ring->ring[offset] != 0x55aa55aa);
8303
8304         cur = (ring->wptr - 1) & ring->buf_mask;
8305         if (likely(cur > offset))
8306                 ring->ring[offset] = cur - offset;
8307         else
8308                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8309 }
8310
8311 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8312 {
8313         int i, r = 0;
8314         struct amdgpu_device *adev = ring->adev;
8315         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8316         struct amdgpu_ring *kiq_ring = &kiq->ring;
8317         unsigned long flags;
8318
8319         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8320                 return -EINVAL;
8321
8322         spin_lock_irqsave(&kiq->ring_lock, flags);
8323
8324         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8325                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8326                 return -ENOMEM;
8327         }
8328
8329         /* assert preemption condition */
8330         amdgpu_ring_set_preempt_cond_exec(ring, false);
8331
8332         /* assert IB preemption, emit the trailing fence */
8333         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8334                                    ring->trail_fence_gpu_addr,
8335                                    ++ring->trail_seq);
8336         amdgpu_ring_commit(kiq_ring);
8337
8338         spin_unlock_irqrestore(&kiq->ring_lock, flags);
8339
8340         /* poll the trailing fence */
8341         for (i = 0; i < adev->usec_timeout; i++) {
8342                 if (ring->trail_seq ==
8343                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8344                         break;
8345                 udelay(1);
8346         }
8347
8348         if (i >= adev->usec_timeout) {
8349                 r = -EINVAL;
8350                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8351         }
8352
8353         /* deassert preemption condition */
8354         amdgpu_ring_set_preempt_cond_exec(ring, true);
8355         return r;
8356 }
8357
8358 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8359 {
8360         struct amdgpu_device *adev = ring->adev;
8361         struct v10_ce_ib_state ce_payload = {0};
8362         uint64_t csa_addr;
8363         int cnt;
8364
8365         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8366         csa_addr = amdgpu_csa_vaddr(ring->adev);
8367
8368         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8369         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8370                                  WRITE_DATA_DST_SEL(8) |
8371                                  WR_CONFIRM) |
8372                                  WRITE_DATA_CACHE_POLICY(0));
8373         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8374                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8375         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8376                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8377
8378         if (resume)
8379                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8380                                            offsetof(struct v10_gfx_meta_data,
8381                                                     ce_payload),
8382                                            sizeof(ce_payload) >> 2);
8383         else
8384                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8385                                            sizeof(ce_payload) >> 2);
8386 }
8387
8388 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8389 {
8390         struct amdgpu_device *adev = ring->adev;
8391         struct v10_de_ib_state de_payload = {0};
8392         uint64_t csa_addr, gds_addr;
8393         int cnt;
8394
8395         csa_addr = amdgpu_csa_vaddr(ring->adev);
8396         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
8397                          PAGE_SIZE);
8398         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8399         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8400
8401         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8402         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8403         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8404                                  WRITE_DATA_DST_SEL(8) |
8405                                  WR_CONFIRM) |
8406                                  WRITE_DATA_CACHE_POLICY(0));
8407         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8408                               offsetof(struct v10_gfx_meta_data, de_payload)));
8409         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8410                               offsetof(struct v10_gfx_meta_data, de_payload)));
8411
8412         if (resume)
8413                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8414                                            offsetof(struct v10_gfx_meta_data,
8415                                                     de_payload),
8416                                            sizeof(de_payload) >> 2);
8417         else
8418                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8419                                            sizeof(de_payload) >> 2);
8420 }
8421
8422 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8423                                     bool secure)
8424 {
8425         uint32_t v = secure ? FRAME_TMZ : 0;
8426
8427         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8428         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8429 }
8430
8431 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8432                                      uint32_t reg_val_offs)
8433 {
8434         struct amdgpu_device *adev = ring->adev;
8435
8436         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8437         amdgpu_ring_write(ring, 0 |     /* src: register*/
8438                                 (5 << 8) |      /* dst: memory */
8439                                 (1 << 20));     /* write confirm */
8440         amdgpu_ring_write(ring, reg);
8441         amdgpu_ring_write(ring, 0);
8442         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8443                                 reg_val_offs * 4));
8444         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8445                                 reg_val_offs * 4));
8446 }
8447
8448 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8449                                    uint32_t val)
8450 {
8451         uint32_t cmd = 0;
8452
8453         switch (ring->funcs->type) {
8454         case AMDGPU_RING_TYPE_GFX:
8455                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8456                 break;
8457         case AMDGPU_RING_TYPE_KIQ:
8458                 cmd = (1 << 16); /* no inc addr */
8459                 break;
8460         default:
8461                 cmd = WR_CONFIRM;
8462                 break;
8463         }
8464         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8465         amdgpu_ring_write(ring, cmd);
8466         amdgpu_ring_write(ring, reg);
8467         amdgpu_ring_write(ring, 0);
8468         amdgpu_ring_write(ring, val);
8469 }
8470
8471 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8472                                         uint32_t val, uint32_t mask)
8473 {
8474         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8475 }
8476
8477 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8478                                                    uint32_t reg0, uint32_t reg1,
8479                                                    uint32_t ref, uint32_t mask)
8480 {
8481         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8482         struct amdgpu_device *adev = ring->adev;
8483         bool fw_version_ok = false;
8484
8485         fw_version_ok = adev->gfx.cp_fw_write_wait;
8486
8487         if (fw_version_ok)
8488                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8489                                        ref, mask, 0x20);
8490         else
8491                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8492                                                            ref, mask);
8493 }
8494
8495 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8496                                          unsigned vmid)
8497 {
8498         struct amdgpu_device *adev = ring->adev;
8499         uint32_t value = 0;
8500
8501         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8502         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8503         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8504         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8505         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8506 }
8507
8508 static void
8509 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8510                                       uint32_t me, uint32_t pipe,
8511                                       enum amdgpu_interrupt_state state)
8512 {
8513         uint32_t cp_int_cntl, cp_int_cntl_reg;
8514
8515         if (!me) {
8516                 switch (pipe) {
8517                 case 0:
8518                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8519                         break;
8520                 case 1:
8521                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8522                         break;
8523                 default:
8524                         DRM_DEBUG("invalid pipe %d\n", pipe);
8525                         return;
8526                 }
8527         } else {
8528                 DRM_DEBUG("invalid me %d\n", me);
8529                 return;
8530         }
8531
8532         switch (state) {
8533         case AMDGPU_IRQ_STATE_DISABLE:
8534                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8535                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8536                                             TIME_STAMP_INT_ENABLE, 0);
8537                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8538                 break;
8539         case AMDGPU_IRQ_STATE_ENABLE:
8540                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8541                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8542                                             TIME_STAMP_INT_ENABLE, 1);
8543                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8544                 break;
8545         default:
8546                 break;
8547         }
8548 }
8549
8550 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8551                                                      int me, int pipe,
8552                                                      enum amdgpu_interrupt_state state)
8553 {
8554         u32 mec_int_cntl, mec_int_cntl_reg;
8555
8556         /*
8557          * amdgpu controls only the first MEC. That's why this function only
8558          * handles the setting of interrupts for this specific MEC. All other
8559          * pipes' interrupts are set by amdkfd.
8560          */
8561
8562         if (me == 1) {
8563                 switch (pipe) {
8564                 case 0:
8565                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8566                         break;
8567                 case 1:
8568                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8569                         break;
8570                 case 2:
8571                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8572                         break;
8573                 case 3:
8574                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8575                         break;
8576                 default:
8577                         DRM_DEBUG("invalid pipe %d\n", pipe);
8578                         return;
8579                 }
8580         } else {
8581                 DRM_DEBUG("invalid me %d\n", me);
8582                 return;
8583         }
8584
8585         switch (state) {
8586         case AMDGPU_IRQ_STATE_DISABLE:
8587                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8588                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8589                                              TIME_STAMP_INT_ENABLE, 0);
8590                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8591                 break;
8592         case AMDGPU_IRQ_STATE_ENABLE:
8593                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8594                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8595                                              TIME_STAMP_INT_ENABLE, 1);
8596                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8597                 break;
8598         default:
8599                 break;
8600         }
8601 }
8602
8603 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8604                                             struct amdgpu_irq_src *src,
8605                                             unsigned type,
8606                                             enum amdgpu_interrupt_state state)
8607 {
8608         switch (type) {
8609         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8610                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8611                 break;
8612         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8613                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8614                 break;
8615         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8616                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8617                 break;
8618         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8619                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8620                 break;
8621         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8622                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8623                 break;
8624         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8625                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8626                 break;
8627         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
8628                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
8629                 break;
8630         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
8631                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
8632                 break;
8633         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
8634                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
8635                 break;
8636         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
8637                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
8638                 break;
8639         default:
8640                 break;
8641         }
8642         return 0;
8643 }
8644
8645 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
8646                              struct amdgpu_irq_src *source,
8647                              struct amdgpu_iv_entry *entry)
8648 {
8649         int i;
8650         u8 me_id, pipe_id, queue_id;
8651         struct amdgpu_ring *ring;
8652
8653         DRM_DEBUG("IH: CP EOP\n");
8654         me_id = (entry->ring_id & 0x0c) >> 2;
8655         pipe_id = (entry->ring_id & 0x03) >> 0;
8656         queue_id = (entry->ring_id & 0x70) >> 4;
8657
8658         switch (me_id) {
8659         case 0:
8660                 if (pipe_id == 0)
8661                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8662                 else
8663                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8664                 break;
8665         case 1:
8666         case 2:
8667                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8668                         ring = &adev->gfx.compute_ring[i];
8669                         /* Per-queue interrupt is supported for MEC starting from VI.
8670                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
8671                           */
8672                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
8673                                 amdgpu_fence_process(ring);
8674                 }
8675                 break;
8676         }
8677         return 0;
8678 }
8679
8680 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
8681                                               struct amdgpu_irq_src *source,
8682                                               unsigned type,
8683                                               enum amdgpu_interrupt_state state)
8684 {
8685         switch (state) {
8686         case AMDGPU_IRQ_STATE_DISABLE:
8687         case AMDGPU_IRQ_STATE_ENABLE:
8688                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8689                                PRIV_REG_INT_ENABLE,
8690                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8691                 break;
8692         default:
8693                 break;
8694         }
8695
8696         return 0;
8697 }
8698
8699 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
8700                                                struct amdgpu_irq_src *source,
8701                                                unsigned type,
8702                                                enum amdgpu_interrupt_state state)
8703 {
8704         switch (state) {
8705         case AMDGPU_IRQ_STATE_DISABLE:
8706         case AMDGPU_IRQ_STATE_ENABLE:
8707                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8708                                PRIV_INSTR_INT_ENABLE,
8709                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8710                 break;
8711         default:
8712                 break;
8713         }
8714
8715         return 0;
8716 }
8717
8718 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
8719                                         struct amdgpu_iv_entry *entry)
8720 {
8721         u8 me_id, pipe_id, queue_id;
8722         struct amdgpu_ring *ring;
8723         int i;
8724
8725         me_id = (entry->ring_id & 0x0c) >> 2;
8726         pipe_id = (entry->ring_id & 0x03) >> 0;
8727         queue_id = (entry->ring_id & 0x70) >> 4;
8728
8729         switch (me_id) {
8730         case 0:
8731                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
8732                         ring = &adev->gfx.gfx_ring[i];
8733                         /* we only enabled 1 gfx queue per pipe for now */
8734                         if (ring->me == me_id && ring->pipe == pipe_id)
8735                                 drm_sched_fault(&ring->sched);
8736                 }
8737                 break;
8738         case 1:
8739         case 2:
8740                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8741                         ring = &adev->gfx.compute_ring[i];
8742                         if (ring->me == me_id && ring->pipe == pipe_id &&
8743                             ring->queue == queue_id)
8744                                 drm_sched_fault(&ring->sched);
8745                 }
8746                 break;
8747         default:
8748                 BUG();
8749         }
8750 }
8751
8752 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
8753                                   struct amdgpu_irq_src *source,
8754                                   struct amdgpu_iv_entry *entry)
8755 {
8756         DRM_ERROR("Illegal register access in command stream\n");
8757         gfx_v10_0_handle_priv_fault(adev, entry);
8758         return 0;
8759 }
8760
8761 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
8762                                    struct amdgpu_irq_src *source,
8763                                    struct amdgpu_iv_entry *entry)
8764 {
8765         DRM_ERROR("Illegal instruction in command stream\n");
8766         gfx_v10_0_handle_priv_fault(adev, entry);
8767         return 0;
8768 }
8769
8770 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
8771                                              struct amdgpu_irq_src *src,
8772                                              unsigned int type,
8773                                              enum amdgpu_interrupt_state state)
8774 {
8775         uint32_t tmp, target;
8776         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8777
8778         if (ring->me == 1)
8779                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8780         else
8781                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
8782         target += ring->pipe;
8783
8784         switch (type) {
8785         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
8786                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
8787                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8788                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8789                                             GENERIC2_INT_ENABLE, 0);
8790                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8791
8792                         tmp = RREG32(target);
8793                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8794                                             GENERIC2_INT_ENABLE, 0);
8795                         WREG32(target, tmp);
8796                 } else {
8797                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8798                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8799                                             GENERIC2_INT_ENABLE, 1);
8800                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8801
8802                         tmp = RREG32(target);
8803                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8804                                             GENERIC2_INT_ENABLE, 1);
8805                         WREG32(target, tmp);
8806                 }
8807                 break;
8808         default:
8809                 BUG(); /* kiq only support GENERIC2_INT now */
8810                 break;
8811         }
8812         return 0;
8813 }
8814
8815 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
8816                              struct amdgpu_irq_src *source,
8817                              struct amdgpu_iv_entry *entry)
8818 {
8819         u8 me_id, pipe_id, queue_id;
8820         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8821
8822         me_id = (entry->ring_id & 0x0c) >> 2;
8823         pipe_id = (entry->ring_id & 0x03) >> 0;
8824         queue_id = (entry->ring_id & 0x70) >> 4;
8825         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
8826                    me_id, pipe_id, queue_id);
8827
8828         amdgpu_fence_process(ring);
8829         return 0;
8830 }
8831
8832 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
8833 {
8834         const unsigned int gcr_cntl =
8835                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
8836                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
8837                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
8838                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
8839                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
8840                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
8841                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
8842                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
8843
8844         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
8845         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
8846         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
8847         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
8848         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
8849         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
8850         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
8851         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
8852         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
8853 }
8854
8855 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
8856         .name = "gfx_v10_0",
8857         .early_init = gfx_v10_0_early_init,
8858         .late_init = gfx_v10_0_late_init,
8859         .sw_init = gfx_v10_0_sw_init,
8860         .sw_fini = gfx_v10_0_sw_fini,
8861         .hw_init = gfx_v10_0_hw_init,
8862         .hw_fini = gfx_v10_0_hw_fini,
8863         .suspend = gfx_v10_0_suspend,
8864         .resume = gfx_v10_0_resume,
8865         .is_idle = gfx_v10_0_is_idle,
8866         .wait_for_idle = gfx_v10_0_wait_for_idle,
8867         .soft_reset = gfx_v10_0_soft_reset,
8868         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
8869         .set_powergating_state = gfx_v10_0_set_powergating_state,
8870         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
8871 };
8872
8873 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
8874         .type = AMDGPU_RING_TYPE_GFX,
8875         .align_mask = 0xff,
8876         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8877         .support_64bit_ptrs = true,
8878         .vmhub = AMDGPU_GFXHUB_0,
8879         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
8880         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
8881         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
8882         .emit_frame_size = /* totally 242 maximum if 16 IBs */
8883                 5 + /* COND_EXEC */
8884                 7 + /* PIPELINE_SYNC */
8885                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8886                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8887                 2 + /* VM_FLUSH */
8888                 8 + /* FENCE for VM_FLUSH */
8889                 20 + /* GDS switch */
8890                 4 + /* double SWITCH_BUFFER,
8891                      * the first COND_EXEC jump to the place
8892                      * just prior to this double SWITCH_BUFFER
8893                      */
8894                 5 + /* COND_EXEC */
8895                 7 + /* HDP_flush */
8896                 4 + /* VGT_flush */
8897                 14 + /* CE_META */
8898                 31 + /* DE_META */
8899                 3 + /* CNTX_CTRL */
8900                 5 + /* HDP_INVL */
8901                 8 + 8 + /* FENCE x2 */
8902                 2 + /* SWITCH_BUFFER */
8903                 8, /* gfx_v10_0_emit_mem_sync */
8904         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
8905         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
8906         .emit_fence = gfx_v10_0_ring_emit_fence,
8907         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8908         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8909         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8910         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8911         .test_ring = gfx_v10_0_ring_test_ring,
8912         .test_ib = gfx_v10_0_ring_test_ib,
8913         .insert_nop = amdgpu_ring_insert_nop,
8914         .pad_ib = amdgpu_ring_generic_pad_ib,
8915         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
8916         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
8917         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
8918         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
8919         .preempt_ib = gfx_v10_0_ring_preempt_ib,
8920         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
8921         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8922         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8923         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8924         .soft_recovery = gfx_v10_0_ring_soft_recovery,
8925         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8926 };
8927
8928 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
8929         .type = AMDGPU_RING_TYPE_COMPUTE,
8930         .align_mask = 0xff,
8931         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8932         .support_64bit_ptrs = true,
8933         .vmhub = AMDGPU_GFXHUB_0,
8934         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8935         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8936         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8937         .emit_frame_size =
8938                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8939                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8940                 5 + /* hdp invalidate */
8941                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8942                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8943                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8944                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8945                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
8946                 8, /* gfx_v10_0_emit_mem_sync */
8947         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8948         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8949         .emit_fence = gfx_v10_0_ring_emit_fence,
8950         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8951         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8952         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8953         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8954         .test_ring = gfx_v10_0_ring_test_ring,
8955         .test_ib = gfx_v10_0_ring_test_ib,
8956         .insert_nop = amdgpu_ring_insert_nop,
8957         .pad_ib = amdgpu_ring_generic_pad_ib,
8958         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8959         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8960         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8961         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8962 };
8963
8964 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
8965         .type = AMDGPU_RING_TYPE_KIQ,
8966         .align_mask = 0xff,
8967         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8968         .support_64bit_ptrs = true,
8969         .vmhub = AMDGPU_GFXHUB_0,
8970         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8971         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8972         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8973         .emit_frame_size =
8974                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8975                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8976                 5 + /*hdp invalidate */
8977                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8978                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8979                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8980                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8981                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
8982         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8983         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8984         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
8985         .test_ring = gfx_v10_0_ring_test_ring,
8986         .test_ib = gfx_v10_0_ring_test_ib,
8987         .insert_nop = amdgpu_ring_insert_nop,
8988         .pad_ib = amdgpu_ring_generic_pad_ib,
8989         .emit_rreg = gfx_v10_0_ring_emit_rreg,
8990         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8991         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8992         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8993 };
8994
8995 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
8996 {
8997         int i;
8998
8999         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9000
9001         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9002                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9003
9004         for (i = 0; i < adev->gfx.num_compute_rings; i++)
9005                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9006 }
9007
9008 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9009         .set = gfx_v10_0_set_eop_interrupt_state,
9010         .process = gfx_v10_0_eop_irq,
9011 };
9012
9013 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9014         .set = gfx_v10_0_set_priv_reg_fault_state,
9015         .process = gfx_v10_0_priv_reg_irq,
9016 };
9017
9018 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9019         .set = gfx_v10_0_set_priv_inst_fault_state,
9020         .process = gfx_v10_0_priv_inst_irq,
9021 };
9022
9023 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9024         .set = gfx_v10_0_kiq_set_interrupt_state,
9025         .process = gfx_v10_0_kiq_irq,
9026 };
9027
9028 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9029 {
9030         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9031         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9032
9033         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9034         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9035
9036         adev->gfx.priv_reg_irq.num_types = 1;
9037         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9038
9039         adev->gfx.priv_inst_irq.num_types = 1;
9040         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9041 }
9042
9043 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9044 {
9045         switch (adev->asic_type) {
9046         case CHIP_NAVI10:
9047         case CHIP_NAVI14:
9048         case CHIP_SIENNA_CICHLID:
9049         case CHIP_NAVY_FLOUNDER:
9050         case CHIP_VANGOGH:
9051         case CHIP_DIMGREY_CAVEFISH:
9052                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9053                 break;
9054         case CHIP_NAVI12:
9055                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9056                 break;
9057         default:
9058                 break;
9059         }
9060 }
9061
9062 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9063 {
9064         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
9065                             adev->gfx.config.max_sh_per_se *
9066                             adev->gfx.config.max_shader_engines;
9067
9068         adev->gds.gds_size = 0x10000;
9069         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9070         adev->gds.gws_size = 64;
9071         adev->gds.oa_size = 16;
9072 }
9073
9074 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9075                                                           u32 bitmap)
9076 {
9077         u32 data;
9078
9079         if (!bitmap)
9080                 return;
9081
9082         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9083         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9084
9085         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9086 }
9087
9088 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9089 {
9090         u32 data, wgp_bitmask;
9091         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
9092         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
9093
9094         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9095         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9096
9097         wgp_bitmask =
9098                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9099
9100         return (~data) & wgp_bitmask;
9101 }
9102
9103 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9104 {
9105         u32 wgp_idx, wgp_active_bitmap;
9106         u32 cu_bitmap_per_wgp, cu_active_bitmap;
9107
9108         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9109         cu_active_bitmap = 0;
9110
9111         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9112                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
9113                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9114                 if (wgp_active_bitmap & (1 << wgp_idx))
9115                         cu_active_bitmap |= cu_bitmap_per_wgp;
9116         }
9117
9118         return cu_active_bitmap;
9119 }
9120
9121 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9122                                  struct amdgpu_cu_info *cu_info)
9123 {
9124         int i, j, k, counter, active_cu_number = 0;
9125         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9126         unsigned disable_masks[4 * 2];
9127
9128         if (!adev || !cu_info)
9129                 return -EINVAL;
9130
9131         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9132
9133         mutex_lock(&adev->grbm_idx_mutex);
9134         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9135                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9136                         bitmap = i * adev->gfx.config.max_sh_per_se + j;
9137                         if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
9138                             ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9139                                 continue;
9140                         mask = 1;
9141                         ao_bitmap = 0;
9142                         counter = 0;
9143                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
9144                         if (i < 4 && j < 2)
9145                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9146                                         adev, disable_masks[i * 2 + j]);
9147                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9148                         cu_info->bitmap[i][j] = bitmap;
9149
9150                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9151                                 if (bitmap & mask) {
9152                                         if (counter < adev->gfx.config.max_cu_per_sh)
9153                                                 ao_bitmap |= mask;
9154                                         counter++;
9155                                 }
9156                                 mask <<= 1;
9157                         }
9158                         active_cu_number += counter;
9159                         if (i < 2 && j < 2)
9160                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9161                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9162                 }
9163         }
9164         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
9165         mutex_unlock(&adev->grbm_idx_mutex);
9166
9167         cu_info->number = active_cu_number;
9168         cu_info->ao_cu_mask = ao_cu_mask;
9169         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9170
9171         return 0;
9172 }
9173
9174 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9175 {
9176         uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9177
9178         efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9179         efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9180         efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9181
9182         vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9183         vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9184         vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9185
9186         max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9187                                                 adev->gfx.config.max_shader_engines);
9188         disabled_sa = efuse_setting | vbios_setting;
9189         disabled_sa &= max_sa_mask;
9190
9191         return disabled_sa;
9192 }
9193
9194 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9195 {
9196         uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9197         uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9198
9199         disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9200
9201         max_sa_per_se = adev->gfx.config.max_sh_per_se;
9202         max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9203         max_shader_engines = adev->gfx.config.max_shader_engines;
9204
9205         for (se_index = 0; max_shader_engines > se_index; se_index++) {
9206                 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9207                 disabled_sa_per_se &= max_sa_per_se_mask;
9208                 if (disabled_sa_per_se == max_sa_per_se_mask) {
9209                         WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9210                         break;
9211                 }
9212         }
9213 }
9214
9215 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
9216 {
9217         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
9218                      (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
9219                      (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
9220                      (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
9221
9222         WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
9223         WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
9224                      (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
9225                      (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
9226                      (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
9227                      (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
9228
9229         WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
9230                      (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
9231                      (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
9232                      (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
9233
9234         WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
9235
9236         WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
9237                      (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
9238 }
9239
9240 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
9241 {
9242         .type = AMD_IP_BLOCK_TYPE_GFX,
9243         .major = 10,
9244         .minor = 0,
9245         .rev = 0,
9246         .funcs = &gfx_v10_0_ip_funcs,
9247 };