drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <drm/ttm/ttm_bo_api.h>
  33 #include <drm/ttm/ttm_bo_driver.h>
  34 #include <drm/ttm/ttm_placement.h>
  35 #include <drm/ttm/ttm_module.h>
  36 #include <drm/ttm/ttm_page_alloc.h>
  37 #include <drm/drmP.h>
  38 #include <drm/amdgpu_drm.h>
  39 #include <linux/seq_file.h>
  40 #include <linux/slab.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/swap.h>
  43 #include <linux/pagemap.h>
  44 #include <linux/debugfs.h>
  45 #include <linux/iommu.h>
  46 #include "amdgpu.h"
  47 #include "amdgpu_object.h"
  48 #include "amdgpu_trace.h"
  49 #include "amdgpu_amdkfd.h"
  50 #include "bif/bif_4_1_d.h"
  51
  52 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
  53
  54 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
  55                              struct ttm_mem_reg *mem, unsigned num_pages,
  56                              uint64_t offset, unsigned window,
  57                              struct amdgpu_ring *ring,
  58                              uint64_t *addr);
  59
  60 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
  61 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev);
  62
  63 /*
  64  * Global memory.
  65  */
  66
  67 /**
  68  * amdgpu_ttm_mem_global_init - Initialize and acquire reference to
  69  * memory object
  70  *
  71  * @ref: Object for initialization.
  72  *
  73  * This is called by drm_global_item_ref() when an object is being
  74  * initialized.
  75  */
  76 static int amdgpu_ttm_mem_global_init(struct drm_global_reference *ref)
  77 {
  78         return ttm_mem_global_init(ref->object);
  79 }
  80
  81 /**
  82  * amdgpu_ttm_mem_global_release - Drop reference to a memory object
  83  *
  84  * @ref: Object being removed
  85  *
  86  * This is called by drm_global_item_unref() when an object is being
  87  * released.
  88  */
  89 static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
  90 {
  91         ttm_mem_global_release(ref->object);
  92 }
  93
  94 /**
  95  * amdgpu_ttm_global_init - Initialize global TTM memory reference structures.
  96  *
  97  * @adev: AMDGPU device for which the global structures need to be registered.
  98  *
  99  * This is called as part of the AMDGPU ttm init from amdgpu_ttm_init()
 100  * during bring up.
 101  */
 102 static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
 103 {
 104         struct drm_global_reference *global_ref;
 105         int r;
 106
 107         /* ensure reference is false in case init fails */
 108         adev->mman.mem_global_referenced = false;
 109
 110         global_ref = &adev->mman.mem_global_ref;
 111         global_ref->global_type = DRM_GLOBAL_TTM_MEM;
 112         global_ref->size = sizeof(struct ttm_mem_global);
 113         global_ref->init = &amdgpu_ttm_mem_global_init;
 114         global_ref->release = &amdgpu_ttm_mem_global_release;
 115         r = drm_global_item_ref(global_ref);
 116         if (r) {
 117                 DRM_ERROR("Failed setting up TTM memory accounting "
 118                           "subsystem.\n");
 119                 goto error_mem;
 120         }
 121
 122         adev->mman.bo_global_ref.mem_glob =
 123                 adev->mman.mem_global_ref.object;
 124         global_ref = &adev->mman.bo_global_ref.ref;
 125         global_ref->global_type = DRM_GLOBAL_TTM_BO;
 126         global_ref->size = sizeof(struct ttm_bo_global);
 127         global_ref->init = &ttm_bo_global_init;
 128         global_ref->release = &ttm_bo_global_release;
 129         r = drm_global_item_ref(global_ref);
 130         if (r) {
 131                 DRM_ERROR("Failed setting up TTM BO subsystem.\n");
 132                 goto error_bo;
 133         }
 134
 135         mutex_init(&adev->mman.gtt_window_lock);
 136
 137         adev->mman.mem_global_referenced = true;
 138
 139         return 0;
 140
 141 error_bo:
 142         drm_global_item_unref(&adev->mman.mem_global_ref);
 143 error_mem:
 144         return r;
 145 }
 146
 147 static void amdgpu_ttm_global_fini(struct amdgpu_device *adev)
 148 {
 149         if (adev->mman.mem_global_referenced) {
 150                 mutex_destroy(&adev->mman.gtt_window_lock);
 151                 drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 152                 drm_global_item_unref(&adev->mman.mem_global_ref);
 153                 adev->mman.mem_global_referenced = false;
 154         }
 155 }
 156
 157 static int amdgpu_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
 158 {
 159         return 0;
 160 }
 161
 162 /**
 163  * amdgpu_init_mem_type - Initialize a memory manager for a specific type of
 164  * memory request.
 165  *
 166  * @bdev: The TTM BO device object (contains a reference to amdgpu_device)
 167  * @type: The type of memory requested
 168  * @man: The memory type manager for each domain
 169  *
 170  * This is called by ttm_bo_init_mm() when a buffer object is being
 171  * initialized.
 172  */
 173 static int amdgpu_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
 174                                 struct ttm_mem_type_manager *man)
 175 {
 176         struct amdgpu_device *adev;
 177
 178         adev = amdgpu_ttm_adev(bdev);
 179
 180         switch (type) {
 181         case TTM_PL_SYSTEM:
 182                 /* System memory */
 183                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
 184                 man->available_caching = TTM_PL_MASK_CACHING;
 185                 man->default_caching = TTM_PL_FLAG_CACHED;
 186                 break;
 187         case TTM_PL_TT:
 188                 /* GTT memory  */
 189                 man->func = &amdgpu_gtt_mgr_func;
 190                 man->gpu_offset = adev->gmc.gart_start;
 191                 man->available_caching = TTM_PL_MASK_CACHING;
 192                 man->default_caching = TTM_PL_FLAG_CACHED;
 193                 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | TTM_MEMTYPE_FLAG_CMA;
 194                 break;
 195         case TTM_PL_VRAM:
 196                 /* "On-card" video ram */
 197                 man->func = &amdgpu_vram_mgr_func;
 198                 man->gpu_offset = adev->gmc.vram_start;
 199                 man->flags = TTM_MEMTYPE_FLAG_FIXED |
 200                              TTM_MEMTYPE_FLAG_MAPPABLE;
 201                 man->available_caching = TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
 202                 man->default_caching = TTM_PL_FLAG_WC;
 203                 break;
 204         case AMDGPU_PL_GDS:
 205         case AMDGPU_PL_GWS:
 206         case AMDGPU_PL_OA:
 207                 /* On-chip GDS memory*/
 208                 man->func = &ttm_bo_manager_func;
 209                 man->gpu_offset = 0;
 210                 man->flags = TTM_MEMTYPE_FLAG_FIXED | TTM_MEMTYPE_FLAG_CMA;
 211                 man->available_caching = TTM_PL_FLAG_UNCACHED;
 212                 man->default_caching = TTM_PL_FLAG_UNCACHED;
 213                 break;
 214         default:
 215                 DRM_ERROR("Unsupported memory type %u\n", (unsigned)type);
 216                 return -EINVAL;
 217         }
 218         return 0;
 219 }
 220
 221 /**
 222  * amdgpu_evict_flags - Compute placement flags
 223  *
 224  * @bo: The buffer object to evict
 225  * @placement: Possible destination(s) for evicted BO
 226  *
 227  * Fill in placement data when ttm_bo_evict() is called
 228  */
 229 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
 230                                 struct ttm_placement *placement)
 231 {
 232         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 233         struct amdgpu_bo *abo;
 234         static const struct ttm_place placements = {
 235                 .fpfn = 0,
 236                 .lpfn = 0,
 237                 .flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM
 238         };
 239
 240         /* Don't handle scatter gather BOs */
 241         if (bo->type == ttm_bo_type_sg) {
 242                 placement->num_placement = 0;
 243                 placement->num_busy_placement = 0;
 244                 return;
 245         }
 246
 247         /* Object isn't an AMDGPU object so ignore */
 248         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 249                 placement->placement = &placements;
 250                 placement->busy_placement = &placements;
 251                 placement->num_placement = 1;
 252                 placement->num_busy_placement = 1;
 253                 return;
 254         }
 255
 256         abo = ttm_to_amdgpu_bo(bo);
 257         switch (bo->mem.mem_type) {
 258         case TTM_PL_VRAM:
 259                 if (!adev->mman.buffer_funcs_enabled) {
 260                         /* Move to system memory */
 261                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 262                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 263                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 264                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 265
 266                         /* Try evicting to the CPU inaccessible part of VRAM
 267                          * first, but only set GTT as busy placement, so this
 268                          * BO will be evicted to GTT rather than causing other
 269                          * BOs to be evicted from VRAM
 270                          */
 271                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 272                                                          AMDGPU_GEM_DOMAIN_GTT);
 273                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 274                         abo->placements[0].lpfn = 0;
 275                         abo->placement.busy_placement = &abo->placements[1];
 276                         abo->placement.num_busy_placement = 1;
 277                 } else {
 278                         /* Move to GTT memory */
 279                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 280                 }
 281                 break;
 282         case TTM_PL_TT:
 283         default:
 284                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 285         }
 286         *placement = abo->placement;
 287 }
 288
 289 /**
 290  * amdgpu_verify_access - Verify access for a mmap call
 291  *
 292  * @bo: The buffer object to map
 293  * @filp: The file pointer from the process performing the mmap
 294  *
 295  * This is called by ttm_bo_mmap() to verify whether a process
 296  * has the right to mmap a BO to their process space.
 297  */
 298 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 299 {
 300         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 301
 302         /*
 303          * Don't verify access for KFD BOs. They don't have a GEM
 304          * object associated with them.
 305          */
 306         if (abo->kfd_bo)
 307                 return 0;
 308
 309         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 310                 return -EPERM;
 311         return drm_vma_node_verify_access(&abo->gem_base.vma_node,
 312                                           filp->private_data);
 313 }
 314
 315 /**
 316  * amdgpu_move_null - Register memory for a buffer object
 317  *
 318  * @bo: The bo to assign the memory to
 319  * @new_mem: The memory to be assigned.
 320  *
 321  * Assign the memory from new_mem to the memory of the buffer object bo.
 322  */
 323 static void amdgpu_move_null(struct ttm_buffer_object *bo,
 324                              struct ttm_mem_reg *new_mem)
 325 {
 326         struct ttm_mem_reg *old_mem = &bo->mem;
 327
 328         BUG_ON(old_mem->mm_node != NULL);
 329         *old_mem = *new_mem;
 330         new_mem->mm_node = NULL;
 331 }
 332
 333 /**
 334  * amdgpu_mm_node_addr - Compute the GPU relative offset of a GTT buffer.
 335  *
 336  * @bo: The bo to assign the memory to.
 337  * @mm_node: Memory manager node for drm allocator.
 338  * @mem: The region where the bo resides.
 339  *
 340  */
 341 static uint64_t amdgpu_mm_node_addr(struct ttm_buffer_object *bo,
 342                                     struct drm_mm_node *mm_node,
 343                                     struct ttm_mem_reg *mem)
 344 {
 345         uint64_t addr = 0;
 346
 347         if (mem->mem_type != TTM_PL_TT || amdgpu_gtt_mgr_has_gart_addr(mem)) {
 348                 addr = mm_node->start << PAGE_SHIFT;
 349                 addr += bo->bdev->man[mem->mem_type].gpu_offset;
 350         }
 351         return addr;
 352 }
 353
 354 /**
 355  * amdgpu_find_mm_node - Helper function finds the drm_mm_node corresponding to
 356  * @offset. It also modifies the offset to be within the drm_mm_node returned
 357  *
 358  * @mem: The region where the bo resides.
 359  * @offset: The offset that drm_mm_node is used for finding.
 360  *
 361  */
 362 static struct drm_mm_node *amdgpu_find_mm_node(struct ttm_mem_reg *mem,
 363                                                unsigned long *offset)
 364 {
 365         struct drm_mm_node *mm_node = mem->mm_node;
 366
 367         while (*offset >= (mm_node->size << PAGE_SHIFT)) {
 368                 *offset -= (mm_node->size << PAGE_SHIFT);
 369                 ++mm_node;
 370         }
 371         return mm_node;
 372 }
 373
 374 /**
 375  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 376  *
 377  * The function copies @size bytes from {src->mem + src->offset} to
 378  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 379  * move and different for a BO to BO copy.
 380  *
 381  * @f: Returns the last fence if multiple jobs are submitted.
 382  */
 383 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 384                                struct amdgpu_copy_mem *src,
 385                                struct amdgpu_copy_mem *dst,
 386                                uint64_t size,
 387                                struct reservation_object *resv,
 388                                struct dma_fence **f)
 389 {
 390         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 391         struct drm_mm_node *src_mm, *dst_mm;
 392         uint64_t src_node_start, dst_node_start, src_node_size,
 393                  dst_node_size, src_page_offset, dst_page_offset;
 394         struct dma_fence *fence = NULL;
 395         int r = 0;
 396         const uint64_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 397                                         AMDGPU_GPU_PAGE_SIZE);
 398
 399         if (!adev->mman.buffer_funcs_enabled) {
 400                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 401                 return -EINVAL;
 402         }
 403
 404         src_mm = amdgpu_find_mm_node(src->mem, &src->offset);
 405         src_node_start = amdgpu_mm_node_addr(src->bo, src_mm, src->mem) +
 406                                              src->offset;
 407         src_node_size = (src_mm->size << PAGE_SHIFT) - src->offset;
 408         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 409
 410         dst_mm = amdgpu_find_mm_node(dst->mem, &dst->offset);
 411         dst_node_start = amdgpu_mm_node_addr(dst->bo, dst_mm, dst->mem) +
 412                                              dst->offset;
 413         dst_node_size = (dst_mm->size << PAGE_SHIFT) - dst->offset;
 414         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 415
 416         mutex_lock(&adev->mman.gtt_window_lock);
 417
 418         while (size) {
 419                 unsigned long cur_size;
 420                 uint64_t from = src_node_start, to = dst_node_start;
 421                 struct dma_fence *next;
 422
 423                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 424                  * begins at an offset, then adjust the size accordingly
 425                  */
 426                 cur_size = min3(min(src_node_size, dst_node_size), size,
 427                                 GTT_MAX_BYTES);
 428                 if (cur_size + src_page_offset > GTT_MAX_BYTES ||
 429                     cur_size + dst_page_offset > GTT_MAX_BYTES)
 430                         cur_size -= max(src_page_offset, dst_page_offset);
 431
 432                 /* Map only what needs to be accessed. Map src to window 0 and
 433                  * dst to window 1
 434                  */
 435                 if (src->mem->mem_type == TTM_PL_TT &&
 436                     !amdgpu_gtt_mgr_has_gart_addr(src->mem)) {
 437                         r = amdgpu_map_buffer(src->bo, src->mem,
 438                                         PFN_UP(cur_size + src_page_offset),
 439                                         src_node_start, 0, ring,
 440                                         &from);
 441                         if (r)
 442                                 goto error;
 443                         /* Adjust the offset because amdgpu_map_buffer returns
 444                          * start of mapped page
 445                          */
 446                         from += src_page_offset;
 447                 }
 448
 449                 if (dst->mem->mem_type == TTM_PL_TT &&
 450                     !amdgpu_gtt_mgr_has_gart_addr(dst->mem)) {
 451                         r = amdgpu_map_buffer(dst->bo, dst->mem,
 452                                         PFN_UP(cur_size + dst_page_offset),
 453                                         dst_node_start, 1, ring,
 454                                         &to);
 455                         if (r)
 456                                 goto error;
 457                         to += dst_page_offset;
 458                 }
 459
 460                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 461                                        resv, &next, false, true);
 462                 if (r)
 463                         goto error;
 464
 465                 dma_fence_put(fence);
 466                 fence = next;
 467
 468                 size -= cur_size;
 469                 if (!size)
 470                         break;
 471
 472                 src_node_size -= cur_size;
 473                 if (!src_node_size) {
 474                         src_node_start = amdgpu_mm_node_addr(src->bo, ++src_mm,
 475                                                              src->mem);
 476                         src_node_size = (src_mm->size << PAGE_SHIFT);
 477                 } else {
 478                         src_node_start += cur_size;
 479                         src_page_offset = src_node_start & (PAGE_SIZE - 1);
 480                 }
 481                 dst_node_size -= cur_size;
 482                 if (!dst_node_size) {
 483                         dst_node_start = amdgpu_mm_node_addr(dst->bo, ++dst_mm,
 484                                                              dst->mem);
 485                         dst_node_size = (dst_mm->size << PAGE_SHIFT);
 486                 } else {
 487                         dst_node_start += cur_size;
 488                         dst_page_offset = dst_node_start & (PAGE_SIZE - 1);
 489                 }
 490         }
 491 error:
 492         mutex_unlock(&adev->mman.gtt_window_lock);
 493         if (f)
 494                 *f = dma_fence_get(fence);
 495         dma_fence_put(fence);
 496         return r;
 497 }
 498
 499 /**
 500  * amdgpu_move_blit - Copy an entire buffer to another buffer
 501  *
 502  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 503  * help move buffers to and from VRAM.
 504  */
 505 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 506                             bool evict, bool no_wait_gpu,
 507                             struct ttm_mem_reg *new_mem,
 508                             struct ttm_mem_reg *old_mem)
 509 {
 510         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 511         struct amdgpu_copy_mem src, dst;
 512         struct dma_fence *fence = NULL;
 513         int r;
 514
 515         src.bo = bo;
 516         dst.bo = bo;
 517         src.mem = old_mem;
 518         dst.mem = new_mem;
 519         src.offset = 0;
 520         dst.offset = 0;
 521
 522         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 523                                        new_mem->num_pages << PAGE_SHIFT,
 524                                        bo->resv, &fence);
 525         if (r)
 526                 goto error;
 527
 528         r = ttm_bo_pipeline_move(bo, fence, evict, new_mem);
 529         dma_fence_put(fence);
 530         return r;
 531
 532 error:
 533         if (fence)
 534                 dma_fence_wait(fence, false);
 535         dma_fence_put(fence);
 536         return r;
 537 }
 538
 539 /**
 540  * amdgpu_move_vram_ram - Copy VRAM buffer to RAM buffer
 541  *
 542  * Called by amdgpu_bo_move().
 543  */
 544 static int amdgpu_move_vram_ram(struct ttm_buffer_object *bo, bool evict,
 545                                 struct ttm_operation_ctx *ctx,
 546                                 struct ttm_mem_reg *new_mem)
 547 {
 548         struct amdgpu_device *adev;
 549         struct ttm_mem_reg *old_mem = &bo->mem;
 550         struct ttm_mem_reg tmp_mem;
 551         struct ttm_place placements;
 552         struct ttm_placement placement;
 553         int r;
 554
 555         adev = amdgpu_ttm_adev(bo->bdev);
 556
 557         /* create space/pages for new_mem in GTT space */
 558         tmp_mem = *new_mem;
 559         tmp_mem.mm_node = NULL;
 560         placement.num_placement = 1;
 561         placement.placement = &placements;
 562         placement.num_busy_placement = 1;
 563         placement.busy_placement = &placements;
 564         placements.fpfn = 0;
 565         placements.lpfn = 0;
 566         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 567         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 568         if (unlikely(r)) {
 569                 return r;
 570         }
 571
 572         /* set caching flags */
 573         r = ttm_tt_set_placement_caching(bo->ttm, tmp_mem.placement);
 574         if (unlikely(r)) {
 575                 goto out_cleanup;
 576         }
 577
 578         /* Bind the memory to the GTT space */
 579         r = ttm_tt_bind(bo->ttm, &tmp_mem, ctx);
 580         if (unlikely(r)) {
 581                 goto out_cleanup;
 582         }
 583
 584         /* blit VRAM to GTT */
 585         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, &tmp_mem, old_mem);
 586         if (unlikely(r)) {
 587                 goto out_cleanup;
 588         }
 589
 590         /* move BO (in tmp_mem) to new_mem */
 591         r = ttm_bo_move_ttm(bo, ctx, new_mem);
 592 out_cleanup:
 593         ttm_bo_mem_put(bo, &tmp_mem);
 594         return r;
 595 }
 596
 597 /**
 598  * amdgpu_move_ram_vram - Copy buffer from RAM to VRAM
 599  *
 600  * Called by amdgpu_bo_move().
 601  */
 602 static int amdgpu_move_ram_vram(struct ttm_buffer_object *bo, bool evict,
 603                                 struct ttm_operation_ctx *ctx,
 604                                 struct ttm_mem_reg *new_mem)
 605 {
 606         struct amdgpu_device *adev;
 607         struct ttm_mem_reg *old_mem = &bo->mem;
 608         struct ttm_mem_reg tmp_mem;
 609         struct ttm_placement placement;
 610         struct ttm_place placements;
 611         int r;
 612
 613         adev = amdgpu_ttm_adev(bo->bdev);
 614
 615         /* make space in GTT for old_mem buffer */
 616         tmp_mem = *new_mem;
 617         tmp_mem.mm_node = NULL;
 618         placement.num_placement = 1;
 619         placement.placement = &placements;
 620         placement.num_busy_placement = 1;
 621         placement.busy_placement = &placements;
 622         placements.fpfn = 0;
 623         placements.lpfn = 0;
 624         placements.flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
 625         r = ttm_bo_mem_space(bo, &placement, &tmp_mem, ctx);
 626         if (unlikely(r)) {
 627                 return r;
 628         }
 629
 630         /* move/bind old memory to GTT space */
 631         r = ttm_bo_move_ttm(bo, ctx, &tmp_mem);
 632         if (unlikely(r)) {
 633                 goto out_cleanup;
 634         }
 635
 636         /* copy to VRAM */
 637         r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu, new_mem, old_mem);
 638         if (unlikely(r)) {
 639                 goto out_cleanup;
 640         }
 641 out_cleanup:
 642         ttm_bo_mem_put(bo, &tmp_mem);
 643         return r;
 644 }
 645
 646 /**
 647  * amdgpu_bo_move - Move a buffer object to a new memory location
 648  *
 649  * Called by ttm_bo_handle_move_mem()
 650  */
 651 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 652                           struct ttm_operation_ctx *ctx,
 653                           struct ttm_mem_reg *new_mem)
 654 {
 655         struct amdgpu_device *adev;
 656         struct amdgpu_bo *abo;
 657         struct ttm_mem_reg *old_mem = &bo->mem;
 658         int r;
 659
 660         /* Can't move a pinned BO */
 661         abo = ttm_to_amdgpu_bo(bo);
 662         if (WARN_ON_ONCE(abo->pin_count > 0))
 663                 return -EINVAL;
 664
 665         adev = amdgpu_ttm_adev(bo->bdev);
 666
 667         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 668                 amdgpu_move_null(bo, new_mem);
 669                 return 0;
 670         }
 671         if ((old_mem->mem_type == TTM_PL_TT &&
 672              new_mem->mem_type == TTM_PL_SYSTEM) ||
 673             (old_mem->mem_type == TTM_PL_SYSTEM &&
 674              new_mem->mem_type == TTM_PL_TT)) {
 675                 /* bind is enough */
 676                 amdgpu_move_null(bo, new_mem);
 677                 return 0;
 678         }
 679
 680         if (!adev->mman.buffer_funcs_enabled)
 681                 goto memcpy;
 682
 683         if (old_mem->mem_type == TTM_PL_VRAM &&
 684             new_mem->mem_type == TTM_PL_SYSTEM) {
 685                 r = amdgpu_move_vram_ram(bo, evict, ctx, new_mem);
 686         } else if (old_mem->mem_type == TTM_PL_SYSTEM &&
 687                    new_mem->mem_type == TTM_PL_VRAM) {
 688                 r = amdgpu_move_ram_vram(bo, evict, ctx, new_mem);
 689         } else {
 690                 r = amdgpu_move_blit(bo, evict, ctx->no_wait_gpu,
 691                                      new_mem, old_mem);
 692         }
 693
 694         if (r) {
 695 memcpy:
 696                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 697                 if (r) {
 698                         return r;
 699                 }
 700         }
 701
 702         if (bo->type == ttm_bo_type_device &&
 703             new_mem->mem_type == TTM_PL_VRAM &&
 704             old_mem->mem_type != TTM_PL_VRAM) {
 705                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 706                  * accesses the BO after it's moved.
 707                  */
 708                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 709         }
 710
 711         /* update statistics */
 712         atomic64_add((u64)bo->num_pages << PAGE_SHIFT, &adev->num_bytes_moved);
 713         return 0;
 714 }
 715
 716 /**
 717  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 718  *
 719  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 720  */
 721 static int amdgpu_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 722 {
 723         struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
 724         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 725         struct drm_mm_node *mm_node = mem->mm_node;
 726
 727         mem->bus.addr = NULL;
 728         mem->bus.offset = 0;
 729         mem->bus.size = mem->num_pages << PAGE_SHIFT;
 730         mem->bus.base = 0;
 731         mem->bus.is_iomem = false;
 732         if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
 733                 return -EINVAL;
 734         switch (mem->mem_type) {
 735         case TTM_PL_SYSTEM:
 736                 /* system memory */
 737                 return 0;
 738         case TTM_PL_TT:
 739                 break;
 740         case TTM_PL_VRAM:
 741                 mem->bus.offset = mem->start << PAGE_SHIFT;
 742                 /* check if it's visible */
 743                 if ((mem->bus.offset + mem->bus.size) > adev->gmc.visible_vram_size)
 744                         return -EINVAL;
 745                 /* Only physically contiguous buffers apply. In a contiguous
 746                  * buffer, size of the first mm_node would match the number of
 747                  * pages in ttm_mem_reg.
 748                  */
 749                 if (adev->mman.aper_base_kaddr &&
 750                     (mm_node->size == mem->num_pages))
 751                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 752                                         mem->bus.offset;
 753
 754                 mem->bus.base = adev->gmc.aper_base;
 755                 mem->bus.is_iomem = true;
 756                 break;
 757         default:
 758                 return -EINVAL;
 759         }
 760         return 0;
 761 }
 762
 763 static void amdgpu_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
 764 {
 765 }
 766
 767 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 768                                            unsigned long page_offset)
 769 {
 770         struct drm_mm_node *mm;
 771         unsigned long offset = (page_offset << PAGE_SHIFT);
 772
 773         mm = amdgpu_find_mm_node(&bo->mem, &offset);
 774         return (bo->mem.bus.base >> PAGE_SHIFT) + mm->start +
 775                 (offset >> PAGE_SHIFT);
 776 }
 777
 778 /*
 779  * TTM backend functions.
 780  */
 781 struct amdgpu_ttm_gup_task_list {
 782         struct list_head        list;
 783         struct task_struct      *task;
 784 };
 785
 786 struct amdgpu_ttm_tt {
 787         struct ttm_dma_tt       ttm;
 788         u64                     offset;
 789         uint64_t                userptr;
 790         struct task_struct      *usertask;
 791         uint32_t                userflags;
 792         spinlock_t              guptasklock;
 793         struct list_head        guptasks;
 794         atomic_t                mmu_invalidations;
 795         uint32_t                last_set_pages;
 796 };
 797
 798 /**
 799  * amdgpu_ttm_tt_get_user_pages - Pin pages of memory pointed to by a USERPTR
 800  * pointer to memory
 801  *
 802  * Called by amdgpu_gem_userptr_ioctl() and amdgpu_cs_parser_bos().
 803  * This provides a wrapper around the get_user_pages() call to provide
 804  * device accessible pages that back user memory.
 805  */
 806 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages)
 807 {
 808         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 809         struct mm_struct *mm = gtt->usertask->mm;
 810         unsigned int flags = 0;
 811         unsigned pinned = 0;
 812         int r;
 813
 814         if (!mm) /* Happens during process shutdown */
 815                 return -ESRCH;
 816
 817         if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 818                 flags |= FOLL_WRITE;
 819
 820         down_read(&mm->mmap_sem);
 821
 822         if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) {
 823                 /*
 824                  * check that we only use anonymous memory to prevent problems
 825                  * with writeback
 826                  */
 827                 unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE;
 828                 struct vm_area_struct *vma;
 829
 830                 vma = find_vma(mm, gtt->userptr);
 831                 if (!vma || vma->vm_file || vma->vm_end < end) {
 832                         up_read(&mm->mmap_sem);
 833                         return -EPERM;
 834                 }
 835         }
 836
 837         /* loop enough times using contiguous pages of memory */
 838         do {
 839                 unsigned num_pages = ttm->num_pages - pinned;
 840                 uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE;
 841                 struct page **p = pages + pinned;
 842                 struct amdgpu_ttm_gup_task_list guptask;
 843
 844                 guptask.task = current;
 845                 spin_lock(&gtt->guptasklock);
 846                 list_add(&guptask.list, &gtt->guptasks);
 847                 spin_unlock(&gtt->guptasklock);
 848
 849                 if (mm == current->mm)
 850                         r = get_user_pages(userptr, num_pages, flags, p, NULL);
 851                 else
 852                         r = get_user_pages_remote(gtt->usertask,
 853                                         mm, userptr, num_pages,
 854                                         flags, p, NULL, NULL);
 855
 856                 spin_lock(&gtt->guptasklock);
 857                 list_del(&guptask.list);
 858                 spin_unlock(&gtt->guptasklock);
 859
 860                 if (r < 0)
 861                         goto release_pages;
 862
 863                 pinned += r;
 864
 865         } while (pinned < ttm->num_pages);
 866
 867         up_read(&mm->mmap_sem);
 868         return 0;
 869
 870 release_pages:
 871         release_pages(pages, pinned);
 872         up_read(&mm->mmap_sem);
 873         return r;
 874 }
 875
 876 /**
 877  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 878  *
 879  * Called by amdgpu_cs_list_validate(). This creates the page list
 880  * that backs user memory and will ultimately be mapped into the device
 881  * address space.
 882  */
 883 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 884 {
 885         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 886         unsigned i;
 887
 888         gtt->last_set_pages = atomic_read(&gtt->mmu_invalidations);
 889         for (i = 0; i < ttm->num_pages; ++i) {
 890                 if (ttm->pages[i])
 891                         put_page(ttm->pages[i]);
 892
 893                 ttm->pages[i] = pages ? pages[i] : NULL;
 894         }
 895 }
 896
 897 /**
 898  * amdgpu_ttm_tt_mark_user_page - Mark pages as dirty
 899  *
 900  * Called while unpinning userptr pages
 901  */
 902 void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm)
 903 {
 904         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 905         unsigned i;
 906
 907         for (i = 0; i < ttm->num_pages; ++i) {
 908                 struct page *page = ttm->pages[i];
 909
 910                 if (!page)
 911                         continue;
 912
 913                 if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY))
 914                         set_page_dirty(page);
 915
 916                 mark_page_accessed(page);
 917         }
 918 }
 919
 920 /**
 921  * amdgpu_ttm_tt_pin_userptr -  prepare the sg table with the user pages
 922  *
 923  * Called by amdgpu_ttm_backend_bind()
 924  **/
 925 static int amdgpu_ttm_tt_pin_userptr(struct ttm_tt *ttm)
 926 {
 927         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 928         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 929         unsigned nents;
 930         int r;
 931
 932         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 933         enum dma_data_direction direction = write ?
 934                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 935
 936         /* Allocate an SG array and squash pages into it */
 937         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 938                                       ttm->num_pages << PAGE_SHIFT,
 939                                       GFP_KERNEL);
 940         if (r)
 941                 goto release_sg;
 942
 943         /* Map SG to device */
 944         r = -ENOMEM;
 945         nents = dma_map_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 946         if (nents != ttm->sg->nents)
 947                 goto release_sg;
 948
 949         /* convert SG to linear array of pages and dma addresses */
 950         drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
 951                                          gtt->ttm.dma_address, ttm->num_pages);
 952
 953         return 0;
 954
 955 release_sg:
 956         kfree(ttm->sg);
 957         return r;
 958 }
 959
 960 /**
 961  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 962  */
 963 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 964 {
 965         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
 966         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 967
 968         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 969         enum dma_data_direction direction = write ?
 970                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 971
 972         /* double check that we don't free the table twice */
 973         if (!ttm->sg->sgl)
 974                 return;
 975
 976         /* unmap the pages mapped to the device */
 977         dma_unmap_sg(adev->dev, ttm->sg->sgl, ttm->sg->nents, direction);
 978
 979         /* mark the pages as dirty */
 980         amdgpu_ttm_tt_mark_user_pages(ttm);
 981
 982         sg_free_table(ttm->sg);
 983 }
 984
 985 int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 986                                 struct ttm_buffer_object *tbo,
 987                                 uint64_t flags)
 988 {
 989         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
 990         struct ttm_tt *ttm = tbo->ttm;
 991         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 992         int r;
 993
 994         if (abo->flags & AMDGPU_GEM_CREATE_MQD_GFX9) {
 995                 uint64_t page_idx = 1;
 996
 997                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
 998                                 ttm->pages, gtt->ttm.dma_address, flags);
 999                 if (r)
1000                         goto gart_bind_fail;
1001
1002                 /* Patch mtype of the second part BO */
1003                 flags &=  ~AMDGPU_PTE_MTYPE_MASK;
1004                 flags |= AMDGPU_PTE_MTYPE(AMDGPU_MTYPE_NC);
1005
1006                 r = amdgpu_gart_bind(adev,
1007                                 gtt->offset + (page_idx << PAGE_SHIFT),
1008                                 ttm->num_pages - page_idx,
1009                                 &ttm->pages[page_idx],
1010                                 &(gtt->ttm.dma_address[page_idx]), flags);
1011         } else {
1012                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1013                                      ttm->pages, gtt->ttm.dma_address, flags);
1014         }
1015
1016 gart_bind_fail:
1017         if (r)
1018                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1019                           ttm->num_pages, gtt->offset);
1020
1021         return r;
1022 }
1023
1024 /**
1025  * amdgpu_ttm_backend_bind - Bind GTT memory
1026  *
1027  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
1028  * This handles binding GTT memory to the device address space.
1029  */
1030 static int amdgpu_ttm_backend_bind(struct ttm_tt *ttm,
1031                                    struct ttm_mem_reg *bo_mem)
1032 {
1033         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1034         struct amdgpu_ttm_tt *gtt = (void*)ttm;
1035         uint64_t flags;
1036         int r = 0;
1037
1038         if (gtt->userptr) {
1039                 r = amdgpu_ttm_tt_pin_userptr(ttm);
1040                 if (r) {
1041                         DRM_ERROR("failed to pin userptr\n");
1042                         return r;
1043                 }
1044         }
1045         if (!ttm->num_pages) {
1046                 WARN(1, "nothing to bind %lu pages for mreg %p back %p!\n",
1047                      ttm->num_pages, bo_mem, ttm);
1048         }
1049
1050         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
1051             bo_mem->mem_type == AMDGPU_PL_GWS ||
1052             bo_mem->mem_type == AMDGPU_PL_OA)
1053                 return -EINVAL;
1054
1055         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
1056                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
1057                 return 0;
1058         }
1059
1060         /* compute PTE flags relevant to this BO memory */
1061         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
1062
1063         /* bind pages into GART page tables */
1064         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
1065         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
1066                 ttm->pages, gtt->ttm.dma_address, flags);
1067
1068         if (r)
1069                 DRM_ERROR("failed to bind %lu pages at 0x%08llX\n",
1070                           ttm->num_pages, gtt->offset);
1071         return r;
1072 }
1073
1074 /**
1075  * amdgpu_ttm_alloc_gart - Allocate GART memory for buffer object
1076  */
1077 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
1078 {
1079         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1080         struct ttm_operation_ctx ctx = { false, false };
1081         struct amdgpu_ttm_tt *gtt = (void*)bo->ttm;
1082         struct ttm_mem_reg tmp;
1083         struct ttm_placement placement;
1084         struct ttm_place placements;
1085         uint64_t flags;
1086         int r;
1087
1088         if (bo->mem.mem_type != TTM_PL_TT ||
1089             amdgpu_gtt_mgr_has_gart_addr(&bo->mem))
1090                 return 0;
1091
1092         /* allocate GTT space */
1093         tmp = bo->mem;
1094         tmp.mm_node = NULL;
1095         placement.num_placement = 1;
1096         placement.placement = &placements;
1097         placement.num_busy_placement = 1;
1098         placement.busy_placement = &placements;
1099         placements.fpfn = 0;
1100         placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
1101         placements.flags = (bo->mem.placement & ~TTM_PL_MASK_MEM) |
1102                 TTM_PL_FLAG_TT;
1103
1104         r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
1105         if (unlikely(r))
1106                 return r;
1107
1108         /* compute PTE flags for this buffer object */
1109         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
1110
1111         /* Bind pages */
1112         gtt->offset = (u64)tmp.start << PAGE_SHIFT;
1113         r = amdgpu_ttm_gart_bind(adev, bo, flags);
1114         if (unlikely(r)) {
1115                 ttm_bo_mem_put(bo, &tmp);
1116                 return r;
1117         }
1118
1119         ttm_bo_mem_put(bo, &bo->mem);
1120         bo->mem = tmp;
1121         bo->offset = (bo->mem.start << PAGE_SHIFT) +
1122                 bo->bdev->man[bo->mem.mem_type].gpu_offset;
1123
1124         return 0;
1125 }
1126
1127 /**
1128  * amdgpu_ttm_recover_gart - Rebind GTT pages
1129  *
1130  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
1131  * rebind GTT pages during a GPU reset.
1132  */
1133 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
1134 {
1135         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1136         uint64_t flags;
1137         int r;
1138
1139         if (!tbo->ttm)
1140                 return 0;
1141
1142         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1143         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1144
1145         return r;
1146 }
1147
1148 /**
1149  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1150  *
1151  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1152  * ttm_tt_destroy().
1153  */
1154 static int amdgpu_ttm_backend_unbind(struct ttm_tt *ttm)
1155 {
1156         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1157         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1158         int r;
1159
1160         /* if the pages have userptr pinning then clear that first */
1161         if (gtt->userptr)
1162                 amdgpu_ttm_tt_unpin_userptr(ttm);
1163
1164         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1165                 return 0;
1166
1167         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1168         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1169         if (r)
1170                 DRM_ERROR("failed to unbind %lu pages at 0x%08llX\n",
1171                           gtt->ttm.ttm.num_pages, gtt->offset);
1172         return r;
1173 }
1174
1175 static void amdgpu_ttm_backend_destroy(struct ttm_tt *ttm)
1176 {
1177         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1178
1179         if (gtt->usertask)
1180                 put_task_struct(gtt->usertask);
1181
1182         ttm_dma_tt_fini(&gtt->ttm);
1183         kfree(gtt);
1184 }
1185
1186 static struct ttm_backend_func amdgpu_backend_func = {
1187         .bind = &amdgpu_ttm_backend_bind,
1188         .unbind = &amdgpu_ttm_backend_unbind,
1189         .destroy = &amdgpu_ttm_backend_destroy,
1190 };
1191
1192 /**
1193  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1194  *
1195  * @bo: The buffer object to create a GTT ttm_tt object around
1196  *
1197  * Called by ttm_tt_create().
1198  */
1199 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1200                                            uint32_t page_flags)
1201 {
1202         struct amdgpu_device *adev;
1203         struct amdgpu_ttm_tt *gtt;
1204
1205         adev = amdgpu_ttm_adev(bo->bdev);
1206
1207         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1208         if (gtt == NULL) {
1209                 return NULL;
1210         }
1211         gtt->ttm.ttm.func = &amdgpu_backend_func;
1212
1213         /* allocate space for the uninitialized page entries */
1214         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags)) {
1215                 kfree(gtt);
1216                 return NULL;
1217         }
1218         return &gtt->ttm.ttm;
1219 }
1220
1221 /**
1222  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1223  *
1224  * Map the pages of a ttm_tt object to an address space visible
1225  * to the underlying device.
1226  */
1227 static int amdgpu_ttm_tt_populate(struct ttm_tt *ttm,
1228                         struct ttm_operation_ctx *ctx)
1229 {
1230         struct amdgpu_device *adev = amdgpu_ttm_adev(ttm->bdev);
1231         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1232         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1233
1234         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1235         if (gtt && gtt->userptr) {
1236                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1237                 if (!ttm->sg)
1238                         return -ENOMEM;
1239
1240                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1241                 ttm->state = tt_unbound;
1242                 return 0;
1243         }
1244
1245         if (slave && ttm->sg) {
1246                 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1247                                                  gtt->ttm.dma_address,
1248                                                  ttm->num_pages);
1249                 ttm->state = tt_unbound;
1250                 return 0;
1251         }
1252
1253 #ifdef CONFIG_SWIOTLB
1254         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1255                 return ttm_dma_populate(&gtt->ttm, adev->dev, ctx);
1256         }
1257 #endif
1258
1259         /* fall back to generic helper to populate the page array
1260          * and map them to the device */
1261         return ttm_populate_and_map_pages(adev->dev, &gtt->ttm, ctx);
1262 }
1263
1264 /**
1265  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1266  *
1267  * Unmaps pages of a ttm_tt object from the device address space and
1268  * unpopulates the page array backing it.
1269  */
1270 static void amdgpu_ttm_tt_unpopulate(struct ttm_tt *ttm)
1271 {
1272         struct amdgpu_device *adev;
1273         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1274         bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1275
1276         if (gtt && gtt->userptr) {
1277                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1278                 kfree(ttm->sg);
1279                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1280                 return;
1281         }
1282
1283         if (slave)
1284                 return;
1285
1286         adev = amdgpu_ttm_adev(ttm->bdev);
1287
1288 #ifdef CONFIG_SWIOTLB
1289         if (adev->need_swiotlb && swiotlb_nr_tbl()) {
1290                 ttm_dma_unpopulate(&gtt->ttm, adev->dev);
1291                 return;
1292         }
1293 #endif
1294
1295         /* fall back to generic helper to unmap and unpopulate array */
1296         ttm_unmap_and_unpopulate_pages(adev->dev, &gtt->ttm);
1297 }
1298
1299 /**
1300  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1301  * task
1302  *
1303  * @ttm: The ttm_tt object to bind this userptr object to
1304  * @addr:  The address in the current tasks VM space to use
1305  * @flags: Requirements of userptr object.
1306  *
1307  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1308  * to current task
1309  */
1310 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1311                               uint32_t flags)
1312 {
1313         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1314
1315         if (gtt == NULL)
1316                 return -EINVAL;
1317
1318         gtt->userptr = addr;
1319         gtt->userflags = flags;
1320
1321         if (gtt->usertask)
1322                 put_task_struct(gtt->usertask);
1323         gtt->usertask = current->group_leader;
1324         get_task_struct(gtt->usertask);
1325
1326         spin_lock_init(&gtt->guptasklock);
1327         INIT_LIST_HEAD(&gtt->guptasks);
1328         atomic_set(&gtt->mmu_invalidations, 0);
1329         gtt->last_set_pages = 0;
1330
1331         return 0;
1332 }
1333
1334 /**
1335  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1336  */
1337 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1338 {
1339         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1340
1341         if (gtt == NULL)
1342                 return NULL;
1343
1344         if (gtt->usertask == NULL)
1345                 return NULL;
1346
1347         return gtt->usertask->mm;
1348 }
1349
1350 /**
1351  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1352  * address range for the current task.
1353  *
1354  */
1355 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1356                                   unsigned long end)
1357 {
1358         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1359         struct amdgpu_ttm_gup_task_list *entry;
1360         unsigned long size;
1361
1362         if (gtt == NULL || !gtt->userptr)
1363                 return false;
1364
1365         /* Return false if no part of the ttm_tt object lies within
1366          * the range
1367          */
1368         size = (unsigned long)gtt->ttm.ttm.num_pages * PAGE_SIZE;
1369         if (gtt->userptr > end || gtt->userptr + size <= start)
1370                 return false;
1371
1372         /* Search the lists of tasks that hold this mapping and see
1373          * if current is one of them.  If it is return false.
1374          */
1375         spin_lock(&gtt->guptasklock);
1376         list_for_each_entry(entry, &gtt->guptasks, list) {
1377                 if (entry->task == current) {
1378                         spin_unlock(&gtt->guptasklock);
1379                         return false;
1380                 }
1381         }
1382         spin_unlock(&gtt->guptasklock);
1383
1384         atomic_inc(&gtt->mmu_invalidations);
1385
1386         return true;
1387 }
1388
1389 /**
1390  * amdgpu_ttm_tt_userptr_invalidated - Has the ttm_tt object been invalidated?
1391  */
1392 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1393                                        int *last_invalidated)
1394 {
1395         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1396         int prev_invalidated = *last_invalidated;
1397
1398         *last_invalidated = atomic_read(&gtt->mmu_invalidations);
1399         return prev_invalidated != *last_invalidated;
1400 }
1401
1402 /**
1403  * amdgpu_ttm_tt_userptr_needs_pages - Have the pages backing this ttm_tt object
1404  * been invalidated since the last time they've been set?
1405  */
1406 bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm)
1407 {
1408         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1409
1410         if (gtt == NULL || !gtt->userptr)
1411                 return false;
1412
1413         return atomic_read(&gtt->mmu_invalidations) != gtt->last_set_pages;
1414 }
1415
1416 /**
1417  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1418  */
1419 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1420 {
1421         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1422
1423         if (gtt == NULL)
1424                 return false;
1425
1426         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1427 }
1428
1429 /**
1430  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1431  *
1432  * @ttm: The ttm_tt object to compute the flags for
1433  * @mem: The memory registry backing this ttm_tt object
1434  */
1435 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1436                                  struct ttm_mem_reg *mem)
1437 {
1438         uint64_t flags = 0;
1439
1440         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1441                 flags |= AMDGPU_PTE_VALID;
1442
1443         if (mem && mem->mem_type == TTM_PL_TT) {
1444                 flags |= AMDGPU_PTE_SYSTEM;
1445
1446                 if (ttm->caching_state == tt_cached)
1447                         flags |= AMDGPU_PTE_SNOOPED;
1448         }
1449
1450         flags |= adev->gart.gart_pte_flags;
1451         flags |= AMDGPU_PTE_READABLE;
1452
1453         if (!amdgpu_ttm_tt_is_readonly(ttm))
1454                 flags |= AMDGPU_PTE_WRITEABLE;
1455
1456         return flags;
1457 }
1458
1459 /**
1460  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1461  * object.
1462  *
1463  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1464  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1465  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1466  * used to clean out a memory space.
1467  */
1468 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1469                                             const struct ttm_place *place)
1470 {
1471         unsigned long num_pages = bo->mem.num_pages;
1472         struct drm_mm_node *node = bo->mem.mm_node;
1473         struct reservation_object_list *flist;
1474         struct dma_fence *f;
1475         int i;
1476
1477         /* If bo is a KFD BO, check if the bo belongs to the current process.
1478          * If true, then return false as any KFD process needs all its BOs to
1479          * be resident to run successfully
1480          */
1481         flist = reservation_object_get_list(bo->resv);
1482         if (flist) {
1483                 for (i = 0; i < flist->shared_count; ++i) {
1484                         f = rcu_dereference_protected(flist->shared[i],
1485                                 reservation_object_held(bo->resv));
1486                         if (amdkfd_fence_check_mm(f, current->mm))
1487                                 return false;
1488                 }
1489         }
1490
1491         switch (bo->mem.mem_type) {
1492         case TTM_PL_TT:
1493                 return true;
1494
1495         case TTM_PL_VRAM:
1496                 /* Check each drm MM node individually */
1497                 while (num_pages) {
1498                         if (place->fpfn < (node->start + node->size) &&
1499                             !(place->lpfn && place->lpfn <= node->start))
1500                                 return true;
1501
1502                         num_pages -= node->size;
1503                         ++node;
1504                 }
1505                 return false;
1506
1507         default:
1508                 break;
1509         }
1510
1511         return ttm_bo_eviction_valuable(bo, place);
1512 }
1513
1514 /**
1515  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1516  *
1517  * @bo:  The buffer object to read/write
1518  * @offset:  Offset into buffer object
1519  * @buf:  Secondary buffer to write/read from
1520  * @len: Length in bytes of access
1521  * @write:  true if writing
1522  *
1523  * This is used to access VRAM that backs a buffer object via MMIO
1524  * access for debugging purposes.
1525  */
1526 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1527                                     unsigned long offset,
1528                                     void *buf, int len, int write)
1529 {
1530         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1531         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1532         struct drm_mm_node *nodes;
1533         uint32_t value = 0;
1534         int ret = 0;
1535         uint64_t pos;
1536         unsigned long flags;
1537
1538         if (bo->mem.mem_type != TTM_PL_VRAM)
1539                 return -EIO;
1540
1541         nodes = amdgpu_find_mm_node(&abo->tbo.mem, &offset);
1542         pos = (nodes->start << PAGE_SHIFT) + offset;
1543
1544         while (len && pos < adev->gmc.mc_vram_size) {
1545                 uint64_t aligned_pos = pos & ~(uint64_t)3;
1546                 uint32_t bytes = 4 - (pos & 3);
1547                 uint32_t shift = (pos & 3) * 8;
1548                 uint32_t mask = 0xffffffff << shift;
1549
1550                 if (len < bytes) {
1551                         mask &= 0xffffffff >> (bytes - len) * 8;
1552                         bytes = len;
1553                 }
1554
1555                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1556                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1557                 WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1558                 if (!write || mask != 0xffffffff)
1559                         value = RREG32_NO_KIQ(mmMM_DATA);
1560                 if (write) {
1561                         value &= ~mask;
1562                         value |= (*(uint32_t *)buf << shift) & mask;
1563                         WREG32_NO_KIQ(mmMM_DATA, value);
1564                 }
1565                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1566                 if (!write) {
1567                         value = (value & mask) >> shift;
1568                         memcpy(buf, &value, bytes);
1569                 }
1570
1571                 ret += bytes;
1572                 buf = (uint8_t *)buf + bytes;
1573                 pos += bytes;
1574                 len -= bytes;
1575                 if (pos >= (nodes->start + nodes->size) << PAGE_SHIFT) {
1576                         ++nodes;
1577                         pos = (nodes->start << PAGE_SHIFT);
1578                 }
1579         }
1580
1581         return ret;
1582 }
1583
1584 static struct ttm_bo_driver amdgpu_bo_driver = {
1585         .ttm_tt_create = &amdgpu_ttm_tt_create,
1586         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1587         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1588         .invalidate_caches = &amdgpu_invalidate_caches,
1589         .init_mem_type = &amdgpu_init_mem_type,
1590         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1591         .evict_flags = &amdgpu_evict_flags,
1592         .move = &amdgpu_bo_move,
1593         .verify_access = &amdgpu_verify_access,
1594         .move_notify = &amdgpu_bo_move_notify,
1595         .fault_reserve_notify = &amdgpu_bo_fault_reserve_notify,
1596         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1597         .io_mem_free = &amdgpu_ttm_io_mem_free,
1598         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1599         .access_memory = &amdgpu_ttm_access_memory
1600 };
1601
1602 /*
1603  * Firmware Reservation functions
1604  */
1605 /**
1606  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1607  *
1608  * @adev: amdgpu_device pointer
1609  *
1610  * free fw reserved vram if it has been reserved.
1611  */
1612 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1613 {
1614         amdgpu_bo_free_kernel(&adev->fw_vram_usage.reserved_bo,
1615                 NULL, &adev->fw_vram_usage.va);
1616 }
1617
1618 /**
1619  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1620  *
1621  * @adev: amdgpu_device pointer
1622  *
1623  * create bo vram reservation from fw.
1624  */
1625 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1626 {
1627         struct ttm_operation_ctx ctx = { false, false };
1628         struct amdgpu_bo_param bp;
1629         int r = 0;
1630         int i;
1631         u64 vram_size = adev->gmc.visible_vram_size;
1632         u64 offset = adev->fw_vram_usage.start_offset;
1633         u64 size = adev->fw_vram_usage.size;
1634         struct amdgpu_bo *bo;
1635
1636         memset(&bp, 0, sizeof(bp));
1637         bp.size = adev->fw_vram_usage.size;
1638         bp.byte_align = PAGE_SIZE;
1639         bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
1640         bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
1641                 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1642         bp.type = ttm_bo_type_kernel;
1643         bp.resv = NULL;
1644         adev->fw_vram_usage.va = NULL;
1645         adev->fw_vram_usage.reserved_bo = NULL;
1646
1647         if (adev->fw_vram_usage.size > 0 &&
1648                 adev->fw_vram_usage.size <= vram_size) {
1649
1650                 r = amdgpu_bo_create(adev, &bp,
1651                                      &adev->fw_vram_usage.reserved_bo);
1652                 if (r)
1653                         goto error_create;
1654
1655                 r = amdgpu_bo_reserve(adev->fw_vram_usage.reserved_bo, false);
1656                 if (r)
1657                         goto error_reserve;
1658
1659                 /* remove the original mem node and create a new one at the
1660                  * request position
1661                  */
1662                 bo = adev->fw_vram_usage.reserved_bo;
1663                 offset = ALIGN(offset, PAGE_SIZE);
1664                 for (i = 0; i < bo->placement.num_placement; ++i) {
1665                         bo->placements[i].fpfn = offset >> PAGE_SHIFT;
1666                         bo->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
1667                 }
1668
1669                 ttm_bo_mem_put(&bo->tbo, &bo->tbo.mem);
1670                 r = ttm_bo_mem_space(&bo->tbo, &bo->placement,
1671                                      &bo->tbo.mem, &ctx);
1672                 if (r)
1673                         goto error_pin;
1674
1675                 r = amdgpu_bo_pin_restricted(adev->fw_vram_usage.reserved_bo,
1676                         AMDGPU_GEM_DOMAIN_VRAM,
1677                         adev->fw_vram_usage.start_offset,
1678                         (adev->fw_vram_usage.start_offset +
1679                         adev->fw_vram_usage.size));
1680                 if (r)
1681                         goto error_pin;
1682                 r = amdgpu_bo_kmap(adev->fw_vram_usage.reserved_bo,
1683                         &adev->fw_vram_usage.va);
1684                 if (r)
1685                         goto error_kmap;
1686
1687                 amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
1688         }
1689         return r;
1690
1691 error_kmap:
1692         amdgpu_bo_unpin(adev->fw_vram_usage.reserved_bo);
1693 error_pin:
1694         amdgpu_bo_unreserve(adev->fw_vram_usage.reserved_bo);
1695 error_reserve:
1696         amdgpu_bo_unref(&adev->fw_vram_usage.reserved_bo);
1697 error_create:
1698         adev->fw_vram_usage.va = NULL;
1699         adev->fw_vram_usage.reserved_bo = NULL;
1700         return r;
1701 }
1702 /**
1703  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1704  * gtt/vram related fields.
1705  *
1706  * This initializes all of the memory space pools that the TTM layer
1707  * will need such as the GTT space (system memory mapped to the device),
1708  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1709  * can be mapped per VMID.
1710  */
1711 int amdgpu_ttm_init(struct amdgpu_device *adev)
1712 {
1713         uint64_t gtt_size;
1714         int r;
1715         u64 vis_vram_limit;
1716
1717         /* initialize global references for vram/gtt */
1718         r = amdgpu_ttm_global_init(adev);
1719         if (r) {
1720                 return r;
1721         }
1722         /* No others user of address space so set it to 0 */
1723         r = ttm_bo_device_init(&adev->mman.bdev,
1724                                adev->mman.bo_global_ref.ref.object,
1725                                &amdgpu_bo_driver,
1726                                adev->ddev->anon_inode->i_mapping,
1727                                DRM_FILE_PAGE_OFFSET,
1728                                adev->need_dma32);
1729         if (r) {
1730                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1731                 return r;
1732         }
1733         adev->mman.initialized = true;
1734
1735         /* We opt to avoid OOM on system pages allocations */
1736         adev->mman.bdev.no_retry = true;
1737
1738         /* Initialize VRAM pool with all of VRAM divided into pages */
1739         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_VRAM,
1740                                 adev->gmc.real_vram_size >> PAGE_SHIFT);
1741         if (r) {
1742                 DRM_ERROR("Failed initializing VRAM heap.\n");
1743                 return r;
1744         }
1745
1746         /* Reduce size of CPU-visible VRAM if requested */
1747         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1748         if (amdgpu_vis_vram_limit > 0 &&
1749             vis_vram_limit <= adev->gmc.visible_vram_size)
1750                 adev->gmc.visible_vram_size = vis_vram_limit;
1751
1752         /* Change the size here instead of the init above so only lpfn is affected */
1753         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1754 #ifdef CONFIG_64BIT
1755         adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1756                                                 adev->gmc.visible_vram_size);
1757 #endif
1758
1759         /*
1760          *The reserved vram for firmware must be pinned to the specified
1761          *place on the VRAM, so reserve it early.
1762          */
1763         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1764         if (r) {
1765                 return r;
1766         }
1767
1768         /* allocate memory as required for VGA
1769          * This is used for VGA emulation and pre-OS scanout buffers to
1770          * avoid display artifacts while transitioning between pre-OS
1771          * and driver.  */
1772         if (adev->gmc.stolen_size) {
1773                 r = amdgpu_bo_create_kernel(adev, adev->gmc.stolen_size, PAGE_SIZE,
1774                                             AMDGPU_GEM_DOMAIN_VRAM,
1775                                             &adev->stolen_vga_memory,
1776                                             NULL, NULL);
1777                 if (r)
1778                         return r;
1779         }
1780         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1781                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1782
1783         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1784          * or whatever the user passed on module init */
1785         if (amdgpu_gtt_size == -1) {
1786                 struct sysinfo si;
1787
1788                 si_meminfo(&si);
1789                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1790                                adev->gmc.mc_vram_size),
1791                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1792         }
1793         else
1794                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1795
1796         /* Initialize GTT memory pool */
1797         r = ttm_bo_init_mm(&adev->mman.bdev, TTM_PL_TT, gtt_size >> PAGE_SHIFT);
1798         if (r) {
1799                 DRM_ERROR("Failed initializing GTT heap.\n");
1800                 return r;
1801         }
1802         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1803                  (unsigned)(gtt_size / (1024 * 1024)));
1804
1805         /* Initialize various on-chip memory pools */
1806         adev->gds.mem.total_size = adev->gds.mem.total_size << AMDGPU_GDS_SHIFT;
1807         adev->gds.mem.gfx_partition_size = adev->gds.mem.gfx_partition_size << AMDGPU_GDS_SHIFT;
1808         adev->gds.mem.cs_partition_size = adev->gds.mem.cs_partition_size << AMDGPU_GDS_SHIFT;
1809         adev->gds.gws.total_size = adev->gds.gws.total_size << AMDGPU_GWS_SHIFT;
1810         adev->gds.gws.gfx_partition_size = adev->gds.gws.gfx_partition_size << AMDGPU_GWS_SHIFT;
1811         adev->gds.gws.cs_partition_size = adev->gds.gws.cs_partition_size << AMDGPU_GWS_SHIFT;
1812         adev->gds.oa.total_size = adev->gds.oa.total_size << AMDGPU_OA_SHIFT;
1813         adev->gds.oa.gfx_partition_size = adev->gds.oa.gfx_partition_size << AMDGPU_OA_SHIFT;
1814         adev->gds.oa.cs_partition_size = adev->gds.oa.cs_partition_size << AMDGPU_OA_SHIFT;
1815         /* GDS Memory */
1816         if (adev->gds.mem.total_size) {
1817                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GDS,
1818                                    adev->gds.mem.total_size >> PAGE_SHIFT);
1819                 if (r) {
1820                         DRM_ERROR("Failed initializing GDS heap.\n");
1821                         return r;
1822                 }
1823         }
1824
1825         /* GWS */
1826         if (adev->gds.gws.total_size) {
1827                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_GWS,
1828                                    adev->gds.gws.total_size >> PAGE_SHIFT);
1829                 if (r) {
1830                         DRM_ERROR("Failed initializing gws heap.\n");
1831                         return r;
1832                 }
1833         }
1834
1835         /* OA */
1836         if (adev->gds.oa.total_size) {
1837                 r = ttm_bo_init_mm(&adev->mman.bdev, AMDGPU_PL_OA,
1838                                    adev->gds.oa.total_size >> PAGE_SHIFT);
1839                 if (r) {
1840                         DRM_ERROR("Failed initializing oa heap.\n");
1841                         return r;
1842                 }
1843         }
1844
1845         /* Register debugfs entries for amdgpu_ttm */
1846         r = amdgpu_ttm_debugfs_init(adev);
1847         if (r) {
1848                 DRM_ERROR("Failed to init debugfs\n");
1849                 return r;
1850         }
1851         return 0;
1852 }
1853
1854 /**
1855  * amdgpu_ttm_late_init - Handle any late initialization for amdgpu_ttm
1856  */
1857 void amdgpu_ttm_late_init(struct amdgpu_device *adev)
1858 {
1859         /* return the VGA stolen memory (if any) back to VRAM */
1860         amdgpu_bo_free_kernel(&adev->stolen_vga_memory, NULL, NULL);
1861 }
1862
1863 /**
1864  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1865  */
1866 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1867 {
1868         if (!adev->mman.initialized)
1869                 return;
1870
1871         amdgpu_ttm_debugfs_fini(adev);
1872         amdgpu_ttm_fw_reserve_vram_fini(adev);
1873         if (adev->mman.aper_base_kaddr)
1874                 iounmap(adev->mman.aper_base_kaddr);
1875         adev->mman.aper_base_kaddr = NULL;
1876
1877         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_VRAM);
1878         ttm_bo_clean_mm(&adev->mman.bdev, TTM_PL_TT);
1879         if (adev->gds.mem.total_size)
1880                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GDS);
1881         if (adev->gds.gws.total_size)
1882                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_GWS);
1883         if (adev->gds.oa.total_size)
1884                 ttm_bo_clean_mm(&adev->mman.bdev, AMDGPU_PL_OA);
1885         ttm_bo_device_release(&adev->mman.bdev);
1886         amdgpu_ttm_global_fini(adev);
1887         adev->mman.initialized = false;
1888         DRM_INFO("amdgpu: ttm finalized\n");
1889 }
1890
1891 /**
1892  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1893  *
1894  * @adev: amdgpu_device pointer
1895  * @enable: true when we can use buffer functions.
1896  *
1897  * Enable/disable use of buffer functions during suspend/resume. This should
1898  * only be called at bootup or when userspace isn't running.
1899  */
1900 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1901 {
1902         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[TTM_PL_VRAM];
1903         uint64_t size;
1904         int r;
1905
1906         if (!adev->mman.initialized || adev->in_gpu_reset ||
1907             adev->mman.buffer_funcs_enabled == enable)
1908                 return;
1909
1910         if (enable) {
1911                 struct amdgpu_ring *ring;
1912                 struct drm_sched_rq *rq;
1913
1914                 ring = adev->mman.buffer_funcs_ring;
1915                 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
1916                 r = drm_sched_entity_init(&adev->mman.entity, &rq, 1, NULL);
1917                 if (r) {
1918                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1919                                   r);
1920                         return;
1921                 }
1922         } else {
1923                 drm_sched_entity_destroy(&adev->mman.entity);
1924                 dma_fence_put(man->move);
1925                 man->move = NULL;
1926         }
1927
1928         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1929         if (enable)
1930                 size = adev->gmc.real_vram_size;
1931         else
1932                 size = adev->gmc.visible_vram_size;
1933         man->size = size >> PAGE_SHIFT;
1934         adev->mman.buffer_funcs_enabled = enable;
1935 }
1936
1937 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1938 {
1939         struct drm_file *file_priv;
1940         struct amdgpu_device *adev;
1941
1942         if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET))
1943                 return -EINVAL;
1944
1945         file_priv = filp->private_data;
1946         adev = file_priv->minor->dev->dev_private;
1947         if (adev == NULL)
1948                 return -EINVAL;
1949
1950         return ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1951 }
1952
1953 static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
1954                              struct ttm_mem_reg *mem, unsigned num_pages,
1955                              uint64_t offset, unsigned window,
1956                              struct amdgpu_ring *ring,
1957                              uint64_t *addr)
1958 {
1959         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
1960         struct amdgpu_device *adev = ring->adev;
1961         struct ttm_tt *ttm = bo->ttm;
1962         struct amdgpu_job *job;
1963         unsigned num_dw, num_bytes;
1964         dma_addr_t *dma_address;
1965         struct dma_fence *fence;
1966         uint64_t src_addr, dst_addr;
1967         uint64_t flags;
1968         int r;
1969
1970         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
1971                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
1972
1973         *addr = adev->gmc.gart_start;
1974         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
1975                 AMDGPU_GPU_PAGE_SIZE;
1976
1977         num_dw = adev->mman.buffer_funcs->copy_num_dw;
1978         while (num_dw & 0x7)
1979                 num_dw++;
1980
1981         num_bytes = num_pages * 8;
1982
1983         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes, &job);
1984         if (r)
1985                 return r;
1986
1987         src_addr = num_dw * 4;
1988         src_addr += job->ibs[0].gpu_addr;
1989
1990         dst_addr = adev->gart.table_addr;
1991         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
1992         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
1993                                 dst_addr, num_bytes);
1994
1995         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1996         WARN_ON(job->ibs[0].length_dw > num_dw);
1997
1998         dma_address = &gtt->ttm.dma_address[offset >> PAGE_SHIFT];
1999         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, mem);
2000         r = amdgpu_gart_map(adev, 0, num_pages, dma_address, flags,
2001                             &job->ibs[0].ptr[num_dw]);
2002         if (r)
2003                 goto error_free;
2004
2005         r = amdgpu_job_submit(job, &adev->mman.entity,
2006                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
2007         if (r)
2008                 goto error_free;
2009
2010         dma_fence_put(fence);
2011
2012         return r;
2013
2014 error_free:
2015         amdgpu_job_free(job);
2016         return r;
2017 }
2018
2019 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
2020                        uint64_t dst_offset, uint32_t byte_count,
2021                        struct reservation_object *resv,
2022                        struct dma_fence **fence, bool direct_submit,
2023                        bool vm_needs_flush)
2024 {
2025         struct amdgpu_device *adev = ring->adev;
2026         struct amdgpu_job *job;
2027
2028         uint32_t max_bytes;
2029         unsigned num_loops, num_dw;
2030         unsigned i;
2031         int r;
2032
2033         if (direct_submit && !ring->ready) {
2034                 DRM_ERROR("Trying to move memory with ring turned off.\n");
2035                 return -EINVAL;
2036         }
2037
2038         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
2039         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
2040         num_dw = num_loops * adev->mman.buffer_funcs->copy_num_dw;
2041
2042         /* for IB padding */
2043         while (num_dw & 0x7)
2044                 num_dw++;
2045
2046         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
2047         if (r)
2048                 return r;
2049
2050         job->vm_needs_flush = vm_needs_flush;
2051         if (resv) {
2052                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2053                                      AMDGPU_FENCE_OWNER_UNDEFINED,
2054                                      false);
2055                 if (r) {
2056                         DRM_ERROR("sync failed (%d).\n", r);
2057                         goto error_free;
2058                 }
2059         }
2060
2061         for (i = 0; i < num_loops; i++) {
2062                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2063
2064                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
2065                                         dst_offset, cur_size_in_bytes);
2066
2067                 src_offset += cur_size_in_bytes;
2068                 dst_offset += cur_size_in_bytes;
2069                 byte_count -= cur_size_in_bytes;
2070         }
2071
2072         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2073         WARN_ON(job->ibs[0].length_dw > num_dw);
2074         if (direct_submit)
2075                 r = amdgpu_job_submit_direct(job, ring, fence);
2076         else
2077                 r = amdgpu_job_submit(job, &adev->mman.entity,
2078                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2079         if (r)
2080                 goto error_free;
2081
2082         return r;
2083
2084 error_free:
2085         amdgpu_job_free(job);
2086         DRM_ERROR("Error scheduling IBs (%d)\n", r);
2087         return r;
2088 }
2089
2090 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
2091                        uint32_t src_data,
2092                        struct reservation_object *resv,
2093                        struct dma_fence **fence)
2094 {
2095         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
2096         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
2097         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
2098
2099         struct drm_mm_node *mm_node;
2100         unsigned long num_pages;
2101         unsigned int num_loops, num_dw;
2102
2103         struct amdgpu_job *job;
2104         int r;
2105
2106         if (!adev->mman.buffer_funcs_enabled) {
2107                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
2108                 return -EINVAL;
2109         }
2110
2111         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
2112                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
2113                 if (r)
2114                         return r;
2115         }
2116
2117         num_pages = bo->tbo.num_pages;
2118         mm_node = bo->tbo.mem.mm_node;
2119         num_loops = 0;
2120         while (num_pages) {
2121                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
2122
2123                 num_loops += DIV_ROUND_UP(byte_count, max_bytes);
2124                 num_pages -= mm_node->size;
2125                 ++mm_node;
2126         }
2127         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
2128
2129         /* for IB padding */
2130         num_dw += 64;
2131
2132         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, &job);
2133         if (r)
2134                 return r;
2135
2136         if (resv) {
2137                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2138                                      AMDGPU_FENCE_OWNER_UNDEFINED, false);
2139                 if (r) {
2140                         DRM_ERROR("sync failed (%d).\n", r);
2141                         goto error_free;
2142                 }
2143         }
2144
2145         num_pages = bo->tbo.num_pages;
2146         mm_node = bo->tbo.mem.mm_node;
2147
2148         while (num_pages) {
2149                 uint32_t byte_count = mm_node->size << PAGE_SHIFT;
2150                 uint64_t dst_addr;
2151
2152                 dst_addr = amdgpu_mm_node_addr(&bo->tbo, mm_node, &bo->tbo.mem);
2153                 while (byte_count) {
2154                         uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
2155
2156                         amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data,
2157                                                 dst_addr, cur_size_in_bytes);
2158
2159                         dst_addr += cur_size_in_bytes;
2160                         byte_count -= cur_size_in_bytes;
2161                 }
2162
2163                 num_pages -= mm_node->size;
2164                 ++mm_node;
2165         }
2166
2167         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2168         WARN_ON(job->ibs[0].length_dw > num_dw);
2169         r = amdgpu_job_submit(job, &adev->mman.entity,
2170                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2171         if (r)
2172                 goto error_free;
2173
2174         return 0;
2175
2176 error_free:
2177         amdgpu_job_free(job);
2178         return r;
2179 }
2180
2181 #if defined(CONFIG_DEBUG_FS)
2182
2183 static int amdgpu_mm_dump_table(struct seq_file *m, void *data)
2184 {
2185         struct drm_info_node *node = (struct drm_info_node *)m->private;
2186         unsigned ttm_pl = *(int *)node->info_ent->data;
2187         struct drm_device *dev = node->minor->dev;
2188         struct amdgpu_device *adev = dev->dev_private;
2189         struct ttm_mem_type_manager *man = &adev->mman.bdev.man[ttm_pl];
2190         struct drm_printer p = drm_seq_file_printer(m);
2191
2192         man->func->debug(man, &p);
2193         return 0;
2194 }
2195
2196 static int ttm_pl_vram = TTM_PL_VRAM;
2197 static int ttm_pl_tt = TTM_PL_TT;
2198
2199 static const struct drm_info_list amdgpu_ttm_debugfs_list[] = {
2200         {"amdgpu_vram_mm", amdgpu_mm_dump_table, 0, &ttm_pl_vram},
2201         {"amdgpu_gtt_mm", amdgpu_mm_dump_table, 0, &ttm_pl_tt},
2202         {"ttm_page_pool", ttm_page_alloc_debugfs, 0, NULL},
2203 #ifdef CONFIG_SWIOTLB
2204         {"ttm_dma_page_pool", ttm_dma_page_alloc_debugfs, 0, NULL}
2205 #endif
2206 };
2207
2208 /**
2209  * amdgpu_ttm_vram_read - Linear read access to VRAM
2210  *
2211  * Accesses VRAM via MMIO for debugging purposes.
2212  */
2213 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2214                                     size_t size, loff_t *pos)
2215 {
2216         struct amdgpu_device *adev = file_inode(f)->i_private;
2217         ssize_t result = 0;
2218         int r;
2219
2220         if (size & 0x3 || *pos & 0x3)
2221                 return -EINVAL;
2222
2223         if (*pos >= adev->gmc.mc_vram_size)
2224                 return -ENXIO;
2225
2226         while (size) {
2227                 unsigned long flags;
2228                 uint32_t value;
2229
2230                 if (*pos >= adev->gmc.mc_vram_size)
2231                         return result;
2232
2233                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2234                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2235                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2236                 value = RREG32_NO_KIQ(mmMM_DATA);
2237                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2238
2239                 r = put_user(value, (uint32_t *)buf);
2240                 if (r)
2241                         return r;
2242
2243                 result += 4;
2244                 buf += 4;
2245                 *pos += 4;
2246                 size -= 4;
2247         }
2248
2249         return result;
2250 }
2251
2252 /**
2253  * amdgpu_ttm_vram_write - Linear write access to VRAM
2254  *
2255  * Accesses VRAM via MMIO for debugging purposes.
2256  */
2257 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2258                                     size_t size, loff_t *pos)
2259 {
2260         struct amdgpu_device *adev = file_inode(f)->i_private;
2261         ssize_t result = 0;
2262         int r;
2263
2264         if (size & 0x3 || *pos & 0x3)
2265                 return -EINVAL;
2266
2267         if (*pos >= adev->gmc.mc_vram_size)
2268                 return -ENXIO;
2269
2270         while (size) {
2271                 unsigned long flags;
2272                 uint32_t value;
2273
2274                 if (*pos >= adev->gmc.mc_vram_size)
2275                         return result;
2276
2277                 r = get_user(value, (uint32_t *)buf);
2278                 if (r)
2279                         return r;
2280
2281                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2282                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2283                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2284                 WREG32_NO_KIQ(mmMM_DATA, value);
2285                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2286
2287                 result += 4;
2288                 buf += 4;
2289                 *pos += 4;
2290                 size -= 4;
2291         }
2292
2293         return result;
2294 }
2295
2296 static const struct file_operations amdgpu_ttm_vram_fops = {
2297         .owner = THIS_MODULE,
2298         .read = amdgpu_ttm_vram_read,
2299         .write = amdgpu_ttm_vram_write,
2300         .llseek = default_llseek,
2301 };
2302
2303 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2304
2305 /**
2306  * amdgpu_ttm_gtt_read - Linear read access to GTT memory
2307  */
2308 static ssize_t amdgpu_ttm_gtt_read(struct file *f, char __user *buf,
2309                                    size_t size, loff_t *pos)
2310 {
2311         struct amdgpu_device *adev = file_inode(f)->i_private;
2312         ssize_t result = 0;
2313         int r;
2314
2315         while (size) {
2316                 loff_t p = *pos / PAGE_SIZE;
2317                 unsigned off = *pos & ~PAGE_MASK;
2318                 size_t cur_size = min_t(size_t, size, PAGE_SIZE - off);
2319                 struct page *page;
2320                 void *ptr;
2321
2322                 if (p >= adev->gart.num_cpu_pages)
2323                         return result;
2324
2325                 page = adev->gart.pages[p];
2326                 if (page) {
2327                         ptr = kmap(page);
2328                         ptr += off;
2329
2330                         r = copy_to_user(buf, ptr, cur_size);
2331                         kunmap(adev->gart.pages[p]);
2332                 } else
2333                         r = clear_user(buf, cur_size);
2334
2335                 if (r)
2336                         return -EFAULT;
2337
2338                 result += cur_size;
2339                 buf += cur_size;
2340                 *pos += cur_size;
2341                 size -= cur_size;
2342         }
2343
2344         return result;
2345 }
2346
2347 static const struct file_operations amdgpu_ttm_gtt_fops = {
2348         .owner = THIS_MODULE,
2349         .read = amdgpu_ttm_gtt_read,
2350         .llseek = default_llseek
2351 };
2352
2353 #endif
2354
2355 /**
2356  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2357  *
2358  * This function is used to read memory that has been mapped to the
2359  * GPU and the known addresses are not physical addresses but instead
2360  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2361  */
2362 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2363                                  size_t size, loff_t *pos)
2364 {
2365         struct amdgpu_device *adev = file_inode(f)->i_private;
2366         struct iommu_domain *dom;
2367         ssize_t result = 0;
2368         int r;
2369
2370         /* retrieve the IOMMU domain if any for this device */
2371         dom = iommu_get_domain_for_dev(adev->dev);
2372
2373         while (size) {
2374                 phys_addr_t addr = *pos & PAGE_MASK;
2375                 loff_t off = *pos & ~PAGE_MASK;
2376                 size_t bytes = PAGE_SIZE - off;
2377                 unsigned long pfn;
2378                 struct page *p;
2379                 void *ptr;
2380
2381                 bytes = bytes < size ? bytes : size;
2382
2383                 /* Translate the bus address to a physical address.  If
2384                  * the domain is NULL it means there is no IOMMU active
2385                  * and the address translation is the identity
2386                  */
2387                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2388
2389                 pfn = addr >> PAGE_SHIFT;
2390                 if (!pfn_valid(pfn))
2391                         return -EPERM;
2392
2393                 p = pfn_to_page(pfn);
2394                 if (p->mapping != adev->mman.bdev.dev_mapping)
2395                         return -EPERM;
2396
2397                 ptr = kmap(p);
2398                 r = copy_to_user(buf, ptr + off, bytes);
2399                 kunmap(p);
2400                 if (r)
2401                         return -EFAULT;
2402
2403                 size -= bytes;
2404                 *pos += bytes;
2405                 result += bytes;
2406         }
2407
2408         return result;
2409 }
2410
2411 /**
2412  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2413  *
2414  * This function is used to write memory that has been mapped to the
2415  * GPU and the known addresses are not physical addresses but instead
2416  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2417  */
2418 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2419                                  size_t size, loff_t *pos)
2420 {
2421         struct amdgpu_device *adev = file_inode(f)->i_private;
2422         struct iommu_domain *dom;
2423         ssize_t result = 0;
2424         int r;
2425
2426         dom = iommu_get_domain_for_dev(adev->dev);
2427
2428         while (size) {
2429                 phys_addr_t addr = *pos & PAGE_MASK;
2430                 loff_t off = *pos & ~PAGE_MASK;
2431                 size_t bytes = PAGE_SIZE - off;
2432                 unsigned long pfn;
2433                 struct page *p;
2434                 void *ptr;
2435
2436                 bytes = bytes < size ? bytes : size;
2437
2438                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2439
2440                 pfn = addr >> PAGE_SHIFT;
2441                 if (!pfn_valid(pfn))
2442                         return -EPERM;
2443
2444                 p = pfn_to_page(pfn);
2445                 if (p->mapping != adev->mman.bdev.dev_mapping)
2446                         return -EPERM;
2447
2448                 ptr = kmap(p);
2449                 r = copy_from_user(ptr + off, buf, bytes);
2450                 kunmap(p);
2451                 if (r)
2452                         return -EFAULT;
2453
2454                 size -= bytes;
2455                 *pos += bytes;
2456                 result += bytes;
2457         }
2458
2459         return result;
2460 }
2461
2462 static const struct file_operations amdgpu_ttm_iomem_fops = {
2463         .owner = THIS_MODULE,
2464         .read = amdgpu_iomem_read,
2465         .write = amdgpu_iomem_write,
2466         .llseek = default_llseek
2467 };
2468
2469 static const struct {
2470         char *name;
2471         const struct file_operations *fops;
2472         int domain;
2473 } ttm_debugfs_entries[] = {
2474         { "amdgpu_vram", &amdgpu_ttm_vram_fops, TTM_PL_VRAM },
2475 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
2476         { "amdgpu_gtt", &amdgpu_ttm_gtt_fops, TTM_PL_TT },
2477 #endif
2478         { "amdgpu_iomem", &amdgpu_ttm_iomem_fops, TTM_PL_SYSTEM },
2479 };
2480
2481 #endif
2482
2483 static int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2484 {
2485 #if defined(CONFIG_DEBUG_FS)
2486         unsigned count;
2487
2488         struct drm_minor *minor = adev->ddev->primary;
2489         struct dentry *ent, *root = minor->debugfs_root;
2490
2491         for (count = 0; count < ARRAY_SIZE(ttm_debugfs_entries); count++) {
2492                 ent = debugfs_create_file(
2493                                 ttm_debugfs_entries[count].name,
2494                                 S_IFREG | S_IRUGO, root,
2495                                 adev,
2496                                 ttm_debugfs_entries[count].fops);
2497                 if (IS_ERR(ent))
2498                         return PTR_ERR(ent);
2499                 if (ttm_debugfs_entries[count].domain == TTM_PL_VRAM)
2500                         i_size_write(ent->d_inode, adev->gmc.mc_vram_size);
2501                 else if (ttm_debugfs_entries[count].domain == TTM_PL_TT)
2502                         i_size_write(ent->d_inode, adev->gmc.gart_size);
2503                 adev->mman.debugfs_entries[count] = ent;
2504         }
2505
2506         count = ARRAY_SIZE(amdgpu_ttm_debugfs_list);
2507
2508 #ifdef CONFIG_SWIOTLB
2509         if (!(adev->need_swiotlb && swiotlb_nr_tbl()))
2510                 --count;
2511 #endif
2512
2513         return amdgpu_debugfs_add_files(adev, amdgpu_ttm_debugfs_list, count);
2514 #else
2515         return 0;
2516 #endif
2517 }
2518
2519 static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
2520 {
2521 #if defined(CONFIG_DEBUG_FS)
2522         unsigned i;
2523
2524         for (i = 0; i < ARRAY_SIZE(ttm_debugfs_entries); i++)
2525                 debugfs_remove(adev->mman.debugfs_entries[i]);
2526 #endif
2527 }