drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  *
  23  */
  24 #include <linux/list.h>
  25 #include <linux/slab.h>
  26 #include <drm/drmP.h>
  27 #include <linux/firmware.h>
  28 #include <drm/amdgpu_drm.h>
  29 #include "amdgpu.h"
  30 #include "atom.h"
  31 #include "amdgpu_ucode.h"
  32
  33 struct amdgpu_cgs_device {
  34         struct cgs_device base;
  35         struct amdgpu_device *adev;
  36 };
  37
  38 #define CGS_FUNC_ADEV                                                   \
  39         struct amdgpu_device *adev =                                    \
  40                 ((struct amdgpu_cgs_device *)cgs_device)->adev
  41
  42
  43 static uint32_t amdgpu_cgs_read_register(struct cgs_device *cgs_device, unsigned offset)
  44 {
  45         CGS_FUNC_ADEV;
  46         return RREG32(offset);
  47 }
  48
  49 static void amdgpu_cgs_write_register(struct cgs_device *cgs_device, unsigned offset,
  50                                       uint32_t value)
  51 {
  52         CGS_FUNC_ADEV;
  53         WREG32(offset, value);
  54 }
  55
  56 static uint32_t amdgpu_cgs_read_ind_register(struct cgs_device *cgs_device,
  57                                              enum cgs_ind_reg space,
  58                                              unsigned index)
  59 {
  60         CGS_FUNC_ADEV;
  61         switch (space) {
  62         case CGS_IND_REG__MMIO:
  63                 return RREG32_IDX(index);
  64         case CGS_IND_REG__PCIE:
  65                 return RREG32_PCIE(index);
  66         case CGS_IND_REG__SMC:
  67                 return RREG32_SMC(index);
  68         case CGS_IND_REG__UVD_CTX:
  69                 return RREG32_UVD_CTX(index);
  70         case CGS_IND_REG__DIDT:
  71                 return RREG32_DIDT(index);
  72         case CGS_IND_REG_GC_CAC:
  73                 return RREG32_GC_CAC(index);
  74         case CGS_IND_REG_SE_CAC:
  75                 return RREG32_SE_CAC(index);
  76         case CGS_IND_REG__AUDIO_ENDPT:
  77                 DRM_ERROR("audio endpt register access not implemented.\n");
  78                 return 0;
  79         }
  80         WARN(1, "Invalid indirect register space");
  81         return 0;
  82 }
  83
  84 static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device,
  85                                           enum cgs_ind_reg space,
  86                                           unsigned index, uint32_t value)
  87 {
  88         CGS_FUNC_ADEV;
  89         switch (space) {
  90         case CGS_IND_REG__MMIO:
  91                 return WREG32_IDX(index, value);
  92         case CGS_IND_REG__PCIE:
  93                 return WREG32_PCIE(index, value);
  94         case CGS_IND_REG__SMC:
  95                 return WREG32_SMC(index, value);
  96         case CGS_IND_REG__UVD_CTX:
  97                 return WREG32_UVD_CTX(index, value);
  98         case CGS_IND_REG__DIDT:
  99                 return WREG32_DIDT(index, value);
 100         case CGS_IND_REG_GC_CAC:
 101                 return WREG32_GC_CAC(index, value);
 102         case CGS_IND_REG_SE_CAC:
 103                 return WREG32_SE_CAC(index, value);
 104         case CGS_IND_REG__AUDIO_ENDPT:
 105                 DRM_ERROR("audio endpt register access not implemented.\n");
 106                 return;
 107         }
 108         WARN(1, "Invalid indirect register space");
 109 }
 110
 111 static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
 112 {
 113         CGS_FUNC_ADEV;
 114         enum AMDGPU_UCODE_ID result = AMDGPU_UCODE_ID_MAXIMUM;
 115
 116         switch (fw_type) {
 117         case CGS_UCODE_ID_SDMA0:
 118                 result = AMDGPU_UCODE_ID_SDMA0;
 119                 break;
 120         case CGS_UCODE_ID_SDMA1:
 121                 result = AMDGPU_UCODE_ID_SDMA1;
 122                 break;
 123         case CGS_UCODE_ID_CP_CE:
 124                 result = AMDGPU_UCODE_ID_CP_CE;
 125                 break;
 126         case CGS_UCODE_ID_CP_PFP:
 127                 result = AMDGPU_UCODE_ID_CP_PFP;
 128                 break;
 129         case CGS_UCODE_ID_CP_ME:
 130                 result = AMDGPU_UCODE_ID_CP_ME;
 131                 break;
 132         case CGS_UCODE_ID_CP_MEC:
 133         case CGS_UCODE_ID_CP_MEC_JT1:
 134                 result = AMDGPU_UCODE_ID_CP_MEC1;
 135                 break;
 136         case CGS_UCODE_ID_CP_MEC_JT2:
 137                 /* for VI. JT2 should be the same as JT1, because:
 138                         1, MEC2 and MEC1 use exactly same FW.
 139                         2, JT2 is not pached but JT1 is.
 140                 */
 141                 if (adev->asic_type >= CHIP_TOPAZ)
 142                         result = AMDGPU_UCODE_ID_CP_MEC1;
 143                 else
 144                         result = AMDGPU_UCODE_ID_CP_MEC2;
 145                 break;
 146         case CGS_UCODE_ID_RLC_G:
 147                 result = AMDGPU_UCODE_ID_RLC_G;
 148                 break;
 149         case CGS_UCODE_ID_STORAGE:
 150                 result = AMDGPU_UCODE_ID_STORAGE;
 151                 break;
 152         default:
 153                 DRM_ERROR("Firmware type not supported\n");
 154         }
 155         return result;
 156 }
 157
 158 static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device,
 159                                         enum cgs_ucode_id type)
 160 {
 161         CGS_FUNC_ADEV;
 162         uint16_t fw_version = 0;
 163
 164         switch (type) {
 165                 case CGS_UCODE_ID_SDMA0:
 166                         fw_version = adev->sdma.instance[0].fw_version;
 167                         break;
 168                 case CGS_UCODE_ID_SDMA1:
 169                         fw_version = adev->sdma.instance[1].fw_version;
 170                         break;
 171                 case CGS_UCODE_ID_CP_CE:
 172                         fw_version = adev->gfx.ce_fw_version;
 173                         break;
 174                 case CGS_UCODE_ID_CP_PFP:
 175                         fw_version = adev->gfx.pfp_fw_version;
 176                         break;
 177                 case CGS_UCODE_ID_CP_ME:
 178                         fw_version = adev->gfx.me_fw_version;
 179                         break;
 180                 case CGS_UCODE_ID_CP_MEC:
 181                         fw_version = adev->gfx.mec_fw_version;
 182                         break;
 183                 case CGS_UCODE_ID_CP_MEC_JT1:
 184                         fw_version = adev->gfx.mec_fw_version;
 185                         break;
 186                 case CGS_UCODE_ID_CP_MEC_JT2:
 187                         fw_version = adev->gfx.mec_fw_version;
 188                         break;
 189                 case CGS_UCODE_ID_RLC_G:
 190                         fw_version = adev->gfx.rlc_fw_version;
 191                         break;
 192                 case CGS_UCODE_ID_STORAGE:
 193                         break;
 194                 default:
 195                         DRM_ERROR("firmware type %d do not have version\n", type);
 196                         break;
 197         }
 198         return fw_version;
 199 }
 200
 201 static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
 202                                         enum cgs_ucode_id type,
 203                                         struct cgs_firmware_info *info)
 204 {
 205         CGS_FUNC_ADEV;
 206
 207         if ((CGS_UCODE_ID_SMU != type) && (CGS_UCODE_ID_SMU_SK != type)) {
 208                 uint64_t gpu_addr;
 209                 uint32_t data_size;
 210                 const struct gfx_firmware_header_v1_0 *header;
 211                 enum AMDGPU_UCODE_ID id;
 212                 struct amdgpu_firmware_info *ucode;
 213
 214                 id = fw_type_convert(cgs_device, type);
 215                 ucode = &adev->firmware.ucode[id];
 216                 if (ucode->fw == NULL)
 217                         return -EINVAL;
 218
 219                 gpu_addr  = ucode->mc_addr;
 220                 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data;
 221                 data_size = le32_to_cpu(header->header.ucode_size_bytes);
 222
 223                 if ((type == CGS_UCODE_ID_CP_MEC_JT1) ||
 224                     (type == CGS_UCODE_ID_CP_MEC_JT2)) {
 225                         gpu_addr += ALIGN(le32_to_cpu(header->header.ucode_size_bytes), PAGE_SIZE);
 226                         data_size = le32_to_cpu(header->jt_size) << 2;
 227                 }
 228
 229                 info->kptr = ucode->kaddr;
 230                 info->image_size = data_size;
 231                 info->mc_addr = gpu_addr;
 232                 info->version = (uint16_t)le32_to_cpu(header->header.ucode_version);
 233
 234                 if (CGS_UCODE_ID_CP_MEC == type)
 235                         info->image_size = le32_to_cpu(header->jt_offset) << 2;
 236
 237                 info->fw_version = amdgpu_get_firmware_version(cgs_device, type);
 238                 info->feature_version = (uint16_t)le32_to_cpu(header->ucode_feature_version);
 239         } else {
 240                 char fw_name[30] = {0};
 241                 int err = 0;
 242                 uint32_t ucode_size;
 243                 uint32_t ucode_start_address;
 244                 const uint8_t *src;
 245                 const struct smc_firmware_header_v1_0 *hdr;
 246                 const struct common_firmware_header *header;
 247                 struct amdgpu_firmware_info *ucode = NULL;
 248
 249                 if (!adev->pm.fw) {
 250                         switch (adev->asic_type) {
 251                         case CHIP_TAHITI:
 252                                 strcpy(fw_name, "radeon/tahiti_smc.bin");
 253                                 break;
 254                         case CHIP_PITCAIRN:
 255                                 if ((adev->pdev->revision == 0x81) &&
 256                                     ((adev->pdev->device == 0x6810) ||
 257                                     (adev->pdev->device == 0x6811))) {
 258                                         info->is_kicker = true;
 259                                         strcpy(fw_name, "radeon/pitcairn_k_smc.bin");
 260                                 } else {
 261                                         strcpy(fw_name, "radeon/pitcairn_smc.bin");
 262                                 }
 263                                 break;
 264                         case CHIP_VERDE:
 265                                 if (((adev->pdev->device == 0x6820) &&
 266                                         ((adev->pdev->revision == 0x81) ||
 267                                         (adev->pdev->revision == 0x83))) ||
 268                                     ((adev->pdev->device == 0x6821) &&
 269                                         ((adev->pdev->revision == 0x83) ||
 270                                         (adev->pdev->revision == 0x87))) ||
 271                                     ((adev->pdev->revision == 0x87) &&
 272                                         ((adev->pdev->device == 0x6823) ||
 273                                         (adev->pdev->device == 0x682b)))) {
 274                                         info->is_kicker = true;
 275                                         strcpy(fw_name, "radeon/verde_k_smc.bin");
 276                                 } else {
 277                                         strcpy(fw_name, "radeon/verde_smc.bin");
 278                                 }
 279                                 break;
 280                         case CHIP_OLAND:
 281                                 if (((adev->pdev->revision == 0x81) &&
 282                                         ((adev->pdev->device == 0x6600) ||
 283                                         (adev->pdev->device == 0x6604) ||
 284                                         (adev->pdev->device == 0x6605) ||
 285                                         (adev->pdev->device == 0x6610))) ||
 286                                     ((adev->pdev->revision == 0x83) &&
 287                                         (adev->pdev->device == 0x6610))) {
 288                                         info->is_kicker = true;
 289                                         strcpy(fw_name, "radeon/oland_k_smc.bin");
 290                                 } else {
 291                                         strcpy(fw_name, "radeon/oland_smc.bin");
 292                                 }
 293                                 break;
 294                         case CHIP_HAINAN:
 295                                 if (((adev->pdev->revision == 0x81) &&
 296                                         (adev->pdev->device == 0x6660)) ||
 297                                     ((adev->pdev->revision == 0x83) &&
 298                                         ((adev->pdev->device == 0x6660) ||
 299                                         (adev->pdev->device == 0x6663) ||
 300                                         (adev->pdev->device == 0x6665) ||
 301                                          (adev->pdev->device == 0x6667)))) {
 302                                         info->is_kicker = true;
 303                                         strcpy(fw_name, "radeon/hainan_k_smc.bin");
 304                                 } else if ((adev->pdev->revision == 0xc3) &&
 305                                          (adev->pdev->device == 0x6665)) {
 306                                         info->is_kicker = true;
 307                                         strcpy(fw_name, "radeon/banks_k_2_smc.bin");
 308                                 } else {
 309                                         strcpy(fw_name, "radeon/hainan_smc.bin");
 310                                 }
 311                                 break;
 312                         case CHIP_BONAIRE:
 313                                 if ((adev->pdev->revision == 0x80) ||
 314                                         (adev->pdev->revision == 0x81) ||
 315                                         (adev->pdev->device == 0x665f)) {
 316                                         info->is_kicker = true;
 317                                         strcpy(fw_name, "amdgpu/bonaire_k_smc.bin");
 318                                 } else {
 319                                         strcpy(fw_name, "amdgpu/bonaire_smc.bin");
 320                                 }
 321                                 break;
 322                         case CHIP_HAWAII:
 323                                 if (adev->pdev->revision == 0x80) {
 324                                         info->is_kicker = true;
 325                                         strcpy(fw_name, "amdgpu/hawaii_k_smc.bin");
 326                                 } else {
 327                                         strcpy(fw_name, "amdgpu/hawaii_smc.bin");
 328                                 }
 329                                 break;
 330                         case CHIP_TOPAZ:
 331                                 if (((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x81)) ||
 332                                     ((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x83)) ||
 333                                     ((adev->pdev->device == 0x6907) && (adev->pdev->revision == 0x87))) {
 334                                         info->is_kicker = true;
 335                                         strcpy(fw_name, "amdgpu/topaz_k_smc.bin");
 336                                 } else
 337                                         strcpy(fw_name, "amdgpu/topaz_smc.bin");
 338                                 break;
 339                         case CHIP_TONGA:
 340                                 if (((adev->pdev->device == 0x6939) && (adev->pdev->revision == 0xf1)) ||
 341                                     ((adev->pdev->device == 0x6938) && (adev->pdev->revision == 0xf1))) {
 342                                         info->is_kicker = true;
 343                                         strcpy(fw_name, "amdgpu/tonga_k_smc.bin");
 344                                 } else
 345                                         strcpy(fw_name, "amdgpu/tonga_smc.bin");
 346                                 break;
 347                         case CHIP_FIJI:
 348                                 strcpy(fw_name, "amdgpu/fiji_smc.bin");
 349                                 break;
 350                         case CHIP_POLARIS11:
 351                                 if (type == CGS_UCODE_ID_SMU) {
 352                                         if (((adev->pdev->device == 0x67ef) &&
 353                                              ((adev->pdev->revision == 0xe0) ||
 354                                               (adev->pdev->revision == 0xe2) ||
 355                                               (adev->pdev->revision == 0xe5))) ||
 356                                             ((adev->pdev->device == 0x67ff) &&
 357                                              ((adev->pdev->revision == 0xcf) ||
 358                                               (adev->pdev->revision == 0xef) ||
 359                                               (adev->pdev->revision == 0xff)))) {
 360                                                 info->is_kicker = true;
 361                                                 strcpy(fw_name, "amdgpu/polaris11_k_smc.bin");
 362                                         } else
 363                                                 strcpy(fw_name, "amdgpu/polaris11_smc.bin");
 364                                 } else if (type == CGS_UCODE_ID_SMU_SK) {
 365                                         strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin");
 366                                 }
 367                                 break;
 368                         case CHIP_POLARIS10:
 369                                 if (type == CGS_UCODE_ID_SMU) {
 370                                         if ((adev->pdev->device == 0x67df) &&
 371                                             ((adev->pdev->revision == 0xe0) ||
 372                                              (adev->pdev->revision == 0xe3) ||
 373                                              (adev->pdev->revision == 0xe4) ||
 374                                              (adev->pdev->revision == 0xe5) ||
 375                                              (adev->pdev->revision == 0xe7) ||
 376                                              (adev->pdev->revision == 0xef))) {
 377                                                 info->is_kicker = true;
 378                                                 strcpy(fw_name, "amdgpu/polaris10_k_smc.bin");
 379                                         } else
 380                                                 strcpy(fw_name, "amdgpu/polaris10_smc.bin");
 381                                 } else if (type == CGS_UCODE_ID_SMU_SK) {
 382                                         strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin");
 383                                 }
 384                                 break;
 385                         case CHIP_POLARIS12:
 386                                 strcpy(fw_name, "amdgpu/polaris12_smc.bin");
 387                                 break;
 388                         case CHIP_VEGAM:
 389                                 strcpy(fw_name, "amdgpu/vegam_smc.bin");
 390                                 break;
 391                         case CHIP_VEGA10:
 392                                 if ((adev->pdev->device == 0x687f) &&
 393                                         ((adev->pdev->revision == 0xc0) ||
 394                                         (adev->pdev->revision == 0xc1) ||
 395                                         (adev->pdev->revision == 0xc3)))
 396                                         strcpy(fw_name, "amdgpu/vega10_acg_smc.bin");
 397                                 else
 398                                         strcpy(fw_name, "amdgpu/vega10_smc.bin");
 399                                 break;
 400                         case CHIP_VEGA12:
 401                                 strcpy(fw_name, "amdgpu/vega12_smc.bin");
 402                                 break;
 403                         case CHIP_VEGA20:
 404                                 strcpy(fw_name, "amdgpu/vega20_smc.bin");
 405                                 break;
 406                         default:
 407                                 DRM_ERROR("SMC firmware not supported\n");
 408                                 return -EINVAL;
 409                         }
 410
 411                         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
 412                         if (err) {
 413                                 DRM_ERROR("Failed to request firmware\n");
 414                                 return err;
 415                         }
 416
 417                         err = amdgpu_ucode_validate(adev->pm.fw);
 418                         if (err) {
 419                                 DRM_ERROR("Failed to load firmware \"%s\"", fw_name);
 420                                 release_firmware(adev->pm.fw);
 421                                 adev->pm.fw = NULL;
 422                                 return err;
 423                         }
 424
 425                         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 426                                 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
 427                                 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
 428                                 ucode->fw = adev->pm.fw;
 429                                 header = (const struct common_firmware_header *)ucode->fw->data;
 430                                 adev->firmware.fw_size +=
 431                                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 432                         }
 433                 }
 434
 435                 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
 436                 amdgpu_ucode_print_smc_hdr(&hdr->header);
 437                 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
 438                 ucode_size = le32_to_cpu(hdr->header.ucode_size_bytes);
 439                 ucode_start_address = le32_to_cpu(hdr->ucode_start_addr);
 440                 src = (const uint8_t *)(adev->pm.fw->data +
 441                        le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 442
 443                 info->version = adev->pm.fw_version;
 444                 info->image_size = ucode_size;
 445                 info->ucode_start_address = ucode_start_address;
 446                 info->kptr = (void *)src;
 447         }
 448         return 0;
 449 }
 450
 451 static const struct cgs_ops amdgpu_cgs_ops = {
 452         .read_register = amdgpu_cgs_read_register,
 453         .write_register = amdgpu_cgs_write_register,
 454         .read_ind_register = amdgpu_cgs_read_ind_register,
 455         .write_ind_register = amdgpu_cgs_write_ind_register,
 456         .get_firmware_info = amdgpu_cgs_get_firmware_info,
 457 };
 458
 459 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)
 460 {
 461         struct amdgpu_cgs_device *cgs_device =
 462                 kmalloc(sizeof(*cgs_device), GFP_KERNEL);
 463
 464         if (!cgs_device) {
 465                 DRM_ERROR("Couldn't allocate CGS device structure\n");
 466                 return NULL;
 467         }
 468
 469         cgs_device->base.ops = &amdgpu_cgs_ops;
 470         cgs_device->adev = adev;
 471
 472         return (struct cgs_device *)cgs_device;
 473 }
 474
 475 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device)
 476 {
 477         kfree(cgs_device);
 478 }