drivers/gpu/drm/amd/include/mes_v11_api_def.h

   1 /*
   2  * Copyright 2022 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifndef __MES_API_DEF_H__
  25 #define __MES_API_DEF_H__
  26
  27 #pragma pack(push, 4)
  28
  29 #define MES_API_VERSION 1
  30
  31 /* Maximum log buffer size for MES. Needs to be updated if MES expands MES_EVT_INTR_HIST_LOG */
  32 #define  AMDGPU_MES_LOG_BUFFER_SIZE  0x4000
  33
  34 /* Driver submits one API(cmd) as a single Frame and this command size is same
  35  * for all API to ease the debugging and parsing of ring buffer.
  36  */
  37 enum { API_FRAME_SIZE_IN_DWORDS = 64 };
  38
  39 /* To avoid command in scheduler context to be overwritten whenenver mutilple
  40  * interrupts come in, this creates another queue.
  41  */
  42 enum { API_NUMBER_OF_COMMAND_MAX = 32 };
  43
  44 enum MES_API_TYPE {
  45         MES_API_TYPE_SCHEDULER = 1,
  46         MES_API_TYPE_MAX
  47 };
  48
  49 enum MES_SCH_API_OPCODE {
  50         MES_SCH_API_SET_HW_RSRC                 = 0,
  51         MES_SCH_API_SET_SCHEDULING_CONFIG       = 1, /* agreegated db, quantums, etc */
  52         MES_SCH_API_ADD_QUEUE                   = 2,
  53         MES_SCH_API_REMOVE_QUEUE                = 3,
  54         MES_SCH_API_PERFORM_YIELD               = 4,
  55         MES_SCH_API_SET_GANG_PRIORITY_LEVEL     = 5,
  56         MES_SCH_API_SUSPEND                     = 6,
  57         MES_SCH_API_RESUME                      = 7,
  58         MES_SCH_API_RESET                       = 8,
  59         MES_SCH_API_SET_LOG_BUFFER              = 9,
  60         MES_SCH_API_CHANGE_GANG_PRORITY         = 10,
  61         MES_SCH_API_QUERY_SCHEDULER_STATUS      = 11,
  62         MES_SCH_API_PROGRAM_GDS                 = 12,
  63         MES_SCH_API_SET_DEBUG_VMID              = 13,
  64         MES_SCH_API_MISC                        = 14,
  65         MES_SCH_API_UPDATE_ROOT_PAGE_TABLE      = 15,
  66         MES_SCH_API_AMD_LOG                     = 16,
  67         MES_SCH_API_SET_HW_RSRC_1               = 19,
  68         MES_SCH_API_MAX                         = 0xFF
  69 };
  70
  71 union MES_API_HEADER {
  72         struct {
  73                 uint32_t type           : 4; /* 0 - Invalid; 1 - Scheduling; 2 - TBD */
  74                 uint32_t opcode         : 8;
  75                 uint32_t dwsize         : 8; /* including header */
  76                 uint32_t reserved       : 12;
  77         };
  78
  79         uint32_t        u32All;
  80 };
  81
  82 enum MES_AMD_PRIORITY_LEVEL {
  83         AMD_PRIORITY_LEVEL_LOW          = 0,
  84         AMD_PRIORITY_LEVEL_NORMAL       = 1,
  85         AMD_PRIORITY_LEVEL_MEDIUM       = 2,
  86         AMD_PRIORITY_LEVEL_HIGH         = 3,
  87         AMD_PRIORITY_LEVEL_REALTIME     = 4,
  88         AMD_PRIORITY_NUM_LEVELS
  89 };
  90
  91 enum MES_QUEUE_TYPE {
  92         MES_QUEUE_TYPE_GFX,
  93         MES_QUEUE_TYPE_COMPUTE,
  94         MES_QUEUE_TYPE_SDMA,
  95         MES_QUEUE_TYPE_MAX,
  96 };
  97
  98 struct MES_API_STATUS {
  99         uint64_t        api_completion_fence_addr;
 100         uint64_t        api_completion_fence_value;
 101 };
 102
 103 enum { MAX_COMPUTE_PIPES = 8 };
 104 enum { MAX_GFX_PIPES = 2 };
 105 enum { MAX_SDMA_PIPES = 2 };
 106
 107 enum { MAX_COMPUTE_HQD_PER_PIPE = 8 };
 108 enum { MAX_GFX_HQD_PER_PIPE = 8 };
 109 enum { MAX_SDMA_HQD_PER_PIPE = 10 };
 110 enum { MAX_SDMA_HQD_PER_PIPE_11_0   = 8 };
 111
 112 enum { MAX_QUEUES_IN_A_GANG = 8 };
 113
 114 enum VM_HUB_TYPE {
 115         VM_HUB_TYPE_GC = 0,
 116         VM_HUB_TYPE_MM = 1,
 117         VM_HUB_TYPE_MAX,
 118 };
 119
 120 enum { VMID_INVALID = 0xffff };
 121
 122 enum { MAX_VMID_GCHUB = 16 };
 123 enum { MAX_VMID_MMHUB = 16 };
 124
 125 enum SET_DEBUG_VMID_OPERATIONS {
 126         DEBUG_VMID_OP_PROGRAM = 0,
 127         DEBUG_VMID_OP_ALLOCATE = 1,
 128         DEBUG_VMID_OP_RELEASE = 2
 129 };
 130
 131 enum MES_LOG_OPERATION {
 132         MES_LOG_OPERATION_CONTEXT_STATE_CHANGE = 0,
 133         MES_LOG_OPERATION_QUEUE_NEW_WORK = 1,
 134         MES_LOG_OPERATION_QUEUE_UNWAIT_SYNC_OBJECT = 2,
 135         MES_LOG_OPERATION_QUEUE_NO_MORE_WORK = 3,
 136         MES_LOG_OPERATION_QUEUE_WAIT_SYNC_OBJECT = 4,
 137         MES_LOG_OPERATION_QUEUE_INVALID = 0xF,
 138 };
 139
 140 enum MES_LOG_CONTEXT_STATE {
 141         MES_LOG_CONTEXT_STATE_IDLE              = 0,
 142         MES_LOG_CONTEXT_STATE_RUNNING           = 1,
 143         MES_LOG_CONTEXT_STATE_READY             = 2,
 144         MES_LOG_CONTEXT_STATE_READY_STANDBY     = 3,
 145         MES_LOG_CONTEXT_STATE_INVALID           = 0xF,
 146 };
 147
 148 struct MES_LOG_CONTEXT_STATE_CHANGE {
 149         void                            *h_context;
 150         enum MES_LOG_CONTEXT_STATE      new_context_state;
 151 };
 152
 153 struct MES_LOG_QUEUE_NEW_WORK {
 154         uint64_t                   h_queue;
 155         uint64_t                   reserved;
 156 };
 157
 158 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT {
 159         uint64_t                   h_queue;
 160         uint64_t                   h_sync_object;
 161 };
 162
 163 struct MES_LOG_QUEUE_NO_MORE_WORK {
 164         uint64_t                   h_queue;
 165         uint64_t                   reserved;
 166 };
 167
 168 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT {
 169         uint64_t                   h_queue;
 170         uint64_t                   h_sync_object;
 171 };
 172
 173 struct MES_LOG_ENTRY_HEADER {
 174         uint32_t        first_free_entry_index;
 175         uint32_t        wraparound_count;
 176         uint64_t        number_of_entries;
 177         uint64_t        reserved[2];
 178 };
 179
 180 struct MES_LOG_ENTRY_DATA {
 181         uint64_t        gpu_time_stamp;
 182         uint32_t        operation_type; /* operation_type is of MES_LOG_OPERATION type */
 183         uint32_t        reserved_operation_type_bits;
 184         union {
 185                 struct MES_LOG_CONTEXT_STATE_CHANGE     context_state_change;
 186                 struct MES_LOG_QUEUE_NEW_WORK           queue_new_work;
 187                 struct MES_LOG_QUEUE_UNWAIT_SYNC_OBJECT queue_unwait_sync_object;
 188                 struct MES_LOG_QUEUE_NO_MORE_WORK       queue_no_more_work;
 189                 struct MES_LOG_QUEUE_WAIT_SYNC_OBJECT   queue_wait_sync_object;
 190                 uint64_t                                all[2];
 191         };
 192 };
 193
 194 struct MES_LOG_BUFFER {
 195         struct MES_LOG_ENTRY_HEADER     header;
 196         struct MES_LOG_ENTRY_DATA       entries[1];
 197 };
 198
 199 enum MES_SWIP_TO_HWIP_DEF {
 200         MES_MAX_HWIP_SEGMENT = 8,
 201 };
 202
 203 union MESAPI_SET_HW_RESOURCES {
 204         struct {
 205                 union MES_API_HEADER    header;
 206                 uint32_t                vmid_mask_mmhub;
 207                 uint32_t                vmid_mask_gfxhub;
 208                 uint32_t                gds_size;
 209                 uint32_t                paging_vmid;
 210                 uint32_t                compute_hqd_mask[MAX_COMPUTE_PIPES];
 211                 uint32_t                gfx_hqd_mask[MAX_GFX_PIPES];
 212                 uint32_t                sdma_hqd_mask[MAX_SDMA_PIPES];
 213                 uint32_t                aggregated_doorbells[AMD_PRIORITY_NUM_LEVELS];
 214                 uint64_t                g_sch_ctx_gpu_mc_ptr;
 215                 uint64_t                query_status_fence_gpu_mc_ptr;
 216                 uint32_t                gc_base[MES_MAX_HWIP_SEGMENT];
 217                 uint32_t                mmhub_base[MES_MAX_HWIP_SEGMENT];
 218                 uint32_t                osssys_base[MES_MAX_HWIP_SEGMENT];
 219                 struct MES_API_STATUS   api_status;
 220                 union {
 221                         struct {
 222                                 uint32_t disable_reset  : 1;
 223                                 uint32_t use_different_vmid_compute : 1;
 224                                 uint32_t disable_mes_log   : 1;
 225                                 uint32_t apply_mmhub_pgvm_invalidate_ack_loss_wa : 1;
 226                                 uint32_t apply_grbm_remote_register_dummy_read_wa : 1;
 227                                 uint32_t second_gfx_pipe_enabled : 1;
 228                                 uint32_t enable_level_process_quantum_check : 1;
 229                                 uint32_t legacy_sch_mode : 1;
 230                                 uint32_t disable_add_queue_wptr_mc_addr : 1;
 231                                 uint32_t enable_mes_event_int_logging : 1;
 232                                 uint32_t enable_reg_active_poll : 1;
 233                                 uint32_t use_disable_queue_in_legacy_uq_preemption : 1;
 234                                 uint32_t send_write_data : 1;
 235                                 uint32_t os_tdr_timeout_override : 1;
 236                                 uint32_t use_rs64mem_for_proc_gang_ctx : 1;
 237                                 uint32_t use_add_queue_unmap_flag_addr : 1;
 238                                 uint32_t enable_mes_sch_stb_log : 1;
 239                                 uint32_t limit_single_process : 1;
 240                                 uint32_t is_strix_tmz_wa_enabled  :1;
 241                                 uint32_t reserved : 13;
 242                         };
 243                         uint32_t        uint32_t_all;
 244                 };
 245                 uint32_t        oversubscription_timer;
 246                 uint64_t        doorbell_info;
 247                 uint64_t        event_intr_history_gpu_mc_ptr;
 248                 uint64_t        timestamp;
 249                 uint32_t        os_tdr_timeout_in_sec;
 250         };
 251
 252         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 253 };
 254
 255 union MESAPI_SET_HW_RESOURCES_1 {
 256         struct {
 257                 union MES_API_HEADER                            header;
 258                 struct MES_API_STATUS                      api_status;
 259                 uint64_t                                                        timestamp;
 260                 union {
 261                         struct {
 262                                 uint32_t enable_mes_info_ctx : 1;
 263                                 uint32_t reserved : 31;
 264                         };
 265                         uint32_t uint32_all;
 266                 };
 267                 uint64_t                                                        mes_info_ctx_mc_addr;
 268                 uint32_t                                                        mes_info_ctx_size;
 269                 uint32_t                                                        mes_kiq_unmap_timeout; // unit is 100ms
 270         };
 271
 272         uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 273 };
 274
 275 union MESAPI__ADD_QUEUE {
 276         struct {
 277                 union MES_API_HEADER            header;
 278                 uint32_t                        process_id;
 279                 uint64_t                        page_table_base_addr;
 280                 uint64_t                        process_va_start;
 281                 uint64_t                        process_va_end;
 282                 uint64_t                        process_quantum;
 283                 uint64_t                        process_context_addr;
 284                 uint64_t                        gang_quantum;
 285                 uint64_t                        gang_context_addr;
 286                 uint32_t                        inprocess_gang_priority;
 287                 enum MES_AMD_PRIORITY_LEVEL     gang_global_priority_level;
 288                 uint32_t                        doorbell_offset;
 289                 uint64_t                        mqd_addr;
 290                 uint64_t                        wptr_addr;
 291                 uint64_t                        h_context;
 292                 uint64_t                        h_queue;
 293                 enum MES_QUEUE_TYPE             queue_type;
 294                 uint32_t                        gds_base;
 295                 uint32_t                        gds_size;
 296                 uint32_t                        gws_base;
 297                 uint32_t                        gws_size;
 298                 uint32_t                        oa_mask;
 299                 uint64_t                        trap_handler_addr;
 300                 uint32_t                        vm_context_cntl;
 301
 302                 struct {
 303                         uint32_t paging                 : 1;
 304                         uint32_t debug_vmid             : 4;
 305                         uint32_t program_gds            : 1;
 306                         uint32_t is_gang_suspended      : 1;
 307                         uint32_t is_tmz_queue           : 1;
 308                         uint32_t map_kiq_utility_queue  : 1;
 309                         uint32_t is_kfd_process         : 1;
 310                         uint32_t trap_en                : 1;
 311                         uint32_t is_aql_queue           : 1;
 312                         uint32_t skip_process_ctx_clear : 1;
 313                         uint32_t map_legacy_kq          : 1;
 314                         uint32_t exclusively_scheduled  : 1;
 315                         uint32_t is_long_running        : 1;
 316                         uint32_t is_dwm_queue           : 1;
 317                         uint32_t is_video_blit_queue    : 1;
 318                         uint32_t reserved               : 14;
 319                 };
 320                 struct MES_API_STATUS       api_status;
 321                 uint64_t                    tma_addr;
 322                 uint32_t                    sch_id;
 323                 uint64_t                    timestamp;
 324                 uint32_t                    process_context_array_index;
 325                 uint32_t                    gang_context_array_index;
 326                 uint32_t                    pipe_id;
 327                 uint32_t                    queue_id;
 328                 uint32_t                    alignment_mode_setting;
 329                 uint64_t                    unmap_flag_addr;
 330         };
 331
 332         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 333 };
 334
 335 union MESAPI__REMOVE_QUEUE {
 336         struct {
 337                 union MES_API_HEADER    header;
 338                 uint32_t                doorbell_offset;
 339                 uint64_t                gang_context_addr;
 340
 341                 struct {
 342                         uint32_t unmap_legacy_gfx_queue   : 1;
 343                         uint32_t unmap_kiq_utility_queue  : 1;
 344                         uint32_t preempt_legacy_gfx_queue : 1;
 345                         uint32_t unmap_legacy_queue       : 1;
 346                         uint32_t reserved                 : 28;
 347                 };
 348                 struct MES_API_STATUS       api_status;
 349
 350                 uint32_t                    pipe_id;
 351                 uint32_t                    queue_id;
 352
 353                 uint64_t                    tf_addr;
 354                 uint32_t                    tf_data;
 355
 356                 enum MES_QUEUE_TYPE         queue_type;
 357         };
 358
 359         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 360 };
 361
 362 union MESAPI__SET_SCHEDULING_CONFIG {
 363         struct {
 364                 union MES_API_HEADER    header;
 365                 /* Grace period when preempting another priority band for this
 366                  * priority band. The value for idle priority band is ignored,
 367                  * as it never preempts other bands.
 368                  */
 369                 uint64_t                grace_period_other_levels[AMD_PRIORITY_NUM_LEVELS];
 370                 /* Default quantum for scheduling across processes within
 371                  * a priority band.
 372                  */
 373                 uint64_t                process_quantum_for_level[AMD_PRIORITY_NUM_LEVELS];
 374                 /* Default grace period for processes that preempt each other
 375                  * within a priority band.
 376                  */
 377                 uint64_t                process_grace_period_same_level[AMD_PRIORITY_NUM_LEVELS];
 378                 /* For normal level this field specifies the target GPU
 379                  * percentage in situations when it's starved by the high level.
 380                  * Valid values are between 0 and 50, with the default being 10.
 381                  */
 382                 uint32_t                normal_yield_percent;
 383                 struct MES_API_STATUS   api_status;
 384         };
 385
 386         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 387 };
 388
 389 union MESAPI__PERFORM_YIELD {
 390         struct {
 391                 union MES_API_HEADER    header;
 392                 uint32_t                dummy;
 393                 struct MES_API_STATUS   api_status;
 394         };
 395
 396         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 397 };
 398
 399 union MESAPI__CHANGE_GANG_PRIORITY_LEVEL {
 400         struct {
 401                 union MES_API_HEADER            header;
 402                 uint32_t                        inprocess_gang_priority;
 403                 enum MES_AMD_PRIORITY_LEVEL     gang_global_priority_level;
 404                 uint64_t                        gang_quantum;
 405                 uint64_t                        gang_context_addr;
 406                 struct MES_API_STATUS           api_status;
 407         };
 408
 409         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 410 };
 411
 412 union MESAPI__SUSPEND {
 413         struct {
 414                 union MES_API_HEADER    header;
 415                 /* false - suspend all gangs; true - specific gang */
 416                 struct {
 417                         uint32_t suspend_all_gangs      : 1;
 418                         uint32_t reserved               : 31;
 419                 };
 420                 /* gang_context_addr is valid only if suspend_all = false */
 421                 uint64_t                gang_context_addr;
 422
 423                 uint64_t                suspend_fence_addr;
 424                 uint32_t                suspend_fence_value;
 425
 426                 struct MES_API_STATUS   api_status;
 427         };
 428
 429         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 430 };
 431
 432 union MESAPI__RESUME {
 433         struct {
 434                 union MES_API_HEADER    header;
 435                 /* false - resume all gangs; true - specified gang */
 436                 struct {
 437                         uint32_t resume_all_gangs       : 1;
 438                         uint32_t reserved               : 31;
 439                 };
 440                 /* valid only if resume_all_gangs = false */
 441                 uint64_t                gang_context_addr;
 442
 443                 struct MES_API_STATUS   api_status;
 444         };
 445
 446         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 447 };
 448
 449 union MESAPI__RESET {
 450         struct {
 451                 union MES_API_HEADER            header;
 452
 453                 struct {
 454                         /* Only reset the queue given by doorbell_offset (not entire gang) */
 455                         uint32_t                reset_queue_only : 1;
 456                         /* Hang detection first then reset any queues that are hung */
 457                         uint32_t                hang_detect_then_reset : 1;
 458                         /* Only do hang detection (no reset) */
 459                         uint32_t                hang_detect_only : 1;
 460                         /* Rest HP and LP kernel queues not managed by MES */
 461                         uint32_t                reset_legacy_gfx : 1;
 462                         uint32_t                reserved : 28;
 463                 };
 464
 465                 uint64_t                        gang_context_addr;
 466
 467                 /* valid only if reset_queue_only = true */
 468                 uint32_t                        doorbell_offset;
 469
 470                 /* valid only if hang_detect_then_reset = true */
 471                 uint64_t                        doorbell_offset_addr;
 472                 enum MES_QUEUE_TYPE             queue_type;
 473
 474                 /* valid only if reset_legacy_gfx = true */
 475                 uint32_t                        pipe_id_lp;
 476                 uint32_t                        queue_id_lp;
 477                 uint32_t                        vmid_id_lp;
 478                 uint64_t                        mqd_mc_addr_lp;
 479                 uint32_t                        doorbell_offset_lp;
 480                 uint64_t                        wptr_addr_lp;
 481
 482                 uint32_t                        pipe_id_hp;
 483                 uint32_t                        queue_id_hp;
 484                 uint32_t                        vmid_id_hp;
 485                 uint64_t                        mqd_mc_addr_hp;
 486                 uint32_t                        doorbell_offset_hp;
 487                 uint64_t                        wptr_addr_hp;
 488
 489                 struct MES_API_STATUS           api_status;
 490         };
 491
 492         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 493 };
 494
 495 union MESAPI__SET_LOGGING_BUFFER {
 496         struct {
 497                 union MES_API_HEADER    header;
 498                 /* There are separate log buffers for each queue type */
 499                 enum MES_QUEUE_TYPE     log_type;
 500                 /* Log buffer GPU Address */
 501                 uint64_t                logging_buffer_addr;
 502                 /* number of entries in the log buffer */
 503                 uint32_t                number_of_entries;
 504                 /* Entry index at which CPU interrupt needs to be signalled */
 505                 uint32_t                interrupt_entry;
 506
 507                 struct MES_API_STATUS   api_status;
 508         };
 509
 510         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 511 };
 512
 513 union MESAPI__QUERY_MES_STATUS {
 514         struct {
 515                 union MES_API_HEADER    header;
 516                 bool                    mes_healthy; /* 0 - not healthy, 1 - healthy */
 517                 struct MES_API_STATUS   api_status;
 518         };
 519
 520         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 521 };
 522
 523 union MESAPI__PROGRAM_GDS {
 524         struct {
 525                 union MES_API_HEADER    header;
 526                 uint64_t                process_context_addr;
 527                 uint32_t                gds_base;
 528                 uint32_t                gds_size;
 529                 uint32_t                gws_base;
 530                 uint32_t                gws_size;
 531                 uint32_t                oa_mask;
 532                 struct MES_API_STATUS   api_status;
 533         };
 534
 535         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 536 };
 537
 538 union MESAPI__SET_DEBUG_VMID {
 539         struct {
 540                 union MES_API_HEADER    header;
 541                 struct MES_API_STATUS   api_status;
 542                 union {
 543                         struct {
 544                                 uint32_t use_gds        : 1;
 545                                 uint32_t operation      : 2;
 546                                 uint32_t reserved       : 29;
 547                         } flags;
 548                         uint32_t        u32All;
 549                 };
 550                 uint32_t                reserved;
 551                 uint32_t                debug_vmid;
 552                 uint64_t                process_context_addr;
 553                 uint64_t                page_table_base_addr;
 554                 uint64_t                process_va_start;
 555                 uint64_t                process_va_end;
 556                 uint32_t                gds_base;
 557                 uint32_t                gds_size;
 558                 uint32_t                gws_base;
 559                 uint32_t                gws_size;
 560                 uint32_t                oa_mask;
 561
 562                 /* output addr of the acquired vmid value */
 563                 uint64_t                output_addr;
 564         };
 565
 566         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 567 };
 568
 569 enum MESAPI_MISC_OPCODE {
 570         MESAPI_MISC__WRITE_REG,
 571         MESAPI_MISC__INV_GART,
 572         MESAPI_MISC__QUERY_STATUS,
 573         MESAPI_MISC__READ_REG,
 574         MESAPI_MISC__WAIT_REG_MEM,
 575         MESAPI_MISC__SET_SHADER_DEBUGGER,
 576         MESAPI_MISC__NOTIFY_WORK_ON_UNMAPPED_QUEUE,
 577         MESAPI_MISC__NOTIFY_TO_UNMAP_PROCESSES,
 578         MESAPI_MISC__CHANGE_CONFIG,
 579         MESAPI_MISC__LAUNCH_CLEANER_SHADER,
 580
 581         MESAPI_MISC__MAX,
 582 };
 583
 584 enum { MISC_DATA_MAX_SIZE_IN_DWORDS = 20 };
 585
 586 struct WRITE_REG {
 587         uint32_t                  reg_offset;
 588         uint32_t                  reg_value;
 589 };
 590
 591 struct READ_REG {
 592         uint32_t                  reg_offset;
 593         uint64_t                  buffer_addr;
 594 };
 595
 596 enum WRM_OPERATION {
 597         WRM_OPERATION__WAIT_REG_MEM,
 598         WRM_OPERATION__WR_WAIT_WR_REG,
 599         WRM_OPERATION__MAX,
 600 };
 601
 602 struct WAIT_REG_MEM {
 603         enum WRM_OPERATION         op;
 604         uint32_t                   reference;
 605         uint32_t                   mask;
 606         uint32_t                   reg_offset1;
 607         uint32_t                   reg_offset2;
 608 };
 609
 610 struct INV_GART {
 611         uint64_t                  inv_range_va_start;
 612         uint64_t                  inv_range_size;
 613 };
 614
 615 struct QUERY_STATUS {
 616         uint32_t context_id;
 617 };
 618
 619 struct SET_SHADER_DEBUGGER {
 620         uint64_t process_context_addr;
 621         union {
 622                 struct {
 623                         uint32_t single_memop : 1;  /* SQ_DEBUG.single_memop */
 624                         uint32_t single_alu_op : 1; /* SQ_DEBUG.single_alu_op */
 625                         uint32_t reserved : 29;
 626                         uint32_t process_ctx_flush : 1;
 627                 };
 628                 uint32_t u32all;
 629         } flags;
 630         uint32_t spi_gdbg_per_vmid_cntl;
 631         uint32_t tcp_watch_cntl[4]; /* TCP_WATCHx_CNTL */
 632         uint32_t trap_en;
 633 };
 634
 635 enum MESAPI_MISC__CHANGE_CONFIG_OPTION {
 636         MESAPI_MISC__CHANGE_CONFIG_OPTION_LIMIT_SINGLE_PROCESS = 0,
 637         MESAPI_MISC__CHANGE_CONFIG_OPTION_ENABLE_HWS_LOGGING_BUFFER = 1,
 638         MESAPI_MISC__CHANGE_CONFIG_OPTION_CHANGE_TDR_CONFIG    = 2,
 639
 640         MESAPI_MISC__CHANGE_CONFIG_OPTION_MAX = 0x1F
 641 };
 642
 643 struct CHANGE_CONFIG {
 644         enum MESAPI_MISC__CHANGE_CONFIG_OPTION opcode;
 645         union {
 646                 struct {
 647                         uint32_t limit_single_process : 1;
 648                         uint32_t enable_hws_logging_buffer : 1;
 649                         uint32_t reserved : 31;
 650                 } bits;
 651                 uint32_t all;
 652         } option;
 653
 654         struct {
 655                 uint32_t tdr_level;
 656                 uint32_t tdr_delay;
 657         } tdr_config;
 658 };
 659
 660 union MESAPI__MISC {
 661         struct {
 662                 union MES_API_HEADER    header;
 663                 enum MESAPI_MISC_OPCODE opcode;
 664                 struct MES_API_STATUS   api_status;
 665
 666                 union {
 667                         struct          WRITE_REG write_reg;
 668                         struct          INV_GART inv_gart;
 669                         struct          QUERY_STATUS query_status;
 670                         struct          READ_REG read_reg;
 671                         struct          WAIT_REG_MEM wait_reg_mem;
 672                         struct          SET_SHADER_DEBUGGER set_shader_debugger;
 673                         enum MES_AMD_PRIORITY_LEVEL queue_sch_level;
 674                         struct          CHANGE_CONFIG change_config;
 675
 676                         uint32_t        data[MISC_DATA_MAX_SIZE_IN_DWORDS];
 677                 };
 678         };
 679
 680         uint32_t        max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 681 };
 682
 683 union MESAPI__UPDATE_ROOT_PAGE_TABLE {
 684         struct {
 685                 union MES_API_HEADER        header;
 686                 uint64_t                    page_table_base_addr;
 687                 uint64_t                    process_context_addr;
 688                 struct MES_API_STATUS       api_status;
 689         };
 690
 691         uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 692 };
 693
 694 union MESAPI_AMD_LOG {
 695         struct {
 696                 union MES_API_HEADER        header;
 697                 uint64_t                    p_buffer_memory;
 698                 uint64_t                    p_buffer_size_used;
 699                 struct MES_API_STATUS       api_status;
 700         };
 701
 702         uint32_t max_dwords_in_api[API_FRAME_SIZE_IN_DWORDS];
 703 };
 704
 705 #pragma pack(pop)
 706 #endif