drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include <drm/amdgpu_drm.h>
  36 #include <drm/drm_cache.h>
  37 #include "amdgpu.h"
  38 #include "amdgpu_trace.h"
  39
  40 static bool amdgpu_need_backup(struct amdgpu_device *adev)
  41 {
  42         if (adev->flags & AMD_IS_APU)
  43                 return false;
  44
  45         if (amdgpu_gpu_recovery == 0 ||
  46             (amdgpu_gpu_recovery == -1  && !amdgpu_sriov_vf(adev)))
  47                 return false;
  48
  49         return true;
  50 }
  51
  52 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  53 {
  54         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
  55         struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
  56
  57         amdgpu_bo_kunmap(bo);
  58
  59         drm_gem_object_release(&bo->gem_base);
  60         amdgpu_bo_unref(&bo->parent);
  61         if (!list_empty(&bo->shadow_list)) {
  62                 mutex_lock(&adev->shadow_list_lock);
  63                 list_del_init(&bo->shadow_list);
  64                 mutex_unlock(&adev->shadow_list_lock);
  65         }
  66         kfree(bo->metadata);
  67         kfree(bo);
  68 }
  69
  70 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
  71 {
  72         if (bo->destroy == &amdgpu_ttm_bo_destroy)
  73                 return true;
  74         return false;
  75 }
  76
  77 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
  78 {
  79         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
  80         struct ttm_placement *placement = &abo->placement;
  81         struct ttm_place *places = abo->placements;
  82         u64 flags = abo->flags;
  83         u32 c = 0;
  84
  85         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
  86                 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
  87
  88                 places[c].fpfn = 0;
  89                 places[c].lpfn = 0;
  90                 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
  91                         TTM_PL_FLAG_VRAM;
  92
  93                 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
  94                         places[c].lpfn = visible_pfn;
  95                 else
  96                         places[c].flags |= TTM_PL_FLAG_TOPDOWN;
  97
  98                 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
  99                         places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
 100                 c++;
 101         }
 102
 103         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 104                 places[c].fpfn = 0;
 105                 if (flags & AMDGPU_GEM_CREATE_SHADOW)
 106                         places[c].lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
 107                 else
 108                         places[c].lpfn = 0;
 109                 places[c].flags = TTM_PL_FLAG_TT;
 110                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 111                         places[c].flags |= TTM_PL_FLAG_WC |
 112                                 TTM_PL_FLAG_UNCACHED;
 113                 else
 114                         places[c].flags |= TTM_PL_FLAG_CACHED;
 115                 c++;
 116         }
 117
 118         if (domain & AMDGPU_GEM_DOMAIN_CPU) {
 119                 places[c].fpfn = 0;
 120                 places[c].lpfn = 0;
 121                 places[c].flags = TTM_PL_FLAG_SYSTEM;
 122                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 123                         places[c].flags |= TTM_PL_FLAG_WC |
 124                                 TTM_PL_FLAG_UNCACHED;
 125                 else
 126                         places[c].flags |= TTM_PL_FLAG_CACHED;
 127                 c++;
 128         }
 129
 130         if (domain & AMDGPU_GEM_DOMAIN_GDS) {
 131                 places[c].fpfn = 0;
 132                 places[c].lpfn = 0;
 133                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS;
 134                 c++;
 135         }
 136
 137         if (domain & AMDGPU_GEM_DOMAIN_GWS) {
 138                 places[c].fpfn = 0;
 139                 places[c].lpfn = 0;
 140                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS;
 141                 c++;
 142         }
 143
 144         if (domain & AMDGPU_GEM_DOMAIN_OA) {
 145                 places[c].fpfn = 0;
 146                 places[c].lpfn = 0;
 147                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA;
 148                 c++;
 149         }
 150
 151         if (!c) {
 152                 places[c].fpfn = 0;
 153                 places[c].lpfn = 0;
 154                 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
 155                 c++;
 156         }
 157
 158         placement->num_placement = c;
 159         placement->placement = places;
 160
 161         placement->num_busy_placement = c;
 162         placement->busy_placement = places;
 163 }
 164
 165 /**
 166  * amdgpu_bo_create_reserved - create reserved BO for kernel use
 167  *
 168  * @adev: amdgpu device object
 169  * @size: size for the new BO
 170  * @align: alignment for the new BO
 171  * @domain: where to place it
 172  * @bo_ptr: resulting BO
 173  * @gpu_addr: GPU addr of the pinned BO
 174  * @cpu_addr: optional CPU address mapping
 175  *
 176  * Allocates and pins a BO for kernel internal use, and returns it still
 177  * reserved.
 178  *
 179  * Returns 0 on success, negative error code otherwise.
 180  */
 181 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
 182                               unsigned long size, int align,
 183                               u32 domain, struct amdgpu_bo **bo_ptr,
 184                               u64 *gpu_addr, void **cpu_addr)
 185 {
 186         bool free = false;
 187         int r;
 188
 189         if (!*bo_ptr) {
 190                 r = amdgpu_bo_create(adev, size, align, true, domain,
 191                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 192                                      AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
 193                                      NULL, NULL, bo_ptr);
 194                 if (r) {
 195                         dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
 196                                 r);
 197                         return r;
 198                 }
 199                 free = true;
 200         }
 201
 202         r = amdgpu_bo_reserve(*bo_ptr, false);
 203         if (r) {
 204                 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
 205                 goto error_free;
 206         }
 207
 208         r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr);
 209         if (r) {
 210                 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
 211                 goto error_unreserve;
 212         }
 213
 214         if (cpu_addr) {
 215                 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
 216                 if (r) {
 217                         dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
 218                         goto error_unreserve;
 219                 }
 220         }
 221
 222         return 0;
 223
 224 error_unreserve:
 225         amdgpu_bo_unreserve(*bo_ptr);
 226
 227 error_free:
 228         if (free)
 229                 amdgpu_bo_unref(bo_ptr);
 230
 231         return r;
 232 }
 233
 234 /**
 235  * amdgpu_bo_create_kernel - create BO for kernel use
 236  *
 237  * @adev: amdgpu device object
 238  * @size: size for the new BO
 239  * @align: alignment for the new BO
 240  * @domain: where to place it
 241  * @bo_ptr: resulting BO
 242  * @gpu_addr: GPU addr of the pinned BO
 243  * @cpu_addr: optional CPU address mapping
 244  *
 245  * Allocates and pins a BO for kernel internal use.
 246  *
 247  * Returns 0 on success, negative error code otherwise.
 248  */
 249 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
 250                             unsigned long size, int align,
 251                             u32 domain, struct amdgpu_bo **bo_ptr,
 252                             u64 *gpu_addr, void **cpu_addr)
 253 {
 254         int r;
 255
 256         r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr,
 257                                       gpu_addr, cpu_addr);
 258
 259         if (r)
 260                 return r;
 261
 262         amdgpu_bo_unreserve(*bo_ptr);
 263
 264         return 0;
 265 }
 266
 267 /**
 268  * amdgpu_bo_free_kernel - free BO for kernel use
 269  *
 270  * @bo: amdgpu BO to free
 271  *
 272  * unmaps and unpin a BO for kernel internal use.
 273  */
 274 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
 275                            void **cpu_addr)
 276 {
 277         if (*bo == NULL)
 278                 return;
 279
 280         if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
 281                 if (cpu_addr)
 282                         amdgpu_bo_kunmap(*bo);
 283
 284                 amdgpu_bo_unpin(*bo);
 285                 amdgpu_bo_unreserve(*bo);
 286         }
 287         amdgpu_bo_unref(bo);
 288
 289         if (gpu_addr)
 290                 *gpu_addr = 0;
 291
 292         if (cpu_addr)
 293                 *cpu_addr = NULL;
 294 }
 295
 296 /* Validate bo size is bit bigger then the request domain */
 297 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
 298                                           unsigned long size, u32 domain)
 299 {
 300         struct ttm_mem_type_manager *man = NULL;
 301
 302         /*
 303          * If GTT is part of requested domains the check must succeed to
 304          * allow fall back to GTT
 305          */
 306         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 307                 man = &adev->mman.bdev.man[TTM_PL_TT];
 308
 309                 if (size < (man->size << PAGE_SHIFT))
 310                         return true;
 311                 else
 312                         goto fail;
 313         }
 314
 315         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
 316                 man = &adev->mman.bdev.man[TTM_PL_VRAM];
 317
 318                 if (size < (man->size << PAGE_SHIFT))
 319                         return true;
 320                 else
 321                         goto fail;
 322         }
 323
 324
 325         /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */
 326         return true;
 327
 328 fail:
 329         DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size,
 330                   man->size << PAGE_SHIFT);
 331         return false;
 332 }
 333
 334 static int amdgpu_bo_do_create(struct amdgpu_device *adev,
 335                                unsigned long size, int byte_align,
 336                                bool kernel, u32 domain, u64 flags,
 337                                struct sg_table *sg,
 338                                struct reservation_object *resv,
 339                                struct amdgpu_bo **bo_ptr)
 340 {
 341         struct ttm_operation_ctx ctx = {
 342                 .interruptible = !kernel,
 343                 .no_wait_gpu = false,
 344                 .resv = resv,
 345                 .flags = TTM_OPT_FLAG_ALLOW_RES_EVICT
 346         };
 347         struct amdgpu_bo *bo;
 348         enum ttm_bo_type type;
 349         unsigned long page_align;
 350         size_t acc_size;
 351         int r;
 352
 353         page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 354         size = ALIGN(size, PAGE_SIZE);
 355
 356         if (!amdgpu_bo_validate_size(adev, size, domain))
 357                 return -ENOMEM;
 358
 359         if (kernel) {
 360                 type = ttm_bo_type_kernel;
 361         } else if (sg) {
 362                 type = ttm_bo_type_sg;
 363         } else {
 364                 type = ttm_bo_type_device;
 365         }
 366         *bo_ptr = NULL;
 367
 368         acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
 369                                        sizeof(struct amdgpu_bo));
 370
 371         bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
 372         if (bo == NULL)
 373                 return -ENOMEM;
 374         drm_gem_private_object_init(adev->ddev, &bo->gem_base, size);
 375         INIT_LIST_HEAD(&bo->shadow_list);
 376         INIT_LIST_HEAD(&bo->va);
 377         bo->preferred_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM |
 378                                          AMDGPU_GEM_DOMAIN_GTT |
 379                                          AMDGPU_GEM_DOMAIN_CPU |
 380                                          AMDGPU_GEM_DOMAIN_GDS |
 381                                          AMDGPU_GEM_DOMAIN_GWS |
 382                                          AMDGPU_GEM_DOMAIN_OA);
 383         bo->allowed_domains = bo->preferred_domains;
 384         if (!kernel && bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 385                 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 386
 387         bo->flags = flags;
 388
 389 #ifdef CONFIG_X86_32
 390         /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
 391          * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
 392          */
 393         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 394 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
 395         /* Don't try to enable write-combining when it can't work, or things
 396          * may be slow
 397          * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
 398          */
 399
 400 #ifndef CONFIG_COMPILE_TEST
 401 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
 402          thanks to write-combining
 403 #endif
 404
 405         if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 406                 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
 407                               "better performance thanks to write-combining\n");
 408         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 409 #else
 410         /* For architectures that don't support WC memory,
 411          * mask out the WC flag from the BO
 412          */
 413         if (!drm_arch_can_wc_memory())
 414                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 415 #endif
 416
 417         bo->tbo.bdev = &adev->mman.bdev;
 418         amdgpu_ttm_placement_from_domain(bo, domain);
 419
 420         r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type,
 421                                  &bo->placement, page_align, &ctx, NULL,
 422                                  acc_size, sg, resv, &amdgpu_ttm_bo_destroy);
 423         if (unlikely(r != 0))
 424                 return r;
 425
 426         if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
 427             bo->tbo.mem.mem_type == TTM_PL_VRAM &&
 428             bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT)
 429                 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
 430                                              ctx.bytes_moved);
 431         else
 432                 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
 433
 434         if (kernel)
 435                 bo->tbo.priority = 1;
 436
 437         if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
 438             bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
 439                 struct dma_fence *fence;
 440
 441                 r = amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence);
 442                 if (unlikely(r))
 443                         goto fail_unreserve;
 444
 445                 amdgpu_bo_fence(bo, fence, false);
 446                 dma_fence_put(bo->tbo.moving);
 447                 bo->tbo.moving = dma_fence_get(fence);
 448                 dma_fence_put(fence);
 449         }
 450         if (!resv)
 451                 amdgpu_bo_unreserve(bo);
 452         *bo_ptr = bo;
 453
 454         trace_amdgpu_bo_create(bo);
 455
 456         /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
 457         if (type == ttm_bo_type_device)
 458                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 459
 460         return 0;
 461
 462 fail_unreserve:
 463         if (!resv)
 464                 ww_mutex_unlock(&bo->tbo.resv->lock);
 465         amdgpu_bo_unref(&bo);
 466         return r;
 467 }
 468
 469 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
 470                                    unsigned long size, int byte_align,
 471                                    struct amdgpu_bo *bo)
 472 {
 473         int r;
 474
 475         if (bo->shadow)
 476                 return 0;
 477
 478         r = amdgpu_bo_do_create(adev, size, byte_align, true,
 479                                 AMDGPU_GEM_DOMAIN_GTT,
 480                                 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
 481                                 AMDGPU_GEM_CREATE_SHADOW,
 482                                 NULL, bo->tbo.resv,
 483                                 &bo->shadow);
 484         if (!r) {
 485                 bo->shadow->parent = amdgpu_bo_ref(bo);
 486                 mutex_lock(&adev->shadow_list_lock);
 487                 list_add_tail(&bo->shadow_list, &adev->shadow_list);
 488                 mutex_unlock(&adev->shadow_list_lock);
 489         }
 490
 491         return r;
 492 }
 493
 494 int amdgpu_bo_create(struct amdgpu_device *adev,
 495                      unsigned long size, int byte_align,
 496                      bool kernel, u32 domain, u64 flags,
 497                      struct sg_table *sg,
 498                      struct reservation_object *resv,
 499                      struct amdgpu_bo **bo_ptr)
 500 {
 501         uint64_t parent_flags = flags & ~AMDGPU_GEM_CREATE_SHADOW;
 502         int r;
 503
 504         r = amdgpu_bo_do_create(adev, size, byte_align, kernel, domain,
 505                                 parent_flags, sg, resv, bo_ptr);
 506         if (r)
 507                 return r;
 508
 509         if ((flags & AMDGPU_GEM_CREATE_SHADOW) && amdgpu_need_backup(adev)) {
 510                 if (!resv)
 511                         WARN_ON(reservation_object_lock((*bo_ptr)->tbo.resv,
 512                                                         NULL));
 513
 514                 r = amdgpu_bo_create_shadow(adev, size, byte_align, (*bo_ptr));
 515
 516                 if (!resv)
 517                         reservation_object_unlock((*bo_ptr)->tbo.resv);
 518
 519                 if (r)
 520                         amdgpu_bo_unref(bo_ptr);
 521         }
 522
 523         return r;
 524 }
 525
 526 int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
 527                                struct amdgpu_ring *ring,
 528                                struct amdgpu_bo *bo,
 529                                struct reservation_object *resv,
 530                                struct dma_fence **fence,
 531                                bool direct)
 532
 533 {
 534         struct amdgpu_bo *shadow = bo->shadow;
 535         uint64_t bo_addr, shadow_addr;
 536         int r;
 537
 538         if (!shadow)
 539                 return -EINVAL;
 540
 541         bo_addr = amdgpu_bo_gpu_offset(bo);
 542         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 543
 544         r = reservation_object_reserve_shared(bo->tbo.resv);
 545         if (r)
 546                 goto err;
 547
 548         r = amdgpu_copy_buffer(ring, bo_addr, shadow_addr,
 549                                amdgpu_bo_size(bo), resv, fence,
 550                                direct, false);
 551         if (!r)
 552                 amdgpu_bo_fence(bo, *fence, true);
 553
 554 err:
 555         return r;
 556 }
 557
 558 int amdgpu_bo_validate(struct amdgpu_bo *bo)
 559 {
 560         struct ttm_operation_ctx ctx = { false, false };
 561         uint32_t domain;
 562         int r;
 563
 564         if (bo->pin_count)
 565                 return 0;
 566
 567         domain = bo->preferred_domains;
 568
 569 retry:
 570         amdgpu_ttm_placement_from_domain(bo, domain);
 571         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 572         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 573                 domain = bo->allowed_domains;
 574                 goto retry;
 575         }
 576
 577         return r;
 578 }
 579
 580 int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev,
 581                                   struct amdgpu_ring *ring,
 582                                   struct amdgpu_bo *bo,
 583                                   struct reservation_object *resv,
 584                                   struct dma_fence **fence,
 585                                   bool direct)
 586
 587 {
 588         struct amdgpu_bo *shadow = bo->shadow;
 589         uint64_t bo_addr, shadow_addr;
 590         int r;
 591
 592         if (!shadow)
 593                 return -EINVAL;
 594
 595         bo_addr = amdgpu_bo_gpu_offset(bo);
 596         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 597
 598         r = reservation_object_reserve_shared(bo->tbo.resv);
 599         if (r)
 600                 goto err;
 601
 602         r = amdgpu_copy_buffer(ring, shadow_addr, bo_addr,
 603                                amdgpu_bo_size(bo), resv, fence,
 604                                direct, false);
 605         if (!r)
 606                 amdgpu_bo_fence(bo, *fence, true);
 607
 608 err:
 609         return r;
 610 }
 611
 612 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
 613 {
 614         void *kptr;
 615         long r;
 616
 617         if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 618                 return -EPERM;
 619
 620         kptr = amdgpu_bo_kptr(bo);
 621         if (kptr) {
 622                 if (ptr)
 623                         *ptr = kptr;
 624                 return 0;
 625         }
 626
 627         r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false,
 628                                                 MAX_SCHEDULE_TIMEOUT);
 629         if (r < 0)
 630                 return r;
 631
 632         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 633         if (r)
 634                 return r;
 635
 636         if (ptr)
 637                 *ptr = amdgpu_bo_kptr(bo);
 638
 639         return 0;
 640 }
 641
 642 void *amdgpu_bo_kptr(struct amdgpu_bo *bo)
 643 {
 644         bool is_iomem;
 645
 646         return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 647 }
 648
 649 void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
 650 {
 651         if (bo->kmap.bo)
 652                 ttm_bo_kunmap(&bo->kmap);
 653 }
 654
 655 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
 656 {
 657         if (bo == NULL)
 658                 return NULL;
 659
 660         ttm_bo_reference(&bo->tbo);
 661         return bo;
 662 }
 663
 664 void amdgpu_bo_unref(struct amdgpu_bo **bo)
 665 {
 666         struct ttm_buffer_object *tbo;
 667
 668         if ((*bo) == NULL)
 669                 return;
 670
 671         tbo = &((*bo)->tbo);
 672         ttm_bo_unref(&tbo);
 673         if (tbo == NULL)
 674                 *bo = NULL;
 675 }
 676
 677 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
 678                              u64 min_offset, u64 max_offset,
 679                              u64 *gpu_addr)
 680 {
 681         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 682         struct ttm_operation_ctx ctx = { false, false };
 683         int r, i;
 684
 685         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
 686                 return -EPERM;
 687
 688         if (WARN_ON_ONCE(min_offset > max_offset))
 689                 return -EINVAL;
 690
 691         /* A shared bo cannot be migrated to VRAM */
 692         if (bo->prime_shared_count && (domain == AMDGPU_GEM_DOMAIN_VRAM))
 693                 return -EINVAL;
 694
 695         if (bo->pin_count) {
 696                 uint32_t mem_type = bo->tbo.mem.mem_type;
 697
 698                 if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
 699                         return -EINVAL;
 700
 701                 bo->pin_count++;
 702                 if (gpu_addr)
 703                         *gpu_addr = amdgpu_bo_gpu_offset(bo);
 704
 705                 if (max_offset != 0) {
 706                         u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset;
 707                         WARN_ON_ONCE(max_offset <
 708                                      (amdgpu_bo_gpu_offset(bo) - domain_start));
 709                 }
 710
 711                 return 0;
 712         }
 713
 714         bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
 715         /* force to pin into visible video ram */
 716         if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
 717                 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 718         amdgpu_ttm_placement_from_domain(bo, domain);
 719         for (i = 0; i < bo->placement.num_placement; i++) {
 720                 unsigned fpfn, lpfn;
 721
 722                 fpfn = min_offset >> PAGE_SHIFT;
 723                 lpfn = max_offset >> PAGE_SHIFT;
 724
 725                 if (fpfn > bo->placements[i].fpfn)
 726                         bo->placements[i].fpfn = fpfn;
 727                 if (!bo->placements[i].lpfn ||
 728                     (lpfn && lpfn < bo->placements[i].lpfn))
 729                         bo->placements[i].lpfn = lpfn;
 730                 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
 731         }
 732
 733         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 734         if (unlikely(r)) {
 735                 dev_err(adev->dev, "%p pin failed\n", bo);
 736                 goto error;
 737         }
 738
 739         r = amdgpu_ttm_alloc_gart(&bo->tbo);
 740         if (unlikely(r)) {
 741                 dev_err(adev->dev, "%p bind failed\n", bo);
 742                 goto error;
 743         }
 744
 745         bo->pin_count = 1;
 746         if (gpu_addr != NULL)
 747                 *gpu_addr = amdgpu_bo_gpu_offset(bo);
 748
 749         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 750         if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
 751                 adev->vram_pin_size += amdgpu_bo_size(bo);
 752                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 753                         adev->invisible_pin_size += amdgpu_bo_size(bo);
 754         } else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
 755                 adev->gart_pin_size += amdgpu_bo_size(bo);
 756         }
 757
 758 error:
 759         return r;
 760 }
 761
 762 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
 763 {
 764         return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr);
 765 }
 766
 767 int amdgpu_bo_unpin(struct amdgpu_bo *bo)
 768 {
 769         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 770         struct ttm_operation_ctx ctx = { false, false };
 771         int r, i;
 772
 773         if (!bo->pin_count) {
 774                 dev_warn(adev->dev, "%p unpin not necessary\n", bo);
 775                 return 0;
 776         }
 777         bo->pin_count--;
 778         if (bo->pin_count)
 779                 return 0;
 780         for (i = 0; i < bo->placement.num_placement; i++) {
 781                 bo->placements[i].lpfn = 0;
 782                 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
 783         }
 784         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 785         if (unlikely(r)) {
 786                 dev_err(adev->dev, "%p validate failed for unpin\n", bo);
 787                 goto error;
 788         }
 789
 790         if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
 791                 adev->vram_pin_size -= amdgpu_bo_size(bo);
 792                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 793                         adev->invisible_pin_size -= amdgpu_bo_size(bo);
 794         } else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
 795                 adev->gart_pin_size -= amdgpu_bo_size(bo);
 796         }
 797
 798 error:
 799         return r;
 800 }
 801
 802 int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
 803 {
 804         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 805         if (0 && (adev->flags & AMD_IS_APU)) {
 806                 /* Useless to evict on IGP chips */
 807                 return 0;
 808         }
 809         return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
 810 }
 811
 812 static const char *amdgpu_vram_names[] = {
 813         "UNKNOWN",
 814         "GDDR1",
 815         "DDR2",
 816         "GDDR3",
 817         "GDDR4",
 818         "GDDR5",
 819         "HBM",
 820         "DDR3"
 821 };
 822
 823 int amdgpu_bo_init(struct amdgpu_device *adev)
 824 {
 825         /* reserve PAT memory space to WC for VRAM */
 826         arch_io_reserve_memtype_wc(adev->gmc.aper_base,
 827                                    adev->gmc.aper_size);
 828
 829         /* Add an MTRR for the VRAM */
 830         adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base,
 831                                               adev->gmc.aper_size);
 832         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 833                  adev->gmc.mc_vram_size >> 20,
 834                  (unsigned long long)adev->gmc.aper_size >> 20);
 835         DRM_INFO("RAM width %dbits %s\n",
 836                  adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]);
 837         return amdgpu_ttm_init(adev);
 838 }
 839
 840 void amdgpu_bo_fini(struct amdgpu_device *adev)
 841 {
 842         amdgpu_ttm_fini(adev);
 843         arch_phys_wc_del(adev->gmc.vram_mtrr);
 844         arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
 845 }
 846
 847 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
 848                              struct vm_area_struct *vma)
 849 {
 850         return ttm_fbdev_mmap(vma, &bo->tbo);
 851 }
 852
 853 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
 854 {
 855         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 856
 857         if (adev->family <= AMDGPU_FAMILY_CZ &&
 858             AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
 859                 return -EINVAL;
 860
 861         bo->tiling_flags = tiling_flags;
 862         return 0;
 863 }
 864
 865 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
 866 {
 867         lockdep_assert_held(&bo->tbo.resv->lock.base);
 868
 869         if (tiling_flags)
 870                 *tiling_flags = bo->tiling_flags;
 871 }
 872
 873 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
 874                             uint32_t metadata_size, uint64_t flags)
 875 {
 876         void *buffer;
 877
 878         if (!metadata_size) {
 879                 if (bo->metadata_size) {
 880                         kfree(bo->metadata);
 881                         bo->metadata = NULL;
 882                         bo->metadata_size = 0;
 883                 }
 884                 return 0;
 885         }
 886
 887         if (metadata == NULL)
 888                 return -EINVAL;
 889
 890         buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
 891         if (buffer == NULL)
 892                 return -ENOMEM;
 893
 894         kfree(bo->metadata);
 895         bo->metadata_flags = flags;
 896         bo->metadata = buffer;
 897         bo->metadata_size = metadata_size;
 898
 899         return 0;
 900 }
 901
 902 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
 903                            size_t buffer_size, uint32_t *metadata_size,
 904                            uint64_t *flags)
 905 {
 906         if (!buffer && !metadata_size)
 907                 return -EINVAL;
 908
 909         if (buffer) {
 910                 if (buffer_size < bo->metadata_size)
 911                         return -EINVAL;
 912
 913                 if (bo->metadata_size)
 914                         memcpy(buffer, bo->metadata, bo->metadata_size);
 915         }
 916
 917         if (metadata_size)
 918                 *metadata_size = bo->metadata_size;
 919         if (flags)
 920                 *flags = bo->metadata_flags;
 921
 922         return 0;
 923 }
 924
 925 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
 926                            bool evict,
 927                            struct ttm_mem_reg *new_mem)
 928 {
 929         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 930         struct amdgpu_bo *abo;
 931         struct ttm_mem_reg *old_mem = &bo->mem;
 932
 933         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 934                 return;
 935
 936         abo = ttm_to_amdgpu_bo(bo);
 937         amdgpu_vm_bo_invalidate(adev, abo, evict);
 938
 939         amdgpu_bo_kunmap(abo);
 940
 941         /* remember the eviction */
 942         if (evict)
 943                 atomic64_inc(&adev->num_evictions);
 944
 945         /* update statistics */
 946         if (!new_mem)
 947                 return;
 948
 949         /* move_notify is called before move happens */
 950         trace_amdgpu_ttm_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
 951 }
 952
 953 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 954 {
 955         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 956         struct ttm_operation_ctx ctx = { false, false };
 957         struct amdgpu_bo *abo;
 958         unsigned long offset, size;
 959         int r;
 960
 961         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 962                 return 0;
 963
 964         abo = ttm_to_amdgpu_bo(bo);
 965
 966         /* Remember that this BO was accessed by the CPU */
 967         abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 968
 969         if (bo->mem.mem_type != TTM_PL_VRAM)
 970                 return 0;
 971
 972         size = bo->mem.num_pages << PAGE_SHIFT;
 973         offset = bo->mem.start << PAGE_SHIFT;
 974         if ((offset + size) <= adev->gmc.visible_vram_size)
 975                 return 0;
 976
 977         /* Can't move a pinned BO to visible VRAM */
 978         if (abo->pin_count > 0)
 979                 return -EINVAL;
 980
 981         /* hurrah the memory is not visible ! */
 982         atomic64_inc(&adev->num_vram_cpu_page_faults);
 983         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 984                                          AMDGPU_GEM_DOMAIN_GTT);
 985
 986         /* Avoid costly evictions; only set GTT as a busy placement */
 987         abo->placement.num_busy_placement = 1;
 988         abo->placement.busy_placement = &abo->placements[1];
 989
 990         r = ttm_bo_validate(bo, &abo->placement, &ctx);
 991         if (unlikely(r != 0))
 992                 return r;
 993
 994         offset = bo->mem.start << PAGE_SHIFT;
 995         /* this should never happen */
 996         if (bo->mem.mem_type == TTM_PL_VRAM &&
 997             (offset + size) > adev->gmc.visible_vram_size)
 998                 return -EINVAL;
 999
1000         return 0;
1001 }
1002
1003 /**
1004  * amdgpu_bo_fence - add fence to buffer object
1005  *
1006  * @bo: buffer object in question
1007  * @fence: fence to add
1008  * @shared: true if fence should be added shared
1009  *
1010  */
1011 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
1012                      bool shared)
1013 {
1014         struct reservation_object *resv = bo->tbo.resv;
1015
1016         if (shared)
1017                 reservation_object_add_shared_fence(resv, fence);
1018         else
1019                 reservation_object_add_excl_fence(resv, fence);
1020 }
1021
1022 /**
1023  * amdgpu_bo_gpu_offset - return GPU offset of bo
1024  * @bo: amdgpu object for which we query the offset
1025  *
1026  * Returns current GPU offset of the object.
1027  *
1028  * Note: object should either be pinned or reserved when calling this
1029  * function, it might be useful to add check for this for debugging.
1030  */
1031 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
1032 {
1033         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
1034         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT &&
1035                      !amdgpu_gtt_mgr_has_gart_addr(&bo->tbo.mem));
1036         WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) &&
1037                      !bo->pin_count);
1038         WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
1039         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&
1040                      !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
1041
1042         return bo->tbo.offset;
1043 }