drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32
  33 #include "gc/gc_11_0_0_offset.h"
  34 #include "gc/gc_11_0_0_sh_mask.h"
  35 #include "gc/gc_11_0_0_default.h"
  36 #include "hdp/hdp_6_0_0_offset.h"
  37 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
  38
  39 #include "soc15_common.h"
  40 #include "soc15.h"
  41 #include "sdma_v6_0_0_pkt_open.h"
  42 #include "nbio_v4_3.h"
  43 #include "sdma_common.h"
  44 #include "sdma_v6_0.h"
  45 #include "v11_structs.h"
  46
  47 MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin");
  48 MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin");
  49 MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin");
  50 MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin");
  51
  52 #define SDMA1_REG_OFFSET 0x600
  53 #define SDMA0_HYP_DEC_REG_START 0x5880
  54 #define SDMA0_HYP_DEC_REG_END 0x589a
  55 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
  56
  57 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev);
  58 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev);
  59 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  60 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev);
  61 static int sdma_v6_0_start(struct amdgpu_device *adev);
  62
  63 static u32 sdma_v6_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
  64 {
  65         u32 base;
  66
  67         if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
  68             internal_offset <= SDMA0_HYP_DEC_REG_END) {
  69                 base = adev->reg_offset[GC_HWIP][0][1];
  70                 if (instance != 0)
  71                         internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
  72         } else {
  73                 base = adev->reg_offset[GC_HWIP][0][0];
  74                 if (instance == 1)
  75                         internal_offset += SDMA1_REG_OFFSET;
  76         }
  77
  78         return base + internal_offset;
  79 }
  80
  81 static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring)
  82 {
  83         unsigned ret;
  84
  85         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE));
  86         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
  87         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
  88         amdgpu_ring_write(ring, 1);
  89         ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
  90         amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
  91
  92         return ret;
  93 }
  94
  95 static void sdma_v6_0_ring_patch_cond_exec(struct amdgpu_ring *ring,
  96                                            unsigned offset)
  97 {
  98         unsigned cur;
  99
 100         BUG_ON(offset > ring->buf_mask);
 101         BUG_ON(ring->ring[offset] != 0x55aa55aa);
 102
 103         cur = (ring->wptr - 1) & ring->buf_mask;
 104         if (cur > offset)
 105                 ring->ring[offset] = cur - offset;
 106         else
 107                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
 108 }
 109
 110 /**
 111  * sdma_v6_0_ring_get_rptr - get the current read pointer
 112  *
 113  * @ring: amdgpu ring pointer
 114  *
 115  * Get the current rptr from the hardware.
 116  */
 117 static uint64_t sdma_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
 118 {
 119         u64 *rptr;
 120
 121         /* XXX check if swapping is necessary on BE */
 122         rptr = (u64 *)ring->rptr_cpu_addr;
 123
 124         DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
 125         return ((*rptr) >> 2);
 126 }
 127
 128 /**
 129  * sdma_v6_0_ring_get_wptr - get the current write pointer
 130  *
 131  * @ring: amdgpu ring pointer
 132  *
 133  * Get the current wptr from the hardware.
 134  */
 135 static uint64_t sdma_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
 136 {
 137         u64 wptr = 0;
 138
 139         if (ring->use_doorbell) {
 140                 /* XXX check if swapping is necessary on BE */
 141                 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
 142                 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
 143         }
 144
 145         return wptr >> 2;
 146 }
 147
 148 /**
 149  * sdma_v6_0_ring_set_wptr - commit the write pointer
 150  *
 151  * @ring: amdgpu ring pointer
 152  *
 153  * Write the wptr back to the hardware.
 154  */
 155 static void sdma_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
 156 {
 157         struct amdgpu_device *adev = ring->adev;
 158         uint32_t *wptr_saved;
 159         uint32_t *is_queue_unmap;
 160         uint64_t aggregated_db_index;
 161         uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_DMA].mqd_size;
 162
 163         DRM_DEBUG("Setting write pointer\n");
 164
 165         if (ring->is_mes_queue) {
 166                 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
 167                 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
 168                                               sizeof(uint32_t));
 169                 aggregated_db_index =
 170                         amdgpu_mes_get_aggregated_doorbell_index(adev,
 171                                                          ring->hw_prio);
 172
 173                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
 174                              ring->wptr << 2);
 175                 *wptr_saved = ring->wptr << 2;
 176                 if (*is_queue_unmap) {
 177                         WDOORBELL64(aggregated_db_index, ring->wptr << 2);
 178                         DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 179                                         ring->doorbell_index, ring->wptr << 2);
 180                         WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 181                 } else {
 182                         DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 183                                         ring->doorbell_index, ring->wptr << 2);
 184                         WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 185
 186                         if (*is_queue_unmap)
 187                                 WDOORBELL64(aggregated_db_index,
 188                                             ring->wptr << 2);
 189                 }
 190         } else {
 191                 if (ring->use_doorbell) {
 192                         DRM_DEBUG("Using doorbell -- "
 193                                   "wptr_offs == 0x%08x "
 194                                   "lower_32_bits(ring->wptr) << 2 == 0x%08x "
 195                                   "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
 196                                   ring->wptr_offs,
 197                                   lower_32_bits(ring->wptr << 2),
 198                                   upper_32_bits(ring->wptr << 2));
 199                         /* XXX check if swapping is necessary on BE */
 200                         atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
 201                                      ring->wptr << 2);
 202                         DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
 203                                   ring->doorbell_index, ring->wptr << 2);
 204                         WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
 205                 } else {
 206                         DRM_DEBUG("Not using doorbell -- "
 207                                   "regSDMA%i_GFX_RB_WPTR == 0x%08x "
 208                                   "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
 209                                   ring->me,
 210                                   lower_32_bits(ring->wptr << 2),
 211                                   ring->me,
 212                                   upper_32_bits(ring->wptr << 2));
 213                         WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,
 214                                         ring->me, regSDMA0_QUEUE0_RB_WPTR),
 215                                         lower_32_bits(ring->wptr << 2));
 216                         WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,
 217                                         ring->me, regSDMA0_QUEUE0_RB_WPTR_HI),
 218                                         upper_32_bits(ring->wptr << 2));
 219                 }
 220         }
 221 }
 222
 223 static void sdma_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 224 {
 225         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 226         int i;
 227
 228         for (i = 0; i < count; i++)
 229                 if (sdma && sdma->burst_nop && (i == 0))
 230                         amdgpu_ring_write(ring, ring->funcs->nop |
 231                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 232                 else
 233                         amdgpu_ring_write(ring, ring->funcs->nop);
 234 }
 235
 236 /**
 237  * sdma_v6_0_ring_emit_ib - Schedule an IB on the DMA engine
 238  *
 239  * @ring: amdgpu ring pointer
 240  * @ib: IB object to schedule
 241  *
 242  * Schedule an IB in the DMA ring.
 243  */
 244 static void sdma_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
 245                                    struct amdgpu_job *job,
 246                                    struct amdgpu_ib *ib,
 247                                    uint32_t flags)
 248 {
 249         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 250         uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
 251
 252         /* An IB packet must end on a 8 DW boundary--the next dword
 253          * must be on a 8-dword boundary. Our IB packet below is 6
 254          * dwords long, thus add x number of NOPs, such that, in
 255          * modular arithmetic,
 256          * wptr + 6 + x = 8k, k >= 0, which in C is,
 257          * (wptr + 6 + x) % 8 = 0.
 258          * The expression below, is a solution of x.
 259          */
 260         sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 261
 262         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) |
 263                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 264         /* base must be 32 byte aligned */
 265         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 266         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 267         amdgpu_ring_write(ring, ib->length_dw);
 268         amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
 269         amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
 270 }
 271
 272 /**
 273  * sdma_v6_0_ring_emit_mem_sync - flush the IB by graphics cache rinse
 274  *
 275  * @ring: amdgpu ring pointer
 276  *
 277  * flush the IB by graphics cache rinse.
 278  */
 279 static void sdma_v6_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
 280 {
 281         uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
 282                             SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
 283                             SDMA_GCR_GLI_INV(1);
 284
 285         /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
 286         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ));
 287         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
 288         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
 289                           SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
 290         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
 291                           SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
 292         amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
 293                           SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
 294 }
 295
 296
 297 /**
 298  * sdma_v6_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 299  *
 300  * @ring: amdgpu ring pointer
 301  *
 302  * Emit an hdp flush packet on the requested DMA ring.
 303  */
 304 static void sdma_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 305 {
 306         struct amdgpu_device *adev = ring->adev;
 307         u32 ref_and_mask = 0;
 308         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
 309
 310         ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
 311
 312         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 313                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 314                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 315         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
 316         amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
 317         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 318         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 319         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 320                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 321 }
 322
 323 /**
 324  * sdma_v6_0_ring_emit_fence - emit a fence on the DMA ring
 325  *
 326  * @ring: amdgpu ring pointer
 327  * @addr: address
 328  * @seq: fence seq number
 329  * @flags: fence flags
 330  *
 331  * Add a DMA fence packet to the ring to write
 332  * the fence seq number and DMA trap packet to generate
 333  * an interrupt if needed.
 334  */
 335 static void sdma_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 336                                       unsigned flags)
 337 {
 338         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 339         /* write the fence */
 340         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) |
 341                           SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
 342         /* zero in first two bits */
 343         BUG_ON(addr & 0x3);
 344         amdgpu_ring_write(ring, lower_32_bits(addr));
 345         amdgpu_ring_write(ring, upper_32_bits(addr));
 346         amdgpu_ring_write(ring, lower_32_bits(seq));
 347
 348         /* optionally write high bits as well */
 349         if (write64bit) {
 350                 addr += 4;
 351                 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) |
 352                                   SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
 353                 /* zero in first two bits */
 354                 BUG_ON(addr & 0x3);
 355                 amdgpu_ring_write(ring, lower_32_bits(addr));
 356                 amdgpu_ring_write(ring, upper_32_bits(addr));
 357                 amdgpu_ring_write(ring, upper_32_bits(seq));
 358         }
 359
 360         if (flags & AMDGPU_FENCE_FLAG_INT) {
 361                 uint32_t ctx = ring->is_mes_queue ?
 362                         (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
 363                 /* generate an interrupt */
 364                 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP));
 365                 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
 366         }
 367 }
 368
 369 /**
 370  * sdma_v6_0_gfx_stop - stop the gfx async dma engines
 371  *
 372  * @adev: amdgpu_device pointer
 373  *
 374  * Stop the gfx async dma ring buffers.
 375  */
 376 static void sdma_v6_0_gfx_stop(struct amdgpu_device *adev)
 377 {
 378         u32 rb_cntl, ib_cntl;
 379         int i;
 380
 381         amdgpu_sdma_unset_buffer_funcs_helper(adev);
 382
 383         for (i = 0; i < adev->sdma.num_instances; i++) {
 384                 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
 385                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0);
 386                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
 387                 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));
 388                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0);
 389                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);
 390         }
 391 }
 392
 393 /**
 394  * sdma_v6_0_rlc_stop - stop the compute async dma engines
 395  *
 396  * @adev: amdgpu_device pointer
 397  *
 398  * Stop the compute async dma queues.
 399  */
 400 static void sdma_v6_0_rlc_stop(struct amdgpu_device *adev)
 401 {
 402         /* XXX todo */
 403 }
 404
 405 /**
 406  * sdma_v6_0_ctxempty_int_enable - enable or disable context empty interrupts
 407  *
 408  * @adev: amdgpu_device pointer
 409  * @enable: enable/disable context switching due to queue empty conditions
 410  *
 411  * Enable or disable the async dma engines queue empty context switch.
 412  */
 413 static void sdma_v6_0_ctxempty_int_enable(struct amdgpu_device *adev, bool enable)
 414 {
 415         u32 f32_cntl;
 416         int i;
 417
 418         if (!amdgpu_sriov_vf(adev)) {
 419                 for (i = 0; i < adev->sdma.num_instances; i++) {
 420                         f32_cntl = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL));
 421                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 422                                         CTXEMPTY_INT_ENABLE, enable ? 1 : 0);
 423                         WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL), f32_cntl);
 424                 }
 425         }
 426 }
 427
 428 /**
 429  * sdma_v6_0_enable - stop the async dma engines
 430  *
 431  * @adev: amdgpu_device pointer
 432  * @enable: enable/disable the DMA MEs.
 433  *
 434  * Halt or unhalt the async dma engines.
 435  */
 436 static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable)
 437 {
 438         u32 f32_cntl;
 439         int i;
 440
 441         if (!enable) {
 442                 sdma_v6_0_gfx_stop(adev);
 443                 sdma_v6_0_rlc_stop(adev);
 444         }
 445
 446         if (amdgpu_sriov_vf(adev))
 447                 return;
 448
 449         for (i = 0; i < adev->sdma.num_instances; i++) {
 450                 f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
 451                 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
 452                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl);
 453         }
 454 }
 455
 456 /**
 457  * sdma_v6_0_gfx_resume - setup and start the async dma engines
 458  *
 459  * @adev: amdgpu_device pointer
 460  *
 461  * Set up the gfx DMA ring buffers and enable them.
 462  * Returns 0 for success, error for failure.
 463  */
 464 static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev)
 465 {
 466         struct amdgpu_ring *ring;
 467         u32 rb_cntl, ib_cntl;
 468         u32 rb_bufsz;
 469         u32 doorbell;
 470         u32 doorbell_offset;
 471         u32 temp;
 472         u64 wptr_gpu_addr;
 473         int i, r;
 474
 475         for (i = 0; i < adev->sdma.num_instances; i++) {
 476                 ring = &adev->sdma.instance[i].ring;
 477
 478                 if (!amdgpu_sriov_vf(adev))
 479                         WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
 480
 481                 /* Set ring buffer size in dwords */
 482                 rb_bufsz = order_base_2(ring->ring_size / 4);
 483                 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
 484                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz);
 485 #ifdef __BIG_ENDIAN
 486                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1);
 487                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL,
 488                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 489 #endif
 490                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1);
 491                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
 492
 493                 /* Initialize the ring buffer's read and write pointers */
 494                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);
 495                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);
 496                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);
 497                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);
 498
 499                 /* setup the wptr shadow polling */
 500                 wptr_gpu_addr = ring->wptr_gpu_addr;
 501                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),
 502                        lower_32_bits(wptr_gpu_addr));
 503                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI),
 504                        upper_32_bits(wptr_gpu_addr));
 505
 506                 /* set the wb address whether it's enabled or not */
 507                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI),
 508                        upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
 509                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO),
 510                        lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
 511
 512                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 513                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0);
 514                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1);
 515
 516                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);
 517                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);
 518
 519                 ring->wptr = 0;
 520
 521                 /* before programing wptr to a less value, need set minor_ptr_update first */
 522                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);
 523
 524                 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
 525                         WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);
 526                         WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
 527                 }
 528
 529                 doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL));
 530                 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET));
 531
 532                 if (ring->use_doorbell) {
 533                         doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);
 534                         doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET,
 535                                         OFFSET, ring->doorbell_index);
 536                 } else {
 537                         doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0);
 538                 }
 539                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell);
 540                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset);
 541
 542                 if (i == 0)
 543                         adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
 544                                                       ring->doorbell_index,
 545                                                       adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances);
 546
 547                 if (amdgpu_sriov_vf(adev))
 548                         sdma_v6_0_ring_set_wptr(ring);
 549
 550                 /* set minor_ptr_update to 0 after wptr programed */
 551                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0);
 552
 553                 /* Set up RESP_MODE to non-copy addresses */
 554                 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL));
 555                 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
 556                 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
 557                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp);
 558
 559                 /* program default cache read and write policy */
 560                 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE));
 561                 /* clean read policy and write policy bits */
 562                 temp &= 0xFF0FFF;
 563                 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
 564                          (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
 565                          SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
 566                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp);
 567
 568                 if (!amdgpu_sriov_vf(adev)) {
 569                         /* unhalt engine */
 570                         temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
 571                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
 572                         temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0);
 573                         WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp);
 574                 }
 575
 576                 /* enable DMA RB */
 577                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1);
 578                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
 579
 580                 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));
 581                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1);
 582 #ifdef __BIG_ENDIAN
 583                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1);
 584 #endif
 585                 /* enable DMA IBs */
 586                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);
 587
 588                 ring->sched.ready = true;
 589
 590                 if (amdgpu_sriov_vf(adev))
 591                         sdma_v6_0_enable(adev, true);
 592
 593                 r = amdgpu_ring_test_helper(ring);
 594                 if (r) {
 595                         ring->sched.ready = false;
 596                         return r;
 597                 }
 598
 599                 if (adev->mman.buffer_funcs_ring == ring)
 600                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 601         }
 602
 603         return 0;
 604 }
 605
 606 /**
 607  * sdma_v6_0_rlc_resume - setup and start the async dma engines
 608  *
 609  * @adev: amdgpu_device pointer
 610  *
 611  * Set up the compute DMA queues and enable them.
 612  * Returns 0 for success, error for failure.
 613  */
 614 static int sdma_v6_0_rlc_resume(struct amdgpu_device *adev)
 615 {
 616         return 0;
 617 }
 618
 619 /**
 620  * sdma_v6_0_load_microcode - load the sDMA ME ucode
 621  *
 622  * @adev: amdgpu_device pointer
 623  *
 624  * Loads the sDMA0/1 ucode.
 625  * Returns 0 for success, -EINVAL if the ucode is not available.
 626  */
 627 static int sdma_v6_0_load_microcode(struct amdgpu_device *adev)
 628 {
 629         const struct sdma_firmware_header_v2_0 *hdr;
 630         const __le32 *fw_data;
 631         u32 fw_size;
 632         int i, j;
 633         bool use_broadcast;
 634
 635         /* halt the MEs */
 636         sdma_v6_0_enable(adev, false);
 637
 638         if (!adev->sdma.instance[0].fw)
 639                 return -EINVAL;
 640
 641         /* use broadcast mode to load SDMA microcode by default */
 642         use_broadcast = true;
 643
 644         if (use_broadcast) {
 645                 dev_info(adev->dev, "Use broadcast method to load SDMA firmware\n");
 646                 /* load Control Thread microcode */
 647                 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data;
 648                 amdgpu_ucode_print_sdma_hdr(&hdr->header);
 649                 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4;
 650
 651                 fw_data = (const __le32 *)
 652                         (adev->sdma.instance[0].fw->data +
 653                                 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 654
 655                 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0);
 656
 657                 for (j = 0; j < fw_size; j++) {
 658                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 659                                 msleep(1);
 660                         WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++));
 661                 }
 662
 663                 /* load Context Switch microcode */
 664                 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4;
 665
 666                 fw_data = (const __le32 *)
 667                         (adev->sdma.instance[0].fw->data +
 668                                 le32_to_cpu(hdr->ctl_ucode_offset));
 669
 670                 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0x8000);
 671
 672                 for (j = 0; j < fw_size; j++) {
 673                         if (amdgpu_emu_mode == 1 && j % 500 == 0)
 674                                 msleep(1);
 675                         WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++));
 676                 }
 677         } else {
 678                 dev_info(adev->dev, "Use legacy method to load SDMA firmware\n");
 679                 for (i = 0; i < adev->sdma.num_instances; i++) {
 680                         /* load Control Thread microcode */
 681                         hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data;
 682                         amdgpu_ucode_print_sdma_hdr(&hdr->header);
 683                         fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4;
 684
 685                         fw_data = (const __le32 *)
 686                                 (adev->sdma.instance[0].fw->data +
 687                                         le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 688
 689                         WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0);
 690
 691                         for (j = 0; j < fw_size; j++) {
 692                                 if (amdgpu_emu_mode == 1 && j % 500 == 0)
 693                                         msleep(1);
 694                                 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 695                         }
 696
 697                         WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);
 698
 699                         /* load Context Switch microcode */
 700                         fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4;
 701
 702                         fw_data = (const __le32 *)
 703                                 (adev->sdma.instance[0].fw->data +
 704                                         le32_to_cpu(hdr->ctl_ucode_offset));
 705
 706                         WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0x8000);
 707
 708                         for (j = 0; j < fw_size; j++) {
 709                                 if (amdgpu_emu_mode == 1 && j % 500 == 0)
 710                                         msleep(1);
 711                                 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
 712                         }
 713
 714                         WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);
 715                 }
 716         }
 717
 718         return 0;
 719 }
 720
 721 static int sdma_v6_0_soft_reset(void *handle)
 722 {
 723         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 724         u32 tmp;
 725         int i;
 726
 727         sdma_v6_0_gfx_stop(adev);
 728
 729         for (i = 0; i < adev->sdma.num_instances; i++) {
 730                 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE));
 731                 tmp |= SDMA0_FREEZE__FREEZE_MASK;
 732                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp);
 733                 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
 734                 tmp |= SDMA0_F32_CNTL__HALT_MASK;
 735                 tmp |= SDMA0_F32_CNTL__TH1_RESET_MASK;
 736                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp);
 737
 738                 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0);
 739
 740                 udelay(100);
 741
 742                 tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i;
 743                 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp);
 744                 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
 745
 746                 udelay(100);
 747
 748                 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0);
 749                 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
 750
 751                 udelay(100);
 752         }
 753
 754         return sdma_v6_0_start(adev);
 755 }
 756
 757 static bool sdma_v6_0_check_soft_reset(void *handle)
 758 {
 759         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 760         struct amdgpu_ring *ring;
 761         int i, r;
 762         long tmo = msecs_to_jiffies(1000);
 763
 764         for (i = 0; i < adev->sdma.num_instances; i++) {
 765                 ring = &adev->sdma.instance[i].ring;
 766                 r = amdgpu_ring_test_ib(ring, tmo);
 767                 if (r)
 768                         return true;
 769         }
 770
 771         return false;
 772 }
 773
 774 /**
 775  * sdma_v6_0_start - setup and start the async dma engines
 776  *
 777  * @adev: amdgpu_device pointer
 778  *
 779  * Set up the DMA engines and enable them.
 780  * Returns 0 for success, error for failure.
 781  */
 782 static int sdma_v6_0_start(struct amdgpu_device *adev)
 783 {
 784         int r = 0;
 785
 786         if (amdgpu_sriov_vf(adev)) {
 787                 sdma_v6_0_enable(adev, false);
 788
 789                 /* set RB registers */
 790                 r = sdma_v6_0_gfx_resume(adev);
 791                 return r;
 792         }
 793
 794         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
 795                 r = sdma_v6_0_load_microcode(adev);
 796                 if (r)
 797                         return r;
 798
 799                 /* The value of regSDMA_F32_CNTL is invalid the moment after loading fw */
 800                 if (amdgpu_emu_mode == 1)
 801                         msleep(1000);
 802         }
 803
 804         /* unhalt the MEs */
 805         sdma_v6_0_enable(adev, true);
 806         /* enable sdma ring preemption */
 807         sdma_v6_0_ctxempty_int_enable(adev, true);
 808
 809         /* start the gfx rings and rlc compute queues */
 810         r = sdma_v6_0_gfx_resume(adev);
 811         if (r)
 812                 return r;
 813         r = sdma_v6_0_rlc_resume(adev);
 814
 815         return r;
 816 }
 817
 818 static int sdma_v6_0_mqd_init(struct amdgpu_device *adev, void *mqd,
 819                               struct amdgpu_mqd_prop *prop)
 820 {
 821         struct v11_sdma_mqd *m = mqd;
 822         uint64_t wb_gpu_addr;
 823
 824         m->sdmax_rlcx_rb_cntl =
 825                 order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT |
 826                 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
 827                 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
 828                 1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT;
 829
 830         m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
 831         m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
 832
 833         wb_gpu_addr = prop->wptr_gpu_addr;
 834         m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
 835         m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
 836
 837         wb_gpu_addr = prop->rptr_gpu_addr;
 838         m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
 839         m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
 840
 841         m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 0,
 842                                                         regSDMA0_QUEUE0_IB_CNTL));
 843
 844         m->sdmax_rlcx_doorbell_offset =
 845                 prop->doorbell_index << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT;
 846
 847         m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);
 848
 849         m->sdmax_rlcx_skip_cntl = 0;
 850         m->sdmax_rlcx_context_status = 0;
 851         m->sdmax_rlcx_doorbell_log = 0;
 852
 853         m->sdmax_rlcx_rb_aql_cntl = regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT;
 854         m->sdmax_rlcx_dummy_reg = regSDMA0_QUEUE0_DUMMY_REG_DEFAULT;
 855
 856         return 0;
 857 }
 858
 859 static void sdma_v6_0_set_mqd_funcs(struct amdgpu_device *adev)
 860 {
 861         adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v11_sdma_mqd);
 862         adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v6_0_mqd_init;
 863 }
 864
 865 /**
 866  * sdma_v6_0_ring_test_ring - simple async dma engine test
 867  *
 868  * @ring: amdgpu_ring structure holding ring information
 869  *
 870  * Test the DMA engine by writing using it to write an
 871  * value to memory.
 872  * Returns 0 for success, error for failure.
 873  */
 874 static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring)
 875 {
 876         struct amdgpu_device *adev = ring->adev;
 877         unsigned i;
 878         unsigned index;
 879         int r;
 880         u32 tmp;
 881         u64 gpu_addr;
 882         volatile uint32_t *cpu_ptr = NULL;
 883
 884         tmp = 0xCAFEDEAD;
 885
 886         if (ring->is_mes_queue) {
 887                 uint32_t offset = 0;
 888                 offset = amdgpu_mes_ctx_get_offs(ring,
 889                                          AMDGPU_MES_CTX_PADDING_OFFS);
 890                 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
 891                 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
 892                 *cpu_ptr = tmp;
 893         } else {
 894                 r = amdgpu_device_wb_get(adev, &index);
 895                 if (r) {
 896                         dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 897                         return r;
 898                 }
 899
 900                 gpu_addr = adev->wb.gpu_addr + (index * 4);
 901                 adev->wb.wb[index] = cpu_to_le32(tmp);
 902         }
 903
 904         r = amdgpu_ring_alloc(ring, 5);
 905         if (r) {
 906                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 907                 amdgpu_device_wb_free(adev, index);
 908                 return r;
 909         }
 910
 911         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
 912                           SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 913         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 914         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 915         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
 916         amdgpu_ring_write(ring, 0xDEADBEEF);
 917         amdgpu_ring_commit(ring);
 918
 919         for (i = 0; i < adev->usec_timeout; i++) {
 920                 if (ring->is_mes_queue)
 921                         tmp = le32_to_cpu(*cpu_ptr);
 922                 else
 923                         tmp = le32_to_cpu(adev->wb.wb[index]);
 924                 if (tmp == 0xDEADBEEF)
 925                         break;
 926                 if (amdgpu_emu_mode == 1)
 927                         msleep(1);
 928                 else
 929                         udelay(1);
 930         }
 931
 932         if (i >= adev->usec_timeout)
 933                 r = -ETIMEDOUT;
 934
 935         if (!ring->is_mes_queue)
 936                 amdgpu_device_wb_free(adev, index);
 937
 938         return r;
 939 }
 940
 941 /**
 942  * sdma_v6_0_ring_test_ib - test an IB on the DMA engine
 943  *
 944  * @ring: amdgpu_ring structure holding ring information
 945  *
 946  * Test a simple IB in the DMA ring.
 947  * Returns 0 on success, error on failure.
 948  */
 949 static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 950 {
 951         struct amdgpu_device *adev = ring->adev;
 952         struct amdgpu_ib ib;
 953         struct dma_fence *f = NULL;
 954         unsigned index;
 955         long r;
 956         u32 tmp = 0;
 957         u64 gpu_addr;
 958         volatile uint32_t *cpu_ptr = NULL;
 959
 960         tmp = 0xCAFEDEAD;
 961         memset(&ib, 0, sizeof(ib));
 962
 963         if (ring->is_mes_queue) {
 964                 uint32_t offset = 0;
 965                 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
 966                 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
 967                 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
 968
 969                 offset = amdgpu_mes_ctx_get_offs(ring,
 970                                          AMDGPU_MES_CTX_PADDING_OFFS);
 971                 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
 972                 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
 973                 *cpu_ptr = tmp;
 974         } else {
 975                 r = amdgpu_device_wb_get(adev, &index);
 976                 if (r) {
 977                         dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 978                         return r;
 979                 }
 980
 981                 gpu_addr = adev->wb.gpu_addr + (index * 4);
 982                 adev->wb.wb[index] = cpu_to_le32(tmp);
 983
 984                 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
 985                 if (r) {
 986                         DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 987                         goto err0;
 988                 }
 989         }
 990
 991         ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
 992                 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 993         ib.ptr[1] = lower_32_bits(gpu_addr);
 994         ib.ptr[2] = upper_32_bits(gpu_addr);
 995         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
 996         ib.ptr[4] = 0xDEADBEEF;
 997         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 998         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 999         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1000         ib.length_dw = 8;
1001
1002         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1003         if (r)
1004                 goto err1;
1005
1006         r = dma_fence_wait_timeout(f, false, timeout);
1007         if (r == 0) {
1008                 DRM_ERROR("amdgpu: IB test timed out\n");
1009                 r = -ETIMEDOUT;
1010                 goto err1;
1011         } else if (r < 0) {
1012                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1013                 goto err1;
1014         }
1015
1016         if (ring->is_mes_queue)
1017                 tmp = le32_to_cpu(*cpu_ptr);
1018         else
1019                 tmp = le32_to_cpu(adev->wb.wb[index]);
1020
1021         if (tmp == 0xDEADBEEF)
1022                 r = 0;
1023         else
1024                 r = -EINVAL;
1025
1026 err1:
1027         amdgpu_ib_free(adev, &ib, NULL);
1028         dma_fence_put(f);
1029 err0:
1030         if (!ring->is_mes_queue)
1031                 amdgpu_device_wb_free(adev, index);
1032         return r;
1033 }
1034
1035
1036 /**
1037  * sdma_v6_0_vm_copy_pte - update PTEs by copying them from the GART
1038  *
1039  * @ib: indirect buffer to fill with commands
1040  * @pe: addr of the page entry
1041  * @src: src addr to copy from
1042  * @count: number of page entries to update
1043  *
1044  * Update PTEs by copying them from the GART using sDMA.
1045  */
1046 static void sdma_v6_0_vm_copy_pte(struct amdgpu_ib *ib,
1047                                   uint64_t pe, uint64_t src,
1048                                   unsigned count)
1049 {
1050         unsigned bytes = count * 8;
1051
1052         ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
1053                 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1054         ib->ptr[ib->length_dw++] = bytes - 1;
1055         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1056         ib->ptr[ib->length_dw++] = lower_32_bits(src);
1057         ib->ptr[ib->length_dw++] = upper_32_bits(src);
1058         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1059         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1060
1061 }
1062
1063 /**
1064  * sdma_v6_0_vm_write_pte - update PTEs by writing them manually
1065  *
1066  * @ib: indirect buffer to fill with commands
1067  * @pe: addr of the page entry
1068  * @value: dst addr to write into pe
1069  * @count: number of page entries to update
1070  * @incr: increase next addr by incr bytes
1071  *
1072  * Update PTEs by writing them manually using sDMA.
1073  */
1074 static void sdma_v6_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1075                                    uint64_t value, unsigned count,
1076                                    uint32_t incr)
1077 {
1078         unsigned ndw = count * 2;
1079
1080         ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
1081                 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1082         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1083         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1084         ib->ptr[ib->length_dw++] = ndw - 1;
1085         for (; ndw > 0; ndw -= 2) {
1086                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1087                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1088                 value += incr;
1089         }
1090 }
1091
1092 /**
1093  * sdma_v6_0_vm_set_pte_pde - update the page tables using sDMA
1094  *
1095  * @ib: indirect buffer to fill with commands
1096  * @pe: addr of the page entry
1097  * @addr: dst addr to write into pe
1098  * @count: number of page entries to update
1099  * @incr: increase next addr by incr bytes
1100  * @flags: access flags
1101  *
1102  * Update the page tables using sDMA.
1103  */
1104 static void sdma_v6_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1105                                      uint64_t pe,
1106                                      uint64_t addr, unsigned count,
1107                                      uint32_t incr, uint64_t flags)
1108 {
1109         /* for physically contiguous pages (vram) */
1110         ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE);
1111         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1112         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1113         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1114         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1115         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1116         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1117         ib->ptr[ib->length_dw++] = incr; /* increment size */
1118         ib->ptr[ib->length_dw++] = 0;
1119         ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1120 }
1121
1122 /**
1123  * sdma_v6_0_ring_pad_ib - pad the IB
1124  * @ib: indirect buffer to fill with padding
1125  *
1126  * Pad the IB with NOPs to a boundary multiple of 8.
1127  */
1128 static void sdma_v6_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1129 {
1130         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1131         u32 pad_count;
1132         int i;
1133
1134         pad_count = (-ib->length_dw) & 0x7;
1135         for (i = 0; i < pad_count; i++)
1136                 if (sdma && sdma->burst_nop && (i == 0))
1137                         ib->ptr[ib->length_dw++] =
1138                                 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) |
1139                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1140                 else
1141                         ib->ptr[ib->length_dw++] =
1142                                 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP);
1143 }
1144
1145 /**
1146  * sdma_v6_0_ring_emit_pipeline_sync - sync the pipeline
1147  *
1148  * @ring: amdgpu_ring pointer
1149  *
1150  * Make sure all previous operations are completed (CIK).
1151  */
1152 static void sdma_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1153 {
1154         uint32_t seq = ring->fence_drv.sync_seq;
1155         uint64_t addr = ring->fence_drv.gpu_addr;
1156
1157         /* wait for idle */
1158         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1159                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1160                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1161                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1162         amdgpu_ring_write(ring, addr & 0xfffffffc);
1163         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1164         amdgpu_ring_write(ring, seq); /* reference */
1165         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1166         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1167                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1168 }
1169
1170 /**
1171  * sdma_v6_0_ring_emit_vm_flush - vm flush using sDMA
1172  *
1173  * @ring: amdgpu_ring pointer
1174  *
1175  * Update the page table base and flush the VM TLB
1176  * using sDMA.
1177  */
1178 static void sdma_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1179                                          unsigned vmid, uint64_t pd_addr)
1180 {
1181         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
1182         uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);
1183
1184         /* Update the PD address for this VMID. */
1185         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
1186                               (hub->ctx_addr_distance * vmid),
1187                               lower_32_bits(pd_addr));
1188         amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
1189                               (hub->ctx_addr_distance * vmid),
1190                               upper_32_bits(pd_addr));
1191
1192         /* Trigger invalidation. */
1193         amdgpu_ring_write(ring,
1194                           SDMA_PKT_VM_INVALIDATION_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1195                           SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(SDMA_SUBOP_VM_INVALIDATION) |
1196                           SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(ring->vm_inv_eng) |
1197                           SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(0x1f));
1198         amdgpu_ring_write(ring, req);
1199         amdgpu_ring_write(ring, 0xFFFFFFFF);
1200         amdgpu_ring_write(ring,
1201                           SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(1 << vmid) |
1202                           SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(0x1F));
1203 }
1204
1205 static void sdma_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
1206                                      uint32_t reg, uint32_t val)
1207 {
1208         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1209                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1210         amdgpu_ring_write(ring, reg);
1211         amdgpu_ring_write(ring, val);
1212 }
1213
1214 static void sdma_v6_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1215                                          uint32_t val, uint32_t mask)
1216 {
1217         amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1218                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1219                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1220         amdgpu_ring_write(ring, reg << 2);
1221         amdgpu_ring_write(ring, 0);
1222         amdgpu_ring_write(ring, val); /* reference */
1223         amdgpu_ring_write(ring, mask); /* mask */
1224         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1225                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1226 }
1227
1228 static void sdma_v6_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1229                                                    uint32_t reg0, uint32_t reg1,
1230                                                    uint32_t ref, uint32_t mask)
1231 {
1232         amdgpu_ring_emit_wreg(ring, reg0, ref);
1233         /* wait for a cycle to reset vm_inv_eng*_ack */
1234         amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1235         amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1236 }
1237
1238 static struct amdgpu_sdma_ras sdma_v6_0_3_ras = {
1239         .ras_block = {
1240                 .ras_late_init = amdgpu_ras_block_late_init,
1241         },
1242 };
1243
1244 static void sdma_v6_0_set_ras_funcs(struct amdgpu_device *adev)
1245 {
1246         switch (adev->ip_versions[SDMA0_HWIP][0]) {
1247         case IP_VERSION(6, 0, 3):
1248                 adev->sdma.ras = &sdma_v6_0_3_ras;
1249                 break;
1250         default:
1251                 break;
1252         }
1253
1254 }
1255
1256 static int sdma_v6_0_early_init(void *handle)
1257 {
1258         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1259
1260         sdma_v6_0_set_ring_funcs(adev);
1261         sdma_v6_0_set_buffer_funcs(adev);
1262         sdma_v6_0_set_vm_pte_funcs(adev);
1263         sdma_v6_0_set_irq_funcs(adev);
1264         sdma_v6_0_set_mqd_funcs(adev);
1265         sdma_v6_0_set_ras_funcs(adev);
1266
1267         return 0;
1268 }
1269
1270 static int sdma_v6_0_sw_init(void *handle)
1271 {
1272         struct amdgpu_ring *ring;
1273         int r, i;
1274         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1275
1276         /* SDMA trap event */
1277         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
1278                               GFX_11_0_0__SRCID__SDMA_TRAP,
1279                               &adev->sdma.trap_irq);
1280         if (r)
1281                 return r;
1282
1283         r = amdgpu_sdma_init_microcode(adev, 0, true);
1284         if (r) {
1285                 DRM_ERROR("Failed to load sdma firmware!\n");
1286                 return r;
1287         }
1288
1289         for (i = 0; i < adev->sdma.num_instances; i++) {
1290                 ring = &adev->sdma.instance[i].ring;
1291                 ring->ring_obj = NULL;
1292                 ring->use_doorbell = true;
1293                 ring->me = i;
1294
1295                 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1296                                 ring->use_doorbell?"true":"false");
1297
1298                 ring->doorbell_index =
1299                         (adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset
1300
1301                 ring->vm_hub = AMDGPU_GFXHUB_0;
1302                 sprintf(ring->name, "sdma%d", i);
1303                 r = amdgpu_ring_init(adev, ring, 1024,
1304                                      &adev->sdma.trap_irq,
1305                                      AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1306                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
1307                 if (r)
1308                         return r;
1309         }
1310
1311         if (amdgpu_sdma_ras_sw_init(adev)) {
1312                 dev_err(adev->dev, "Failed to initialize sdma ras block!\n");
1313                 return -EINVAL;
1314         }
1315
1316         return r;
1317 }
1318
1319 static int sdma_v6_0_sw_fini(void *handle)
1320 {
1321         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1322         int i;
1323
1324         for (i = 0; i < adev->sdma.num_instances; i++)
1325                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1326
1327         amdgpu_sdma_destroy_inst_ctx(adev, true);
1328
1329         return 0;
1330 }
1331
1332 static int sdma_v6_0_hw_init(void *handle)
1333 {
1334         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1335
1336         return sdma_v6_0_start(adev);
1337 }
1338
1339 static int sdma_v6_0_hw_fini(void *handle)
1340 {
1341         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1342
1343         if (amdgpu_sriov_vf(adev)) {
1344                 /* disable the scheduler for SDMA */
1345                 amdgpu_sdma_unset_buffer_funcs_helper(adev);
1346                 return 0;
1347         }
1348
1349         sdma_v6_0_ctxempty_int_enable(adev, false);
1350         sdma_v6_0_enable(adev, false);
1351
1352         return 0;
1353 }
1354
1355 static int sdma_v6_0_suspend(void *handle)
1356 {
1357         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1358
1359         return sdma_v6_0_hw_fini(adev);
1360 }
1361
1362 static int sdma_v6_0_resume(void *handle)
1363 {
1364         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1365
1366         return sdma_v6_0_hw_init(adev);
1367 }
1368
1369 static bool sdma_v6_0_is_idle(void *handle)
1370 {
1371         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1372         u32 i;
1373
1374         for (i = 0; i < adev->sdma.num_instances; i++) {
1375                 u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));
1376
1377                 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1378                         return false;
1379         }
1380
1381         return true;
1382 }
1383
1384 static int sdma_v6_0_wait_for_idle(void *handle)
1385 {
1386         unsigned i;
1387         u32 sdma0, sdma1;
1388         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1389
1390         for (i = 0; i < adev->usec_timeout; i++) {
1391                 sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG));
1392                 sdma1 = RREG32(sdma_v6_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG));
1393
1394                 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1395                         return 0;
1396                 udelay(1);
1397         }
1398         return -ETIMEDOUT;
1399 }
1400
1401 static int sdma_v6_0_ring_preempt_ib(struct amdgpu_ring *ring)
1402 {
1403         int i, r = 0;
1404         struct amdgpu_device *adev = ring->adev;
1405         u32 index = 0;
1406         u64 sdma_gfx_preempt;
1407
1408         amdgpu_sdma_get_index_from_ring(ring, &index);
1409         sdma_gfx_preempt =
1410                 sdma_v6_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT);
1411
1412         /* assert preemption condition */
1413         amdgpu_ring_set_preempt_cond_exec(ring, false);
1414
1415         /* emit the trailing fence */
1416         ring->trail_seq += 1;
1417         amdgpu_ring_alloc(ring, 10);
1418         sdma_v6_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1419                                   ring->trail_seq, 0);
1420         amdgpu_ring_commit(ring);
1421
1422         /* assert IB preemption */
1423         WREG32(sdma_gfx_preempt, 1);
1424
1425         /* poll the trailing fence */
1426         for (i = 0; i < adev->usec_timeout; i++) {
1427                 if (ring->trail_seq ==
1428                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1429                         break;
1430                 udelay(1);
1431         }
1432
1433         if (i >= adev->usec_timeout) {
1434                 r = -EINVAL;
1435                 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1436         }
1437
1438         /* deassert IB preemption */
1439         WREG32(sdma_gfx_preempt, 0);
1440
1441         /* deassert the preemption condition */
1442         amdgpu_ring_set_preempt_cond_exec(ring, true);
1443         return r;
1444 }
1445
1446 static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev,
1447                                         struct amdgpu_irq_src *source,
1448                                         unsigned type,
1449                                         enum amdgpu_interrupt_state state)
1450 {
1451         u32 sdma_cntl;
1452
1453         u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL);
1454
1455         if (!amdgpu_sriov_vf(adev)) {
1456                 sdma_cntl = RREG32(reg_offset);
1457                 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1458                                 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1459                 WREG32(reg_offset, sdma_cntl);
1460         }
1461
1462         return 0;
1463 }
1464
1465 static int sdma_v6_0_process_trap_irq(struct amdgpu_device *adev,
1466                                       struct amdgpu_irq_src *source,
1467                                       struct amdgpu_iv_entry *entry)
1468 {
1469         int instances, queue;
1470         uint32_t mes_queue_id = entry->src_data[0];
1471
1472         DRM_DEBUG("IH: SDMA trap\n");
1473
1474         if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1475                 struct amdgpu_mes_queue *queue;
1476
1477                 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1478
1479                 spin_lock(&adev->mes.queue_id_lock);
1480                 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1481                 if (queue) {
1482                         DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1483                         amdgpu_fence_process(queue->ring);
1484                 }
1485                 spin_unlock(&adev->mes.queue_id_lock);
1486                 return 0;
1487         }
1488
1489         queue = entry->ring_id & 0xf;
1490         instances = (entry->ring_id & 0xf0) >> 4;
1491         if (instances > 1) {
1492                 DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n");
1493                 return -EINVAL;
1494         }
1495
1496         switch (entry->client_id) {
1497         case SOC21_IH_CLIENTID_GFX:
1498                 switch (queue) {
1499                 case 0:
1500                         amdgpu_fence_process(&adev->sdma.instance[instances].ring);
1501                         break;
1502                 default:
1503                         break;
1504                 }
1505                 break;
1506         }
1507         return 0;
1508 }
1509
1510 static int sdma_v6_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1511                                               struct amdgpu_irq_src *source,
1512                                               struct amdgpu_iv_entry *entry)
1513 {
1514         return 0;
1515 }
1516
1517 static int sdma_v6_0_set_clockgating_state(void *handle,
1518                                            enum amd_clockgating_state state)
1519 {
1520         return 0;
1521 }
1522
1523 static int sdma_v6_0_set_powergating_state(void *handle,
1524                                           enum amd_powergating_state state)
1525 {
1526         return 0;
1527 }
1528
1529 static void sdma_v6_0_get_clockgating_state(void *handle, u64 *flags)
1530 {
1531 }
1532
1533 const struct amd_ip_funcs sdma_v6_0_ip_funcs = {
1534         .name = "sdma_v6_0",
1535         .early_init = sdma_v6_0_early_init,
1536         .late_init = NULL,
1537         .sw_init = sdma_v6_0_sw_init,
1538         .sw_fini = sdma_v6_0_sw_fini,
1539         .hw_init = sdma_v6_0_hw_init,
1540         .hw_fini = sdma_v6_0_hw_fini,
1541         .suspend = sdma_v6_0_suspend,
1542         .resume = sdma_v6_0_resume,
1543         .is_idle = sdma_v6_0_is_idle,
1544         .wait_for_idle = sdma_v6_0_wait_for_idle,
1545         .soft_reset = sdma_v6_0_soft_reset,
1546         .check_soft_reset = sdma_v6_0_check_soft_reset,
1547         .set_clockgating_state = sdma_v6_0_set_clockgating_state,
1548         .set_powergating_state = sdma_v6_0_set_powergating_state,
1549         .get_clockgating_state = sdma_v6_0_get_clockgating_state,
1550 };
1551
1552 static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = {
1553         .type = AMDGPU_RING_TYPE_SDMA,
1554         .align_mask = 0xf,
1555         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1556         .support_64bit_ptrs = true,
1557         .secure_submission_supported = true,
1558         .get_rptr = sdma_v6_0_ring_get_rptr,
1559         .get_wptr = sdma_v6_0_ring_get_wptr,
1560         .set_wptr = sdma_v6_0_ring_set_wptr,
1561         .emit_frame_size =
1562                 5 + /* sdma_v6_0_ring_init_cond_exec */
1563                 6 + /* sdma_v6_0_ring_emit_hdp_flush */
1564                 6 + /* sdma_v6_0_ring_emit_pipeline_sync */
1565                 /* sdma_v6_0_ring_emit_vm_flush */
1566                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1567                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1568                 10 + 10 + 10, /* sdma_v6_0_ring_emit_fence x3 for user fence, vm fence */
1569         .emit_ib_size = 5 + 7 + 6, /* sdma_v6_0_ring_emit_ib */
1570         .emit_ib = sdma_v6_0_ring_emit_ib,
1571         .emit_mem_sync = sdma_v6_0_ring_emit_mem_sync,
1572         .emit_fence = sdma_v6_0_ring_emit_fence,
1573         .emit_pipeline_sync = sdma_v6_0_ring_emit_pipeline_sync,
1574         .emit_vm_flush = sdma_v6_0_ring_emit_vm_flush,
1575         .emit_hdp_flush = sdma_v6_0_ring_emit_hdp_flush,
1576         .test_ring = sdma_v6_0_ring_test_ring,
1577         .test_ib = sdma_v6_0_ring_test_ib,
1578         .insert_nop = sdma_v6_0_ring_insert_nop,
1579         .pad_ib = sdma_v6_0_ring_pad_ib,
1580         .emit_wreg = sdma_v6_0_ring_emit_wreg,
1581         .emit_reg_wait = sdma_v6_0_ring_emit_reg_wait,
1582         .emit_reg_write_reg_wait = sdma_v6_0_ring_emit_reg_write_reg_wait,
1583         .init_cond_exec = sdma_v6_0_ring_init_cond_exec,
1584         .patch_cond_exec = sdma_v6_0_ring_patch_cond_exec,
1585         .preempt_ib = sdma_v6_0_ring_preempt_ib,
1586 };
1587
1588 static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev)
1589 {
1590         int i;
1591
1592         for (i = 0; i < adev->sdma.num_instances; i++) {
1593                 adev->sdma.instance[i].ring.funcs = &sdma_v6_0_ring_funcs;
1594                 adev->sdma.instance[i].ring.me = i;
1595         }
1596 }
1597
1598 static const struct amdgpu_irq_src_funcs sdma_v6_0_trap_irq_funcs = {
1599         .set = sdma_v6_0_set_trap_irq_state,
1600         .process = sdma_v6_0_process_trap_irq,
1601 };
1602
1603 static const struct amdgpu_irq_src_funcs sdma_v6_0_illegal_inst_irq_funcs = {
1604         .process = sdma_v6_0_process_illegal_inst_irq,
1605 };
1606
1607 static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1608 {
1609         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1610                                         adev->sdma.num_instances;
1611         adev->sdma.trap_irq.funcs = &sdma_v6_0_trap_irq_funcs;
1612         adev->sdma.illegal_inst_irq.funcs = &sdma_v6_0_illegal_inst_irq_funcs;
1613 }
1614
1615 /**
1616  * sdma_v6_0_emit_copy_buffer - copy buffer using the sDMA engine
1617  *
1618  * @ib: indirect buffer to fill with commands
1619  * @src_offset: src GPU address
1620  * @dst_offset: dst GPU address
1621  * @byte_count: number of bytes to xfer
1622  * @tmz: if a secure copy should be used
1623  *
1624  * Copy GPU buffers using the DMA engine.
1625  * Used by the amdgpu ttm implementation to move pages if
1626  * registered as the asic copy callback.
1627  */
1628 static void sdma_v6_0_emit_copy_buffer(struct amdgpu_ib *ib,
1629                                        uint64_t src_offset,
1630                                        uint64_t dst_offset,
1631                                        uint32_t byte_count,
1632                                        bool tmz)
1633 {
1634         ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
1635                 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1636                 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1637         ib->ptr[ib->length_dw++] = byte_count - 1;
1638         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1639         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1640         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1641         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1642         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1643 }
1644
1645 /**
1646  * sdma_v6_0_emit_fill_buffer - fill buffer using the sDMA engine
1647  *
1648  * @ib: indirect buffer to fill
1649  * @src_data: value to write to buffer
1650  * @dst_offset: dst GPU address
1651  * @byte_count: number of bytes to xfer
1652  *
1653  * Fill GPU buffers using the DMA engine.
1654  */
1655 static void sdma_v6_0_emit_fill_buffer(struct amdgpu_ib *ib,
1656                                        uint32_t src_data,
1657                                        uint64_t dst_offset,
1658                                        uint32_t byte_count)
1659 {
1660         ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_CONST_FILL);
1661         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1662         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1663         ib->ptr[ib->length_dw++] = src_data;
1664         ib->ptr[ib->length_dw++] = byte_count - 1;
1665 }
1666
1667 static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = {
1668         .copy_max_bytes = 0x400000,
1669         .copy_num_dw = 7,
1670         .emit_copy_buffer = sdma_v6_0_emit_copy_buffer,
1671
1672         .fill_max_bytes = 0x400000,
1673         .fill_num_dw = 5,
1674         .emit_fill_buffer = sdma_v6_0_emit_fill_buffer,
1675 };
1676
1677 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev)
1678 {
1679         adev->mman.buffer_funcs = &sdma_v6_0_buffer_funcs;
1680         adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1681 }
1682
1683 static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = {
1684         .copy_pte_num_dw = 7,
1685         .copy_pte = sdma_v6_0_vm_copy_pte,
1686         .write_pte = sdma_v6_0_vm_write_pte,
1687         .set_pte_pde = sdma_v6_0_vm_set_pte_pde,
1688 };
1689
1690 static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1691 {
1692         unsigned i;
1693
1694         adev->vm_manager.vm_pte_funcs = &sdma_v6_0_vm_pte_funcs;
1695         for (i = 0; i < adev->sdma.num_instances; i++) {
1696                 adev->vm_manager.vm_pte_scheds[i] =
1697                         &adev->sdma.instance[i].ring.sched;
1698         }
1699         adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1700 }
1701
1702 const struct amdgpu_ip_block_version sdma_v6_0_ip_block = {
1703         .type = AMD_IP_BLOCK_TYPE_SDMA,
1704         .major = 6,
1705         .minor = 0,
1706         .rev = 0,
1707         .funcs = &sdma_v6_0_ip_funcs,
1708 };