drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c

   1 /*
   2  * Copyright 2022 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "mmhub_v1_8.h"
  25
  26 #include "mmhub/mmhub_1_8_0_offset.h"
  27 #include "mmhub/mmhub_1_8_0_sh_mask.h"
  28 #include "vega10_enum.h"
  29
  30 #include "soc15_common.h"
  31 #include "soc15.h"
  32
  33 #define regVM_L2_CNTL3_DEFAULT  0x80100007
  34 #define regVM_L2_CNTL4_DEFAULT  0x000000c1
  35
  36 static u64 mmhub_v1_8_get_fb_location(struct amdgpu_device *adev)
  37 {
  38         u64 base = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE);
  39         u64 top = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP);
  40
  41         base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
  42         base <<= 24;
  43
  44         top &= MC_VM_FB_LOCATION_TOP__FB_TOP_MASK;
  45         top <<= 24;
  46
  47         adev->gmc.fb_start = base;
  48         adev->gmc.fb_end = top;
  49
  50         return base;
  51 }
  52
  53 static void mmhub_v1_8_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
  54                                 uint64_t page_table_base)
  55 {
  56         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
  57
  58         WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
  59                             hub->ctx_addr_distance * vmid, lower_32_bits(page_table_base));
  60
  61         WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
  62                             hub->ctx_addr_distance * vmid, upper_32_bits(page_table_base));
  63 }
  64
  65 static void mmhub_v1_8_init_gart_aperture_regs(struct amdgpu_device *adev)
  66 {
  67         uint64_t pt_base;
  68
  69         if (adev->gmc.pdb0_bo)
  70                 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo);
  71         else
  72                 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
  73
  74         mmhub_v1_8_setup_vm_pt_regs(adev, 0, pt_base);
  75
  76         /* If use GART for FB translation, vmid0 page table covers both
  77          * vram and system memory (gart)
  78          */
  79         if (adev->gmc.pdb0_bo) {
  80                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  81                              (u32)(adev->gmc.fb_start >> 12));
  82                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  83                              (u32)(adev->gmc.fb_start >> 44));
  84
  85                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
  86                              (u32)(adev->gmc.gart_end >> 12));
  87                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
  88                              (u32)(adev->gmc.gart_end >> 44));
  89
  90         } else {
  91                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  92                              (u32)(adev->gmc.gart_start >> 12));
  93                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  94                              (u32)(adev->gmc.gart_start >> 44));
  95
  96                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
  97                              (u32)(adev->gmc.gart_end >> 12));
  98                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
  99                              (u32)(adev->gmc.gart_end >> 44));
 100         }
 101 }
 102
 103 static void mmhub_v1_8_init_system_aperture_regs(struct amdgpu_device *adev)
 104 {
 105         uint64_t value;
 106         uint32_t tmp;
 107
 108         /* Program the AGP BAR */
 109         WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BASE, 0);
 110         WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
 111         WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
 112
 113         /* Program the system aperture low logical page number. */
 114         WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 115                      min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 116
 117         WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 118                      max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 119
 120         /* In the case squeezing vram into GART aperture, we don't use
 121          * FB aperture and AGP aperture. Disable them.
 122          */
 123         if (adev->gmc.pdb0_bo) {
 124                 WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BOT, 0xFFFFFF);
 125                 WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_TOP, 0);
 126                 WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP, 0);
 127                 WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);
 128                 WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF);
 129                 WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);
 130         }
 131         if (amdgpu_sriov_vf(adev))
 132                 return;
 133
 134         /* Set default page address. */
 135         value = amdgpu_gmc_vram_mc2pa(adev, adev->mem_scratch.gpu_addr);
 136         WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 137                      (u32)(value >> 12));
 138         WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 139                      (u32)(value >> 44));
 140
 141         /* Program "protection fault". */
 142         WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 143                      (u32)(adev->dummy_page_addr >> 12));
 144         WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 145                      (u32)((u64)adev->dummy_page_addr >> 44));
 146
 147         tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL2);
 148         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
 149                             ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 150         WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL2, tmp);
 151 }
 152
 153 static void mmhub_v1_8_init_tlb_regs(struct amdgpu_device *adev)
 154 {
 155         uint32_t tmp;
 156
 157         /* Setup TLB control */
 158         tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);
 159
 160         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 161         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 162         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 163                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 164         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 165                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 166         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 167                             MTYPE, MTYPE_UC);/* XXX for emulation. */
 168         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
 169
 170         WREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL, tmp);
 171 }
 172
 173 static void mmhub_v1_8_init_cache_regs(struct amdgpu_device *adev)
 174 {
 175         uint32_t tmp;
 176
 177         if (amdgpu_sriov_vf(adev))
 178                 return;
 179
 180         /* Setup L2 cache */
 181         tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL);
 182         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 183         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 184         /* XXX for emulation, Refer to closed source code.*/
 185         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
 186                             0);
 187         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
 188         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 189         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 190         WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL, tmp);
 191
 192         tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL2);
 193         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 194         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 195         WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL2, tmp);
 196
 197         tmp = regVM_L2_CNTL3_DEFAULT;
 198         if (adev->gmc.translate_further) {
 199                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
 200                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 201                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 202         } else {
 203                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
 204                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 205                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 206         }
 207         WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL3, tmp);
 208
 209         tmp = regVM_L2_CNTL4_DEFAULT;
 210         if (adev->gmc.xgmi.connected_to_cpu) {
 211                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
 212                                     VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
 213                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
 214                                     VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
 215         } else {
 216                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
 217                                     VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 218                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
 219                                     VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 220         }
 221         WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL4, tmp);
 222 }
 223
 224 static void mmhub_v1_8_enable_system_domain(struct amdgpu_device *adev)
 225 {
 226         uint32_t tmp;
 227
 228         tmp = RREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_CNTL);
 229         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 230         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,
 231                         adev->gmc.vmid0_page_table_depth);
 232         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,
 233                         adev->gmc.vmid0_page_table_block_size);
 234         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
 235                             RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 236         WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_CNTL, tmp);
 237 }
 238
 239 static void mmhub_v1_8_disable_identity_aperture(struct amdgpu_device *adev)
 240 {
 241         if (amdgpu_sriov_vf(adev))
 242                 return;
 243
 244         WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32, 0xFFFFFFFF);
 245         WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32, 0x0000000F);
 246
 247         WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
 248         WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
 249
 250         WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
 251         WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
 252 }
 253
 254 static void mmhub_v1_8_setup_vmid_config(struct amdgpu_device *adev)
 255 {
 256         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 257         unsigned num_level, block_size;
 258         uint32_t tmp;
 259         int i;
 260
 261         num_level = adev->vm_manager.num_level;
 262         block_size = adev->vm_manager.block_size;
 263         if (adev->gmc.translate_further)
 264                 num_level -= 1;
 265         else
 266                 block_size -= 9;
 267
 268         for (i = 0; i <= 14; i++) {
 269                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL, i);
 270                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 271                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 272                                     num_level);
 273                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 274                                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 275                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 276                                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 277                                     1);
 278                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 279                                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 280                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 281                                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 282                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 283                                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 284                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 285                                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 286                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 287                                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 288                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 289                                     PAGE_TABLE_BLOCK_SIZE,
 290                                     block_size);
 291                 /* On Aldebaran, XNACK can be enabled in the SQ per-process.
 292                  * Retry faults need to be enabled for that to work.
 293                  */
 294                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 295                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 296                                     1);
 297                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL,
 298                                     i * hub->ctx_distance, tmp);
 299                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
 300                                     i * hub->ctx_addr_distance, 0);
 301                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
 302                                     i * hub->ctx_addr_distance, 0);
 303                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
 304                                     i * hub->ctx_addr_distance,
 305                                     lower_32_bits(adev->vm_manager.max_pfn - 1));
 306                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
 307                                     i * hub->ctx_addr_distance,
 308                                     upper_32_bits(adev->vm_manager.max_pfn - 1));
 309         }
 310 }
 311
 312 static void mmhub_v1_8_program_invalidation(struct amdgpu_device *adev)
 313 {
 314         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 315         unsigned i;
 316
 317         for (i = 0; i < 18; ++i) {
 318                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 319                                     i * hub->eng_addr_distance, 0xffffffff);
 320                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 321                                     i * hub->eng_addr_distance, 0x1f);
 322         }
 323 }
 324
 325 static int mmhub_v1_8_gart_enable(struct amdgpu_device *adev)
 326 {
 327         if (amdgpu_sriov_vf(adev)) {
 328                 /*
 329                  * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
 330                  * VF copy registers so vbios post doesn't program them, for
 331                  * SRIOV driver need to program them
 332                  */
 333                 WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE,
 334                              adev->gmc.vram_start >> 24);
 335                 WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP,
 336                              adev->gmc.vram_end >> 24);
 337         }
 338
 339         /* GART Enable. */
 340         mmhub_v1_8_init_gart_aperture_regs(adev);
 341         mmhub_v1_8_init_system_aperture_regs(adev);
 342         mmhub_v1_8_init_tlb_regs(adev);
 343         mmhub_v1_8_init_cache_regs(adev);
 344
 345         mmhub_v1_8_enable_system_domain(adev);
 346         mmhub_v1_8_disable_identity_aperture(adev);
 347         mmhub_v1_8_setup_vmid_config(adev);
 348         mmhub_v1_8_program_invalidation(adev);
 349
 350         return 0;
 351 }
 352
 353 static void mmhub_v1_8_gart_disable(struct amdgpu_device *adev)
 354 {
 355         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 356         u32 tmp;
 357         u32 i;
 358
 359         /* Disable all tables */
 360         for (i = 0; i < 16; i++)
 361                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_CNTL,
 362                                     i * hub->ctx_distance, 0);
 363
 364         /* Setup TLB control */
 365         tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);
 366         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 367         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 368                             ENABLE_ADVANCED_DRIVER_MODEL, 0);
 369         WREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL, tmp);
 370
 371         if (!amdgpu_sriov_vf(adev)) {
 372                 /* Setup L2 cache */
 373                 tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL);
 374                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 375                 WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL, tmp);
 376                 WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL3, 0);
 377         }
 378 }
 379
 380 /**
 381  * mmhub_v1_8_set_fault_enable_default - update GART/VM fault handling
 382  *
 383  * @adev: amdgpu_device pointer
 384  * @value: true redirects VM faults to the default page
 385  */
 386 static void mmhub_v1_8_set_fault_enable_default(struct amdgpu_device *adev, bool value)
 387 {
 388         u32 tmp;
 389
 390         if (amdgpu_sriov_vf(adev))
 391                 return;
 392
 393         tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL);
 394         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 395                             RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 396         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 397                             PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 398         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 399                             PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 400         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 401                             PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 402         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 403                             TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 404                             value);
 405         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 406                             NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 407         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 408                             DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 409         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 410                             VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 411         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 412                             READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 413         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 414                             WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 415         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 416                             EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 417         if (!value) {
 418                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 419                                     CRASH_ON_NO_RETRY_FAULT, 1);
 420                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 421                                     CRASH_ON_RETRY_FAULT, 1);
 422         }
 423
 424         WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL, tmp);
 425 }
 426
 427 static void mmhub_v1_8_init(struct amdgpu_device *adev)
 428 {
 429         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 430
 431         hub->ctx0_ptb_addr_lo32 =
 432                 SOC15_REG_OFFSET(MMHUB, 0,
 433                                  regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 434         hub->ctx0_ptb_addr_hi32 =
 435                 SOC15_REG_OFFSET(MMHUB, 0,
 436                                  regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 437         hub->vm_inv_eng0_req =
 438                 SOC15_REG_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_REQ);
 439         hub->vm_inv_eng0_ack =
 440                 SOC15_REG_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ACK);
 441         hub->vm_context0_cntl =
 442                 SOC15_REG_OFFSET(MMHUB, 0, regVM_CONTEXT0_CNTL);
 443         hub->vm_l2_pro_fault_status =
 444                 SOC15_REG_OFFSET(MMHUB, 0, regVM_L2_PROTECTION_FAULT_STATUS);
 445         hub->vm_l2_pro_fault_cntl =
 446                 SOC15_REG_OFFSET(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL);
 447
 448         hub->ctx_distance = regVM_CONTEXT1_CNTL - regVM_CONTEXT0_CNTL;
 449         hub->ctx_addr_distance = regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
 450                 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
 451         hub->eng_distance = regVM_INVALIDATE_ENG1_REQ - regVM_INVALIDATE_ENG0_REQ;
 452         hub->eng_addr_distance = regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
 453                 regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
 454
 455 }
 456
 457 static int mmhub_v1_8_set_clockgating(struct amdgpu_device *adev,
 458                                       enum amd_clockgating_state state)
 459 {
 460         return 0;
 461 }
 462
 463 static void mmhub_v1_8_get_clockgating(struct amdgpu_device *adev, u64 *flags)
 464 {
 465
 466 }
 467
 468 const struct amdgpu_mmhub_funcs mmhub_v1_8_funcs = {
 469         .get_fb_location = mmhub_v1_8_get_fb_location,
 470         .init = mmhub_v1_8_init,
 471         .gart_enable = mmhub_v1_8_gart_enable,
 472         .set_fault_enable_default = mmhub_v1_8_set_fault_enable_default,
 473         .gart_disable = mmhub_v1_8_gart_disable,
 474         .setup_vm_pt_regs = mmhub_v1_8_setup_vm_pt_regs,
 475         .set_clockgating = mmhub_v1_8_set_clockgating,
 476         .get_clockgating = mmhub_v1_8_get_clockgating,
 477 };