drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "amdgpu.h"
  25 #include "amdgpu_jpeg.h"
  26 #include "soc15.h"
  27 #include "soc15d.h"
  28 #include "jpeg_v2_0.h"
  29 #include "jpeg_v2_5.h"
  30
  31 #include "vcn/vcn_2_5_offset.h"
  32 #include "vcn/vcn_2_5_sh_mask.h"
  33 #include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
  34
  35 #define mmUVD_JPEG_PITCH_INTERNAL_OFFSET                        0x401f
  36
  37 #define JPEG25_MAX_HW_INSTANCES_ARCTURUS                        2
  38
  39 static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
  40 static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev);
  41 static int jpeg_v2_5_set_powergating_state(void *handle,
  42                                 enum amd_powergating_state state);
  43 static void jpeg_v2_5_set_ras_funcs(struct amdgpu_device *adev);
  44
  45 static int amdgpu_ih_clientid_jpeg[] = {
  46         SOC15_IH_CLIENTID_VCN,
  47         SOC15_IH_CLIENTID_VCN1
  48 };
  49
  50 /**
  51  * jpeg_v2_5_early_init - set function pointers
  52  *
  53  * @handle: amdgpu_device pointer
  54  *
  55  * Set ring and irq function pointers
  56  */
  57 static int jpeg_v2_5_early_init(void *handle)
  58 {
  59         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  60         u32 harvest;
  61         int i;
  62
  63         adev->jpeg.num_jpeg_inst = JPEG25_MAX_HW_INSTANCES_ARCTURUS;
  64         for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
  65                 harvest = RREG32_SOC15(JPEG, i, mmCC_UVD_HARVESTING);
  66                 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK)
  67                         adev->jpeg.harvest_config |= 1 << i;
  68         }
  69         if (adev->jpeg.harvest_config == (AMDGPU_JPEG_HARVEST_JPEG0 |
  70                                          AMDGPU_JPEG_HARVEST_JPEG1))
  71                 return -ENOENT;
  72
  73         jpeg_v2_5_set_dec_ring_funcs(adev);
  74         jpeg_v2_5_set_irq_funcs(adev);
  75         jpeg_v2_5_set_ras_funcs(adev);
  76
  77         return 0;
  78 }
  79
  80 /**
  81  * jpeg_v2_5_sw_init - sw init for JPEG block
  82  *
  83  * @handle: amdgpu_device pointer
  84  *
  85  * Load firmware and sw initialization
  86  */
  87 static int jpeg_v2_5_sw_init(void *handle)
  88 {
  89         struct amdgpu_ring *ring;
  90         int i, r;
  91         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  92
  93         for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
  94                 if (adev->jpeg.harvest_config & (1 << i))
  95                         continue;
  96
  97                 /* JPEG TRAP */
  98                 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_jpeg[i],
  99                                 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst[i].irq);
 100                 if (r)
 101                         return r;
 102
 103                 /* JPEG DJPEG POISON EVENT */
 104                 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_jpeg[i],
 105                         VCN_2_6__SRCID_DJPEG0_POISON, &adev->jpeg.inst[i].irq);
 106                 if (r)
 107                         return r;
 108
 109                 /* JPEG EJPEG POISON EVENT */
 110                 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_jpeg[i],
 111                         VCN_2_6__SRCID_EJPEG0_POISON, &adev->jpeg.inst[i].irq);
 112                 if (r)
 113                         return r;
 114         }
 115
 116         r = amdgpu_jpeg_sw_init(adev);
 117         if (r)
 118                 return r;
 119
 120         r = amdgpu_jpeg_resume(adev);
 121         if (r)
 122                 return r;
 123
 124         for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
 125                 if (adev->jpeg.harvest_config & (1 << i))
 126                         continue;
 127
 128                 ring = &adev->jpeg.inst[i].ring_dec;
 129                 ring->use_doorbell = true;
 130                 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0))
 131                         ring->vm_hub = AMDGPU_MMHUB_1;
 132                 else
 133                         ring->vm_hub = AMDGPU_MMHUB_0;
 134                 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8 * i;
 135                 sprintf(ring->name, "jpeg_dec_%d", i);
 136                 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst[i].irq,
 137                                      0, AMDGPU_RING_PRIO_DEFAULT, NULL);
 138                 if (r)
 139                         return r;
 140
 141                 adev->jpeg.internal.jpeg_pitch = mmUVD_JPEG_PITCH_INTERNAL_OFFSET;
 142                 adev->jpeg.inst[i].external.jpeg_pitch = SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_PITCH);
 143         }
 144
 145         r = amdgpu_jpeg_ras_sw_init(adev);
 146         if (r)
 147                 return r;
 148
 149         return 0;
 150 }
 151
 152 /**
 153  * jpeg_v2_5_sw_fini - sw fini for JPEG block
 154  *
 155  * @handle: amdgpu_device pointer
 156  *
 157  * JPEG suspend and free up sw allocation
 158  */
 159 static int jpeg_v2_5_sw_fini(void *handle)
 160 {
 161         int r;
 162         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 163
 164         r = amdgpu_jpeg_suspend(adev);
 165         if (r)
 166                 return r;
 167
 168         r = amdgpu_jpeg_sw_fini(adev);
 169
 170         return r;
 171 }
 172
 173 /**
 174  * jpeg_v2_5_hw_init - start and test JPEG block
 175  *
 176  * @handle: amdgpu_device pointer
 177  *
 178  */
 179 static int jpeg_v2_5_hw_init(void *handle)
 180 {
 181         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 182         struct amdgpu_ring *ring;
 183         int i, r;
 184
 185         for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
 186                 if (adev->jpeg.harvest_config & (1 << i))
 187                         continue;
 188
 189                 ring = &adev->jpeg.inst[i].ring_dec;
 190                 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
 191                         (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 8 * i, i);
 192
 193                 r = amdgpu_ring_test_helper(ring);
 194                 if (r)
 195                         return r;
 196         }
 197
 198         DRM_INFO("JPEG decode initialized successfully.\n");
 199
 200         return 0;
 201 }
 202
 203 /**
 204  * jpeg_v2_5_hw_fini - stop the hardware block
 205  *
 206  * @handle: amdgpu_device pointer
 207  *
 208  * Stop the JPEG block, mark ring as not ready any more
 209  */
 210 static int jpeg_v2_5_hw_fini(void *handle)
 211 {
 212         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 213         int i;
 214
 215         cancel_delayed_work_sync(&adev->vcn.idle_work);
 216
 217         for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
 218                 if (adev->jpeg.harvest_config & (1 << i))
 219                         continue;
 220
 221                 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
 222                       RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS))
 223                         jpeg_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
 224         }
 225
 226         return 0;
 227 }
 228
 229 /**
 230  * jpeg_v2_5_suspend - suspend JPEG block
 231  *
 232  * @handle: amdgpu_device pointer
 233  *
 234  * HW fini and suspend JPEG block
 235  */
 236 static int jpeg_v2_5_suspend(void *handle)
 237 {
 238         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 239         int r;
 240
 241         r = jpeg_v2_5_hw_fini(adev);
 242         if (r)
 243                 return r;
 244
 245         r = amdgpu_jpeg_suspend(adev);
 246
 247         return r;
 248 }
 249
 250 /**
 251  * jpeg_v2_5_resume - resume JPEG block
 252  *
 253  * @handle: amdgpu_device pointer
 254  *
 255  * Resume firmware and hw init JPEG block
 256  */
 257 static int jpeg_v2_5_resume(void *handle)
 258 {
 259         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 260         int r;
 261
 262         r = amdgpu_jpeg_resume(adev);
 263         if (r)
 264                 return r;
 265
 266         r = jpeg_v2_5_hw_init(adev);
 267
 268         return r;
 269 }
 270
 271 static void jpeg_v2_5_disable_clock_gating(struct amdgpu_device *adev, int inst)
 272 {
 273         uint32_t data;
 274
 275         data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);
 276         if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
 277                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 278         else
 279                 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 280
 281         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 282         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 283         WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data);
 284
 285         data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE);
 286         data &= ~(JPEG_CGC_GATE__JPEG_DEC_MASK
 287                 | JPEG_CGC_GATE__JPEG2_DEC_MASK
 288                 | JPEG_CGC_GATE__JMCIF_MASK
 289                 | JPEG_CGC_GATE__JRBBM_MASK);
 290         WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data);
 291
 292         data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL);
 293         data &= ~(JPEG_CGC_CTRL__JPEG_DEC_MODE_MASK
 294                 | JPEG_CGC_CTRL__JPEG2_DEC_MODE_MASK
 295                 | JPEG_CGC_CTRL__JMCIF_MODE_MASK
 296                 | JPEG_CGC_CTRL__JRBBM_MODE_MASK);
 297         WREG32_SOC15(JPEG, inst, mmJPEG_CGC_CTRL, data);
 298 }
 299
 300 static void jpeg_v2_5_enable_clock_gating(struct amdgpu_device *adev, int inst)
 301 {
 302         uint32_t data;
 303
 304         data = RREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE);
 305         data |= (JPEG_CGC_GATE__JPEG_DEC_MASK
 306                 |JPEG_CGC_GATE__JPEG2_DEC_MASK
 307                 |JPEG_CGC_GATE__JPEG_ENC_MASK
 308                 |JPEG_CGC_GATE__JMCIF_MASK
 309                 |JPEG_CGC_GATE__JRBBM_MASK);
 310         WREG32_SOC15(JPEG, inst, mmJPEG_CGC_GATE, data);
 311 }
 312
 313 /**
 314  * jpeg_v2_5_start - start JPEG block
 315  *
 316  * @adev: amdgpu_device pointer
 317  *
 318  * Setup and start the JPEG block
 319  */
 320 static int jpeg_v2_5_start(struct amdgpu_device *adev)
 321 {
 322         struct amdgpu_ring *ring;
 323         int i;
 324
 325         for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
 326                 if (adev->jpeg.harvest_config & (1 << i))
 327                         continue;
 328
 329                 ring = &adev->jpeg.inst[i].ring_dec;
 330                 /* disable anti hang mechanism */
 331                 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS), 0,
 332                         ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
 333
 334                 /* JPEG disable CGC */
 335                 jpeg_v2_5_disable_clock_gating(adev, i);
 336
 337                 /* MJPEG global tiling registers */
 338                 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX8_ADDR_CONFIG,
 339                         adev->gfx.config.gb_addr_config);
 340                 WREG32_SOC15(JPEG, i, mmJPEG_DEC_GFX10_ADDR_CONFIG,
 341                         adev->gfx.config.gb_addr_config);
 342
 343                 /* enable JMI channel */
 344                 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL), 0,
 345                         ~UVD_JMI_CNTL__SOFT_RESET_MASK);
 346
 347                 /* enable System Interrupt for JRBC */
 348                 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmJPEG_SYS_INT_EN),
 349                         JPEG_SYS_INT_EN__DJRBC_MASK,
 350                         ~JPEG_SYS_INT_EN__DJRBC_MASK);
 351
 352                 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_VMID, 0);
 353                 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
 354                 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
 355                         lower_32_bits(ring->gpu_addr));
 356                 WREG32_SOC15(JPEG, i, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
 357                         upper_32_bits(ring->gpu_addr));
 358                 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_RPTR, 0);
 359                 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR, 0);
 360                 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_CNTL, 0x00000002L);
 361                 WREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_SIZE, ring->ring_size / 4);
 362                 ring->wptr = RREG32_SOC15(JPEG, i, mmUVD_JRBC_RB_WPTR);
 363         }
 364
 365         return 0;
 366 }
 367
 368 /**
 369  * jpeg_v2_5_stop - stop JPEG block
 370  *
 371  * @adev: amdgpu_device pointer
 372  *
 373  * stop the JPEG block
 374  */
 375 static int jpeg_v2_5_stop(struct amdgpu_device *adev)
 376 {
 377         int i;
 378
 379         for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
 380                 if (adev->jpeg.harvest_config & (1 << i))
 381                         continue;
 382
 383                 /* reset JMI */
 384                 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JMI_CNTL),
 385                         UVD_JMI_CNTL__SOFT_RESET_MASK,
 386                         ~UVD_JMI_CNTL__SOFT_RESET_MASK);
 387
 388                 jpeg_v2_5_enable_clock_gating(adev, i);
 389
 390                 /* enable anti hang mechanism */
 391                 WREG32_P(SOC15_REG_OFFSET(JPEG, i, mmUVD_JPEG_POWER_STATUS),
 392                         UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
 393                         ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
 394         }
 395
 396         return 0;
 397 }
 398
 399 /**
 400  * jpeg_v2_5_dec_ring_get_rptr - get read pointer
 401  *
 402  * @ring: amdgpu_ring pointer
 403  *
 404  * Returns the current hardware read pointer
 405  */
 406 static uint64_t jpeg_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring)
 407 {
 408         struct amdgpu_device *adev = ring->adev;
 409
 410         return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_RPTR);
 411 }
 412
 413 /**
 414  * jpeg_v2_5_dec_ring_get_wptr - get write pointer
 415  *
 416  * @ring: amdgpu_ring pointer
 417  *
 418  * Returns the current hardware write pointer
 419  */
 420 static uint64_t jpeg_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring)
 421 {
 422         struct amdgpu_device *adev = ring->adev;
 423
 424         if (ring->use_doorbell)
 425                 return *ring->wptr_cpu_addr;
 426         else
 427                 return RREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR);
 428 }
 429
 430 /**
 431  * jpeg_v2_5_dec_ring_set_wptr - set write pointer
 432  *
 433  * @ring: amdgpu_ring pointer
 434  *
 435  * Commits the write pointer to the hardware
 436  */
 437 static void jpeg_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
 438 {
 439         struct amdgpu_device *adev = ring->adev;
 440
 441         if (ring->use_doorbell) {
 442                 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
 443                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
 444         } else {
 445                 WREG32_SOC15(JPEG, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
 446         }
 447 }
 448
 449 /**
 450  * jpeg_v2_6_dec_ring_insert_start - insert a start command
 451  *
 452  * @ring: amdgpu_ring pointer
 453  *
 454  * Write a start command to the ring.
 455  */
 456 static void jpeg_v2_6_dec_ring_insert_start(struct amdgpu_ring *ring)
 457 {
 458         amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
 459                 0, 0, PACKETJ_TYPE0));
 460         amdgpu_ring_write(ring, 0x6aa04); /* PCTL0_MMHUB_DEEPSLEEP_IB */
 461
 462         amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
 463                 0, 0, PACKETJ_TYPE0));
 464         amdgpu_ring_write(ring, 0x80000000 | (1 << (ring->me * 2 + 14)));
 465 }
 466
 467 /**
 468  * jpeg_v2_6_dec_ring_insert_end - insert a end command
 469  *
 470  * @ring: amdgpu_ring pointer
 471  *
 472  * Write a end command to the ring.
 473  */
 474 static void jpeg_v2_6_dec_ring_insert_end(struct amdgpu_ring *ring)
 475 {
 476         amdgpu_ring_write(ring, PACKETJ(mmUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET,
 477                 0, 0, PACKETJ_TYPE0));
 478         amdgpu_ring_write(ring, 0x6aa04); /* PCTL0_MMHUB_DEEPSLEEP_IB */
 479
 480         amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR,
 481                 0, 0, PACKETJ_TYPE0));
 482         amdgpu_ring_write(ring, (1 << (ring->me * 2 + 14)));
 483 }
 484
 485 static bool jpeg_v2_5_is_idle(void *handle)
 486 {
 487         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 488         int i, ret = 1;
 489
 490         for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
 491                 if (adev->jpeg.harvest_config & (1 << i))
 492                         continue;
 493
 494                 ret &= (((RREG32_SOC15(JPEG, i, mmUVD_JRBC_STATUS) &
 495                         UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
 496                         UVD_JRBC_STATUS__RB_JOB_DONE_MASK));
 497         }
 498
 499         return ret;
 500 }
 501
 502 static int jpeg_v2_5_wait_for_idle(void *handle)
 503 {
 504         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 505         int i, ret;
 506
 507         for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
 508                 if (adev->jpeg.harvest_config & (1 << i))
 509                         continue;
 510
 511                 ret = SOC15_WAIT_ON_RREG(JPEG, i, mmUVD_JRBC_STATUS,
 512                         UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
 513                         UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
 514                 if (ret)
 515                         return ret;
 516         }
 517
 518         return 0;
 519 }
 520
 521 static int jpeg_v2_5_set_clockgating_state(void *handle,
 522                                           enum amd_clockgating_state state)
 523 {
 524         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 525         bool enable = (state == AMD_CG_STATE_GATE);
 526         int i;
 527
 528         for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
 529                 if (adev->jpeg.harvest_config & (1 << i))
 530                         continue;
 531
 532                 if (enable) {
 533                         if (!jpeg_v2_5_is_idle(handle))
 534                                 return -EBUSY;
 535                         jpeg_v2_5_enable_clock_gating(adev, i);
 536                 } else {
 537                         jpeg_v2_5_disable_clock_gating(adev, i);
 538                 }
 539         }
 540
 541         return 0;
 542 }
 543
 544 static int jpeg_v2_5_set_powergating_state(void *handle,
 545                                           enum amd_powergating_state state)
 546 {
 547         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 548         int ret;
 549
 550         if(state == adev->jpeg.cur_state)
 551                 return 0;
 552
 553         if (state == AMD_PG_STATE_GATE)
 554                 ret = jpeg_v2_5_stop(adev);
 555         else
 556                 ret = jpeg_v2_5_start(adev);
 557
 558         if(!ret)
 559                 adev->jpeg.cur_state = state;
 560
 561         return ret;
 562 }
 563
 564 static int jpeg_v2_5_set_interrupt_state(struct amdgpu_device *adev,
 565                                         struct amdgpu_irq_src *source,
 566                                         unsigned type,
 567                                         enum amdgpu_interrupt_state state)
 568 {
 569         return 0;
 570 }
 571
 572 static int jpeg_v2_5_process_interrupt(struct amdgpu_device *adev,
 573                                       struct amdgpu_irq_src *source,
 574                                       struct amdgpu_iv_entry *entry)
 575 {
 576         uint32_t ip_instance;
 577
 578         switch (entry->client_id) {
 579         case SOC15_IH_CLIENTID_VCN:
 580                 ip_instance = 0;
 581                 break;
 582         case SOC15_IH_CLIENTID_VCN1:
 583                 ip_instance = 1;
 584                 break;
 585         default:
 586                 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
 587                 return 0;
 588         }
 589
 590         DRM_DEBUG("IH: JPEG TRAP\n");
 591
 592         switch (entry->src_id) {
 593         case VCN_2_0__SRCID__JPEG_DECODE:
 594                 amdgpu_fence_process(&adev->jpeg.inst[ip_instance].ring_dec);
 595                 break;
 596         case VCN_2_6__SRCID_DJPEG0_POISON:
 597         case VCN_2_6__SRCID_EJPEG0_POISON:
 598                 amdgpu_jpeg_process_poison_irq(adev, source, entry);
 599                 break;
 600         default:
 601                 DRM_ERROR("Unhandled interrupt: %d %d\n",
 602                           entry->src_id, entry->src_data[0]);
 603                 break;
 604         }
 605
 606         return 0;
 607 }
 608
 609 static const struct amd_ip_funcs jpeg_v2_5_ip_funcs = {
 610         .name = "jpeg_v2_5",
 611         .early_init = jpeg_v2_5_early_init,
 612         .late_init = NULL,
 613         .sw_init = jpeg_v2_5_sw_init,
 614         .sw_fini = jpeg_v2_5_sw_fini,
 615         .hw_init = jpeg_v2_5_hw_init,
 616         .hw_fini = jpeg_v2_5_hw_fini,
 617         .suspend = jpeg_v2_5_suspend,
 618         .resume = jpeg_v2_5_resume,
 619         .is_idle = jpeg_v2_5_is_idle,
 620         .wait_for_idle = jpeg_v2_5_wait_for_idle,
 621         .check_soft_reset = NULL,
 622         .pre_soft_reset = NULL,
 623         .soft_reset = NULL,
 624         .post_soft_reset = NULL,
 625         .set_clockgating_state = jpeg_v2_5_set_clockgating_state,
 626         .set_powergating_state = jpeg_v2_5_set_powergating_state,
 627 };
 628
 629 static const struct amd_ip_funcs jpeg_v2_6_ip_funcs = {
 630         .name = "jpeg_v2_6",
 631         .early_init = jpeg_v2_5_early_init,
 632         .late_init = NULL,
 633         .sw_init = jpeg_v2_5_sw_init,
 634         .sw_fini = jpeg_v2_5_sw_fini,
 635         .hw_init = jpeg_v2_5_hw_init,
 636         .hw_fini = jpeg_v2_5_hw_fini,
 637         .suspend = jpeg_v2_5_suspend,
 638         .resume = jpeg_v2_5_resume,
 639         .is_idle = jpeg_v2_5_is_idle,
 640         .wait_for_idle = jpeg_v2_5_wait_for_idle,
 641         .check_soft_reset = NULL,
 642         .pre_soft_reset = NULL,
 643         .soft_reset = NULL,
 644         .post_soft_reset = NULL,
 645         .set_clockgating_state = jpeg_v2_5_set_clockgating_state,
 646         .set_powergating_state = jpeg_v2_5_set_powergating_state,
 647 };
 648
 649 static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = {
 650         .type = AMDGPU_RING_TYPE_VCN_JPEG,
 651         .align_mask = 0xf,
 652         .get_rptr = jpeg_v2_5_dec_ring_get_rptr,
 653         .get_wptr = jpeg_v2_5_dec_ring_get_wptr,
 654         .set_wptr = jpeg_v2_5_dec_ring_set_wptr,
 655         .emit_frame_size =
 656                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
 657                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
 658                 8 + /* jpeg_v2_5_dec_ring_emit_vm_flush */
 659                 18 + 18 + /* jpeg_v2_5_dec_ring_emit_fence x2 vm fence */
 660                 8 + 16,
 661         .emit_ib_size = 22, /* jpeg_v2_5_dec_ring_emit_ib */
 662         .emit_ib = jpeg_v2_0_dec_ring_emit_ib,
 663         .emit_fence = jpeg_v2_0_dec_ring_emit_fence,
 664         .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
 665         .test_ring = amdgpu_jpeg_dec_ring_test_ring,
 666         .test_ib = amdgpu_jpeg_dec_ring_test_ib,
 667         .insert_nop = jpeg_v2_0_dec_ring_nop,
 668         .insert_start = jpeg_v2_0_dec_ring_insert_start,
 669         .insert_end = jpeg_v2_0_dec_ring_insert_end,
 670         .pad_ib = amdgpu_ring_generic_pad_ib,
 671         .begin_use = amdgpu_jpeg_ring_begin_use,
 672         .end_use = amdgpu_jpeg_ring_end_use,
 673         .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
 674         .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
 675         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
 676 };
 677
 678 static const struct amdgpu_ring_funcs jpeg_v2_6_dec_ring_vm_funcs = {
 679         .type = AMDGPU_RING_TYPE_VCN_JPEG,
 680         .align_mask = 0xf,
 681         .get_rptr = jpeg_v2_5_dec_ring_get_rptr,
 682         .get_wptr = jpeg_v2_5_dec_ring_get_wptr,
 683         .set_wptr = jpeg_v2_5_dec_ring_set_wptr,
 684         .emit_frame_size =
 685                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
 686                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
 687                 8 + /* jpeg_v2_5_dec_ring_emit_vm_flush */
 688                 18 + 18 + /* jpeg_v2_5_dec_ring_emit_fence x2 vm fence */
 689                 8 + 16,
 690         .emit_ib_size = 22, /* jpeg_v2_5_dec_ring_emit_ib */
 691         .emit_ib = jpeg_v2_0_dec_ring_emit_ib,
 692         .emit_fence = jpeg_v2_0_dec_ring_emit_fence,
 693         .emit_vm_flush = jpeg_v2_0_dec_ring_emit_vm_flush,
 694         .test_ring = amdgpu_jpeg_dec_ring_test_ring,
 695         .test_ib = amdgpu_jpeg_dec_ring_test_ib,
 696         .insert_nop = jpeg_v2_0_dec_ring_nop,
 697         .insert_start = jpeg_v2_6_dec_ring_insert_start,
 698         .insert_end = jpeg_v2_6_dec_ring_insert_end,
 699         .pad_ib = amdgpu_ring_generic_pad_ib,
 700         .begin_use = amdgpu_jpeg_ring_begin_use,
 701         .end_use = amdgpu_jpeg_ring_end_use,
 702         .emit_wreg = jpeg_v2_0_dec_ring_emit_wreg,
 703         .emit_reg_wait = jpeg_v2_0_dec_ring_emit_reg_wait,
 704         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
 705 };
 706
 707 static void jpeg_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
 708 {
 709         int i;
 710
 711         for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
 712                 if (adev->jpeg.harvest_config & (1 << i))
 713                         continue;
 714                 if (adev->asic_type == CHIP_ARCTURUS)
 715                         adev->jpeg.inst[i].ring_dec.funcs = &jpeg_v2_5_dec_ring_vm_funcs;
 716                 else  /* CHIP_ALDEBARAN */
 717                         adev->jpeg.inst[i].ring_dec.funcs = &jpeg_v2_6_dec_ring_vm_funcs;
 718                 adev->jpeg.inst[i].ring_dec.me = i;
 719                 DRM_INFO("JPEG(%d) JPEG decode is enabled in VM mode\n", i);
 720         }
 721 }
 722
 723 static const struct amdgpu_irq_src_funcs jpeg_v2_5_irq_funcs = {
 724         .set = jpeg_v2_5_set_interrupt_state,
 725         .process = jpeg_v2_5_process_interrupt,
 726 };
 727
 728 static void jpeg_v2_5_set_irq_funcs(struct amdgpu_device *adev)
 729 {
 730         int i;
 731
 732         for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
 733                 if (adev->jpeg.harvest_config & (1 << i))
 734                         continue;
 735
 736                 adev->jpeg.inst[i].irq.num_types = 1;
 737                 adev->jpeg.inst[i].irq.funcs = &jpeg_v2_5_irq_funcs;
 738         }
 739 }
 740
 741 const struct amdgpu_ip_block_version jpeg_v2_5_ip_block =
 742 {
 743                 .type = AMD_IP_BLOCK_TYPE_JPEG,
 744                 .major = 2,
 745                 .minor = 5,
 746                 .rev = 0,
 747                 .funcs = &jpeg_v2_5_ip_funcs,
 748 };
 749
 750 const struct amdgpu_ip_block_version jpeg_v2_6_ip_block =
 751 {
 752                 .type = AMD_IP_BLOCK_TYPE_JPEG,
 753                 .major = 2,
 754                 .minor = 6,
 755                 .rev = 0,
 756                 .funcs = &jpeg_v2_6_ip_funcs,
 757 };
 758
 759 static uint32_t jpeg_v2_6_query_poison_by_instance(struct amdgpu_device *adev,
 760                 uint32_t instance, uint32_t sub_block)
 761 {
 762         uint32_t poison_stat = 0, reg_value = 0;
 763
 764         switch (sub_block) {
 765         case AMDGPU_JPEG_V2_6_JPEG0:
 766                 reg_value = RREG32_SOC15(JPEG, instance, mmUVD_RAS_JPEG0_STATUS);
 767                 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG0_STATUS, POISONED_PF);
 768                 break;
 769         case AMDGPU_JPEG_V2_6_JPEG1:
 770                 reg_value = RREG32_SOC15(JPEG, instance, mmUVD_RAS_JPEG1_STATUS);
 771                 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_JPEG1_STATUS, POISONED_PF);
 772                 break;
 773         default:
 774                 break;
 775         }
 776
 777         if (poison_stat)
 778                 dev_info(adev->dev, "Poison detected in JPEG%d sub_block%d\n",
 779                         instance, sub_block);
 780
 781         return poison_stat;
 782 }
 783
 784 static bool jpeg_v2_6_query_ras_poison_status(struct amdgpu_device *adev)
 785 {
 786         uint32_t inst = 0, sub = 0, poison_stat = 0;
 787
 788         for (inst = 0; inst < adev->jpeg.num_jpeg_inst; inst++)
 789                 for (sub = 0; sub < AMDGPU_JPEG_V2_6_MAX_SUB_BLOCK; sub++)
 790                         poison_stat +=
 791                         jpeg_v2_6_query_poison_by_instance(adev, inst, sub);
 792
 793         return !!poison_stat;
 794 }
 795
 796 const struct amdgpu_ras_block_hw_ops jpeg_v2_6_ras_hw_ops = {
 797         .query_poison_status = jpeg_v2_6_query_ras_poison_status,
 798 };
 799
 800 static struct amdgpu_jpeg_ras jpeg_v2_6_ras = {
 801         .ras_block = {
 802                 .hw_ops = &jpeg_v2_6_ras_hw_ops,
 803         },
 804 };
 805
 806 static void jpeg_v2_5_set_ras_funcs(struct amdgpu_device *adev)
 807 {
 808         switch (adev->ip_versions[JPEG_HWIP][0]) {
 809         case IP_VERSION(2, 6, 0):
 810                 adev->jpeg.ras = &jpeg_v2_6_ras;
 811                 break;
 812         default:
 813                 break;
 814         }
 815 }