drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32
  33 #include <linux/dma-mapping.h>
  34 #include <linux/iommu.h>
  35 #include <linux/pagemap.h>
  36 #include <linux/sched/task.h>
  37 #include <linux/sched/mm.h>
  38 #include <linux/seq_file.h>
  39 #include <linux/slab.h>
  40 #include <linux/swap.h>
  41 #include <linux/swiotlb.h>
  42 #include <linux/dma-buf.h>
  43 #include <linux/sizes.h>
  44
  45 #include <drm/ttm/ttm_bo_api.h>
  46 #include <drm/ttm/ttm_bo_driver.h>
  47 #include <drm/ttm/ttm_placement.h>
  48
  49 #include <drm/amdgpu_drm.h>
  50
  51 #include "amdgpu.h"
  52 #include "amdgpu_object.h"
  53 #include "amdgpu_trace.h"
  54 #include "amdgpu_amdkfd.h"
  55 #include "amdgpu_sdma.h"
  56 #include "amdgpu_ras.h"
  57 #include "amdgpu_atomfirmware.h"
  58 #include "amdgpu_res_cursor.h"
  59 #include "bif/bif_4_1_d.h"
  60
  61 #define AMDGPU_TTM_VRAM_MAX_DW_READ     (size_t)128
  62
  63 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
  64                                    struct ttm_tt *ttm,
  65                                    struct ttm_resource *bo_mem);
  66 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
  67                                       struct ttm_tt *ttm);
  68
  69 static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
  70                                     unsigned int type,
  71                                     uint64_t size_in_page)
  72 {
  73         return ttm_range_man_init(&adev->mman.bdev, type,
  74                                   false, size_in_page);
  75 }
  76
  77 /**
  78  * amdgpu_evict_flags - Compute placement flags
  79  *
  80  * @bo: The buffer object to evict
  81  * @placement: Possible destination(s) for evicted BO
  82  *
  83  * Fill in placement data when ttm_bo_evict() is called
  84  */
  85 static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
  86                                 struct ttm_placement *placement)
  87 {
  88         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
  89         struct amdgpu_bo *abo;
  90         static const struct ttm_place placements = {
  91                 .fpfn = 0,
  92                 .lpfn = 0,
  93                 .mem_type = TTM_PL_SYSTEM,
  94                 .flags = 0
  95         };
  96
  97         /* Don't handle scatter gather BOs */
  98         if (bo->type == ttm_bo_type_sg) {
  99                 placement->num_placement = 0;
 100                 placement->num_busy_placement = 0;
 101                 return;
 102         }
 103
 104         /* Object isn't an AMDGPU object so ignore */
 105         if (!amdgpu_bo_is_amdgpu_bo(bo)) {
 106                 placement->placement = &placements;
 107                 placement->busy_placement = &placements;
 108                 placement->num_placement = 1;
 109                 placement->num_busy_placement = 1;
 110                 return;
 111         }
 112
 113         abo = ttm_to_amdgpu_bo(bo);
 114         switch (bo->mem.mem_type) {
 115         case AMDGPU_PL_GDS:
 116         case AMDGPU_PL_GWS:
 117         case AMDGPU_PL_OA:
 118                 placement->num_placement = 0;
 119                 placement->num_busy_placement = 0;
 120                 return;
 121
 122         case TTM_PL_VRAM:
 123                 if (!adev->mman.buffer_funcs_enabled) {
 124                         /* Move to system memory */
 125                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 126                 } else if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
 127                            !(abo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) &&
 128                            amdgpu_bo_in_cpu_visible_vram(abo)) {
 129
 130                         /* Try evicting to the CPU inaccessible part of VRAM
 131                          * first, but only set GTT as busy placement, so this
 132                          * BO will be evicted to GTT rather than causing other
 133                          * BOs to be evicted from VRAM
 134                          */
 135                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 136                                                          AMDGPU_GEM_DOMAIN_GTT);
 137                         abo->placements[0].fpfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
 138                         abo->placements[0].lpfn = 0;
 139                         abo->placement.busy_placement = &abo->placements[1];
 140                         abo->placement.num_busy_placement = 1;
 141                 } else {
 142                         /* Move to GTT memory */
 143                         amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT);
 144                 }
 145                 break;
 146         case TTM_PL_TT:
 147         default:
 148                 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU);
 149                 break;
 150         }
 151         *placement = abo->placement;
 152 }
 153
 154 /**
 155  * amdgpu_verify_access - Verify access for a mmap call
 156  *
 157  * @bo: The buffer object to map
 158  * @filp: The file pointer from the process performing the mmap
 159  *
 160  * This is called by ttm_bo_mmap() to verify whether a process
 161  * has the right to mmap a BO to their process space.
 162  */
 163 static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp)
 164 {
 165         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 166
 167         if (amdgpu_ttm_tt_get_usermm(bo->ttm))
 168                 return -EPERM;
 169         return drm_vma_node_verify_access(&abo->tbo.base.vma_node,
 170                                           filp->private_data);
 171 }
 172
 173 /**
 174  * amdgpu_ttm_map_buffer - Map memory into the GART windows
 175  * @bo: buffer object to map
 176  * @mem: memory object to map
 177  * @mm_cur: range to map
 178  * @num_pages: number of pages to map
 179  * @window: which GART window to use
 180  * @ring: DMA ring to use for the copy
 181  * @tmz: if we should setup a TMZ enabled mapping
 182  * @addr: resulting address inside the MC address space
 183  *
 184  * Setup one of the GART windows to access a specific piece of memory or return
 185  * the physical address for local memory.
 186  */
 187 static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
 188                                  struct ttm_resource *mem,
 189                                  struct amdgpu_res_cursor *mm_cur,
 190                                  unsigned num_pages, unsigned window,
 191                                  struct amdgpu_ring *ring, bool tmz,
 192                                  uint64_t *addr)
 193 {
 194         struct amdgpu_device *adev = ring->adev;
 195         struct amdgpu_job *job;
 196         unsigned num_dw, num_bytes;
 197         struct dma_fence *fence;
 198         uint64_t src_addr, dst_addr;
 199         void *cpu_addr;
 200         uint64_t flags;
 201         unsigned int i;
 202         int r;
 203
 204         BUG_ON(adev->mman.buffer_funcs->copy_max_bytes <
 205                AMDGPU_GTT_MAX_TRANSFER_SIZE * 8);
 206
 207         /* Map only what can't be accessed directly */
 208         if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
 209                 *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) +
 210                         mm_cur->start;
 211                 return 0;
 212         }
 213
 214         *addr = adev->gmc.gart_start;
 215         *addr += (u64)window * AMDGPU_GTT_MAX_TRANSFER_SIZE *
 216                 AMDGPU_GPU_PAGE_SIZE;
 217         *addr += mm_cur->start & ~PAGE_MASK;
 218
 219         num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
 220         num_bytes = num_pages * 8;
 221
 222         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4 + num_bytes,
 223                                      AMDGPU_IB_POOL_DELAYED, &job);
 224         if (r)
 225                 return r;
 226
 227         src_addr = num_dw * 4;
 228         src_addr += job->ibs[0].gpu_addr;
 229
 230         dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 231         dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 232         amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 233                                 dst_addr, num_bytes, false);
 234
 235         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 236         WARN_ON(job->ibs[0].length_dw > num_dw);
 237
 238         flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, mem);
 239         if (tmz)
 240                 flags |= AMDGPU_PTE_TMZ;
 241
 242         cpu_addr = &job->ibs[0].ptr[num_dw];
 243
 244         if (mem->mem_type == TTM_PL_TT) {
 245                 dma_addr_t *dma_addr;
 246
 247                 dma_addr = &bo->ttm->dma_address[mm_cur->start >> PAGE_SHIFT];
 248                 r = amdgpu_gart_map(adev, 0, num_pages, dma_addr, flags,
 249                                     cpu_addr);
 250                 if (r)
 251                         goto error_free;
 252         } else {
 253                 dma_addr_t dma_address;
 254
 255                 dma_address = mm_cur->start;
 256                 dma_address += adev->vm_manager.vram_base_offset;
 257
 258                 for (i = 0; i < num_pages; ++i) {
 259                         r = amdgpu_gart_map(adev, i << PAGE_SHIFT, 1,
 260                                             &dma_address, flags, cpu_addr);
 261                         if (r)
 262                                 goto error_free;
 263
 264                         dma_address += PAGE_SIZE;
 265                 }
 266         }
 267
 268         r = amdgpu_job_submit(job, &adev->mman.entity,
 269                               AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 270         if (r)
 271                 goto error_free;
 272
 273         dma_fence_put(fence);
 274
 275         return r;
 276
 277 error_free:
 278         amdgpu_job_free(job);
 279         return r;
 280 }
 281
 282 /**
 283  * amdgpu_copy_ttm_mem_to_mem - Helper function for copy
 284  * @adev: amdgpu device
 285  * @src: buffer/address where to read from
 286  * @dst: buffer/address where to write to
 287  * @size: number of bytes to copy
 288  * @tmz: if a secure copy should be used
 289  * @resv: resv object to sync to
 290  * @f: Returns the last fence if multiple jobs are submitted.
 291  *
 292  * The function copies @size bytes from {src->mem + src->offset} to
 293  * {dst->mem + dst->offset}. src->bo and dst->bo could be same BO for a
 294  * move and different for a BO to BO copy.
 295  *
 296  */
 297 int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
 298                                const struct amdgpu_copy_mem *src,
 299                                const struct amdgpu_copy_mem *dst,
 300                                uint64_t size, bool tmz,
 301                                struct dma_resv *resv,
 302                                struct dma_fence **f)
 303 {
 304         const uint32_t GTT_MAX_BYTES = (AMDGPU_GTT_MAX_TRANSFER_SIZE *
 305                                         AMDGPU_GPU_PAGE_SIZE);
 306
 307         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
 308         struct amdgpu_res_cursor src_mm, dst_mm;
 309         struct dma_fence *fence = NULL;
 310         int r = 0;
 311
 312         if (!adev->mman.buffer_funcs_enabled) {
 313                 DRM_ERROR("Trying to move memory with ring turned off.\n");
 314                 return -EINVAL;
 315         }
 316
 317         amdgpu_res_first(src->mem, src->offset, size, &src_mm);
 318         amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm);
 319
 320         mutex_lock(&adev->mman.gtt_window_lock);
 321         while (src_mm.remaining) {
 322                 uint32_t src_page_offset = src_mm.start & ~PAGE_MASK;
 323                 uint32_t dst_page_offset = dst_mm.start & ~PAGE_MASK;
 324                 struct dma_fence *next;
 325                 uint32_t cur_size;
 326                 uint64_t from, to;
 327
 328                 /* Copy size cannot exceed GTT_MAX_BYTES. So if src or dst
 329                  * begins at an offset, then adjust the size accordingly
 330                  */
 331                 cur_size = max(src_page_offset, dst_page_offset);
 332                 cur_size = min(min3(src_mm.size, dst_mm.size, size),
 333                                (uint64_t)(GTT_MAX_BYTES - cur_size));
 334
 335                 /* Map src to window 0 and dst to window 1. */
 336                 r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm,
 337                                           PFN_UP(cur_size + src_page_offset),
 338                                           0, ring, tmz, &from);
 339                 if (r)
 340                         goto error;
 341
 342                 r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm,
 343                                           PFN_UP(cur_size + dst_page_offset),
 344                                           1, ring, tmz, &to);
 345                 if (r)
 346                         goto error;
 347
 348                 r = amdgpu_copy_buffer(ring, from, to, cur_size,
 349                                        resv, &next, false, true, tmz);
 350                 if (r)
 351                         goto error;
 352
 353                 dma_fence_put(fence);
 354                 fence = next;
 355
 356                 amdgpu_res_next(&src_mm, cur_size);
 357                 amdgpu_res_next(&dst_mm, cur_size);
 358         }
 359 error:
 360         mutex_unlock(&adev->mman.gtt_window_lock);
 361         if (f)
 362                 *f = dma_fence_get(fence);
 363         dma_fence_put(fence);
 364         return r;
 365 }
 366
 367 /*
 368  * amdgpu_move_blit - Copy an entire buffer to another buffer
 369  *
 370  * This is a helper called by amdgpu_bo_move() and amdgpu_move_vram_ram() to
 371  * help move buffers to and from VRAM.
 372  */
 373 static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 374                             bool evict,
 375                             struct ttm_resource *new_mem,
 376                             struct ttm_resource *old_mem)
 377 {
 378         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 379         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
 380         struct amdgpu_copy_mem src, dst;
 381         struct dma_fence *fence = NULL;
 382         int r;
 383
 384         src.bo = bo;
 385         dst.bo = bo;
 386         src.mem = old_mem;
 387         dst.mem = new_mem;
 388         src.offset = 0;
 389         dst.offset = 0;
 390
 391         r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
 392                                        new_mem->num_pages << PAGE_SHIFT,
 393                                        amdgpu_bo_encrypted(abo),
 394                                        bo->base.resv, &fence);
 395         if (r)
 396                 goto error;
 397
 398         /* clear the space being freed */
 399         if (old_mem->mem_type == TTM_PL_VRAM &&
 400             (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 401                 struct dma_fence *wipe_fence = NULL;
 402
 403                 r = amdgpu_fill_buffer(ttm_to_amdgpu_bo(bo), AMDGPU_POISON,
 404                                        NULL, &wipe_fence);
 405                 if (r) {
 406                         goto error;
 407                 } else if (wipe_fence) {
 408                         dma_fence_put(fence);
 409                         fence = wipe_fence;
 410                 }
 411         }
 412
 413         /* Always block for VM page tables before committing the new location */
 414         if (bo->type == ttm_bo_type_kernel)
 415                 r = ttm_bo_move_accel_cleanup(bo, fence, true, false, new_mem);
 416         else
 417                 r = ttm_bo_move_accel_cleanup(bo, fence, evict, true, new_mem);
 418         dma_fence_put(fence);
 419         return r;
 420
 421 error:
 422         if (fence)
 423                 dma_fence_wait(fence, false);
 424         dma_fence_put(fence);
 425         return r;
 426 }
 427
 428 /*
 429  * amdgpu_mem_visible - Check that memory can be accessed by ttm_bo_move_memcpy
 430  *
 431  * Called by amdgpu_bo_move()
 432  */
 433 static bool amdgpu_mem_visible(struct amdgpu_device *adev,
 434                                struct ttm_resource *mem)
 435 {
 436         uint64_t mem_size = (u64)mem->num_pages << PAGE_SHIFT;
 437         struct amdgpu_res_cursor cursor;
 438
 439         if (mem->mem_type == TTM_PL_SYSTEM ||
 440             mem->mem_type == TTM_PL_TT)
 441                 return true;
 442         if (mem->mem_type != TTM_PL_VRAM)
 443                 return false;
 444
 445         amdgpu_res_first(mem, 0, mem_size, &cursor);
 446
 447         /* ttm_resource_ioremap only supports contiguous memory */
 448         if (cursor.size != mem_size)
 449                 return false;
 450
 451         return cursor.start + cursor.size <= adev->gmc.visible_vram_size;
 452 }
 453
 454 /*
 455  * amdgpu_bo_move - Move a buffer object to a new memory location
 456  *
 457  * Called by ttm_bo_handle_move_mem()
 458  */
 459 static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict,
 460                           struct ttm_operation_ctx *ctx,
 461                           struct ttm_resource *new_mem,
 462                           struct ttm_place *hop)
 463 {
 464         struct amdgpu_device *adev;
 465         struct amdgpu_bo *abo;
 466         struct ttm_resource *old_mem = &bo->mem;
 467         int r;
 468
 469         if (new_mem->mem_type == TTM_PL_TT) {
 470                 r = amdgpu_ttm_backend_bind(bo->bdev, bo->ttm, new_mem);
 471                 if (r)
 472                         return r;
 473         }
 474
 475         /* Can't move a pinned BO */
 476         abo = ttm_to_amdgpu_bo(bo);
 477         if (WARN_ON_ONCE(abo->tbo.pin_count > 0))
 478                 return -EINVAL;
 479
 480         adev = amdgpu_ttm_adev(bo->bdev);
 481
 482         if (old_mem->mem_type == TTM_PL_SYSTEM && bo->ttm == NULL) {
 483                 ttm_bo_move_null(bo, new_mem);
 484                 goto out;
 485         }
 486         if (old_mem->mem_type == TTM_PL_SYSTEM &&
 487             new_mem->mem_type == TTM_PL_TT) {
 488                 ttm_bo_move_null(bo, new_mem);
 489                 goto out;
 490         }
 491         if (old_mem->mem_type == TTM_PL_TT &&
 492             new_mem->mem_type == TTM_PL_SYSTEM) {
 493                 r = ttm_bo_wait_ctx(bo, ctx);
 494                 if (r)
 495                         return r;
 496
 497                 amdgpu_ttm_backend_unbind(bo->bdev, bo->ttm);
 498                 ttm_resource_free(bo, &bo->mem);
 499                 ttm_bo_assign_mem(bo, new_mem);
 500                 goto out;
 501         }
 502
 503         if (old_mem->mem_type == AMDGPU_PL_GDS ||
 504             old_mem->mem_type == AMDGPU_PL_GWS ||
 505             old_mem->mem_type == AMDGPU_PL_OA ||
 506             new_mem->mem_type == AMDGPU_PL_GDS ||
 507             new_mem->mem_type == AMDGPU_PL_GWS ||
 508             new_mem->mem_type == AMDGPU_PL_OA) {
 509                 /* Nothing to save here */
 510                 ttm_bo_move_null(bo, new_mem);
 511                 goto out;
 512         }
 513
 514         if (adev->mman.buffer_funcs_enabled) {
 515                 if (((old_mem->mem_type == TTM_PL_SYSTEM &&
 516                       new_mem->mem_type == TTM_PL_VRAM) ||
 517                      (old_mem->mem_type == TTM_PL_VRAM &&
 518                       new_mem->mem_type == TTM_PL_SYSTEM))) {
 519                         hop->fpfn = 0;
 520                         hop->lpfn = 0;
 521                         hop->mem_type = TTM_PL_TT;
 522                         hop->flags = 0;
 523                         return -EMULTIHOP;
 524                 }
 525
 526                 r = amdgpu_move_blit(bo, evict, new_mem, old_mem);
 527         } else {
 528                 r = -ENODEV;
 529         }
 530
 531         if (r) {
 532                 /* Check that all memory is CPU accessible */
 533                 if (!amdgpu_mem_visible(adev, old_mem) ||
 534                     !amdgpu_mem_visible(adev, new_mem)) {
 535                         pr_err("Move buffer fallback to memcpy unavailable\n");
 536                         return r;
 537                 }
 538
 539                 r = ttm_bo_move_memcpy(bo, ctx, new_mem);
 540                 if (r)
 541                         return r;
 542         }
 543
 544         if (bo->type == ttm_bo_type_device &&
 545             new_mem->mem_type == TTM_PL_VRAM &&
 546             old_mem->mem_type != TTM_PL_VRAM) {
 547                 /* amdgpu_bo_fault_reserve_notify will re-set this if the CPU
 548                  * accesses the BO after it's moved.
 549                  */
 550                 abo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 551         }
 552
 553 out:
 554         /* update statistics */
 555         atomic64_add(bo->base.size, &adev->num_bytes_moved);
 556         amdgpu_bo_move_notify(bo, evict, new_mem);
 557         return 0;
 558 }
 559
 560 /*
 561  * amdgpu_ttm_io_mem_reserve - Reserve a block of memory during a fault
 562  *
 563  * Called by ttm_mem_io_reserve() ultimately via ttm_bo_vm_fault()
 564  */
 565 static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, struct ttm_resource *mem)
 566 {
 567         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 568         struct drm_mm_node *mm_node = mem->mm_node;
 569         size_t bus_size = (size_t)mem->num_pages << PAGE_SHIFT;
 570
 571         switch (mem->mem_type) {
 572         case TTM_PL_SYSTEM:
 573                 /* system memory */
 574                 return 0;
 575         case TTM_PL_TT:
 576                 break;
 577         case TTM_PL_VRAM:
 578                 mem->bus.offset = mem->start << PAGE_SHIFT;
 579                 /* check if it's visible */
 580                 if ((mem->bus.offset + bus_size) > adev->gmc.visible_vram_size)
 581                         return -EINVAL;
 582                 /* Only physically contiguous buffers apply. In a contiguous
 583                  * buffer, size of the first mm_node would match the number of
 584                  * pages in ttm_resource.
 585                  */
 586                 if (adev->mman.aper_base_kaddr &&
 587                     (mm_node->size == mem->num_pages))
 588                         mem->bus.addr = (u8 *)adev->mman.aper_base_kaddr +
 589                                         mem->bus.offset;
 590
 591                 mem->bus.offset += adev->gmc.aper_base;
 592                 mem->bus.is_iomem = true;
 593                 if (adev->gmc.xgmi.connected_to_cpu)
 594                         mem->bus.caching = ttm_cached;
 595                 else
 596                         mem->bus.caching = ttm_write_combined;
 597                 break;
 598         default:
 599                 return -EINVAL;
 600         }
 601         return 0;
 602 }
 603
 604 static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo,
 605                                            unsigned long page_offset)
 606 {
 607         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 608         struct amdgpu_res_cursor cursor;
 609
 610         amdgpu_res_first(&bo->mem, (u64)page_offset << PAGE_SHIFT, 0, &cursor);
 611         return (adev->gmc.aper_base + cursor.start) >> PAGE_SHIFT;
 612 }
 613
 614 /**
 615  * amdgpu_ttm_domain_start - Returns GPU start address
 616  * @adev: amdgpu device object
 617  * @type: type of the memory
 618  *
 619  * Returns:
 620  * GPU start address of a memory domain
 621  */
 622
 623 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type)
 624 {
 625         switch (type) {
 626         case TTM_PL_TT:
 627                 return adev->gmc.gart_start;
 628         case TTM_PL_VRAM:
 629                 return adev->gmc.vram_start;
 630         }
 631
 632         return 0;
 633 }
 634
 635 /*
 636  * TTM backend functions.
 637  */
 638 struct amdgpu_ttm_tt {
 639         struct ttm_tt   ttm;
 640         struct drm_gem_object   *gobj;
 641         u64                     offset;
 642         uint64_t                userptr;
 643         struct task_struct      *usertask;
 644         uint32_t                userflags;
 645         bool                    bound;
 646 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 647         struct hmm_range        *range;
 648 #endif
 649 };
 650
 651 #ifdef CONFIG_DRM_AMDGPU_USERPTR
 652 /*
 653  * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user
 654  * memory and start HMM tracking CPU page table update
 655  *
 656  * Calling function must call amdgpu_ttm_tt_userptr_range_done() once and only
 657  * once afterwards to stop HMM tracking
 658  */
 659 int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages)
 660 {
 661         struct ttm_tt *ttm = bo->tbo.ttm;
 662         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 663         unsigned long start = gtt->userptr;
 664         struct vm_area_struct *vma;
 665         struct mm_struct *mm;
 666         bool readonly;
 667         int r = 0;
 668
 669         mm = bo->notifier.mm;
 670         if (unlikely(!mm)) {
 671                 DRM_DEBUG_DRIVER("BO is not registered?\n");
 672                 return -EFAULT;
 673         }
 674
 675         /* Another get_user_pages is running at the same time?? */
 676         if (WARN_ON(gtt->range))
 677                 return -EFAULT;
 678
 679         if (!mmget_not_zero(mm)) /* Happens during process shutdown */
 680                 return -ESRCH;
 681
 682         mmap_read_lock(mm);
 683         vma = find_vma(mm, start);
 684         mmap_read_unlock(mm);
 685         if (unlikely(!vma || start < vma->vm_start)) {
 686                 r = -EFAULT;
 687                 goto out_putmm;
 688         }
 689         if (unlikely((gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) &&
 690                 vma->vm_file)) {
 691                 r = -EPERM;
 692                 goto out_putmm;
 693         }
 694
 695         readonly = amdgpu_ttm_tt_is_readonly(ttm);
 696         r = amdgpu_hmm_range_get_pages(&bo->notifier, mm, pages, start,
 697                                        ttm->num_pages, &gtt->range, readonly,
 698                                        false);
 699 out_putmm:
 700         mmput(mm);
 701
 702         return r;
 703 }
 704
 705 /*
 706  * amdgpu_ttm_tt_userptr_range_done - stop HMM track the CPU page table change
 707  * Check if the pages backing this ttm range have been invalidated
 708  *
 709  * Returns: true if pages are still valid
 710  */
 711 bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
 712 {
 713         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 714         bool r = false;
 715
 716         if (!gtt || !gtt->userptr)
 717                 return false;
 718
 719         DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n",
 720                 gtt->userptr, ttm->num_pages);
 721
 722         WARN_ONCE(!gtt->range || !gtt->range->hmm_pfns,
 723                 "No user pages to check\n");
 724
 725         if (gtt->range) {
 726                 /*
 727                  * FIXME: Must always hold notifier_lock for this, and must
 728                  * not ignore the return code.
 729                  */
 730                 r = amdgpu_hmm_range_get_pages_done(gtt->range);
 731                 gtt->range = NULL;
 732         }
 733
 734         return !r;
 735 }
 736 #endif
 737
 738 /*
 739  * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary.
 740  *
 741  * Called by amdgpu_cs_list_validate(). This creates the page list
 742  * that backs user memory and will ultimately be mapped into the device
 743  * address space.
 744  */
 745 void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages)
 746 {
 747         unsigned long i;
 748
 749         for (i = 0; i < ttm->num_pages; ++i)
 750                 ttm->pages[i] = pages ? pages[i] : NULL;
 751 }
 752
 753 /*
 754  * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages
 755  *
 756  * Called by amdgpu_ttm_backend_bind()
 757  **/
 758 static int amdgpu_ttm_tt_pin_userptr(struct ttm_device *bdev,
 759                                      struct ttm_tt *ttm)
 760 {
 761         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 762         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 763         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 764         enum dma_data_direction direction = write ?
 765                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 766         int r;
 767
 768         /* Allocate an SG array and squash pages into it */
 769         r = sg_alloc_table_from_pages(ttm->sg, ttm->pages, ttm->num_pages, 0,
 770                                       (u64)ttm->num_pages << PAGE_SHIFT,
 771                                       GFP_KERNEL);
 772         if (r)
 773                 goto release_sg;
 774
 775         /* Map SG to device */
 776         r = dma_map_sgtable(adev->dev, ttm->sg, direction, 0);
 777         if (r)
 778                 goto release_sg;
 779
 780         /* convert SG to linear array of pages and dma addresses */
 781         drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
 782                                        ttm->num_pages);
 783
 784         return 0;
 785
 786 release_sg:
 787         kfree(ttm->sg);
 788         ttm->sg = NULL;
 789         return r;
 790 }
 791
 792 /*
 793  * amdgpu_ttm_tt_unpin_userptr - Unpin and unmap userptr pages
 794  */
 795 static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev,
 796                                         struct ttm_tt *ttm)
 797 {
 798         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 799         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 800         int write = !(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
 801         enum dma_data_direction direction = write ?
 802                 DMA_BIDIRECTIONAL : DMA_TO_DEVICE;
 803
 804         /* double check that we don't free the table twice */
 805         if (!ttm->sg || !ttm->sg->sgl)
 806                 return;
 807
 808         /* unmap the pages mapped to the device */
 809         dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0);
 810         sg_free_table(ttm->sg);
 811
 812 #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
 813         if (gtt->range) {
 814                 unsigned long i;
 815
 816                 for (i = 0; i < ttm->num_pages; i++) {
 817                         if (ttm->pages[i] !=
 818                             hmm_pfn_to_page(gtt->range->hmm_pfns[i]))
 819                                 break;
 820                 }
 821
 822                 WARN((i == ttm->num_pages), "Missing get_user_page_done\n");
 823         }
 824 #endif
 825 }
 826
 827 static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
 828                                 struct ttm_buffer_object *tbo,
 829                                 uint64_t flags)
 830 {
 831         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(tbo);
 832         struct ttm_tt *ttm = tbo->ttm;
 833         struct amdgpu_ttm_tt *gtt = (void *)ttm;
 834         int r;
 835
 836         if (amdgpu_bo_encrypted(abo))
 837                 flags |= AMDGPU_PTE_TMZ;
 838
 839         if (abo->flags & AMDGPU_GEM_CREATE_CP_MQD_GFX9) {
 840                 uint64_t page_idx = 1;
 841
 842                 r = amdgpu_gart_bind(adev, gtt->offset, page_idx,
 843                                 ttm->pages, gtt->ttm.dma_address, flags);
 844                 if (r)
 845                         goto gart_bind_fail;
 846
 847                 /* The memory type of the first page defaults to UC. Now
 848                  * modify the memory type to NC from the second page of
 849                  * the BO onward.
 850                  */
 851                 flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
 852                 flags |= AMDGPU_PTE_MTYPE_VG10(AMDGPU_MTYPE_NC);
 853
 854                 r = amdgpu_gart_bind(adev,
 855                                 gtt->offset + (page_idx << PAGE_SHIFT),
 856                                 ttm->num_pages - page_idx,
 857                                 &ttm->pages[page_idx],
 858                                 &(gtt->ttm.dma_address[page_idx]), flags);
 859         } else {
 860                 r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 861                                      ttm->pages, gtt->ttm.dma_address, flags);
 862         }
 863
 864 gart_bind_fail:
 865         if (r)
 866                 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
 867                           ttm->num_pages, gtt->offset);
 868
 869         return r;
 870 }
 871
 872 /*
 873  * amdgpu_ttm_backend_bind - Bind GTT memory
 874  *
 875  * Called by ttm_tt_bind() on behalf of ttm_bo_handle_move_mem().
 876  * This handles binding GTT memory to the device address space.
 877  */
 878 static int amdgpu_ttm_backend_bind(struct ttm_device *bdev,
 879                                    struct ttm_tt *ttm,
 880                                    struct ttm_resource *bo_mem)
 881 {
 882         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
 883         struct amdgpu_ttm_tt *gtt = (void*)ttm;
 884         uint64_t flags;
 885         int r = 0;
 886
 887         if (!bo_mem)
 888                 return -EINVAL;
 889
 890         if (gtt->bound)
 891                 return 0;
 892
 893         if (gtt->userptr) {
 894                 r = amdgpu_ttm_tt_pin_userptr(bdev, ttm);
 895                 if (r) {
 896                         DRM_ERROR("failed to pin userptr\n");
 897                         return r;
 898                 }
 899         }
 900         if (!ttm->num_pages) {
 901                 WARN(1, "nothing to bind %u pages for mreg %p back %p!\n",
 902                      ttm->num_pages, bo_mem, ttm);
 903         }
 904
 905         if (bo_mem->mem_type == AMDGPU_PL_GDS ||
 906             bo_mem->mem_type == AMDGPU_PL_GWS ||
 907             bo_mem->mem_type == AMDGPU_PL_OA)
 908                 return -EINVAL;
 909
 910         if (!amdgpu_gtt_mgr_has_gart_addr(bo_mem)) {
 911                 gtt->offset = AMDGPU_BO_INVALID_OFFSET;
 912                 return 0;
 913         }
 914
 915         /* compute PTE flags relevant to this BO memory */
 916         flags = amdgpu_ttm_tt_pte_flags(adev, ttm, bo_mem);
 917
 918         /* bind pages into GART page tables */
 919         gtt->offset = (u64)bo_mem->start << PAGE_SHIFT;
 920         r = amdgpu_gart_bind(adev, gtt->offset, ttm->num_pages,
 921                 ttm->pages, gtt->ttm.dma_address, flags);
 922
 923         if (r)
 924                 DRM_ERROR("failed to bind %u pages at 0x%08llX\n",
 925                           ttm->num_pages, gtt->offset);
 926         gtt->bound = true;
 927         return r;
 928 }
 929
 930 /*
 931  * amdgpu_ttm_alloc_gart - Make sure buffer object is accessible either
 932  * through AGP or GART aperture.
 933  *
 934  * If bo is accessible through AGP aperture, then use AGP aperture
 935  * to access bo; otherwise allocate logical space in GART aperture
 936  * and map bo to GART aperture.
 937  */
 938 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo)
 939 {
 940         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 941         struct ttm_operation_ctx ctx = { false, false };
 942         struct amdgpu_ttm_tt *gtt = (void *)bo->ttm;
 943         struct ttm_resource tmp;
 944         struct ttm_placement placement;
 945         struct ttm_place placements;
 946         uint64_t addr, flags;
 947         int r;
 948
 949         if (bo->mem.start != AMDGPU_BO_INVALID_OFFSET)
 950                 return 0;
 951
 952         addr = amdgpu_gmc_agp_addr(bo);
 953         if (addr != AMDGPU_BO_INVALID_OFFSET) {
 954                 bo->mem.start = addr >> PAGE_SHIFT;
 955         } else {
 956
 957                 /* allocate GART space */
 958                 tmp = bo->mem;
 959                 tmp.mm_node = NULL;
 960                 placement.num_placement = 1;
 961                 placement.placement = &placements;
 962                 placement.num_busy_placement = 1;
 963                 placement.busy_placement = &placements;
 964                 placements.fpfn = 0;
 965                 placements.lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
 966                 placements.mem_type = TTM_PL_TT;
 967                 placements.flags = bo->mem.placement;
 968
 969                 r = ttm_bo_mem_space(bo, &placement, &tmp, &ctx);
 970                 if (unlikely(r))
 971                         return r;
 972
 973                 /* compute PTE flags for this buffer object */
 974                 flags = amdgpu_ttm_tt_pte_flags(adev, bo->ttm, &tmp);
 975
 976                 /* Bind pages */
 977                 gtt->offset = (u64)tmp.start << PAGE_SHIFT;
 978                 r = amdgpu_ttm_gart_bind(adev, bo, flags);
 979                 if (unlikely(r)) {
 980                         ttm_resource_free(bo, &tmp);
 981                         return r;
 982                 }
 983
 984                 ttm_resource_free(bo, &bo->mem);
 985                 bo->mem = tmp;
 986         }
 987
 988         return 0;
 989 }
 990
 991 /*
 992  * amdgpu_ttm_recover_gart - Rebind GTT pages
 993  *
 994  * Called by amdgpu_gtt_mgr_recover() from amdgpu_device_reset() to
 995  * rebind GTT pages during a GPU reset.
 996  */
 997 int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo)
 998 {
 999         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
1000         uint64_t flags;
1001         int r;
1002
1003         if (!tbo->ttm)
1004                 return 0;
1005
1006         flags = amdgpu_ttm_tt_pte_flags(adev, tbo->ttm, &tbo->mem);
1007         r = amdgpu_ttm_gart_bind(adev, tbo, flags);
1008
1009         return r;
1010 }
1011
1012 /*
1013  * amdgpu_ttm_backend_unbind - Unbind GTT mapped pages
1014  *
1015  * Called by ttm_tt_unbind() on behalf of ttm_bo_move_ttm() and
1016  * ttm_tt_destroy().
1017  */
1018 static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev,
1019                                       struct ttm_tt *ttm)
1020 {
1021         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1022         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1023         int r;
1024
1025         /* if the pages have userptr pinning then clear that first */
1026         if (gtt->userptr)
1027                 amdgpu_ttm_tt_unpin_userptr(bdev, ttm);
1028
1029         if (!gtt->bound)
1030                 return;
1031
1032         if (gtt->offset == AMDGPU_BO_INVALID_OFFSET)
1033                 return;
1034
1035         /* unbind shouldn't be done for GDS/GWS/OA in ttm_bo_clean_mm */
1036         r = amdgpu_gart_unbind(adev, gtt->offset, ttm->num_pages);
1037         if (r)
1038                 DRM_ERROR("failed to unbind %u pages at 0x%08llX\n",
1039                           gtt->ttm.num_pages, gtt->offset);
1040         gtt->bound = false;
1041 }
1042
1043 static void amdgpu_ttm_backend_destroy(struct ttm_device *bdev,
1044                                        struct ttm_tt *ttm)
1045 {
1046         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1047
1048         amdgpu_ttm_backend_unbind(bdev, ttm);
1049         ttm_tt_destroy_common(bdev, ttm);
1050         if (gtt->usertask)
1051                 put_task_struct(gtt->usertask);
1052
1053         ttm_tt_fini(&gtt->ttm);
1054         kfree(gtt);
1055 }
1056
1057 /**
1058  * amdgpu_ttm_tt_create - Create a ttm_tt object for a given BO
1059  *
1060  * @bo: The buffer object to create a GTT ttm_tt object around
1061  * @page_flags: Page flags to be added to the ttm_tt object
1062  *
1063  * Called by ttm_tt_create().
1064  */
1065 static struct ttm_tt *amdgpu_ttm_tt_create(struct ttm_buffer_object *bo,
1066                                            uint32_t page_flags)
1067 {
1068         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1069         struct amdgpu_ttm_tt *gtt;
1070         enum ttm_caching caching;
1071
1072         gtt = kzalloc(sizeof(struct amdgpu_ttm_tt), GFP_KERNEL);
1073         if (gtt == NULL) {
1074                 return NULL;
1075         }
1076         gtt->gobj = &bo->base;
1077
1078         if (abo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
1079                 caching = ttm_write_combined;
1080         else
1081                 caching = ttm_cached;
1082
1083         /* allocate space for the uninitialized page entries */
1084         if (ttm_sg_tt_init(&gtt->ttm, bo, page_flags, caching)) {
1085                 kfree(gtt);
1086                 return NULL;
1087         }
1088         return &gtt->ttm;
1089 }
1090
1091 /*
1092  * amdgpu_ttm_tt_populate - Map GTT pages visible to the device
1093  *
1094  * Map the pages of a ttm_tt object to an address space visible
1095  * to the underlying device.
1096  */
1097 static int amdgpu_ttm_tt_populate(struct ttm_device *bdev,
1098                                   struct ttm_tt *ttm,
1099                                   struct ttm_operation_ctx *ctx)
1100 {
1101         struct amdgpu_device *adev = amdgpu_ttm_adev(bdev);
1102         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1103
1104         /* user pages are bound by amdgpu_ttm_tt_pin_userptr() */
1105         if (gtt && gtt->userptr) {
1106                 ttm->sg = kzalloc(sizeof(struct sg_table), GFP_KERNEL);
1107                 if (!ttm->sg)
1108                         return -ENOMEM;
1109
1110                 ttm->page_flags |= TTM_PAGE_FLAG_SG;
1111                 return 0;
1112         }
1113
1114         if (ttm->page_flags & TTM_PAGE_FLAG_SG) {
1115                 if (!ttm->sg) {
1116                         struct dma_buf_attachment *attach;
1117                         struct sg_table *sgt;
1118
1119                         attach = gtt->gobj->import_attach;
1120                         sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL);
1121                         if (IS_ERR(sgt))
1122                                 return PTR_ERR(sgt);
1123
1124                         ttm->sg = sgt;
1125                 }
1126
1127                 drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address,
1128                                                ttm->num_pages);
1129                 return 0;
1130         }
1131
1132         return ttm_pool_alloc(&adev->mman.bdev.pool, ttm, ctx);
1133 }
1134
1135 /*
1136  * amdgpu_ttm_tt_unpopulate - unmap GTT pages and unpopulate page arrays
1137  *
1138  * Unmaps pages of a ttm_tt object from the device address space and
1139  * unpopulates the page array backing it.
1140  */
1141 static void amdgpu_ttm_tt_unpopulate(struct ttm_device *bdev,
1142                                      struct ttm_tt *ttm)
1143 {
1144         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1145         struct amdgpu_device *adev;
1146
1147         if (gtt && gtt->userptr) {
1148                 amdgpu_ttm_tt_set_user_pages(ttm, NULL);
1149                 kfree(ttm->sg);
1150                 ttm->page_flags &= ~TTM_PAGE_FLAG_SG;
1151                 return;
1152         }
1153
1154         if (ttm->sg && gtt->gobj->import_attach) {
1155                 struct dma_buf_attachment *attach;
1156
1157                 attach = gtt->gobj->import_attach;
1158                 dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL);
1159                 ttm->sg = NULL;
1160                 return;
1161         }
1162
1163         if (ttm->page_flags & TTM_PAGE_FLAG_SG)
1164                 return;
1165
1166         adev = amdgpu_ttm_adev(bdev);
1167         return ttm_pool_free(&adev->mman.bdev.pool, ttm);
1168 }
1169
1170 /**
1171  * amdgpu_ttm_tt_set_userptr - Initialize userptr GTT ttm_tt for the current
1172  * task
1173  *
1174  * @bo: The ttm_buffer_object to bind this userptr to
1175  * @addr:  The address in the current tasks VM space to use
1176  * @flags: Requirements of userptr object.
1177  *
1178  * Called by amdgpu_gem_userptr_ioctl() to bind userptr pages
1179  * to current task
1180  */
1181 int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
1182                               uint64_t addr, uint32_t flags)
1183 {
1184         struct amdgpu_ttm_tt *gtt;
1185
1186         if (!bo->ttm) {
1187                 /* TODO: We want a separate TTM object type for userptrs */
1188                 bo->ttm = amdgpu_ttm_tt_create(bo, 0);
1189                 if (bo->ttm == NULL)
1190                         return -ENOMEM;
1191         }
1192
1193         gtt = (void *)bo->ttm;
1194         gtt->userptr = addr;
1195         gtt->userflags = flags;
1196
1197         if (gtt->usertask)
1198                 put_task_struct(gtt->usertask);
1199         gtt->usertask = current->group_leader;
1200         get_task_struct(gtt->usertask);
1201
1202         return 0;
1203 }
1204
1205 /*
1206  * amdgpu_ttm_tt_get_usermm - Return memory manager for ttm_tt object
1207  */
1208 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm)
1209 {
1210         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1211
1212         if (gtt == NULL)
1213                 return NULL;
1214
1215         if (gtt->usertask == NULL)
1216                 return NULL;
1217
1218         return gtt->usertask->mm;
1219 }
1220
1221 /*
1222  * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an
1223  * address range for the current task.
1224  *
1225  */
1226 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1227                                   unsigned long end)
1228 {
1229         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1230         unsigned long size;
1231
1232         if (gtt == NULL || !gtt->userptr)
1233                 return false;
1234
1235         /* Return false if no part of the ttm_tt object lies within
1236          * the range
1237          */
1238         size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE;
1239         if (gtt->userptr > end || gtt->userptr + size <= start)
1240                 return false;
1241
1242         return true;
1243 }
1244
1245 /*
1246  * amdgpu_ttm_tt_is_userptr - Have the pages backing by userptr?
1247  */
1248 bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm)
1249 {
1250         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1251
1252         if (gtt == NULL || !gtt->userptr)
1253                 return false;
1254
1255         return true;
1256 }
1257
1258 /*
1259  * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only?
1260  */
1261 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
1262 {
1263         struct amdgpu_ttm_tt *gtt = (void *)ttm;
1264
1265         if (gtt == NULL)
1266                 return false;
1267
1268         return !!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY);
1269 }
1270
1271 /**
1272  * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
1273  *
1274  * @ttm: The ttm_tt object to compute the flags for
1275  * @mem: The memory registry backing this ttm_tt object
1276  *
1277  * Figure out the flags to use for a VM PDE (Page Directory Entry).
1278  */
1279 uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem)
1280 {
1281         uint64_t flags = 0;
1282
1283         if (mem && mem->mem_type != TTM_PL_SYSTEM)
1284                 flags |= AMDGPU_PTE_VALID;
1285
1286         if (mem && mem->mem_type == TTM_PL_TT) {
1287                 flags |= AMDGPU_PTE_SYSTEM;
1288
1289                 if (ttm->caching == ttm_cached)
1290                         flags |= AMDGPU_PTE_SNOOPED;
1291         }
1292
1293         if (mem && mem->mem_type == TTM_PL_VRAM &&
1294                         mem->bus.caching == ttm_cached)
1295                 flags |= AMDGPU_PTE_SNOOPED;
1296
1297         return flags;
1298 }
1299
1300 /**
1301  * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
1302  *
1303  * @adev: amdgpu_device pointer
1304  * @ttm: The ttm_tt object to compute the flags for
1305  * @mem: The memory registry backing this ttm_tt object
1306  *
1307  * Figure out the flags to use for a VM PTE (Page Table Entry).
1308  */
1309 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1310                                  struct ttm_resource *mem)
1311 {
1312         uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
1313
1314         flags |= adev->gart.gart_pte_flags;
1315         flags |= AMDGPU_PTE_READABLE;
1316
1317         if (!amdgpu_ttm_tt_is_readonly(ttm))
1318                 flags |= AMDGPU_PTE_WRITEABLE;
1319
1320         return flags;
1321 }
1322
1323 /*
1324  * amdgpu_ttm_bo_eviction_valuable - Check to see if we can evict a buffer
1325  * object.
1326  *
1327  * Return true if eviction is sensible. Called by ttm_mem_evict_first() on
1328  * behalf of ttm_bo_mem_force_space() which tries to evict buffer objects until
1329  * it can find space for a new object and by ttm_bo_force_list_clean() which is
1330  * used to clean out a memory space.
1331  */
1332 static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo,
1333                                             const struct ttm_place *place)
1334 {
1335         unsigned long num_pages = bo->mem.num_pages;
1336         struct amdgpu_res_cursor cursor;
1337         struct dma_resv_list *flist;
1338         struct dma_fence *f;
1339         int i;
1340
1341         if (bo->type == ttm_bo_type_kernel &&
1342             !amdgpu_vm_evictable(ttm_to_amdgpu_bo(bo)))
1343                 return false;
1344
1345         /* If bo is a KFD BO, check if the bo belongs to the current process.
1346          * If true, then return false as any KFD process needs all its BOs to
1347          * be resident to run successfully
1348          */
1349         flist = dma_resv_get_list(bo->base.resv);
1350         if (flist) {
1351                 for (i = 0; i < flist->shared_count; ++i) {
1352                         f = rcu_dereference_protected(flist->shared[i],
1353                                 dma_resv_held(bo->base.resv));
1354                         if (amdkfd_fence_check_mm(f, current->mm))
1355                                 return false;
1356                 }
1357         }
1358
1359         switch (bo->mem.mem_type) {
1360         case TTM_PL_TT:
1361                 if (amdgpu_bo_is_amdgpu_bo(bo) &&
1362                     amdgpu_bo_encrypted(ttm_to_amdgpu_bo(bo)))
1363                         return false;
1364                 return true;
1365
1366         case TTM_PL_VRAM:
1367                 /* Check each drm MM node individually */
1368                 amdgpu_res_first(&bo->mem, 0, (u64)num_pages << PAGE_SHIFT,
1369                                  &cursor);
1370                 while (cursor.remaining) {
1371                         if (place->fpfn < PFN_DOWN(cursor.start + cursor.size)
1372                             && !(place->lpfn &&
1373                                  place->lpfn <= PFN_DOWN(cursor.start)))
1374                                 return true;
1375
1376                         amdgpu_res_next(&cursor, cursor.size);
1377                 }
1378                 return false;
1379
1380         default:
1381                 break;
1382         }
1383
1384         return ttm_bo_eviction_valuable(bo, place);
1385 }
1386
1387 /**
1388  * amdgpu_ttm_access_memory - Read or Write memory that backs a buffer object.
1389  *
1390  * @bo:  The buffer object to read/write
1391  * @offset:  Offset into buffer object
1392  * @buf:  Secondary buffer to write/read from
1393  * @len: Length in bytes of access
1394  * @write:  true if writing
1395  *
1396  * This is used to access VRAM that backs a buffer object via MMIO
1397  * access for debugging purposes.
1398  */
1399 static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
1400                                     unsigned long offset, void *buf, int len,
1401                                     int write)
1402 {
1403         struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
1404         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
1405         struct amdgpu_res_cursor cursor;
1406         unsigned long flags;
1407         uint32_t value = 0;
1408         int ret = 0;
1409
1410         if (bo->mem.mem_type != TTM_PL_VRAM)
1411                 return -EIO;
1412
1413         amdgpu_res_first(&bo->mem, offset, len, &cursor);
1414         while (cursor.remaining) {
1415                 uint64_t aligned_pos = cursor.start & ~(uint64_t)3;
1416                 uint64_t bytes = 4 - (cursor.start & 3);
1417                 uint32_t shift = (cursor.start & 3) * 8;
1418                 uint32_t mask = 0xffffffff << shift;
1419
1420                 if (cursor.size < bytes) {
1421                         mask &= 0xffffffff >> (bytes - cursor.size) * 8;
1422                         bytes = cursor.size;
1423                 }
1424
1425                 if (mask != 0xffffffff) {
1426                         spin_lock_irqsave(&adev->mmio_idx_lock, flags);
1427                         WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)aligned_pos) | 0x80000000);
1428                         WREG32_NO_KIQ(mmMM_INDEX_HI, aligned_pos >> 31);
1429                         value = RREG32_NO_KIQ(mmMM_DATA);
1430                         if (write) {
1431                                 value &= ~mask;
1432                                 value |= (*(uint32_t *)buf << shift) & mask;
1433                                 WREG32_NO_KIQ(mmMM_DATA, value);
1434                         }
1435                         spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
1436                         if (!write) {
1437                                 value = (value & mask) >> shift;
1438                                 memcpy(buf, &value, bytes);
1439                         }
1440                 } else {
1441                         bytes = cursor.size & ~0x3ULL;
1442                         amdgpu_device_vram_access(adev, cursor.start,
1443                                                   (uint32_t *)buf, bytes,
1444                                                   write);
1445                 }
1446
1447                 ret += bytes;
1448                 buf = (uint8_t *)buf + bytes;
1449                 amdgpu_res_next(&cursor, bytes);
1450         }
1451
1452         return ret;
1453 }
1454
1455 static void
1456 amdgpu_bo_delete_mem_notify(struct ttm_buffer_object *bo)
1457 {
1458         amdgpu_bo_move_notify(bo, false, NULL);
1459 }
1460
1461 static struct ttm_device_funcs amdgpu_bo_driver = {
1462         .ttm_tt_create = &amdgpu_ttm_tt_create,
1463         .ttm_tt_populate = &amdgpu_ttm_tt_populate,
1464         .ttm_tt_unpopulate = &amdgpu_ttm_tt_unpopulate,
1465         .ttm_tt_destroy = &amdgpu_ttm_backend_destroy,
1466         .eviction_valuable = amdgpu_ttm_bo_eviction_valuable,
1467         .evict_flags = &amdgpu_evict_flags,
1468         .move = &amdgpu_bo_move,
1469         .verify_access = &amdgpu_verify_access,
1470         .delete_mem_notify = &amdgpu_bo_delete_mem_notify,
1471         .release_notify = &amdgpu_bo_release_notify,
1472         .io_mem_reserve = &amdgpu_ttm_io_mem_reserve,
1473         .io_mem_pfn = amdgpu_ttm_io_mem_pfn,
1474         .access_memory = &amdgpu_ttm_access_memory,
1475         .del_from_lru_notify = &amdgpu_vm_del_from_lru_notify
1476 };
1477
1478 /*
1479  * Firmware Reservation functions
1480  */
1481 /**
1482  * amdgpu_ttm_fw_reserve_vram_fini - free fw reserved vram
1483  *
1484  * @adev: amdgpu_device pointer
1485  *
1486  * free fw reserved vram if it has been reserved.
1487  */
1488 static void amdgpu_ttm_fw_reserve_vram_fini(struct amdgpu_device *adev)
1489 {
1490         amdgpu_bo_free_kernel(&adev->mman.fw_vram_usage_reserved_bo,
1491                 NULL, &adev->mman.fw_vram_usage_va);
1492 }
1493
1494 /**
1495  * amdgpu_ttm_fw_reserve_vram_init - create bo vram reservation from fw
1496  *
1497  * @adev: amdgpu_device pointer
1498  *
1499  * create bo vram reservation from fw.
1500  */
1501 static int amdgpu_ttm_fw_reserve_vram_init(struct amdgpu_device *adev)
1502 {
1503         uint64_t vram_size = adev->gmc.visible_vram_size;
1504
1505         adev->mman.fw_vram_usage_va = NULL;
1506         adev->mman.fw_vram_usage_reserved_bo = NULL;
1507
1508         if (adev->mman.fw_vram_usage_size == 0 ||
1509             adev->mman.fw_vram_usage_size > vram_size)
1510                 return 0;
1511
1512         return amdgpu_bo_create_kernel_at(adev,
1513                                           adev->mman.fw_vram_usage_start_offset,
1514                                           adev->mman.fw_vram_usage_size,
1515                                           AMDGPU_GEM_DOMAIN_VRAM,
1516                                           &adev->mman.fw_vram_usage_reserved_bo,
1517                                           &adev->mman.fw_vram_usage_va);
1518 }
1519
1520 /*
1521  * Memoy training reservation functions
1522  */
1523
1524 /**
1525  * amdgpu_ttm_training_reserve_vram_fini - free memory training reserved vram
1526  *
1527  * @adev: amdgpu_device pointer
1528  *
1529  * free memory training reserved vram if it has been reserved.
1530  */
1531 static int amdgpu_ttm_training_reserve_vram_fini(struct amdgpu_device *adev)
1532 {
1533         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1534
1535         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
1536         amdgpu_bo_free_kernel(&ctx->c2p_bo, NULL, NULL);
1537         ctx->c2p_bo = NULL;
1538
1539         return 0;
1540 }
1541
1542 static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
1543 {
1544         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1545
1546         memset(ctx, 0, sizeof(*ctx));
1547
1548         ctx->c2p_train_data_offset =
1549                 ALIGN((adev->gmc.mc_vram_size - adev->mman.discovery_tmr_size - SZ_1M), SZ_1M);
1550         ctx->p2c_train_data_offset =
1551                 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
1552         ctx->train_data_size =
1553                 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
1554
1555         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
1556                         ctx->train_data_size,
1557                         ctx->p2c_train_data_offset,
1558                         ctx->c2p_train_data_offset);
1559 }
1560
1561 /*
1562  * reserve TMR memory at the top of VRAM which holds
1563  * IP Discovery data and is protected by PSP.
1564  */
1565 static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev)
1566 {
1567         int ret;
1568         struct psp_memory_training_context *ctx = &adev->psp.mem_train_ctx;
1569         bool mem_train_support = false;
1570
1571         if (!amdgpu_sriov_vf(adev)) {
1572                 ret = amdgpu_mem_train_support(adev);
1573                 if (ret == 1)
1574                         mem_train_support = true;
1575                 else if (ret == -1)
1576                         return -EINVAL;
1577                 else
1578                         DRM_DEBUG("memory training does not support!\n");
1579         }
1580
1581         /*
1582          * Query reserved tmr size through atom firmwareinfo for Sienna_Cichlid and onwards for all
1583          * the use cases (IP discovery/G6 memory training/profiling/diagnostic data.etc)
1584          *
1585          * Otherwise, fallback to legacy approach to check and reserve tmr block for ip
1586          * discovery data and G6 memory training data respectively
1587          */
1588         adev->mman.discovery_tmr_size =
1589                 amdgpu_atomfirmware_get_fw_reserved_fb_size(adev);
1590         if (!adev->mman.discovery_tmr_size)
1591                 adev->mman.discovery_tmr_size = DISCOVERY_TMR_OFFSET;
1592
1593         if (mem_train_support) {
1594                 /* reserve vram for mem train according to TMR location */
1595                 amdgpu_ttm_training_data_block_init(adev);
1596                 ret = amdgpu_bo_create_kernel_at(adev,
1597                                          ctx->c2p_train_data_offset,
1598                                          ctx->train_data_size,
1599                                          AMDGPU_GEM_DOMAIN_VRAM,
1600                                          &ctx->c2p_bo,
1601                                          NULL);
1602                 if (ret) {
1603                         DRM_ERROR("alloc c2p_bo failed(%d)!\n", ret);
1604                         amdgpu_ttm_training_reserve_vram_fini(adev);
1605                         return ret;
1606                 }
1607                 ctx->init = PSP_MEM_TRAIN_RESERVE_SUCCESS;
1608         }
1609
1610         ret = amdgpu_bo_create_kernel_at(adev,
1611                                 adev->gmc.real_vram_size - adev->mman.discovery_tmr_size,
1612                                 adev->mman.discovery_tmr_size,
1613                                 AMDGPU_GEM_DOMAIN_VRAM,
1614                                 &adev->mman.discovery_memory,
1615                                 NULL);
1616         if (ret) {
1617                 DRM_ERROR("alloc tmr failed(%d)!\n", ret);
1618                 amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1619                 return ret;
1620         }
1621
1622         return 0;
1623 }
1624
1625 /*
1626  * amdgpu_ttm_init - Init the memory management (ttm) as well as various
1627  * gtt/vram related fields.
1628  *
1629  * This initializes all of the memory space pools that the TTM layer
1630  * will need such as the GTT space (system memory mapped to the device),
1631  * VRAM (on-board memory), and on-chip memories (GDS, GWS, OA) which
1632  * can be mapped per VMID.
1633  */
1634 int amdgpu_ttm_init(struct amdgpu_device *adev)
1635 {
1636         uint64_t gtt_size;
1637         int r;
1638         u64 vis_vram_limit;
1639
1640         mutex_init(&adev->mman.gtt_window_lock);
1641
1642         /* No others user of address space so set it to 0 */
1643         r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev,
1644                                adev_to_drm(adev)->anon_inode->i_mapping,
1645                                adev_to_drm(adev)->vma_offset_manager,
1646                                adev->need_swiotlb,
1647                                dma_addressing_limited(adev->dev));
1648         if (r) {
1649                 DRM_ERROR("failed initializing buffer object driver(%d).\n", r);
1650                 return r;
1651         }
1652         adev->mman.initialized = true;
1653
1654         /* Initialize VRAM pool with all of VRAM divided into pages */
1655         r = amdgpu_vram_mgr_init(adev);
1656         if (r) {
1657                 DRM_ERROR("Failed initializing VRAM heap.\n");
1658                 return r;
1659         }
1660
1661         /* Reduce size of CPU-visible VRAM if requested */
1662         vis_vram_limit = (u64)amdgpu_vis_vram_limit * 1024 * 1024;
1663         if (amdgpu_vis_vram_limit > 0 &&
1664             vis_vram_limit <= adev->gmc.visible_vram_size)
1665                 adev->gmc.visible_vram_size = vis_vram_limit;
1666
1667         /* Change the size here instead of the init above so only lpfn is affected */
1668         amdgpu_ttm_set_buffer_funcs_status(adev, false);
1669 #ifdef CONFIG_64BIT
1670 #ifdef CONFIG_X86
1671         if (adev->gmc.xgmi.connected_to_cpu)
1672                 adev->mman.aper_base_kaddr = ioremap_cache(adev->gmc.aper_base,
1673                                 adev->gmc.visible_vram_size);
1674
1675         else
1676 #endif
1677                 adev->mman.aper_base_kaddr = ioremap_wc(adev->gmc.aper_base,
1678                                 adev->gmc.visible_vram_size);
1679 #endif
1680
1681         /*
1682          *The reserved vram for firmware must be pinned to the specified
1683          *place on the VRAM, so reserve it early.
1684          */
1685         r = amdgpu_ttm_fw_reserve_vram_init(adev);
1686         if (r) {
1687                 return r;
1688         }
1689
1690         /*
1691          * only NAVI10 and onwards ASIC support for IP discovery.
1692          * If IP discovery enabled, a block of memory should be
1693          * reserved for IP discovey.
1694          */
1695         if (adev->mman.discovery_bin) {
1696                 r = amdgpu_ttm_reserve_tmr(adev);
1697                 if (r)
1698                         return r;
1699         }
1700
1701         /* allocate memory as required for VGA
1702          * This is used for VGA emulation and pre-OS scanout buffers to
1703          * avoid display artifacts while transitioning between pre-OS
1704          * and driver.  */
1705         r = amdgpu_bo_create_kernel_at(adev, 0, adev->mman.stolen_vga_size,
1706                                        AMDGPU_GEM_DOMAIN_VRAM,
1707                                        &adev->mman.stolen_vga_memory,
1708                                        NULL);
1709         if (r)
1710                 return r;
1711         r = amdgpu_bo_create_kernel_at(adev, adev->mman.stolen_vga_size,
1712                                        adev->mman.stolen_extended_size,
1713                                        AMDGPU_GEM_DOMAIN_VRAM,
1714                                        &adev->mman.stolen_extended_memory,
1715                                        NULL);
1716         if (r)
1717                 return r;
1718
1719         DRM_INFO("amdgpu: %uM of VRAM memory ready\n",
1720                  (unsigned) (adev->gmc.real_vram_size / (1024 * 1024)));
1721
1722         /* Compute GTT size, either bsaed on 3/4th the size of RAM size
1723          * or whatever the user passed on module init */
1724         if (amdgpu_gtt_size == -1) {
1725                 struct sysinfo si;
1726
1727                 si_meminfo(&si);
1728                 gtt_size = min(max((AMDGPU_DEFAULT_GTT_SIZE_MB << 20),
1729                                adev->gmc.mc_vram_size),
1730                                ((uint64_t)si.totalram * si.mem_unit * 3/4));
1731         }
1732         else
1733                 gtt_size = (uint64_t)amdgpu_gtt_size << 20;
1734
1735         /* Initialize GTT memory pool */
1736         r = amdgpu_gtt_mgr_init(adev, gtt_size);
1737         if (r) {
1738                 DRM_ERROR("Failed initializing GTT heap.\n");
1739                 return r;
1740         }
1741         DRM_INFO("amdgpu: %uM of GTT memory ready.\n",
1742                  (unsigned)(gtt_size / (1024 * 1024)));
1743
1744         /* Initialize various on-chip memory pools */
1745         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GDS, adev->gds.gds_size);
1746         if (r) {
1747                 DRM_ERROR("Failed initializing GDS heap.\n");
1748                 return r;
1749         }
1750
1751         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_GWS, adev->gds.gws_size);
1752         if (r) {
1753                 DRM_ERROR("Failed initializing gws heap.\n");
1754                 return r;
1755         }
1756
1757         r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_OA, adev->gds.oa_size);
1758         if (r) {
1759                 DRM_ERROR("Failed initializing oa heap.\n");
1760                 return r;
1761         }
1762
1763         return 0;
1764 }
1765
1766 /*
1767  * amdgpu_ttm_fini - De-initialize the TTM memory pools
1768  */
1769 void amdgpu_ttm_fini(struct amdgpu_device *adev)
1770 {
1771         if (!adev->mman.initialized)
1772                 return;
1773
1774         amdgpu_ttm_training_reserve_vram_fini(adev);
1775         /* return the stolen vga memory back to VRAM */
1776         amdgpu_bo_free_kernel(&adev->mman.stolen_vga_memory, NULL, NULL);
1777         amdgpu_bo_free_kernel(&adev->mman.stolen_extended_memory, NULL, NULL);
1778         /* return the IP Discovery TMR memory back to VRAM */
1779         amdgpu_bo_free_kernel(&adev->mman.discovery_memory, NULL, NULL);
1780         amdgpu_ttm_fw_reserve_vram_fini(adev);
1781
1782         if (adev->mman.aper_base_kaddr)
1783                 iounmap(adev->mman.aper_base_kaddr);
1784         adev->mman.aper_base_kaddr = NULL;
1785
1786         amdgpu_vram_mgr_fini(adev);
1787         amdgpu_gtt_mgr_fini(adev);
1788         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GDS);
1789         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_GWS);
1790         ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_OA);
1791         ttm_device_fini(&adev->mman.bdev);
1792         adev->mman.initialized = false;
1793         DRM_INFO("amdgpu: ttm finalized\n");
1794 }
1795
1796 /**
1797  * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
1798  *
1799  * @adev: amdgpu_device pointer
1800  * @enable: true when we can use buffer functions.
1801  *
1802  * Enable/disable use of buffer functions during suspend/resume. This should
1803  * only be called at bootup or when userspace isn't running.
1804  */
1805 void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1806 {
1807         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
1808         uint64_t size;
1809         int r;
1810
1811         if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
1812             adev->mman.buffer_funcs_enabled == enable)
1813                 return;
1814
1815         if (enable) {
1816                 struct amdgpu_ring *ring;
1817                 struct drm_gpu_scheduler *sched;
1818
1819                 ring = adev->mman.buffer_funcs_ring;
1820                 sched = &ring->sched;
1821                 r = drm_sched_entity_init(&adev->mman.entity,
1822                                           DRM_SCHED_PRIORITY_KERNEL, &sched,
1823                                           1, NULL);
1824                 if (r) {
1825                         DRM_ERROR("Failed setting up TTM BO move entity (%d)\n",
1826                                   r);
1827                         return;
1828                 }
1829         } else {
1830                 drm_sched_entity_destroy(&adev->mman.entity);
1831                 dma_fence_put(man->move);
1832                 man->move = NULL;
1833         }
1834
1835         /* this just adjusts TTM size idea, which sets lpfn to the correct value */
1836         if (enable)
1837                 size = adev->gmc.real_vram_size;
1838         else
1839                 size = adev->gmc.visible_vram_size;
1840         man->size = size >> PAGE_SHIFT;
1841         adev->mman.buffer_funcs_enabled = enable;
1842 }
1843
1844 static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf)
1845 {
1846         struct ttm_buffer_object *bo = vmf->vma->vm_private_data;
1847         vm_fault_t ret;
1848
1849         ret = ttm_bo_vm_reserve(bo, vmf);
1850         if (ret)
1851                 return ret;
1852
1853         ret = amdgpu_bo_fault_reserve_notify(bo);
1854         if (ret)
1855                 goto unlock;
1856
1857         ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot,
1858                                        TTM_BO_VM_NUM_PREFAULT, 1);
1859         if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT))
1860                 return ret;
1861
1862 unlock:
1863         dma_resv_unlock(bo->base.resv);
1864         return ret;
1865 }
1866
1867 static const struct vm_operations_struct amdgpu_ttm_vm_ops = {
1868         .fault = amdgpu_ttm_fault,
1869         .open = ttm_bo_vm_open,
1870         .close = ttm_bo_vm_close,
1871         .access = ttm_bo_vm_access
1872 };
1873
1874 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma)
1875 {
1876         struct drm_file *file_priv = filp->private_data;
1877         struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev);
1878         int r;
1879
1880         r = ttm_bo_mmap(filp, vma, &adev->mman.bdev);
1881         if (unlikely(r != 0))
1882                 return r;
1883
1884         vma->vm_ops = &amdgpu_ttm_vm_ops;
1885         return 0;
1886 }
1887
1888 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
1889                        uint64_t dst_offset, uint32_t byte_count,
1890                        struct dma_resv *resv,
1891                        struct dma_fence **fence, bool direct_submit,
1892                        bool vm_needs_flush, bool tmz)
1893 {
1894         enum amdgpu_ib_pool_type pool = direct_submit ? AMDGPU_IB_POOL_DIRECT :
1895                 AMDGPU_IB_POOL_DELAYED;
1896         struct amdgpu_device *adev = ring->adev;
1897         struct amdgpu_job *job;
1898
1899         uint32_t max_bytes;
1900         unsigned num_loops, num_dw;
1901         unsigned i;
1902         int r;
1903
1904         if (direct_submit && !ring->sched.ready) {
1905                 DRM_ERROR("Trying to move memory with ring turned off.\n");
1906                 return -EINVAL;
1907         }
1908
1909         max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
1910         num_loops = DIV_ROUND_UP(byte_count, max_bytes);
1911         num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
1912
1913         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, pool, &job);
1914         if (r)
1915                 return r;
1916
1917         if (vm_needs_flush) {
1918                 job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo ?
1919                                         adev->gmc.pdb0_bo : adev->gart.bo);
1920                 job->vm_needs_flush = true;
1921         }
1922         if (resv) {
1923                 r = amdgpu_sync_resv(adev, &job->sync, resv,
1924                                      AMDGPU_SYNC_ALWAYS,
1925                                      AMDGPU_FENCE_OWNER_UNDEFINED);
1926                 if (r) {
1927                         DRM_ERROR("sync failed (%d).\n", r);
1928                         goto error_free;
1929                 }
1930         }
1931
1932         for (i = 0; i < num_loops; i++) {
1933                 uint32_t cur_size_in_bytes = min(byte_count, max_bytes);
1934
1935                 amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_offset,
1936                                         dst_offset, cur_size_in_bytes, tmz);
1937
1938                 src_offset += cur_size_in_bytes;
1939                 dst_offset += cur_size_in_bytes;
1940                 byte_count -= cur_size_in_bytes;
1941         }
1942
1943         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
1944         WARN_ON(job->ibs[0].length_dw > num_dw);
1945         if (direct_submit)
1946                 r = amdgpu_job_submit_direct(job, ring, fence);
1947         else
1948                 r = amdgpu_job_submit(job, &adev->mman.entity,
1949                                       AMDGPU_FENCE_OWNER_UNDEFINED, fence);
1950         if (r)
1951                 goto error_free;
1952
1953         return r;
1954
1955 error_free:
1956         amdgpu_job_free(job);
1957         DRM_ERROR("Error scheduling IBs (%d)\n", r);
1958         return r;
1959 }
1960
1961 int amdgpu_fill_buffer(struct amdgpu_bo *bo,
1962                        uint32_t src_data,
1963                        struct dma_resv *resv,
1964                        struct dma_fence **fence)
1965 {
1966         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1967         uint32_t max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
1968         struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
1969
1970         struct amdgpu_res_cursor cursor;
1971         unsigned int num_loops, num_dw;
1972         uint64_t num_bytes;
1973
1974         struct amdgpu_job *job;
1975         int r;
1976
1977         if (!adev->mman.buffer_funcs_enabled) {
1978                 DRM_ERROR("Trying to clear memory with ring turned off.\n");
1979                 return -EINVAL;
1980         }
1981
1982         if (bo->tbo.mem.mem_type == TTM_PL_TT) {
1983                 r = amdgpu_ttm_alloc_gart(&bo->tbo);
1984                 if (r)
1985                         return r;
1986         }
1987
1988         num_bytes = bo->tbo.mem.num_pages << PAGE_SHIFT;
1989         num_loops = 0;
1990
1991         amdgpu_res_first(&bo->tbo.mem, 0, num_bytes, &cursor);
1992         while (cursor.remaining) {
1993                 num_loops += DIV_ROUND_UP_ULL(cursor.size, max_bytes);
1994                 amdgpu_res_next(&cursor, cursor.size);
1995         }
1996         num_dw = num_loops * adev->mman.buffer_funcs->fill_num_dw;
1997
1998         /* for IB padding */
1999         num_dw += 64;
2000
2001         r = amdgpu_job_alloc_with_ib(adev, num_dw * 4, AMDGPU_IB_POOL_DELAYED,
2002                                      &job);
2003         if (r)
2004                 return r;
2005
2006         if (resv) {
2007                 r = amdgpu_sync_resv(adev, &job->sync, resv,
2008                                      AMDGPU_SYNC_ALWAYS,
2009                                      AMDGPU_FENCE_OWNER_UNDEFINED);
2010                 if (r) {
2011                         DRM_ERROR("sync failed (%d).\n", r);
2012                         goto error_free;
2013                 }
2014         }
2015
2016         amdgpu_res_first(&bo->tbo.mem, 0, num_bytes, &cursor);
2017         while (cursor.remaining) {
2018                 uint32_t cur_size = min_t(uint64_t, cursor.size, max_bytes);
2019                 uint64_t dst_addr = cursor.start;
2020
2021                 dst_addr += amdgpu_ttm_domain_start(adev, bo->tbo.mem.mem_type);
2022                 amdgpu_emit_fill_buffer(adev, &job->ibs[0], src_data, dst_addr,
2023                                         cur_size);
2024
2025                 amdgpu_res_next(&cursor, cur_size);
2026         }
2027
2028         amdgpu_ring_pad_ib(ring, &job->ibs[0]);
2029         WARN_ON(job->ibs[0].length_dw > num_dw);
2030         r = amdgpu_job_submit(job, &adev->mman.entity,
2031                               AMDGPU_FENCE_OWNER_UNDEFINED, fence);
2032         if (r)
2033                 goto error_free;
2034
2035         return 0;
2036
2037 error_free:
2038         amdgpu_job_free(job);
2039         return r;
2040 }
2041
2042 #if defined(CONFIG_DEBUG_FS)
2043
2044 static int amdgpu_mm_vram_table_show(struct seq_file *m, void *unused)
2045 {
2046         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2047         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2048                                                             TTM_PL_VRAM);
2049         struct drm_printer p = drm_seq_file_printer(m);
2050
2051         man->func->debug(man, &p);
2052         return 0;
2053 }
2054
2055 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused)
2056 {
2057         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2058
2059         return ttm_pool_debugfs(&adev->mman.bdev.pool, m);
2060 }
2061
2062 static int amdgpu_mm_tt_table_show(struct seq_file *m, void *unused)
2063 {
2064         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2065         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2066                                                             TTM_PL_TT);
2067         struct drm_printer p = drm_seq_file_printer(m);
2068
2069         man->func->debug(man, &p);
2070         return 0;
2071 }
2072
2073 static int amdgpu_mm_gds_table_show(struct seq_file *m, void *unused)
2074 {
2075         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2076         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2077                                                             AMDGPU_PL_GDS);
2078         struct drm_printer p = drm_seq_file_printer(m);
2079
2080         man->func->debug(man, &p);
2081         return 0;
2082 }
2083
2084 static int amdgpu_mm_gws_table_show(struct seq_file *m, void *unused)
2085 {
2086         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2087         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2088                                                             AMDGPU_PL_GWS);
2089         struct drm_printer p = drm_seq_file_printer(m);
2090
2091         man->func->debug(man, &p);
2092         return 0;
2093 }
2094
2095 static int amdgpu_mm_oa_table_show(struct seq_file *m, void *unused)
2096 {
2097         struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
2098         struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev,
2099                                                             AMDGPU_PL_OA);
2100         struct drm_printer p = drm_seq_file_printer(m);
2101
2102         man->func->debug(man, &p);
2103         return 0;
2104 }
2105
2106 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_vram_table);
2107 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_tt_table);
2108 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gds_table);
2109 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_gws_table);
2110 DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_oa_table);
2111 DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool);
2112
2113 /*
2114  * amdgpu_ttm_vram_read - Linear read access to VRAM
2115  *
2116  * Accesses VRAM via MMIO for debugging purposes.
2117  */
2118 static ssize_t amdgpu_ttm_vram_read(struct file *f, char __user *buf,
2119                                     size_t size, loff_t *pos)
2120 {
2121         struct amdgpu_device *adev = file_inode(f)->i_private;
2122         ssize_t result = 0;
2123
2124         if (size & 0x3 || *pos & 0x3)
2125                 return -EINVAL;
2126
2127         if (*pos >= adev->gmc.mc_vram_size)
2128                 return -ENXIO;
2129
2130         size = min(size, (size_t)(adev->gmc.mc_vram_size - *pos));
2131         while (size) {
2132                 size_t bytes = min(size, AMDGPU_TTM_VRAM_MAX_DW_READ * 4);
2133                 uint32_t value[AMDGPU_TTM_VRAM_MAX_DW_READ];
2134
2135                 amdgpu_device_vram_access(adev, *pos, value, bytes, false);
2136                 if (copy_to_user(buf, value, bytes))
2137                         return -EFAULT;
2138
2139                 result += bytes;
2140                 buf += bytes;
2141                 *pos += bytes;
2142                 size -= bytes;
2143         }
2144
2145         return result;
2146 }
2147
2148 /*
2149  * amdgpu_ttm_vram_write - Linear write access to VRAM
2150  *
2151  * Accesses VRAM via MMIO for debugging purposes.
2152  */
2153 static ssize_t amdgpu_ttm_vram_write(struct file *f, const char __user *buf,
2154                                     size_t size, loff_t *pos)
2155 {
2156         struct amdgpu_device *adev = file_inode(f)->i_private;
2157         ssize_t result = 0;
2158         int r;
2159
2160         if (size & 0x3 || *pos & 0x3)
2161                 return -EINVAL;
2162
2163         if (*pos >= adev->gmc.mc_vram_size)
2164                 return -ENXIO;
2165
2166         while (size) {
2167                 unsigned long flags;
2168                 uint32_t value;
2169
2170                 if (*pos >= adev->gmc.mc_vram_size)
2171                         return result;
2172
2173                 r = get_user(value, (uint32_t *)buf);
2174                 if (r)
2175                         return r;
2176
2177                 spin_lock_irqsave(&adev->mmio_idx_lock, flags);
2178                 WREG32_NO_KIQ(mmMM_INDEX, ((uint32_t)*pos) | 0x80000000);
2179                 WREG32_NO_KIQ(mmMM_INDEX_HI, *pos >> 31);
2180                 WREG32_NO_KIQ(mmMM_DATA, value);
2181                 spin_unlock_irqrestore(&adev->mmio_idx_lock, flags);
2182
2183                 result += 4;
2184                 buf += 4;
2185                 *pos += 4;
2186                 size -= 4;
2187         }
2188
2189         return result;
2190 }
2191
2192 static const struct file_operations amdgpu_ttm_vram_fops = {
2193         .owner = THIS_MODULE,
2194         .read = amdgpu_ttm_vram_read,
2195         .write = amdgpu_ttm_vram_write,
2196         .llseek = default_llseek,
2197 };
2198
2199 /*
2200  * amdgpu_iomem_read - Virtual read access to GPU mapped memory
2201  *
2202  * This function is used to read memory that has been mapped to the
2203  * GPU and the known addresses are not physical addresses but instead
2204  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2205  */
2206 static ssize_t amdgpu_iomem_read(struct file *f, char __user *buf,
2207                                  size_t size, loff_t *pos)
2208 {
2209         struct amdgpu_device *adev = file_inode(f)->i_private;
2210         struct iommu_domain *dom;
2211         ssize_t result = 0;
2212         int r;
2213
2214         /* retrieve the IOMMU domain if any for this device */
2215         dom = iommu_get_domain_for_dev(adev->dev);
2216
2217         while (size) {
2218                 phys_addr_t addr = *pos & PAGE_MASK;
2219                 loff_t off = *pos & ~PAGE_MASK;
2220                 size_t bytes = PAGE_SIZE - off;
2221                 unsigned long pfn;
2222                 struct page *p;
2223                 void *ptr;
2224
2225                 bytes = bytes < size ? bytes : size;
2226
2227                 /* Translate the bus address to a physical address.  If
2228                  * the domain is NULL it means there is no IOMMU active
2229                  * and the address translation is the identity
2230                  */
2231                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2232
2233                 pfn = addr >> PAGE_SHIFT;
2234                 if (!pfn_valid(pfn))
2235                         return -EPERM;
2236
2237                 p = pfn_to_page(pfn);
2238                 if (p->mapping != adev->mman.bdev.dev_mapping)
2239                         return -EPERM;
2240
2241                 ptr = kmap(p);
2242                 r = copy_to_user(buf, ptr + off, bytes);
2243                 kunmap(p);
2244                 if (r)
2245                         return -EFAULT;
2246
2247                 size -= bytes;
2248                 *pos += bytes;
2249                 result += bytes;
2250         }
2251
2252         return result;
2253 }
2254
2255 /*
2256  * amdgpu_iomem_write - Virtual write access to GPU mapped memory
2257  *
2258  * This function is used to write memory that has been mapped to the
2259  * GPU and the known addresses are not physical addresses but instead
2260  * bus addresses (e.g., what you'd put in an IB or ring buffer).
2261  */
2262 static ssize_t amdgpu_iomem_write(struct file *f, const char __user *buf,
2263                                  size_t size, loff_t *pos)
2264 {
2265         struct amdgpu_device *adev = file_inode(f)->i_private;
2266         struct iommu_domain *dom;
2267         ssize_t result = 0;
2268         int r;
2269
2270         dom = iommu_get_domain_for_dev(adev->dev);
2271
2272         while (size) {
2273                 phys_addr_t addr = *pos & PAGE_MASK;
2274                 loff_t off = *pos & ~PAGE_MASK;
2275                 size_t bytes = PAGE_SIZE - off;
2276                 unsigned long pfn;
2277                 struct page *p;
2278                 void *ptr;
2279
2280                 bytes = bytes < size ? bytes : size;
2281
2282                 addr = dom ? iommu_iova_to_phys(dom, addr) : addr;
2283
2284                 pfn = addr >> PAGE_SHIFT;
2285                 if (!pfn_valid(pfn))
2286                         return -EPERM;
2287
2288                 p = pfn_to_page(pfn);
2289                 if (p->mapping != adev->mman.bdev.dev_mapping)
2290                         return -EPERM;
2291
2292                 ptr = kmap(p);
2293                 r = copy_from_user(ptr + off, buf, bytes);
2294                 kunmap(p);
2295                 if (r)
2296                         return -EFAULT;
2297
2298                 size -= bytes;
2299                 *pos += bytes;
2300                 result += bytes;
2301         }
2302
2303         return result;
2304 }
2305
2306 static const struct file_operations amdgpu_ttm_iomem_fops = {
2307         .owner = THIS_MODULE,
2308         .read = amdgpu_iomem_read,
2309         .write = amdgpu_iomem_write,
2310         .llseek = default_llseek
2311 };
2312
2313 #endif
2314
2315 void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev)
2316 {
2317 #if defined(CONFIG_DEBUG_FS)
2318         struct drm_minor *minor = adev_to_drm(adev)->primary;
2319         struct dentry *root = minor->debugfs_root;
2320
2321         debugfs_create_file_size("amdgpu_vram", 0444, root, adev,
2322                                  &amdgpu_ttm_vram_fops, adev->gmc.mc_vram_size);
2323         debugfs_create_file("amdgpu_iomem", 0444, root, adev,
2324                             &amdgpu_ttm_iomem_fops);
2325         debugfs_create_file("amdgpu_vram_mm", 0444, root, adev,
2326                             &amdgpu_mm_vram_table_fops);
2327         debugfs_create_file("amdgpu_gtt_mm", 0444, root, adev,
2328                             &amdgpu_mm_tt_table_fops);
2329         debugfs_create_file("amdgpu_gds_mm", 0444, root, adev,
2330                             &amdgpu_mm_gds_table_fops);
2331         debugfs_create_file("amdgpu_gws_mm", 0444, root, adev,
2332                             &amdgpu_mm_gws_table_fops);
2333         debugfs_create_file("amdgpu_oa_mm", 0444, root, adev,
2334                             &amdgpu_mm_oa_table_fops);
2335         debugfs_create_file("ttm_page_pool", 0444, root, adev,
2336                             &amdgpu_ttm_page_pool_fops);
2337 #endif
2338 }