drivers/gpu/drm/i915/gt/intel_reset.c

   1 /*
   2  * SPDX-License-Identifier: MIT
   3  *
   4  * Copyright © 2008-2018 Intel Corporation
   5  */
   6
   7 #include <linux/sched/mm.h>
   8 #include <linux/stop_machine.h>
   9
  10 #include "display/intel_display_types.h"
  11 #include "display/intel_overlay.h"
  12
  13 #include "gem/i915_gem_context.h"
  14
  15 #include "i915_drv.h"
  16 #include "i915_gpu_error.h"
  17 #include "i915_irq.h"
  18 #include "intel_breadcrumbs.h"
  19 #include "intel_engine_pm.h"
  20 #include "intel_gt.h"
  21 #include "intel_gt_pm.h"
  22 #include "intel_gt_requests.h"
  23 #include "intel_reset.h"
  24
  25 #include "uc/intel_guc.h"
  26 #include "uc/intel_guc_submission.h"
  27
  28 #define RESET_MAX_RETRIES 3
  29
  30 /* XXX How to handle concurrent GGTT updates using tiling registers? */
  31 #define RESET_UNDER_STOP_MACHINE 0
  32
  33 static void rmw_set_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 set)
  34 {
  35         intel_uncore_rmw_fw(uncore, reg, 0, set);
  36 }
  37
  38 static void rmw_clear_fw(struct intel_uncore *uncore, i915_reg_t reg, u32 clr)
  39 {
  40         intel_uncore_rmw_fw(uncore, reg, clr, 0);
  41 }
  42
  43 static void skip_context(struct i915_request *rq)
  44 {
  45         struct intel_context *hung_ctx = rq->context;
  46
  47         list_for_each_entry_from_rcu(rq, &hung_ctx->timeline->requests, link) {
  48                 if (!i915_request_is_active(rq))
  49                         return;
  50
  51                 if (rq->context == hung_ctx) {
  52                         i915_request_set_error_once(rq, -EIO);
  53                         __i915_request_skip(rq);
  54                 }
  55         }
  56 }
  57
  58 static void client_mark_guilty(struct i915_gem_context *ctx, bool banned)
  59 {
  60         struct drm_i915_file_private *file_priv = ctx->file_priv;
  61         unsigned long prev_hang;
  62         unsigned int score;
  63
  64         if (IS_ERR_OR_NULL(file_priv))
  65                 return;
  66
  67         score = 0;
  68         if (banned)
  69                 score = I915_CLIENT_SCORE_CONTEXT_BAN;
  70
  71         prev_hang = xchg(&file_priv->hang_timestamp, jiffies);
  72         if (time_before(jiffies, prev_hang + I915_CLIENT_FAST_HANG_JIFFIES))
  73                 score += I915_CLIENT_SCORE_HANG_FAST;
  74
  75         if (score) {
  76                 atomic_add(score, &file_priv->ban_score);
  77
  78                 drm_dbg(&ctx->i915->drm,
  79                         "client %s: gained %u ban score, now %u\n",
  80                         ctx->name, score,
  81                         atomic_read(&file_priv->ban_score));
  82         }
  83 }
  84
  85 static bool mark_guilty(struct i915_request *rq)
  86 {
  87         struct i915_gem_context *ctx;
  88         unsigned long prev_hang;
  89         bool banned;
  90         int i;
  91
  92         if (intel_context_is_closed(rq->context)) {
  93                 intel_context_set_banned(rq->context);
  94                 return true;
  95         }
  96
  97         rcu_read_lock();
  98         ctx = rcu_dereference(rq->context->gem_context);
  99         if (ctx && !kref_get_unless_zero(&ctx->ref))
 100                 ctx = NULL;
 101         rcu_read_unlock();
 102         if (!ctx)
 103                 return intel_context_is_banned(rq->context);
 104
 105         atomic_inc(&ctx->guilty_count);
 106
 107         /* Cool contexts are too cool to be banned! (Used for reset testing.) */
 108         if (!i915_gem_context_is_bannable(ctx)) {
 109                 banned = false;
 110                 goto out;
 111         }
 112
 113         drm_notice(&ctx->i915->drm,
 114                    "%s context reset due to GPU hang\n",
 115                    ctx->name);
 116
 117         /* Record the timestamp for the last N hangs */
 118         prev_hang = ctx->hang_timestamp[0];
 119         for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp) - 1; i++)
 120                 ctx->hang_timestamp[i] = ctx->hang_timestamp[i + 1];
 121         ctx->hang_timestamp[i] = jiffies;
 122
 123         /* If we have hung N+1 times in rapid succession, we ban the context! */
 124         banned = !i915_gem_context_is_recoverable(ctx);
 125         if (time_before(jiffies, prev_hang + CONTEXT_FAST_HANG_JIFFIES))
 126                 banned = true;
 127         if (banned) {
 128                 drm_dbg(&ctx->i915->drm, "context %s: guilty %d, banned\n",
 129                         ctx->name, atomic_read(&ctx->guilty_count));
 130                 intel_context_set_banned(rq->context);
 131         }
 132
 133         client_mark_guilty(ctx, banned);
 134
 135 out:
 136         i915_gem_context_put(ctx);
 137         return banned;
 138 }
 139
 140 static void mark_innocent(struct i915_request *rq)
 141 {
 142         struct i915_gem_context *ctx;
 143
 144         rcu_read_lock();
 145         ctx = rcu_dereference(rq->context->gem_context);
 146         if (ctx)
 147                 atomic_inc(&ctx->active_count);
 148         rcu_read_unlock();
 149 }
 150
 151 void __i915_request_reset(struct i915_request *rq, bool guilty)
 152 {
 153         RQ_TRACE(rq, "guilty? %s\n", yesno(guilty));
 154
 155         GEM_BUG_ON(i915_request_completed(rq));
 156
 157         rcu_read_lock(); /* protect the GEM context */
 158         if (guilty) {
 159                 i915_request_set_error_once(rq, -EIO);
 160                 __i915_request_skip(rq);
 161                 if (mark_guilty(rq))
 162                         skip_context(rq);
 163         } else {
 164                 i915_request_set_error_once(rq, -EAGAIN);
 165                 mark_innocent(rq);
 166         }
 167         rcu_read_unlock();
 168 }
 169
 170 static bool i915_in_reset(struct pci_dev *pdev)
 171 {
 172         u8 gdrst;
 173
 174         pci_read_config_byte(pdev, I915_GDRST, &gdrst);
 175         return gdrst & GRDOM_RESET_STATUS;
 176 }
 177
 178 static int i915_do_reset(struct intel_gt *gt,
 179                          intel_engine_mask_t engine_mask,
 180                          unsigned int retry)
 181 {
 182         struct pci_dev *pdev = gt->i915->drm.pdev;
 183         int err;
 184
 185         /* Assert reset for at least 20 usec, and wait for acknowledgement. */
 186         pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
 187         udelay(50);
 188         err = wait_for_atomic(i915_in_reset(pdev), 50);
 189
 190         /* Clear the reset request. */
 191         pci_write_config_byte(pdev, I915_GDRST, 0);
 192         udelay(50);
 193         if (!err)
 194                 err = wait_for_atomic(!i915_in_reset(pdev), 50);
 195
 196         return err;
 197 }
 198
 199 static bool g4x_reset_complete(struct pci_dev *pdev)
 200 {
 201         u8 gdrst;
 202
 203         pci_read_config_byte(pdev, I915_GDRST, &gdrst);
 204         return (gdrst & GRDOM_RESET_ENABLE) == 0;
 205 }
 206
 207 static int g33_do_reset(struct intel_gt *gt,
 208                         intel_engine_mask_t engine_mask,
 209                         unsigned int retry)
 210 {
 211         struct pci_dev *pdev = gt->i915->drm.pdev;
 212
 213         pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
 214         return wait_for_atomic(g4x_reset_complete(pdev), 50);
 215 }
 216
 217 static int g4x_do_reset(struct intel_gt *gt,
 218                         intel_engine_mask_t engine_mask,
 219                         unsigned int retry)
 220 {
 221         struct pci_dev *pdev = gt->i915->drm.pdev;
 222         struct intel_uncore *uncore = gt->uncore;
 223         int ret;
 224
 225         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
 226         rmw_set_fw(uncore, VDECCLK_GATE_D, VCP_UNIT_CLOCK_GATE_DISABLE);
 227         intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D);
 228
 229         pci_write_config_byte(pdev, I915_GDRST,
 230                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 231         ret =  wait_for_atomic(g4x_reset_complete(pdev), 50);
 232         if (ret) {
 233                 GT_TRACE(gt, "Wait for media reset failed\n");
 234                 goto out;
 235         }
 236
 237         pci_write_config_byte(pdev, I915_GDRST,
 238                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
 239         ret =  wait_for_atomic(g4x_reset_complete(pdev), 50);
 240         if (ret) {
 241                 GT_TRACE(gt, "Wait for render reset failed\n");
 242                 goto out;
 243         }
 244
 245 out:
 246         pci_write_config_byte(pdev, I915_GDRST, 0);
 247
 248         rmw_clear_fw(uncore, VDECCLK_GATE_D, VCP_UNIT_CLOCK_GATE_DISABLE);
 249         intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D);
 250
 251         return ret;
 252 }
 253
 254 static int ilk_do_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask,
 255                         unsigned int retry)
 256 {
 257         struct intel_uncore *uncore = gt->uncore;
 258         int ret;
 259
 260         intel_uncore_write_fw(uncore, ILK_GDSR,
 261                               ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
 262         ret = __intel_wait_for_register_fw(uncore, ILK_GDSR,
 263                                            ILK_GRDOM_RESET_ENABLE, 0,
 264                                            5000, 0,
 265                                            NULL);
 266         if (ret) {
 267                 GT_TRACE(gt, "Wait for render reset failed\n");
 268                 goto out;
 269         }
 270
 271         intel_uncore_write_fw(uncore, ILK_GDSR,
 272                               ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
 273         ret = __intel_wait_for_register_fw(uncore, ILK_GDSR,
 274                                            ILK_GRDOM_RESET_ENABLE, 0,
 275                                            5000, 0,
 276                                            NULL);
 277         if (ret) {
 278                 GT_TRACE(gt, "Wait for media reset failed\n");
 279                 goto out;
 280         }
 281
 282 out:
 283         intel_uncore_write_fw(uncore, ILK_GDSR, 0);
 284         intel_uncore_posting_read_fw(uncore, ILK_GDSR);
 285         return ret;
 286 }
 287
 288 /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
 289 static int gen6_hw_domain_reset(struct intel_gt *gt, u32 hw_domain_mask)
 290 {
 291         struct intel_uncore *uncore = gt->uncore;
 292         int err;
 293
 294         /*
 295          * GEN6_GDRST is not in the gt power well, no need to check
 296          * for fifo space for the write or forcewake the chip for
 297          * the read
 298          */
 299         intel_uncore_write_fw(uncore, GEN6_GDRST, hw_domain_mask);
 300
 301         /* Wait for the device to ack the reset requests */
 302         err = __intel_wait_for_register_fw(uncore,
 303                                            GEN6_GDRST, hw_domain_mask, 0,
 304                                            500, 0,
 305                                            NULL);
 306         if (err)
 307                 GT_TRACE(gt,
 308                          "Wait for 0x%08x engines reset failed\n",
 309                          hw_domain_mask);
 310
 311         return err;
 312 }
 313
 314 static int gen6_reset_engines(struct intel_gt *gt,
 315                               intel_engine_mask_t engine_mask,
 316                               unsigned int retry)
 317 {
 318         static const u32 hw_engine_mask[] = {
 319                 [RCS0]  = GEN6_GRDOM_RENDER,
 320                 [BCS0]  = GEN6_GRDOM_BLT,
 321                 [VCS0]  = GEN6_GRDOM_MEDIA,
 322                 [VCS1]  = GEN8_GRDOM_MEDIA2,
 323                 [VECS0] = GEN6_GRDOM_VECS,
 324         };
 325         struct intel_engine_cs *engine;
 326         u32 hw_mask;
 327
 328         if (engine_mask == ALL_ENGINES) {
 329                 hw_mask = GEN6_GRDOM_FULL;
 330         } else {
 331                 intel_engine_mask_t tmp;
 332
 333                 hw_mask = 0;
 334                 for_each_engine_masked(engine, gt, engine_mask, tmp) {
 335                         GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
 336                         hw_mask |= hw_engine_mask[engine->id];
 337                 }
 338         }
 339
 340         return gen6_hw_domain_reset(gt, hw_mask);
 341 }
 342
 343 static int gen11_lock_sfc(struct intel_engine_cs *engine, u32 *hw_mask)
 344 {
 345         struct intel_uncore *uncore = engine->uncore;
 346         u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
 347         i915_reg_t sfc_forced_lock, sfc_forced_lock_ack;
 348         u32 sfc_forced_lock_bit, sfc_forced_lock_ack_bit;
 349         i915_reg_t sfc_usage;
 350         u32 sfc_usage_bit;
 351         u32 sfc_reset_bit;
 352         int ret;
 353
 354         switch (engine->class) {
 355         case VIDEO_DECODE_CLASS:
 356                 if ((BIT(engine->instance) & vdbox_sfc_access) == 0)
 357                         return 0;
 358
 359                 sfc_forced_lock = GEN11_VCS_SFC_FORCED_LOCK(engine);
 360                 sfc_forced_lock_bit = GEN11_VCS_SFC_FORCED_LOCK_BIT;
 361
 362                 sfc_forced_lock_ack = GEN11_VCS_SFC_LOCK_STATUS(engine);
 363                 sfc_forced_lock_ack_bit  = GEN11_VCS_SFC_LOCK_ACK_BIT;
 364
 365                 sfc_usage = GEN11_VCS_SFC_LOCK_STATUS(engine);
 366                 sfc_usage_bit = GEN11_VCS_SFC_USAGE_BIT;
 367                 sfc_reset_bit = GEN11_VCS_SFC_RESET_BIT(engine->instance);
 368                 break;
 369
 370         case VIDEO_ENHANCEMENT_CLASS:
 371                 sfc_forced_lock = GEN11_VECS_SFC_FORCED_LOCK(engine);
 372                 sfc_forced_lock_bit = GEN11_VECS_SFC_FORCED_LOCK_BIT;
 373
 374                 sfc_forced_lock_ack = GEN11_VECS_SFC_LOCK_ACK(engine);
 375                 sfc_forced_lock_ack_bit  = GEN11_VECS_SFC_LOCK_ACK_BIT;
 376
 377                 sfc_usage = GEN11_VECS_SFC_USAGE(engine);
 378                 sfc_usage_bit = GEN11_VECS_SFC_USAGE_BIT;
 379                 sfc_reset_bit = GEN11_VECS_SFC_RESET_BIT(engine->instance);
 380                 break;
 381
 382         default:
 383                 return 0;
 384         }
 385
 386         /*
 387          * If the engine is using a SFC, tell the engine that a software reset
 388          * is going to happen. The engine will then try to force lock the SFC.
 389          * If SFC ends up being locked to the engine we want to reset, we have
 390          * to reset it as well (we will unlock it once the reset sequence is
 391          * completed).
 392          */
 393         if (!(intel_uncore_read_fw(uncore, sfc_usage) & sfc_usage_bit))
 394                 return 0;
 395
 396         rmw_set_fw(uncore, sfc_forced_lock, sfc_forced_lock_bit);
 397
 398         ret = __intel_wait_for_register_fw(uncore,
 399                                            sfc_forced_lock_ack,
 400                                            sfc_forced_lock_ack_bit,
 401                                            sfc_forced_lock_ack_bit,
 402                                            1000, 0, NULL);
 403
 404         /* Was the SFC released while we were trying to lock it? */
 405         if (!(intel_uncore_read_fw(uncore, sfc_usage) & sfc_usage_bit))
 406                 return 0;
 407
 408         if (ret) {
 409                 ENGINE_TRACE(engine, "Wait for SFC forced lock ack failed\n");
 410                 return ret;
 411         }
 412
 413         *hw_mask |= sfc_reset_bit;
 414         return 0;
 415 }
 416
 417 static void gen11_unlock_sfc(struct intel_engine_cs *engine)
 418 {
 419         struct intel_uncore *uncore = engine->uncore;
 420         u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
 421         i915_reg_t sfc_forced_lock;
 422         u32 sfc_forced_lock_bit;
 423
 424         switch (engine->class) {
 425         case VIDEO_DECODE_CLASS:
 426                 if ((BIT(engine->instance) & vdbox_sfc_access) == 0)
 427                         return;
 428
 429                 sfc_forced_lock = GEN11_VCS_SFC_FORCED_LOCK(engine);
 430                 sfc_forced_lock_bit = GEN11_VCS_SFC_FORCED_LOCK_BIT;
 431                 break;
 432
 433         case VIDEO_ENHANCEMENT_CLASS:
 434                 sfc_forced_lock = GEN11_VECS_SFC_FORCED_LOCK(engine);
 435                 sfc_forced_lock_bit = GEN11_VECS_SFC_FORCED_LOCK_BIT;
 436                 break;
 437
 438         default:
 439                 return;
 440         }
 441
 442         rmw_clear_fw(uncore, sfc_forced_lock, sfc_forced_lock_bit);
 443 }
 444
 445 static int gen11_reset_engines(struct intel_gt *gt,
 446                                intel_engine_mask_t engine_mask,
 447                                unsigned int retry)
 448 {
 449         static const u32 hw_engine_mask[] = {
 450                 [RCS0]  = GEN11_GRDOM_RENDER,
 451                 [BCS0]  = GEN11_GRDOM_BLT,
 452                 [VCS0]  = GEN11_GRDOM_MEDIA,
 453                 [VCS1]  = GEN11_GRDOM_MEDIA2,
 454                 [VCS2]  = GEN11_GRDOM_MEDIA3,
 455                 [VCS3]  = GEN11_GRDOM_MEDIA4,
 456                 [VECS0] = GEN11_GRDOM_VECS,
 457                 [VECS1] = GEN11_GRDOM_VECS2,
 458         };
 459         struct intel_engine_cs *engine;
 460         intel_engine_mask_t tmp;
 461         u32 hw_mask;
 462         int ret;
 463
 464         if (engine_mask == ALL_ENGINES) {
 465                 hw_mask = GEN11_GRDOM_FULL;
 466         } else {
 467                 hw_mask = 0;
 468                 for_each_engine_masked(engine, gt, engine_mask, tmp) {
 469                         GEM_BUG_ON(engine->id >= ARRAY_SIZE(hw_engine_mask));
 470                         hw_mask |= hw_engine_mask[engine->id];
 471                         ret = gen11_lock_sfc(engine, &hw_mask);
 472                         if (ret)
 473                                 goto sfc_unlock;
 474                 }
 475         }
 476
 477         ret = gen6_hw_domain_reset(gt, hw_mask);
 478
 479 sfc_unlock:
 480         /*
 481          * We unlock the SFC based on the lock status and not the result of
 482          * gen11_lock_sfc to make sure that we clean properly if something
 483          * wrong happened during the lock (e.g. lock acquired after timeout
 484          * expiration).
 485          */
 486         if (engine_mask != ALL_ENGINES)
 487                 for_each_engine_masked(engine, gt, engine_mask, tmp)
 488                         gen11_unlock_sfc(engine);
 489
 490         return ret;
 491 }
 492
 493 static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
 494 {
 495         struct intel_uncore *uncore = engine->uncore;
 496         const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base);
 497         u32 request, mask, ack;
 498         int ret;
 499
 500         if (I915_SELFTEST_ONLY(should_fail(&engine->reset_timeout, 1)))
 501                 return -ETIMEDOUT;
 502
 503         ack = intel_uncore_read_fw(uncore, reg);
 504         if (ack & RESET_CTL_CAT_ERROR) {
 505                 /*
 506                  * For catastrophic errors, ready-for-reset sequence
 507                  * needs to be bypassed: HAS#396813
 508                  */
 509                 request = RESET_CTL_CAT_ERROR;
 510                 mask = RESET_CTL_CAT_ERROR;
 511
 512                 /* Catastrophic errors need to be cleared by HW */
 513                 ack = 0;
 514         } else if (!(ack & RESET_CTL_READY_TO_RESET)) {
 515                 request = RESET_CTL_REQUEST_RESET;
 516                 mask = RESET_CTL_READY_TO_RESET;
 517                 ack = RESET_CTL_READY_TO_RESET;
 518         } else {
 519                 return 0;
 520         }
 521
 522         intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request));
 523         ret = __intel_wait_for_register_fw(uncore, reg, mask, ack,
 524                                            700, 0, NULL);
 525         if (ret)
 526                 drm_err(&engine->i915->drm,
 527                         "%s reset request timed out: {request: %08x, RESET_CTL: %08x}\n",
 528                         engine->name, request,
 529                         intel_uncore_read_fw(uncore, reg));
 530
 531         return ret;
 532 }
 533
 534 static void gen8_engine_reset_cancel(struct intel_engine_cs *engine)
 535 {
 536         intel_uncore_write_fw(engine->uncore,
 537                               RING_RESET_CTL(engine->mmio_base),
 538                               _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
 539 }
 540
 541 static int gen8_reset_engines(struct intel_gt *gt,
 542                               intel_engine_mask_t engine_mask,
 543                               unsigned int retry)
 544 {
 545         struct intel_engine_cs *engine;
 546         const bool reset_non_ready = retry >= 1;
 547         intel_engine_mask_t tmp;
 548         int ret;
 549
 550         for_each_engine_masked(engine, gt, engine_mask, tmp) {
 551                 ret = gen8_engine_reset_prepare(engine);
 552                 if (ret && !reset_non_ready)
 553                         goto skip_reset;
 554
 555                 /*
 556                  * If this is not the first failed attempt to prepare,
 557                  * we decide to proceed anyway.
 558                  *
 559                  * By doing so we risk context corruption and with
 560                  * some gens (kbl), possible system hang if reset
 561                  * happens during active bb execution.
 562                  *
 563                  * We rather take context corruption instead of
 564                  * failed reset with a wedged driver/gpu. And
 565                  * active bb execution case should be covered by
 566                  * stop_engines() we have before the reset.
 567                  */
 568         }
 569
 570         if (INTEL_GEN(gt->i915) >= 11)
 571                 ret = gen11_reset_engines(gt, engine_mask, retry);
 572         else
 573                 ret = gen6_reset_engines(gt, engine_mask, retry);
 574
 575 skip_reset:
 576         for_each_engine_masked(engine, gt, engine_mask, tmp)
 577                 gen8_engine_reset_cancel(engine);
 578
 579         return ret;
 580 }
 581
 582 static int mock_reset(struct intel_gt *gt,
 583                       intel_engine_mask_t mask,
 584                       unsigned int retry)
 585 {
 586         return 0;
 587 }
 588
 589 typedef int (*reset_func)(struct intel_gt *,
 590                           intel_engine_mask_t engine_mask,
 591                           unsigned int retry);
 592
 593 static reset_func intel_get_gpu_reset(const struct intel_gt *gt)
 594 {
 595         struct drm_i915_private *i915 = gt->i915;
 596
 597         if (is_mock_gt(gt))
 598                 return mock_reset;
 599         else if (INTEL_GEN(i915) >= 8)
 600                 return gen8_reset_engines;
 601         else if (INTEL_GEN(i915) >= 6)
 602                 return gen6_reset_engines;
 603         else if (INTEL_GEN(i915) >= 5)
 604                 return ilk_do_reset;
 605         else if (IS_G4X(i915))
 606                 return g4x_do_reset;
 607         else if (IS_G33(i915) || IS_PINEVIEW(i915))
 608                 return g33_do_reset;
 609         else if (INTEL_GEN(i915) >= 3)
 610                 return i915_do_reset;
 611         else
 612                 return NULL;
 613 }
 614
 615 int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask)
 616 {
 617         const int retries = engine_mask == ALL_ENGINES ? RESET_MAX_RETRIES : 1;
 618         reset_func reset;
 619         int ret = -ETIMEDOUT;
 620         int retry;
 621
 622         reset = intel_get_gpu_reset(gt);
 623         if (!reset)
 624                 return -ENODEV;
 625
 626         /*
 627          * If the power well sleeps during the reset, the reset
 628          * request may be dropped and never completes (causing -EIO).
 629          */
 630         intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
 631         for (retry = 0; ret == -ETIMEDOUT && retry < retries; retry++) {
 632                 GT_TRACE(gt, "engine_mask=%x\n", engine_mask);
 633                 preempt_disable();
 634                 ret = reset(gt, engine_mask, retry);
 635                 preempt_enable();
 636         }
 637         intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
 638
 639         return ret;
 640 }
 641
 642 bool intel_has_gpu_reset(const struct intel_gt *gt)
 643 {
 644         if (!gt->i915->params.reset)
 645                 return NULL;
 646
 647         return intel_get_gpu_reset(gt);
 648 }
 649
 650 bool intel_has_reset_engine(const struct intel_gt *gt)
 651 {
 652         if (gt->i915->params.reset < 2)
 653                 return false;
 654
 655         return INTEL_INFO(gt->i915)->has_reset_engine;
 656 }
 657
 658 int intel_reset_guc(struct intel_gt *gt)
 659 {
 660         u32 guc_domain =
 661                 INTEL_GEN(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
 662         int ret;
 663
 664         GEM_BUG_ON(!HAS_GT_UC(gt->i915));
 665
 666         intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
 667         ret = gen6_hw_domain_reset(gt, guc_domain);
 668         intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
 669
 670         return ret;
 671 }
 672
 673 /*
 674  * Ensure irq handler finishes, and not run again.
 675  * Also return the active request so that we only search for it once.
 676  */
 677 static void reset_prepare_engine(struct intel_engine_cs *engine)
 678 {
 679         /*
 680          * During the reset sequence, we must prevent the engine from
 681          * entering RC6. As the context state is undefined until we restart
 682          * the engine, if it does enter RC6 during the reset, the state
 683          * written to the powercontext is undefined and so we may lose
 684          * GPU state upon resume, i.e. fail to restart after a reset.
 685          */
 686         intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
 687         if (engine->reset.prepare)
 688                 engine->reset.prepare(engine);
 689 }
 690
 691 static void revoke_mmaps(struct intel_gt *gt)
 692 {
 693         int i;
 694
 695         for (i = 0; i < gt->ggtt->num_fences; i++) {
 696                 struct drm_vma_offset_node *node;
 697                 struct i915_vma *vma;
 698                 u64 vma_offset;
 699
 700                 vma = READ_ONCE(gt->ggtt->fence_regs[i].vma);
 701                 if (!vma)
 702                         continue;
 703
 704                 if (!i915_vma_has_userfault(vma))
 705                         continue;
 706
 707                 GEM_BUG_ON(vma->fence != &gt->ggtt->fence_regs[i]);
 708
 709                 if (!vma->mmo)
 710                         continue;
 711
 712                 node = &vma->mmo->vma_node;
 713                 vma_offset = vma->ggtt_view.partial.offset << PAGE_SHIFT;
 714
 715                 unmap_mapping_range(gt->i915->drm.anon_inode->i_mapping,
 716                                     drm_vma_node_offset_addr(node) + vma_offset,
 717                                     vma->size,
 718                                     1);
 719         }
 720 }
 721
 722 static intel_engine_mask_t reset_prepare(struct intel_gt *gt)
 723 {
 724         struct intel_engine_cs *engine;
 725         intel_engine_mask_t awake = 0;
 726         enum intel_engine_id id;
 727
 728         for_each_engine(engine, gt, id) {
 729                 if (intel_engine_pm_get_if_awake(engine))
 730                         awake |= engine->mask;
 731                 reset_prepare_engine(engine);
 732         }
 733
 734         intel_uc_reset_prepare(&gt->uc);
 735
 736         return awake;
 737 }
 738
 739 static void gt_revoke(struct intel_gt *gt)
 740 {
 741         revoke_mmaps(gt);
 742 }
 743
 744 static int gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
 745 {
 746         struct intel_engine_cs *engine;
 747         enum intel_engine_id id;
 748         int err;
 749
 750         /*
 751          * Everything depends on having the GTT running, so we need to start
 752          * there.
 753          */
 754         err = i915_ggtt_enable_hw(gt->i915);
 755         if (err)
 756                 return err;
 757
 758         local_bh_disable();
 759         for_each_engine(engine, gt, id)
 760                 __intel_engine_reset(engine, stalled_mask & engine->mask);
 761         local_bh_enable();
 762
 763         intel_ggtt_restore_fences(gt->ggtt);
 764
 765         return err;
 766 }
 767
 768 static void reset_finish_engine(struct intel_engine_cs *engine)
 769 {
 770         if (engine->reset.finish)
 771                 engine->reset.finish(engine);
 772         intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL);
 773
 774         intel_engine_signal_breadcrumbs(engine);
 775 }
 776
 777 static void reset_finish(struct intel_gt *gt, intel_engine_mask_t awake)
 778 {
 779         struct intel_engine_cs *engine;
 780         enum intel_engine_id id;
 781
 782         for_each_engine(engine, gt, id) {
 783                 reset_finish_engine(engine);
 784                 if (awake & engine->mask)
 785                         intel_engine_pm_put(engine);
 786         }
 787 }
 788
 789 static void nop_submit_request(struct i915_request *request)
 790 {
 791         struct intel_engine_cs *engine = request->engine;
 792         unsigned long flags;
 793
 794         RQ_TRACE(request, "-EIO\n");
 795         i915_request_set_error_once(request, -EIO);
 796
 797         spin_lock_irqsave(&engine->active.lock, flags);
 798         __i915_request_submit(request);
 799         i915_request_mark_complete(request);
 800         spin_unlock_irqrestore(&engine->active.lock, flags);
 801
 802         intel_engine_signal_breadcrumbs(engine);
 803 }
 804
 805 static void __intel_gt_set_wedged(struct intel_gt *gt)
 806 {
 807         struct intel_engine_cs *engine;
 808         intel_engine_mask_t awake;
 809         enum intel_engine_id id;
 810
 811         if (test_bit(I915_WEDGED, &gt->reset.flags))
 812                 return;
 813
 814         GT_TRACE(gt, "start\n");
 815
 816         /*
 817          * First, stop submission to hw, but do not yet complete requests by
 818          * rolling the global seqno forward (since this would complete requests
 819          * for which we haven't set the fence error to EIO yet).
 820          */
 821         awake = reset_prepare(gt);
 822
 823         /* Even if the GPU reset fails, it should still stop the engines */
 824         if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
 825                 __intel_gt_reset(gt, ALL_ENGINES);
 826
 827         for_each_engine(engine, gt, id)
 828                 engine->submit_request = nop_submit_request;
 829
 830         /*
 831          * Make sure no request can slip through without getting completed by
 832          * either this call here to intel_engine_write_global_seqno, or the one
 833          * in nop_submit_request.
 834          */
 835         synchronize_rcu_expedited();
 836         set_bit(I915_WEDGED, &gt->reset.flags);
 837
 838         /* Mark all executing requests as skipped */
 839         local_bh_disable();
 840         for_each_engine(engine, gt, id)
 841                 if (engine->reset.cancel)
 842                         engine->reset.cancel(engine);
 843         local_bh_enable();
 844
 845         reset_finish(gt, awake);
 846
 847         GT_TRACE(gt, "end\n");
 848 }
 849
 850 void intel_gt_set_wedged(struct intel_gt *gt)
 851 {
 852         intel_wakeref_t wakeref;
 853
 854         if (test_bit(I915_WEDGED, &gt->reset.flags))
 855                 return;
 856
 857         wakeref = intel_runtime_pm_get(gt->uncore->rpm);
 858         mutex_lock(&gt->reset.mutex);
 859
 860         if (GEM_SHOW_DEBUG()) {
 861                 struct drm_printer p = drm_debug_printer(__func__);
 862                 struct intel_engine_cs *engine;
 863                 enum intel_engine_id id;
 864
 865                 drm_printf(&p, "called from %pS\n", (void *)_RET_IP_);
 866                 for_each_engine(engine, gt, id) {
 867                         if (intel_engine_is_idle(engine))
 868                                 continue;
 869
 870                         intel_engine_dump(engine, &p, "%s\n", engine->name);
 871                 }
 872         }
 873
 874         __intel_gt_set_wedged(gt);
 875
 876         mutex_unlock(&gt->reset.mutex);
 877         intel_runtime_pm_put(gt->uncore->rpm, wakeref);
 878 }
 879
 880 static bool __intel_gt_unset_wedged(struct intel_gt *gt)
 881 {
 882         struct intel_gt_timelines *timelines = &gt->timelines;
 883         struct intel_timeline *tl;
 884         bool ok;
 885
 886         if (!test_bit(I915_WEDGED, &gt->reset.flags))
 887                 return true;
 888
 889         /* Never fully initialised, recovery impossible */
 890         if (intel_gt_has_unrecoverable_error(gt))
 891                 return false;
 892
 893         GT_TRACE(gt, "start\n");
 894
 895         /*
 896          * Before unwedging, make sure that all pending operations
 897          * are flushed and errored out - we may have requests waiting upon
 898          * third party fences. We marked all inflight requests as EIO, and
 899          * every execbuf since returned EIO, for consistency we want all
 900          * the currently pending requests to also be marked as EIO, which
 901          * is done inside our nop_submit_request - and so we must wait.
 902          *
 903          * No more can be submitted until we reset the wedged bit.
 904          */
 905         spin_lock(&timelines->lock);
 906         list_for_each_entry(tl, &timelines->active_list, link) {
 907                 struct dma_fence *fence;
 908
 909                 fence = i915_active_fence_get(&tl->last_request);
 910                 if (!fence)
 911                         continue;
 912
 913                 spin_unlock(&timelines->lock);
 914
 915                 /*
 916                  * All internal dependencies (i915_requests) will have
 917                  * been flushed by the set-wedge, but we may be stuck waiting
 918                  * for external fences. These should all be capped to 10s
 919                  * (I915_FENCE_TIMEOUT) so this wait should not be unbounded
 920                  * in the worst case.
 921                  */
 922                 dma_fence_default_wait(fence, false, MAX_SCHEDULE_TIMEOUT);
 923                 dma_fence_put(fence);
 924
 925                 /* Restart iteration after droping lock */
 926                 spin_lock(&timelines->lock);
 927                 tl = list_entry(&timelines->active_list, typeof(*tl), link);
 928         }
 929         spin_unlock(&timelines->lock);
 930
 931         /* We must reset pending GPU events before restoring our submission */
 932         ok = !HAS_EXECLISTS(gt->i915); /* XXX better agnosticism desired */
 933         if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
 934                 ok = __intel_gt_reset(gt, ALL_ENGINES) == 0;
 935         if (!ok) {
 936                 /*
 937                  * Warn CI about the unrecoverable wedged condition.
 938                  * Time for a reboot.
 939                  */
 940                 add_taint_for_CI(gt->i915, TAINT_WARN);
 941                 return false;
 942         }
 943
 944         /*
 945          * Undo nop_submit_request. We prevent all new i915 requests from
 946          * being queued (by disallowing execbuf whilst wedged) so having
 947          * waited for all active requests above, we know the system is idle
 948          * and do not have to worry about a thread being inside
 949          * engine->submit_request() as we swap over. So unlike installing
 950          * the nop_submit_request on reset, we can do this from normal
 951          * context and do not require stop_machine().
 952          */
 953         intel_engines_reset_default_submission(gt);
 954
 955         GT_TRACE(gt, "end\n");
 956
 957         smp_mb__before_atomic(); /* complete takeover before enabling execbuf */
 958         clear_bit(I915_WEDGED, &gt->reset.flags);
 959
 960         return true;
 961 }
 962
 963 bool intel_gt_unset_wedged(struct intel_gt *gt)
 964 {
 965         bool result;
 966
 967         mutex_lock(&gt->reset.mutex);
 968         result = __intel_gt_unset_wedged(gt);
 969         mutex_unlock(&gt->reset.mutex);
 970
 971         return result;
 972 }
 973
 974 static int do_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
 975 {
 976         int err, i;
 977
 978         gt_revoke(gt);
 979
 980         err = __intel_gt_reset(gt, ALL_ENGINES);
 981         for (i = 0; err && i < RESET_MAX_RETRIES; i++) {
 982                 msleep(10 * (i + 1));
 983                 err = __intel_gt_reset(gt, ALL_ENGINES);
 984         }
 985         if (err)
 986                 return err;
 987
 988         return gt_reset(gt, stalled_mask);
 989 }
 990
 991 static int resume(struct intel_gt *gt)
 992 {
 993         struct intel_engine_cs *engine;
 994         enum intel_engine_id id;
 995         int ret;
 996
 997         for_each_engine(engine, gt, id) {
 998                 ret = intel_engine_resume(engine);
 999                 if (ret)
1000                         return ret;
1001         }
1002
1003         return 0;
1004 }
1005
1006 /**
1007  * intel_gt_reset - reset chip after a hang
1008  * @gt: #intel_gt to reset
1009  * @stalled_mask: mask of the stalled engines with the guilty requests
1010  * @reason: user error message for why we are resetting
1011  *
1012  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1013  * on failure.
1014  *
1015  * Procedure is fairly simple:
1016  *   - reset the chip using the reset reg
1017  *   - re-init context state
1018  *   - re-init hardware status page
1019  *   - re-init ring buffer
1020  *   - re-init interrupt state
1021  *   - re-init display
1022  */
1023 void intel_gt_reset(struct intel_gt *gt,
1024                     intel_engine_mask_t stalled_mask,
1025                     const char *reason)
1026 {
1027         intel_engine_mask_t awake;
1028         int ret;
1029
1030         GT_TRACE(gt, "flags=%lx\n", gt->reset.flags);
1031
1032         might_sleep();
1033         GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &gt->reset.flags));
1034         mutex_lock(&gt->reset.mutex);
1035
1036         /* Clear any previous failed attempts at recovery. Time to try again. */
1037         if (!__intel_gt_unset_wedged(gt))
1038                 goto unlock;
1039
1040         if (reason)
1041                 drm_notice(&gt->i915->drm,
1042                            "Resetting chip for %s\n", reason);
1043         atomic_inc(&gt->i915->gpu_error.reset_count);
1044
1045         awake = reset_prepare(gt);
1046
1047         if (!intel_has_gpu_reset(gt)) {
1048                 if (gt->i915->params.reset)
1049                         drm_err(&gt->i915->drm, "GPU reset not supported\n");
1050                 else
1051                         drm_dbg(&gt->i915->drm, "GPU reset disabled\n");
1052                 goto error;
1053         }
1054
1055         if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
1056                 intel_runtime_pm_disable_interrupts(gt->i915);
1057
1058         if (do_reset(gt, stalled_mask)) {
1059                 drm_err(&gt->i915->drm, "Failed to reset chip\n");
1060                 goto taint;
1061         }
1062
1063         if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
1064                 intel_runtime_pm_enable_interrupts(gt->i915);
1065
1066         intel_overlay_reset(gt->i915);
1067
1068         /*
1069          * Next we need to restore the context, but we don't use those
1070          * yet either...
1071          *
1072          * Ring buffer needs to be re-initialized in the KMS case, or if X
1073          * was running at the time of the reset (i.e. we weren't VT
1074          * switched away).
1075          */
1076         ret = intel_gt_init_hw(gt);
1077         if (ret) {
1078                 drm_err(&gt->i915->drm,
1079                         "Failed to initialise HW following reset (%d)\n",
1080                         ret);
1081                 goto taint;
1082         }
1083
1084         ret = resume(gt);
1085         if (ret)
1086                 goto taint;
1087
1088 finish:
1089         reset_finish(gt, awake);
1090 unlock:
1091         mutex_unlock(&gt->reset.mutex);
1092         return;
1093
1094 taint:
1095         /*
1096          * History tells us that if we cannot reset the GPU now, we
1097          * never will. This then impacts everything that is run
1098          * subsequently. On failing the reset, we mark the driver
1099          * as wedged, preventing further execution on the GPU.
1100          * We also want to go one step further and add a taint to the
1101          * kernel so that any subsequent faults can be traced back to
1102          * this failure. This is important for CI, where if the
1103          * GPU/driver fails we would like to reboot and restart testing
1104          * rather than continue on into oblivion. For everyone else,
1105          * the system should still plod along, but they have been warned!
1106          */
1107         add_taint_for_CI(gt->i915, TAINT_WARN);
1108 error:
1109         __intel_gt_set_wedged(gt);
1110         goto finish;
1111 }
1112
1113 static int intel_gt_reset_engine(struct intel_engine_cs *engine)
1114 {
1115         return __intel_gt_reset(engine->gt, engine->mask);
1116 }
1117
1118 int __intel_engine_reset_bh(struct intel_engine_cs *engine, const char *msg)
1119 {
1120         struct intel_gt *gt = engine->gt;
1121         bool uses_guc = intel_engine_in_guc_submission_mode(engine);
1122         int ret;
1123
1124         ENGINE_TRACE(engine, "flags=%lx\n", gt->reset.flags);
1125         GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &gt->reset.flags));
1126
1127         if (!intel_engine_pm_get_if_awake(engine))
1128                 return 0;
1129
1130         reset_prepare_engine(engine);
1131
1132         if (msg)
1133                 drm_notice(&engine->i915->drm,
1134                            "Resetting %s for %s\n", engine->name, msg);
1135         atomic_inc(&engine->i915->gpu_error.reset_engine_count[engine->uabi_class]);
1136
1137         if (!uses_guc)
1138                 ret = intel_gt_reset_engine(engine);
1139         else
1140                 ret = intel_guc_reset_engine(&engine->gt->uc.guc, engine);
1141         if (ret) {
1142                 /* If we fail here, we expect to fallback to a global reset */
1143                 ENGINE_TRACE(engine, "Failed to reset, err: %d\n", ret);
1144                 goto out;
1145         }
1146
1147         /*
1148          * The request that caused the hang is stuck on elsp, we know the
1149          * active request and can drop it, adjust head to skip the offending
1150          * request to resume executing remaining requests in the queue.
1151          */
1152         __intel_engine_reset(engine, true);
1153
1154         /*
1155          * The engine and its registers (and workarounds in case of render)
1156          * have been reset to their default values. Follow the init_ring
1157          * process to program RING_MODE, HWSP and re-enable submission.
1158          */
1159         ret = intel_engine_resume(engine);
1160
1161 out:
1162         intel_engine_cancel_stop_cs(engine);
1163         reset_finish_engine(engine);
1164         intel_engine_pm_put_async(engine);
1165         return ret;
1166 }
1167
1168 /**
1169  * intel_engine_reset - reset GPU engine to recover from a hang
1170  * @engine: engine to reset
1171  * @msg: reason for GPU reset; or NULL for no drm_notice()
1172  *
1173  * Reset a specific GPU engine. Useful if a hang is detected.
1174  * Returns zero on successful reset or otherwise an error code.
1175  *
1176  * Procedure is:
1177  *  - identifies the request that caused the hang and it is dropped
1178  *  - reset engine (which will force the engine to idle)
1179  *  - re-init/configure engine
1180  */
1181 int intel_engine_reset(struct intel_engine_cs *engine, const char *msg)
1182 {
1183         int err;
1184
1185         local_bh_disable();
1186         err = __intel_engine_reset_bh(engine, msg);
1187         local_bh_enable();
1188
1189         return err;
1190 }
1191
1192 static void intel_gt_reset_global(struct intel_gt *gt,
1193                                   u32 engine_mask,
1194                                   const char *reason)
1195 {
1196         struct kobject *kobj = &gt->i915->drm.primary->kdev->kobj;
1197         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1198         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1199         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1200         struct intel_wedge_me w;
1201
1202         kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
1203
1204         GT_TRACE(gt, "resetting chip, engines=%x\n", engine_mask);
1205         kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
1206
1207         /* Use a watchdog to ensure that our reset completes */
1208         intel_wedge_on_timeout(&w, gt, 5 * HZ) {
1209                 intel_display_prepare_reset(gt->i915);
1210
1211                 /* Flush everyone using a resource about to be clobbered */
1212                 synchronize_srcu_expedited(&gt->reset.backoff_srcu);
1213
1214                 intel_gt_reset(gt, engine_mask, reason);
1215
1216                 intel_display_finish_reset(gt->i915);
1217         }
1218
1219         if (!test_bit(I915_WEDGED, &gt->reset.flags))
1220                 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);
1221 }
1222
1223 /**
1224  * intel_gt_handle_error - handle a gpu error
1225  * @gt: the intel_gt
1226  * @engine_mask: mask representing engines that are hung
1227  * @flags: control flags
1228  * @fmt: Error message format string
1229  *
1230  * Do some basic checking of register state at error time and
1231  * dump it to the syslog.  Also call i915_capture_error_state() to make
1232  * sure we get a record and make it available in debugfs.  Fire a uevent
1233  * so userspace knows something bad happened (should trigger collection
1234  * of a ring dump etc.).
1235  */
1236 void intel_gt_handle_error(struct intel_gt *gt,
1237                            intel_engine_mask_t engine_mask,
1238                            unsigned long flags,
1239                            const char *fmt, ...)
1240 {
1241         struct intel_engine_cs *engine;
1242         intel_wakeref_t wakeref;
1243         intel_engine_mask_t tmp;
1244         char error_msg[80];
1245         char *msg = NULL;
1246
1247         if (fmt) {
1248                 va_list args;
1249
1250                 va_start(args, fmt);
1251                 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
1252                 va_end(args);
1253
1254                 msg = error_msg;
1255         }
1256
1257         /*
1258          * In most cases it's guaranteed that we get here with an RPM
1259          * reference held, for example because there is a pending GPU
1260          * request that won't finish until the reset is done. This
1261          * isn't the case at least when we get here by doing a
1262          * simulated reset via debugfs, so get an RPM reference.
1263          */
1264         wakeref = intel_runtime_pm_get(gt->uncore->rpm);
1265
1266         engine_mask &= gt->info.engine_mask;
1267
1268         if (flags & I915_ERROR_CAPTURE) {
1269                 i915_capture_error_state(gt, engine_mask);
1270                 intel_gt_clear_error_registers(gt, engine_mask);
1271         }
1272
1273         /*
1274          * Try engine reset when available. We fall back to full reset if
1275          * single reset fails.
1276          */
1277         if (intel_has_reset_engine(gt) && !intel_gt_is_wedged(gt)) {
1278                 local_bh_disable();
1279                 for_each_engine_masked(engine, gt, engine_mask, tmp) {
1280                         BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
1281                         if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
1282                                              &gt->reset.flags))
1283                                 continue;
1284
1285                         if (__intel_engine_reset_bh(engine, msg) == 0)
1286                                 engine_mask &= ~engine->mask;
1287
1288                         clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id,
1289                                               &gt->reset.flags);
1290                 }
1291                 local_bh_enable();
1292         }
1293
1294         if (!engine_mask)
1295                 goto out;
1296
1297         /* Full reset needs the mutex, stop any other user trying to do so. */
1298         if (test_and_set_bit(I915_RESET_BACKOFF, &gt->reset.flags)) {
1299                 wait_event(gt->reset.queue,
1300                            !test_bit(I915_RESET_BACKOFF, &gt->reset.flags));
1301                 goto out; /* piggy-back on the other reset */
1302         }
1303
1304         /* Make sure i915_reset_trylock() sees the I915_RESET_BACKOFF */
1305         synchronize_rcu_expedited();
1306
1307         /* Prevent any other reset-engine attempt. */
1308         for_each_engine(engine, gt, tmp) {
1309                 while (test_and_set_bit(I915_RESET_ENGINE + engine->id,
1310                                         &gt->reset.flags))
1311                         wait_on_bit(&gt->reset.flags,
1312                                     I915_RESET_ENGINE + engine->id,
1313                                     TASK_UNINTERRUPTIBLE);
1314         }
1315
1316         intel_gt_reset_global(gt, engine_mask, msg);
1317
1318         for_each_engine(engine, gt, tmp)
1319                 clear_bit_unlock(I915_RESET_ENGINE + engine->id,
1320                                  &gt->reset.flags);
1321         clear_bit_unlock(I915_RESET_BACKOFF, &gt->reset.flags);
1322         smp_mb__after_atomic();
1323         wake_up_all(&gt->reset.queue);
1324
1325 out:
1326         intel_runtime_pm_put(gt->uncore->rpm, wakeref);
1327 }
1328
1329 int intel_gt_reset_trylock(struct intel_gt *gt, int *srcu)
1330 {
1331         might_lock(&gt->reset.backoff_srcu);
1332         might_sleep();
1333
1334         rcu_read_lock();
1335         while (test_bit(I915_RESET_BACKOFF, &gt->reset.flags)) {
1336                 rcu_read_unlock();
1337
1338                 if (wait_event_interruptible(gt->reset.queue,
1339                                              !test_bit(I915_RESET_BACKOFF,
1340                                                        &gt->reset.flags)))
1341                         return -EINTR;
1342
1343                 rcu_read_lock();
1344         }
1345         *srcu = srcu_read_lock(&gt->reset.backoff_srcu);
1346         rcu_read_unlock();
1347
1348         return 0;
1349 }
1350
1351 void intel_gt_reset_unlock(struct intel_gt *gt, int tag)
1352 __releases(&gt->reset.backoff_srcu)
1353 {
1354         srcu_read_unlock(&gt->reset.backoff_srcu, tag);
1355 }
1356
1357 int intel_gt_terminally_wedged(struct intel_gt *gt)
1358 {
1359         might_sleep();
1360
1361         if (!intel_gt_is_wedged(gt))
1362                 return 0;
1363
1364         if (intel_gt_has_unrecoverable_error(gt))
1365                 return -EIO;
1366
1367         /* Reset still in progress? Maybe we will recover? */
1368         if (wait_event_interruptible(gt->reset.queue,
1369                                      !test_bit(I915_RESET_BACKOFF,
1370                                                &gt->reset.flags)))
1371                 return -EINTR;
1372
1373         return intel_gt_is_wedged(gt) ? -EIO : 0;
1374 }
1375
1376 void intel_gt_set_wedged_on_init(struct intel_gt *gt)
1377 {
1378         BUILD_BUG_ON(I915_RESET_ENGINE + I915_NUM_ENGINES >
1379                      I915_WEDGED_ON_INIT);
1380         intel_gt_set_wedged(gt);
1381         set_bit(I915_WEDGED_ON_INIT, &gt->reset.flags);
1382
1383         /* Wedged on init is non-recoverable */
1384         add_taint_for_CI(gt->i915, TAINT_WARN);
1385 }
1386
1387 void intel_gt_set_wedged_on_fini(struct intel_gt *gt)
1388 {
1389         intel_gt_set_wedged(gt);
1390         set_bit(I915_WEDGED_ON_FINI, &gt->reset.flags);
1391         intel_gt_retire_requests(gt); /* cleanup any wedged requests */
1392 }
1393
1394 void intel_gt_init_reset(struct intel_gt *gt)
1395 {
1396         init_waitqueue_head(&gt->reset.queue);
1397         mutex_init(&gt->reset.mutex);
1398         init_srcu_struct(&gt->reset.backoff_srcu);
1399
1400         /*
1401          * While undesirable to wait inside the shrinker, complain anyway.
1402          *
1403          * If we have to wait during shrinking, we guarantee forward progress
1404          * by forcing the reset. Therefore during the reset we must not
1405          * re-enter the shrinker. By declaring that we take the reset mutex
1406          * within the shrinker, we forbid ourselves from performing any
1407          * fs-reclaim or taking related locks during reset.
1408          */
1409         i915_gem_shrinker_taints_mutex(gt->i915, &gt->reset.mutex);
1410
1411         /* no GPU until we are ready! */
1412         __set_bit(I915_WEDGED, &gt->reset.flags);
1413 }
1414
1415 void intel_gt_fini_reset(struct intel_gt *gt)
1416 {
1417         cleanup_srcu_struct(&gt->reset.backoff_srcu);
1418 }
1419
1420 static void intel_wedge_me(struct work_struct *work)
1421 {
1422         struct intel_wedge_me *w = container_of(work, typeof(*w), work.work);
1423
1424         drm_err(&w->gt->i915->drm,
1425                 "%s timed out, cancelling all in-flight rendering.\n",
1426                 w->name);
1427         intel_gt_set_wedged(w->gt);
1428 }
1429
1430 void __intel_init_wedge(struct intel_wedge_me *w,
1431                         struct intel_gt *gt,
1432                         long timeout,
1433                         const char *name)
1434 {
1435         w->gt = gt;
1436         w->name = name;
1437
1438         INIT_DELAYED_WORK_ONSTACK(&w->work, intel_wedge_me);
1439         schedule_delayed_work(&w->work, timeout);
1440 }
1441
1442 void __intel_fini_wedge(struct intel_wedge_me *w)
1443 {
1444         cancel_delayed_work_sync(&w->work);
1445         destroy_delayed_work_on_stack(&w->work);
1446         w->gt = NULL;
1447 }
1448
1449 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1450 #include "selftest_reset.c"
1451 #include "selftest_hangcheck.c"
1452 #endif