drivers/gpu/drm/mediatek/mtk_disp_rdma.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015 MediaTek Inc.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/component.h>
   8 #include <linux/module.h>
   9 #include <linux/of_device.h>
  10 #include <linux/of_irq.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/soc/mediatek/mtk-cmdq.h>
  13
  14 #include "mtk_disp_drv.h"
  15 #include "mtk_drm_crtc.h"
  16 #include "mtk_drm_ddp_comp.h"
  17
  18 #define DISP_REG_RDMA_INT_ENABLE                0x0000
  19 #define DISP_REG_RDMA_INT_STATUS                0x0004
  20 #define RDMA_TARGET_LINE_INT                            BIT(5)
  21 #define RDMA_FIFO_UNDERFLOW_INT                         BIT(4)
  22 #define RDMA_EOF_ABNORMAL_INT                           BIT(3)
  23 #define RDMA_FRAME_END_INT                              BIT(2)
  24 #define RDMA_FRAME_START_INT                            BIT(1)
  25 #define RDMA_REG_UPDATE_INT                             BIT(0)
  26 #define DISP_REG_RDMA_GLOBAL_CON                0x0010
  27 #define RDMA_ENGINE_EN                                  BIT(0)
  28 #define RDMA_MODE_MEMORY                                BIT(1)
  29 #define DISP_REG_RDMA_SIZE_CON_0                0x0014
  30 #define RDMA_MATRIX_ENABLE                              BIT(17)
  31 #define RDMA_MATRIX_INT_MTX_SEL                         GENMASK(23, 20)
  32 #define RDMA_MATRIX_INT_MTX_BT601_to_RGB                (6 << 20)
  33 #define DISP_REG_RDMA_SIZE_CON_1                0x0018
  34 #define DISP_REG_RDMA_TARGET_LINE               0x001c
  35 #define DISP_RDMA_MEM_CON                       0x0024
  36 #define MEM_MODE_INPUT_FORMAT_RGB565                    (0x000 << 4)
  37 #define MEM_MODE_INPUT_FORMAT_RGB888                    (0x001 << 4)
  38 #define MEM_MODE_INPUT_FORMAT_RGBA8888                  (0x002 << 4)
  39 #define MEM_MODE_INPUT_FORMAT_ARGB8888                  (0x003 << 4)
  40 #define MEM_MODE_INPUT_FORMAT_UYVY                      (0x004 << 4)
  41 #define MEM_MODE_INPUT_FORMAT_YUYV                      (0x005 << 4)
  42 #define MEM_MODE_INPUT_SWAP                             BIT(8)
  43 #define DISP_RDMA_MEM_SRC_PITCH                 0x002c
  44 #define DISP_RDMA_MEM_GMC_SETTING_0             0x0030
  45 #define DISP_REG_RDMA_FIFO_CON                  0x0040
  46 #define RDMA_FIFO_UNDERFLOW_EN                          BIT(31)
  47 #define RDMA_FIFO_PSEUDO_SIZE(bytes)                    (((bytes) / 16) << 16)
  48 #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes)         ((bytes) / 16)
  49 #define RDMA_FIFO_SIZE(rdma)                    ((rdma)->data->fifo_size)
  50 #define DISP_RDMA_MEM_START_ADDR                0x0f00
  51
  52 #define RDMA_MEM_GMC                            0x40402020
  53
  54 struct mtk_disp_rdma_data {
  55         unsigned int fifo_size;
  56 };
  57
  58 /**
  59  * struct mtk_disp_rdma - DISP_RDMA driver structure
  60  * @ddp_comp: structure containing type enum and hardware resources
  61  * @crtc: associated crtc to report irq events to
  62  * @data: local driver data
  63  */
  64 struct mtk_disp_rdma {
  65         struct clk                      *clk;
  66         void __iomem                    *regs;
  67         struct cmdq_client_reg          cmdq_reg;
  68         const struct mtk_disp_rdma_data *data;
  69         void                            (*vblank_cb)(void *data);
  70         void                            *vblank_cb_data;
  71         u32                             fifo_size;
  72 };
  73
  74 static irqreturn_t mtk_disp_rdma_irq_handler(int irq, void *dev_id)
  75 {
  76         struct mtk_disp_rdma *priv = dev_id;
  77
  78         /* Clear frame completion interrupt */
  79         writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS);
  80
  81         if (!priv->vblank_cb)
  82                 return IRQ_NONE;
  83
  84         priv->vblank_cb(priv->vblank_cb_data);
  85
  86         return IRQ_HANDLED;
  87 }
  88
  89 static void rdma_update_bits(struct device *dev, unsigned int reg,
  90                              unsigned int mask, unsigned int val)
  91 {
  92         struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
  93         unsigned int tmp = readl(rdma->regs + reg);
  94
  95         tmp = (tmp & ~mask) | (val & mask);
  96         writel(tmp, rdma->regs + reg);
  97 }
  98
  99 void mtk_rdma_enable_vblank(struct device *dev,
 100                             void (*vblank_cb)(void *),
 101                             void *vblank_cb_data)
 102 {
 103         struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
 104
 105         rdma->vblank_cb = vblank_cb;
 106         rdma->vblank_cb_data = vblank_cb_data;
 107         rdma_update_bits(dev, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT,
 108                          RDMA_FRAME_END_INT);
 109 }
 110
 111 void mtk_rdma_disable_vblank(struct device *dev)
 112 {
 113         struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
 114
 115         rdma->vblank_cb = NULL;
 116         rdma->vblank_cb_data = NULL;
 117         rdma_update_bits(dev, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 0);
 118 }
 119
 120 int mtk_rdma_clk_enable(struct device *dev)
 121 {
 122         struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
 123
 124         return clk_prepare_enable(rdma->clk);
 125 }
 126
 127 void mtk_rdma_clk_disable(struct device *dev)
 128 {
 129         struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
 130
 131         clk_disable_unprepare(rdma->clk);
 132 }
 133
 134 void mtk_rdma_start(struct device *dev)
 135 {
 136         rdma_update_bits(dev, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN,
 137                          RDMA_ENGINE_EN);
 138 }
 139
 140 void mtk_rdma_stop(struct device *dev)
 141 {
 142         rdma_update_bits(dev, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0);
 143 }
 144
 145 void mtk_rdma_config(struct device *dev, unsigned int width,
 146                      unsigned int height, unsigned int vrefresh,
 147                      unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
 148 {
 149         unsigned int threshold;
 150         unsigned int reg;
 151         struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
 152         u32 rdma_fifo_size;
 153
 154         mtk_ddp_write_mask(cmdq_pkt, width, &rdma->cmdq_reg, rdma->regs,
 155                            DISP_REG_RDMA_SIZE_CON_0, 0xfff);
 156         mtk_ddp_write_mask(cmdq_pkt, height, &rdma->cmdq_reg, rdma->regs,
 157                            DISP_REG_RDMA_SIZE_CON_1, 0xfffff);
 158
 159         if (rdma->fifo_size)
 160                 rdma_fifo_size = rdma->fifo_size;
 161         else
 162                 rdma_fifo_size = RDMA_FIFO_SIZE(rdma);
 163
 164         /*
 165          * Enable FIFO underflow since DSI and DPI can't be blocked.
 166          * Keep the FIFO pseudo size reset default of 8 KiB. Set the
 167          * output threshold to 6 microseconds with 7/6 overhead to
 168          * account for blanking, and with a pixel depth of 4 bytes:
 169          */
 170         threshold = width * height * vrefresh * 4 * 7 / 1000000;
 171         reg = RDMA_FIFO_UNDERFLOW_EN |
 172               RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) |
 173               RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
 174         mtk_ddp_write(cmdq_pkt, reg, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_FIFO_CON);
 175 }
 176
 177 static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
 178                                      unsigned int fmt)
 179 {
 180         /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"
 181          * is defined in mediatek HW data sheet.
 182          * The alphabet order in XXX is no relation to data
 183          * arrangement in memory.
 184          */
 185         switch (fmt) {
 186         default:
 187         case DRM_FORMAT_RGB565:
 188                 return MEM_MODE_INPUT_FORMAT_RGB565;
 189         case DRM_FORMAT_BGR565:
 190                 return MEM_MODE_INPUT_FORMAT_RGB565 | MEM_MODE_INPUT_SWAP;
 191         case DRM_FORMAT_RGB888:
 192                 return MEM_MODE_INPUT_FORMAT_RGB888;
 193         case DRM_FORMAT_BGR888:
 194                 return MEM_MODE_INPUT_FORMAT_RGB888 | MEM_MODE_INPUT_SWAP;
 195         case DRM_FORMAT_RGBX8888:
 196         case DRM_FORMAT_RGBA8888:
 197                 return MEM_MODE_INPUT_FORMAT_ARGB8888;
 198         case DRM_FORMAT_BGRX8888:
 199         case DRM_FORMAT_BGRA8888:
 200                 return MEM_MODE_INPUT_FORMAT_ARGB8888 | MEM_MODE_INPUT_SWAP;
 201         case DRM_FORMAT_XRGB8888:
 202         case DRM_FORMAT_ARGB8888:
 203                 return MEM_MODE_INPUT_FORMAT_RGBA8888;
 204         case DRM_FORMAT_XBGR8888:
 205         case DRM_FORMAT_ABGR8888:
 206                 return MEM_MODE_INPUT_FORMAT_RGBA8888 | MEM_MODE_INPUT_SWAP;
 207         case DRM_FORMAT_UYVY:
 208                 return MEM_MODE_INPUT_FORMAT_UYVY;
 209         case DRM_FORMAT_YUYV:
 210                 return MEM_MODE_INPUT_FORMAT_YUYV;
 211         }
 212 }
 213
 214 unsigned int mtk_rdma_layer_nr(struct device *dev)
 215 {
 216         return 1;
 217 }
 218
 219 void mtk_rdma_layer_config(struct device *dev, unsigned int idx,
 220                            struct mtk_plane_state *state,
 221                            struct cmdq_pkt *cmdq_pkt)
 222 {
 223         struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
 224         struct mtk_plane_pending_state *pending = &state->pending;
 225         unsigned int addr = pending->addr;
 226         unsigned int pitch = pending->pitch & 0xffff;
 227         unsigned int fmt = pending->format;
 228         unsigned int con;
 229
 230         con = rdma_fmt_convert(rdma, fmt);
 231         mtk_ddp_write_relaxed(cmdq_pkt, con, &rdma->cmdq_reg, rdma->regs, DISP_RDMA_MEM_CON);
 232
 233         if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) {
 234                 mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, &rdma->cmdq_reg, rdma->regs,
 235                                    DISP_REG_RDMA_SIZE_CON_0,
 236                                    RDMA_MATRIX_ENABLE);
 237                 mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RGB,
 238                                    &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_SIZE_CON_0,
 239                                    RDMA_MATRIX_INT_MTX_SEL);
 240         } else {
 241                 mtk_ddp_write_mask(cmdq_pkt, 0, &rdma->cmdq_reg, rdma->regs,
 242                                    DISP_REG_RDMA_SIZE_CON_0,
 243                                    RDMA_MATRIX_ENABLE);
 244         }
 245         mtk_ddp_write_relaxed(cmdq_pkt, addr, &rdma->cmdq_reg, rdma->regs,
 246                               DISP_RDMA_MEM_START_ADDR);
 247         mtk_ddp_write_relaxed(cmdq_pkt, pitch, &rdma->cmdq_reg, rdma->regs,
 248                               DISP_RDMA_MEM_SRC_PITCH);
 249         mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, &rdma->cmdq_reg, rdma->regs,
 250                       DISP_RDMA_MEM_GMC_SETTING_0);
 251         mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, &rdma->cmdq_reg, rdma->regs,
 252                            DISP_REG_RDMA_GLOBAL_CON, RDMA_MODE_MEMORY);
 253
 254 }
 255
 256 static int mtk_disp_rdma_bind(struct device *dev, struct device *master,
 257                               void *data)
 258 {
 259         return 0;
 260
 261 }
 262
 263 static void mtk_disp_rdma_unbind(struct device *dev, struct device *master,
 264                                  void *data)
 265 {
 266 }
 267
 268 static const struct component_ops mtk_disp_rdma_component_ops = {
 269         .bind   = mtk_disp_rdma_bind,
 270         .unbind = mtk_disp_rdma_unbind,
 271 };
 272
 273 static int mtk_disp_rdma_probe(struct platform_device *pdev)
 274 {
 275         struct device *dev = &pdev->dev;
 276         struct mtk_disp_rdma *priv;
 277         struct resource *res;
 278         int irq;
 279         int ret;
 280
 281         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 282         if (!priv)
 283                 return -ENOMEM;
 284
 285         irq = platform_get_irq(pdev, 0);
 286         if (irq < 0)
 287                 return irq;
 288
 289         priv->clk = devm_clk_get(dev, NULL);
 290         if (IS_ERR(priv->clk)) {
 291                 dev_err(dev, "failed to get rdma clk\n");
 292                 return PTR_ERR(priv->clk);
 293         }
 294
 295         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 296         priv->regs = devm_ioremap_resource(dev, res);
 297         if (IS_ERR(priv->regs)) {
 298                 dev_err(dev, "failed to ioremap rdma\n");
 299                 return PTR_ERR(priv->regs);
 300         }
 301 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 302         ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
 303         if (ret)
 304                 dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
 305 #endif
 306
 307         if (of_find_property(dev->of_node, "mediatek,rdma-fifo-size", &ret)) {
 308                 ret = of_property_read_u32(dev->of_node,
 309                                            "mediatek,rdma-fifo-size",
 310                                            &priv->fifo_size);
 311                 if (ret) {
 312                         dev_err(dev, "Failed to get rdma fifo size\n");
 313                         return ret;
 314                 }
 315         }
 316
 317         /* Disable and clear pending interrupts */
 318         writel(0x0, priv->regs + DISP_REG_RDMA_INT_ENABLE);
 319         writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS);
 320
 321         ret = devm_request_irq(dev, irq, mtk_disp_rdma_irq_handler,
 322                                IRQF_TRIGGER_NONE, dev_name(dev), priv);
 323         if (ret < 0) {
 324                 dev_err(dev, "Failed to request irq %d: %d\n", irq, ret);
 325                 return ret;
 326         }
 327
 328         priv->data = of_device_get_match_data(dev);
 329
 330         platform_set_drvdata(pdev, priv);
 331
 332         ret = component_add(dev, &mtk_disp_rdma_component_ops);
 333         if (ret)
 334                 dev_err(dev, "Failed to add component: %d\n", ret);
 335
 336         return ret;
 337 }
 338
 339 static int mtk_disp_rdma_remove(struct platform_device *pdev)
 340 {
 341         component_del(&pdev->dev, &mtk_disp_rdma_component_ops);
 342
 343         return 0;
 344 }
 345
 346 static const struct mtk_disp_rdma_data mt2701_rdma_driver_data = {
 347         .fifo_size = SZ_4K,
 348 };
 349
 350 static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = {
 351         .fifo_size = SZ_8K,
 352 };
 353
 354 static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
 355         .fifo_size = 5 * SZ_1K,
 356 };
 357
 358 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 359         { .compatible = "mediatek,mt2701-disp-rdma",
 360           .data = &mt2701_rdma_driver_data},
 361         { .compatible = "mediatek,mt8173-disp-rdma",
 362           .data = &mt8173_rdma_driver_data},
 363         { .compatible = "mediatek,mt8183-disp-rdma",
 364           .data = &mt8183_rdma_driver_data},
 365         {},
 366 };
 367 MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
 368
 369 struct platform_driver mtk_disp_rdma_driver = {
 370         .probe          = mtk_disp_rdma_probe,
 371         .remove         = mtk_disp_rdma_remove,
 372         .driver         = {
 373                 .name   = "mediatek-disp-rdma",
 374                 .owner  = THIS_MODULE,
 375                 .of_match_table = mtk_disp_rdma_driver_dt_match,
 376         },
 377 };